Intersil ISL9208IRZ Multi-cell li-ion battery pack ocp/analog front end Datasheet

ISL9208
®
Data Sheet
February 16, 2007
Multi-Cell Li-ion Battery Pack OCP/Analog
Front End
The ISL9208 is an overcurrent protection device and analog
front end for a microcontroller in a multi-cell Li-ion battery
pack. The ISL9208 supports battery pack configurations
consisting of 5 cells to 7 cells in series and 1 or more cells in
parallel. The ISL9208 provides integral overcurrent
protection circuitry, short circuit protection, an internal 3.3V
voltage regulator, internal cell balancing switches, cell
voltage monitor level shifters, and drive circuitry for external
FET devices for control of pack charge and discharge.
Selectable overcurrent and short circuit thresholds reside in
internal RAM registers. An external microcontroller sets the
thresholds by setting register values through an I2C serial
interface. Internal registers also contain the detection delays
for overcurrent and short circuit conditions.
Using an internal analog multiplexer the ISL9208 provides
monitoring of each cell voltage plus internal and external
temperature by a separate microcontroller with an A/D
converter. Software on this microcontroller implements all
battery pack control functionality, except for overcurrent and
short circuit shutdown.
Ordering Information
PART NUMBER
(Note)
ISL9208IRZ*
PART
MARKING
PACKAGE
(Pb-free)
ISL9208 IRZ
32 Ld 5x5 QFN
PKG.
DWG. #
L32.5x5B
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
FN6446.0
Features
• Software selectable overcurrent protection levels and
variable protect detection times
- 4 discharge overcurrent thresholds
- 4 short circuit thresholds
- 4 charge overcurrent thresholds
- 8 overcurrent delay times (Charge)
- 8 overcurrent delay times (Discharge)
- 2 short circuit delay times (Discharge)
• Automatic FET turn-off and cell balance disable on
reaching external (battery) or internal (IC) temperature
limit.
• Automatic over-ride of cell balance on reaching internal
(IC) temperature limit.
• Fast short circuit pack shutdown
• Can use current sense resistor, FET rDS(ON), or Sense
FET for overcurrent detection.
• Four battery backed software controlled flags.
• Allows three different FET controls:
- Back-to-back N-Channel FETs for charge and discharge
control
- Single N-Channel discharge FET.
- Single N-Channel FET for discharge, with separate,
optional (smaller) back-to-back N-channel FETs for
charge.
• Integrated Charge/Discharge FET Drive Circuitry with
200µA (typ) turn-on current and 150mA (typ) Discharge
FET turn-off current.
• 10% Accurate 3.3V voltage regulator (minimum 25mA out
with external NPN transistor having current gain of 70).
• Monitored cell voltage output stable in 100µs.
• Internal Cell balancing FETs handle up to 200mA of
balancing current for each cell (with the number of cells
being balanced limited by the maximum package power
dissipation of 400mW).
• Simple I2C host interface
• Sleep operation with programmable negative edge or
positive edge wake up.
• <10µA Sleep Mode
• Pb-free plus anneal available (RoHS compliant)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL9208
Pinout
RGO
TEMP3V
RGC
WKUP
SDA
NC
SCL
NC
ISL9208
(32 LD QFN)
TOP VIEW
32 31 30 29 28 27 26 25
1
24
TEMPI
VC7/VCC
2
23
AO
CB7
3
22
VMON
VCELL6
4
21
CFET
5
20
DFET
6
19
CSENSE
7
18
DSENSE
DSREF
VSS
CB1
VCELL1
CB4
8
17
9 10 11 12 13 14 15 16
CB2
CB5
VCELL4
VCELL2
VCELL5
CB3
CB6
VCELL3
NC
Functional Diagram
SCL SDA
I2C I/F
VC7/VCC
CB7
CELL
VOLTAGES
VCELL6
2
CB6
VCELL5
CB3
VCELL2
CB2
3.3VDC
REGULATOR
OSC
VCELL1
FET CONTROL
CIRCUITRY
CB1
WKUP
RGC
RGO
CONTROL
LOGIC
TEMPERATURE
SENSOR, INT/EXT
COMPARATOR
EXT TEMP
2
CSENSE
VSS
DSREF
DSENSE
BACKUP
SUPPLY
VMON
VCELL3
POWER
CONTROL
REGISTERS
OVERCURRENT
PROTECTION
CIRCUITS
(THRESHOLD
DETECT AND
TIMING)
CFET
CB4
LEVEL
SHIFTERS/
CELL
BALANCE
CIRCUITS
DFET
CB5
VCELL4
MUX
7
AO
TEMPI TEMP3V
FN6446.0
February 16, 2007
ISL9208
Pin Names
SYMBOL
DESCRIPTION
VC7/VCC Battery cell 7 voltage input/VCC supply. This pin is used to monitor the voltage of this battery cell externally at pin
AO. This pin also provides the operating voltage for the IC circuitry.
VCELLN Battery cell N voltage input. This pin is used to monitor the voltage of this battery cell externally at pin AO. VCELLN
connects to the positive terminal of CELLN and the negative terminal of CELLN + 1.
CBN
Cell balancing FET control output N. This internal FET diverts a fraction of the current around a cell while the cell is
being charged or adds to the current pulled from a cell during discharge in order to perform a cell voltage balancing
operation. This function is generally used to reduce the voltage on an individual cell relative to other cells in the pack.
The cell balancing FETs are turned on or off by an external controller.
VSS
Ground. This pin connects to the most negative terminal in the battery string.
DSREF
Discharge current sense reference. This input provides a separate reference point for the charge and discharge
current monitoring circuits. WIth a separate reference connection, it is possible to minimize errors that result from
voltage drops on the ground lead when the load is drawing large currents. If a separate reference is not necessary,
connect this pin to VSS.
DSENSE Discharge current sense monitor. This input monitors the discharge current by monitoring a voltage. It can monitor
the voltage across a sense resistor, or the voltage across the DFET, or by using a FET with a current sense pin. The
voltage on this pin is measured with reference to DSREF.
CSENSE Charge current sense monitor. This input monitors the charge current by monitoring a voltage. It can monitor the
voltage across a sense resistor, or the voltage across the CFET, or by using a FET with a current sense pin. The voltage
on this pin is measured with reference to VSS.
DFET
Discharge FET control. The ISL9208 controls the gate of a discharge FET through this pin. The power FET is a
N-Channel device. The FET is turned on only by the microcontroller. The FET can be turned off by the microcontroller,
but the ISL9208 also turns off the FET in the event of an overcurrent or short circuit condition. If the microcontroller
detects an undervoltage condition on any of the battery cells, it can turn off the discharge FET by controlling this output
with a control bit.
CFET
Charge FET control. The ISL9208 controls the gate of a charge FET through this pin. The power FET is a N-Channel
device. The FET is turned on only by the microcontroller. The FET can be turned off by the microcontroller, but the
ISL9208 also turns off the FET in the event of an overcurrent condition. If the microcontroller detects an overvoltage
condition on any of the battery cells, it can turn off the FET by controlling this output with a control bit.
VMON
Discharge load monitoring. In the event of an overcurrent or short circuit condition, the microcontroller can enable an
internal resistor that connects between the VMON pin and VSS. When the FETs open because of an overcurrent or
short circuit condition and the load remains, the voltage at VMON will be near the VCC voltage. When the load is
released, the voltage at VMON drops below a threshold indicating that the overcurrent or short circuit condition is
resolved. At this point, the LDFAIL flag is cleared and operation can resume.
AO
Analog multiplexer output. The analog output pin is used by an external microcontroller to monitor the cell voltages
and temperature sensor voltages. The microcontroller selects the specific voltage being applied to the output by writing
to a control register.
TEMP3V Temperature monitor output control. This pin outputs a voltage to be used in a divider that consists of a fixed resistor
and a thermistor. The thermistor is located in close proximity to the cells. The TEMP3V output is connected internally
to the RGO voltage through a PMOS switch only during a measurement of the temperature, otherwise the TEMP3V
output is off. The TEMP3V output can be turned on continuously with a special control bit.
Microcontroller wake up control. The TEMP3V pin is also turned on when any of the DSC, DOC, or COC bits are set.
This can be used to wake up a sleeping microcontroller to respond to overcurrent conditions with its own control
mechanism.
TEMPI
Temperature monitor input. This pin inputs the voltage across a thermistor to determine the temperature of the cells.
When this input drops below TEMP3V/13, an external over-temperature condition exists. The TEMPI voltage is also fed
to the AO output pin through an analog multiplexer so the temperature of the cells can be monitored by the
microcontroller.
3
FN6446.0
February 16, 2007
ISL9208
Pin Names (Continued)
SYMBOL
DESCRIPTION
RGO
Regulated output voltage. This pin connects to the emitter of an external NPN transistor and works in conjunction with
the RGC pin to provides a regulated 3.3V. The voltage at this pin provides feedback for the regulator and power for
many of the ISL9208 internal circuits as well as providing the 3.3V output voltage for the microcontroller and other
external circuits.
RGC
Regulated output control. This pin connects to the base of an external NPN transistor and works in conjunction with
the RGO pin to provide a regulated 3.3V. The RGC output provides the control signal for the external transistor to
provide the 3.3V regulated voltage on the RGO pin.
WKUP
Wake up Voltage. This input wakes up the part when the voltage crosses a turn-on threshold (wake up is edge
triggered). The condition of the pin is reflected in the WKUP bit (The WKUP bit is level sensitive.)
• WKPOL bit = ”1”: the device wakes up on the rising edge of the WKUP pin. Also, the WKUP bit is HIGH only when
the WKUP pin voltage > threshold.
• WKPOL bit = ”0”, the device wakes up on the falling edge of the WKUP pin. Also, the WKUP bit is HIGH only when
the WKUP pin voltage < threshold.
SDA
Serial Data. This is the bidirectional data line for an I2C interface.
SCL
Serial Clock. This is the clock input for an I2C communication link.
4
FN6446.0
February 16, 2007
ISL9208
Absolute Maximum Ratings
Thermal Information
Power Supply Voltage, VCC . . . . . . . . . .VSS - 0.5V to VSS + 36.0V
Cell voltage, VCELL
VCELLN - (VCELLN-1), VCELL1-VSS . . . . . . . . . . . . . -0.5V to 5V
Terminal Voltage, VTERM1
(SCL, SDA, CSENSE, DSENSE, TEMPI, RGO, AO, TEMP3V)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS-0.5 to VRGO + 0.5V
Terminal Voltage, VTERM2 (CFET, VMON) . . . . VSS - 22.0V to VCC
Terminal Voltage, VTERM3 (WKUP)
. . . . . . . . . . . . . . . . . . . . . . . . . . . VSS - 0.5V to VCC(VCC < 27V)
Terminal Voltage, VTERM4 (RGC) . . . . . . . . . . . . . VSS - 0.5V to 5V
Terminal Voltage, VTERM5, (all other pins)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS - 0.5V to VCC + 0.5V
Thermal Resistance (Typical, Note 1, 2)
θJA (°C/W)
θJC (°C/W)
32 Ld QFN . . . . . . . . . . . . . . . . . . . . . .
32
2
Continuous Package Power Dissipation . . . . . . . . . . . . . . . . .400mW
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to +125°C
Lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . . +300°C
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . . 5V to 10V
Operating Voltage:
VCC pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 to 30.1V
VCELL1-VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 4.3V
VCELLN-(VCELLN-1). . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 4.3V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. θJC, “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Operating Specifications Over the recommended operating conditions unless otherwise specified
PARAMETER
SYMBOL
Operating Voltage
TEST CONDITION
VCC
MIN
TYP
MAX
UNIT
30.1
V
4
9.2
V
1.7
2.3
V
9.2
Power Up Condition 1
VPORVCC VCC voltage (Note 3)
Power Up Condition 2 Threshold
VPOR123 VCELL1 - VSS and VCELL2 - VCELL1 and
VCELL3 - VCELL2 (rising)
(Note 3)
Power Up Condition 2 Hysteresis
VPORhys VCELL1 - VSS and VCELL2 - VCELL1 and
VCELL3 - VCELL2 (falling)
(Note 3)
1.1
70
3.3V Regulated Voltage
VRGO
0µA < IRGC < 350µA
3.0
3.3
3.3VDC Voltage Regulator Control
Current Limit
IRGC
(Control current at output of RGC.
Recommend NPN with gain of 70+)
0.35
0.50
VCC Supply Current
IVCC1
Power up defaults, WKUP pin = 0V.
RGO Supply Current
IRGO1
VCC Supply Current
IVCC2
RGO Supply Current
IRGO2
VCC Supply Current
IVCC3
RGO Supply Current
IRGO3
mV
3.6
V
mA
400
510
µA
300
410
µA
500
700
µA
450
650
µA
Default register settings, except
SLEEP bit = 1. WKUP pin = VCELL1
10
µA
1
µA
LDMONEN bit = 1, VMON floating,
CFET = 1, DFET=1, WKPOL bit = 1,
VWKUP = 10V, [AO3:AO0] bits = 03H.
VCELL Input Current - VCELL1
IVCELL1
AO3:AO0 bits = 0000H
14
µA
VCELL Input Current - VCELLN
IVCELLN AO3:AO0 bits = 0000H
10
µA
5
FN6446.0
February 16, 2007
ISL9208
Operating Specifications Over the recommended operating conditions unless otherwise specified (Continued)
PARAMETER
SYMBOL
TEST CONDITION
MIN
TYP
MAX
UNIT
VOCD = 0.10V (OCDV1, OCDV0 = 0, 0)
0.08
0.10
0.12
V
VOCD = 0.12V (OCDV1, OCDV0 = 0,1)
0.10
0.12
0.14
V
VOCD = 0.14V (OCDV1, OCDV0 = 1,0)
0.12
0.14
0.16
V
VOCD = 0.16V (OCDV1, OCDV0 = 1,1)
0.14
0.16
0.18
V
VOCC = 0.10V (OCCV1, OCCV0 = 0, 0)
-0.12
-0.10
-0.07
V
VOCC = 0.12V (OCCV1, OCCV0 = 0,1)
-0.14
-0.12
-0.09
V
VOCC = 0.14V (OCCV1, OCCV0 = 1,0)
-0.16
-0.14
-0.11
V
VOCC = 0.16V (OCCV1, OCCV0 = 1,1)
-0.18
-0.16
-0.13
V
VOC = 0.20V (SCDV1, SCDV0 = 0, 0)
0.15
0.20
0.25
V
VOC = 0.35V (SCDV1, SCDV0 = 0,1)
0.30
0.35
0.40
V
VOC = 0.65V (SCDV1, SCDV0 = 1, 0)
0.60
0.65
0.70
V
VOC = 1.20V (SCDV1, SCDV0 = 1,1)
1.10
1.20
1.30
V
LDMONEN bit = “1”
1.1
1.45
1.8
V
OVERCURRENT/SHORT CIRCUIT PROTECTION SPECIFICATIONS
VOCD
Overcurrent Detection Threshold
(Discharge) Voltage Relative To
DSREF
(Default in Boldface)
Overcurrent Detection Threshold
(Charge) Voltage Relative to DSREF
(Default in Boldface)
VOCC
VSC
Short Current Detection Threshold
Voltage Relative to DSREF
(Default in Boldface)
Load Monitor Input Threshold
(Falling Edge)
VVMON
VVMONH LDMONEN bit = “1”
Load Monitor Input Threshold
(Hysteresis)
Load Monitor Current
IVMON
Short Circuit Time-out
tSCD
Over Discharge Current Time-out
(Default In Boldface)
tOCD
6
0.25
mV
20
40
60
µA
Short circuit detection delay (SCLONG
bit = ‘0’)
70
150
220
µs
Short circuit detection delay (SCLONG
bit = ‘1’)
4
8
12
ms
tOCD = 128ms (OCDT1, OCDT0 = 0, 0 and
DTDIV = 0)
64
128
192
ms
tOCD = 256ms (OCDT1, OCDT0 = 0, 1 and
DTDIV = 0)
128
256
384
ms
tOCD = 512ms (OCDT1, OCDT0 = 1, 0 and
DTDIV = 0)
256
512
768
ms
tOCD = 1024ms (OCDT1, OCDT0 = 1, 1 and
DTDIV = 0)
512
1024
1536
ms
tOCD = 2ms (OCDT1, OCDT0 = 0, 0 and
DTDIV = 1)
1
2
3
ms
tOCD = 4ms (OCDT1, OCDT0 = 0, 1 and
DTDIV = 1)
2
4
6
ms
tOCD = 8ms (OCDT1, OCDT0 = 1, 0 and
DTDIV = 1)
4
8
12
ms
tOCD = 16ms (OCDT1, OCDT0 = 1, 1 and
DTDIV = 1)
8
16
24
ms
FN6446.0
February 16, 2007
ISL9208
Operating Specifications Over the recommended operating conditions unless otherwise specified (Continued)
PARAMETER
SYMBOL
Over Charge Current Time-out
(Default In Boldface)
tOCC
TEST CONDITION
MIN
TYP
MAX
UNIT
tOCC = 64ms (OCCT1,OCCT0 = 0, 0 and
CTDIV = 0)
32
64
96
ms
tOCC = 128ms (OCCT1, OCCT0 = 0, 1 and
CTDIV = 0)
64
128
192
ms
tOCC = 256ms (OCCT1, OCCT0 = 1, 0 and
CTDIV = 0)
128
256
384
ms
tOCC = 512ms (OCCT1, OCCT0 = 1, 1 and
CTDIV = 0)
256
512
768
ms
tOCC = 2ms (OCCT1, OCCT0 = 0, 0 and
CTDIV = 1)
1
2
3
ms
tOCC = 4ms (OCCT1, OCCT0 = 0, 1 and
CTDIV = 1)
2
4
6
ms
tOCC = 8ms (OCCT1, OCCT0 = 1, 0 and
CTDIV = 1)
4
8
12
ms
tOCC = 16ms (OCCT1, OCCT0 = 1, 1 and
CTDIV = 1)
8
16
24
ms
OVER-TEMPERATURE PROTECTION SPECIFICATIONS
Internal Temperature Shutdown
Threshold
TINTSD
Internal Temperature Hysteresis
THYS
Internal Over-temperature Turn On
Delay Time
tITD
External Temperature Output Current
IXT
External Temperature Limit Threshold
TXTF
Temperature drop needed to restore
operation after over-temperature shutdown.
125
°C
20
°C
128
ms
Current output capability at TEMP3V pin
1.2
mA
Voltage at VTEMPI; Relative to falling
edge V TEMP3V
-20
0
+20
mV
60
110
160
mV
------------------------------
13
External Temperature Limit Hysteresis
TXTH
Voltage at VTEMPI.
External Temperature Monitor Delay
tXTD
Delay between activating the external sensor
and the internal over-temperature detection.
1
ms
External Temperature Autoscan On
Time
tXTAON
TEMP3V is ON (3.3V)
4
ms
External Temperature Autoscan Off
Time
tXTAOFF TEMP3V output is off.
508
ms
7
FN6446.0
February 16, 2007
ISL9208
Operating Specifications Over the recommended operating conditions unless otherwise specified (Continued)
PARAMETER
SYMBOL
TEST CONDITION
MIN
TYP
MAX
UNIT
4
30
mV
10
mV
ANALOG OUTPUT SPECIFICATIONS
Cell Monitor Analog Output Voltage
Accuracy
VAOC
[VCELLN - (VCELLN-1)]/2 - AO
-15
Cell Monitor Analog Output External
Temperature Accuracy
VAOXT
External temperature monitoring accuracy.
Voltage error at AO when monitoring TEMPI
voltage (measured with TEMPI = 1V)
-10
Internal Temperature Monitor Output
Voltage Slope
Internal Temperature Monitor Output
VINTMON Internal temperature monitor voltage change
TINT25
Output at +25°C
tVSC
From SCL falling edge at data bit 0 of
command to AO output stable within 0.5% of
final value. AO voltage steps from 0V to 2V.
(CAO = 10pF)
(Note 7)
Cell Balance Transistor rDS(ON)
RCB
(Note 6)
Cell Balance Transistor Current
ICB
AO Output Stabilization Time
-3.5
mV/°C
1.31
V
0.1
ms
CELL BALANCE SPECIFICATIONS
Ω
5
200
mA
6.5
V
WAKE UP/SLEEP SPECIFICATIONS
Device WKUP Pin Voltage Threshold
(WKUP Pin Active High - Rising Edge)
Device Wkup Pin Hysteresis
(WKUP Pin Active High)
VWKUP1 WKUP pin rising edge (WKPOL = 1)
Device wakes up and sets WKUP flag HIGH.
3.5
5.0
100
VWKUP1H WKUP pin falling edge hystersis
(WKPOL = 1) sets WKUP flag LOW (does not
automatically enter sleep mode)
mV
Input Resistance On WKUP
RWKUP
Device WKUP Pin Active Voltage
Threshold (WKUP Pin Active Low Falling Edge)
VWKUP2 WKUP pin falling edge (WKPOL = 0)
VCELL1 - 2.6 VCELL1 - 2.0 VCELL1 - 1.2
Device wakes up and sets WKUP flag HIGH.
Resistance from WKUP pin to VSS
(WKPOL = 1)
130
Device Wake-up Delay
tWKUP
Delay after voltage on WKUP pin crosses the
threshold (rising or falling) before activating
the WKUP bit.
330
200
VWKUP2H WKUP pin rising edge hysteresis
(WKPOL = 0) sets WKUP flag LOW (does not
automatically enter sleep mode)
Device Wkup Pin Hysteresis
(WKUP Pin Active Low)
230
16
32
kΩ
V
mV
48
ms
FET CONTROL SPECIFICATIONS (FOR VCELL1, VCELL2, VCELL3 VOLTAGES FROM 2.8V TO 4.3V)
Control Outputs Response Time
(CFET, DFET)
tCO
Bit 0 to start of control signal (DFET)
Bit 1 to start of control signal (CFET)
1.0
µs
CFET Gate Voltage
VCFET
No load on CFET
VCELL3 - 0.5
VCELL3
V
DFETGate Voltage
VDFET
No load on DFET
VCELL3 - 0.5
VCELL3
V
FET Turn On Current (DFET)
IDFON
DFET voltage = 0 to VCELL3 -1.5V
80
130
400
µA
FET Turn On Current (CFET)
ICF(ON)
CFET voltage = 0 to VCELL3 - 1.5V
80
200
400
µA
FET Turn Off Current (DFET)
IDF(OFF) DFET voltage = VDFET to 1V
100
180
DFET Resistance to VSS
RDF(OFF) VDFET <1V (When turning off the FET)
8
mA
11
Ω
FN6446.0
February 16, 2007
ISL9208
Operating Specifications Over the recommended operating conditions unless otherwise specified (Continued)
PARAMETER
SYMBOL
TEST CONDITION
MIN
TYP
MAX
UNIT
SERIAL INTERFACE CHARACTERISTICS (OVER RECOMMENDED OPERATING CONDITIONS UNLESS OTHERWISE SPECIFIED)
SCL Clock Frequency
fSCL
100
kHz
Pulse Width Suppression Time at SDA
and SCL Inputs
tIN
Any pulse narrower than the max spec is
suppressed.
50
ns
SCL Falling Edge to SDA Output Data
Valid
tAA
From SCL falling crossing VIH(min), until
SDA exits the VIL(max) to VIH(min) window.
3.5
µs
Time the Bus Must Be Free Before Start
of New Transmission
tBUF
SDA crossing VIH(min) during a STOP
condition to SDA crossing VIH(min) during
the following START condition.
4.7
µs
Clock Low Time
tLOW
Measured at the VIL(max) crossing.
4.7
µs
Clock High Time
tHIGH
Measured at the VIH(min) crossing.
4.0
µs
Start Condition Setup Time
tSU:STA
SCL rising edge to SDA falling edge. Both
crossing the VIH(min) level.
4.7
µs
Start Condition Hold Time
tHD:STA
From SDA falling edge crossing VIL(max) to
SCL falling edge crossing VIH(min).
4.0
µs
Input Data Setup Time
tSU:DAT
From SDA exiting the VIL(max) to VIH(min)
window to SCL rising edge crossing VIL(min).
250
ns
Input Data Hold Time
tHD:DAT
From SCL rising edge crossing VIH(min) to
SDA entering the VIL(max) to VIH(min)
window.
0
µs
Stop Condition Setup Time
tSU:STO
From SCL rising edge crossing VIH(min) to
SDA rising edge crossing VIL(max).
4.0
µs
Stop Condition Hold Time
tHD:STO From SDA rising edge to SCL falling edge.
Both crossing VIH(min).
4.0
µs
300
ns
Data Output Hold Time
tDH
From SCL falling edge crossing VIL(max)
until SDA enters the VIL(max) to VIH(min)
window. (Note 4)
SDA and SCL Rise Time
tR
From VIL(max) to VIH(min).
1000
ns
SDA and SCL Fall Time
tF
From VIH(min) to VIL(max).
300
ns
Capacitive Loading Of SDA Or SCL
Cb
Total on-chip and off-chip
400
pF
SDA and SCL Bus Pull-up ResistorOff Chip
ROUT
Input Leakage Current (SCL, SDA)
ILI
Input Buffer Low Voltage (SCL, SDA)
VIL
Input Buffer High Voltage (SCL, SDA)
VIH
Output Buffer Low Voltage (SDA)
SDA and SCL Input Buffer Hysteresis
Maximum is determined by tR and tF.
For CB = 400pF, max is about 2~2.5kΩ
For CB = 40pF, max is about 15kΩ to 20kΩ
1
kΩ
-10
10
µA
Voltage relative to VSS of the device.
-0.3
VRGO x 0.3
V
Voltage relative to VSS of the device.
VRGO x 0.7
VRGO + 0.1V
V
0.4
V
VOL
IOL = 1mA
2
I CHYST Sleep bit = 0
0.05 * VRGO
V
NOTE:
3. Power up of the device requires all VCELL1, VCELL2, VCELL3, and VCC to be above the limits specified.
4. The device provides an internal hold time of at least 300ns for the SDA signal to bridge the unidentified region of the falling edge of SCL.
5. Typical +125°C ±10%, based on design and characterization data.
6. Typical 5Ω ±2Ω, based on design and characterization data.
7. Maximum output capacitance = 15pF.
9
FN6446.0
February 16, 2007
ISL9208
Wake up timing (WKPOL = 0)
<tWKUP
VWKUP2H
VWKUP2
<tWKUP
WKUP PIN
tWKUP
tWKUP
WKUP BIT
Wake up timing (WKPOL = 1)
<tWKUP
VWKUP1
VWKUP1H
WKUP PIN
<tWKUP
tWKUP
tWKUP
WKUP BIT
Change in Voltage Source, FET Control
SCL
BIT
3
SDA
BIT
2
BIT
1
BIT
0
BIT
1
BIT
0
DATA
AO
tVSC
tCO
tCO
tVSC
tCO
DFET
CFET
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February 16, 2007
ISL9208
Automatic Temperature Scan
AUTO TEMP CONTROL
(INTERNAL ACTIVATION)
508ms
MONITOR TIME = 4ms
3.3V
HIGH IMPEDANCE
TEMP3V PIN
EXTERNAL
TEMPERATURE
OVER-TEMPERATURE
THRESHOLD
TMP3V/13
DELAY TIME = 1ms
DELAY TIME = 1ms
MONITOR TEMP DURING THIS
TIME PERIOD
XOT BIT
FET SHUTDOWN AND CELL BALANCE TURN OFF
(IF ENABLED)
Discharge Overcurrent/Short Circuit Monitor (assumes DENOCD and DENSCD bits are ‘0’)
VSC
VOCD
VDSENSE
tSCD
DOC BIT
DSC BIT
tSCD
tOCD
‘1’
‘0’
‘1’
‘0’
3.3V
TEMP3V
OUTPUT
REGISTER 1 READ
REGISTER 1 READ
VCELL3
DFET
OUTPUT
UC TURNS ON DFET
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February 16, 2007
ISL9208
Charge Overcurrent Monitor (assumes DENOCC bit is ‘0’)
VCSENSE
VOCC
tOCC
‘1’
‘0’
COC BIT
3.3V
TEMP3V
OUTPUT
REGISTER 1 READ
12V
CFET
OUTPUT
µC TURNS ON CFET
Serial Interface Timing Diagrams
Bus Timing
tF
tHIGH
tLOW
tR
SCL
tSU:STA
tSU:DAT
tHD:DAT
tSU:STO
tHD:STA
SDA
(INPUT TIMING)
tAA
tBUF
tDH
SDA
(OUTPUT TIMING)
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
WILL BE
STEADY
MAY CHANGE
FROM LOW
TO HIGH
WILL CHANGE
FROM LOW
TO HIGH
MAY CHANGE
FROM HIGH
TO LOW
WILL CHANGE
FROM HIGH
TO LOW
12
WAVEFORM
INPUTS
OUTPUTS
DON’T CARE:
CHANGES
ALLOWED
CHANGING:
STATE NOT
KNOWN
N/A
CENTER LINE
IS HIGH
IMPEDANCE
FN6446.0
February 16, 2007
ISL9208
Registers
TABLE 1. REGISTERS
ADDR
REGISTER
READ/WRITE
7
6
5
4
3
2
1
0
00H
Config/Op
Status
Read only
Reserved
Reserved
SA
Single AFE
WKUP
WKUP pin
Status
Reserved
Reserved
Reserved
Reserved
01H
Operating
Status
Read only
Reserved
Reserved
XOT
Ext over
temp
IOT
Int over
Temp
LDFAIL
Load Fail
(VMON)
DSC
Short
Circuit
Cell Balance
Read/Write
CB7ON
CB6ON
CB5ON
CB4ON
CB3ON
CB2ON
CB1ON
Reserved
AO2
AO1
AO0
(Note 10)
02H
COC
DOC
Discharge Charge OC
OC
Cell balance FET control bits
03H
Analog Out
Read/Write
UFLG1
UFLG0
User Flag 1 User Flag 0
Reserved
Reserved
AO3
Analog output select bits
04H
FET Control
Read/Write
SLEEP
Force
Sleep
(Note 11)
LDMONEN
Turn on
VMON
connection
Reserved
Reserved
Reserved
Reserved
CFET
Turn on
Charge
FET
(Note 12)
DFET
Turn on
Discharge
FET
(Note 12)
05H
Discharge Set
Read/Write
(Write only if
DISSETEN
bit set)
DENOCD
OCDV1
OCDV0
DENSCD
SCDV1
SCDV0
OCDT1
OCDT0
Read/Write
(Write only if
CHSETEN bit
set)
DENOCC
OCCV1
Turn off
automatic
OCC
control
Overcurrent Charge
Threshold Voltage
06H
Charge Set
Turn off
automatic
OCD
control
Overcurrent Discharge
Threshold Voltage
07H
Feature Set
Read/Write
(Write only if
FSETEN
bit set)
DIS3
ATMPOFF
Turn off Disable 3.3V
automatic reg. (device
external
requires
temp scan
external
3.3V)
08H
Write Enable
Read/Write
FSETEN
Enable
Feature
Set writes
09H:FFH
Reserved
NA
OCCV0
TMP3ON
Turn on
Temp3V
Short Circuit Discharge
Turn off
Threshold Voltage
automatic
SCD control
Overcurrent Discharge
Time-out
OCCT1
SCLONG
Long Shortcircuit delay
CTDIV
Divide
charge
time by 32
DTDIV
Divide
discharge
time by 64
DISXTSD
Disable
external
thermal
shutdown
DISITSD
Disable
internal
thermal
shutdown
POR
DISWKUP
Force POR Disable
WKUP pin
UFLG3
UFLG2
Reserved
CHSETEN DISSETEN
User Flag 3 User Flag 2
Enable
Enable
Charge Set Discharge
Set writes
writes
OCCT0
Overcurrent Charge
Time-out
Reserved
WKPOL
Wake Up
Polarity
Reserved
RESERVED
NOTES:
8. A “1” written to a control or configuration bit causes the action to be taken. A “1” read from a status bit indicates that the condition exists.
9. “Reserved” indicates that the bit or register is reserved for future expansion. When writing to addresses 2, 3, 4, and 8: write a reserved bit with
the value “0”. Do not write to reserved registers at addresses 09H through FFH. Ignore reserved bits that are returned in a read operation.
10. These status bits are automatically cleared when the register is read. All other status bits are cleared when the condition is cleared.
11. This SLEEP bit is cleared on initial power up, by the WKUP pin going high (when WKPOL = ”1”) or by the WKUP pin going low (when
WKPOL = ”0”), and by writing a “0” to the location with an I2C command.
12. When the automatic responses are enabled, these bits are automatically reset by hardware when an overcurrent or short circuit condition turns
off the FETs. At all other times, an I2C write operation controls the output to the respective FET and a read returns the current state of the FET
drive output circuit (though not the actual voltage at the output pin.)
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ISL9208
Status Registers
TABLE 2. CONFIG/OP STATUS REGISTER (ADDR: 00H)
BIT
FUNCTION
DESCRIPTION
7
RESERVED
Reserved for future expansion.
6
RESERVED
Reserved for future expansion.
5
SA
Single AFE
Indicates the device is an ISL9208. This bit is set in the chip and cannot be changed.
4
WKUP
This bit is set and reset by hardware.
Wakeup pin status When ‘WKPOL’ is HIGH:
’WKUP’ HIGH = WKUP pin > Threshold voltage
‘WKUP’ LOW = WKUP pin < Threshold voltage
When ‘WKPOL’ is LOW:
’WKUP’ HIGH = WKUP pin < Threshold voltage
‘WKUP’ LOW = WKUP pin > Threshold voltage
3
RESERVED
Reserved for future expansion.
2
RESERVED
Reserved for future expansion.
1
RESERVED
Reserved for future expansion.
0
RESERVED
Reserved for future expansion.
TABLE 3. OPERATING STATUS REGISTER (ADDR: 01H)
BIT
FUNCTION
DESCRIPTION
7
RESERVED
Reserved for future expansion.
6
RESERVED
Reserved for future expansion.
5
XOT
Ext Over-temp
This bit is set to “1” when the external thermistor indicates an over-temperature condition. If the temperature
condition has cleared, this bit is reset when the register is read.
4
IOT
Int Over-temp
This bit is set to “1” when the internal thermistor indicates an over-temperature condition. If the temperature condition
has cleared, this bit is reset when the register is read.
3
LDFAIL
When the function is enabled, this bit is set to “1” by hardware when a discharge overcurrent or short circuit condition
Load Fail (VMON) occurs and the load remains heavy. When the load fail condition is cleared or under a light load, the bit is reset when
the register is read.
2
DSC
Short Circuit
This bit is set by hardware when a short circuit condition occurs during discharge. When the discharge short circuit
condition is removed, the bit is reset when the register is read.
1
DOC
Discharge OC
This bit is set by hardware when an overcurrent condition occurs during discharge. When the discharge overcurrent
condition is removed, the bit is reset when the register is read.
0
COC
Charge OC
This bit is set by hardware when an overcurrent condition occurs during charge. When the charge overcurrent
condition is removed, the bit is reset when the register is read.
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ISL9208
Control Registers
TABLE 4. CELL BALANCE CONTROL REGISTER (ADDR: 02H)
CONTROL REGISTER BITS
BIT 7
CB7ON
BIT 6
CB6ON
BIT 5
CB5ON
BIT 4
CB4ON
BIT 3
CB3ON
BIT 2
CB2ON
BIT 1
CB1ON
x
x
x
x
x
x
1
Cell1 ON
x
x
x
x
x
x
0
Cell1 OFF
x
x
x
x
x
1
x
Cell2 ON
x
x
x
x
x
0
x
Cell2 OFF
x
x
x
x
1
x
x
Cell3 ON
x
x
x
x
0
x
x
Cell3 OFF
x
x
x
1
x
x
x
Cell4 ON
x
x
x
0
x
x
x
Cell4 OFF
x
x
1
x
x
x
x
Cell5 ON
x
x
0
x
x
x
x
Cell5 OFF
x
1
x
x
x
x
x
Cell6 ON
x
0
x
x
x
x
x
Cell6 OFF
1
x
x
x
x
x
x
Cell7 ON
0
x
x
x
x
x
x
Cell7 OFF
Bit 0
RESERVED
BALANCE
Reserved for future expansion
TABLE 5. ANALOG OUT CONTROL REGISTER (ADDR: 03H)
BITS
FUNCTION
DESCRIPTION
7
UFLG1
User Flag 1
General purpose flag usable by microcontroller software. This bit is battery backed up, even
when RGO turns off.
6
UFLG0
User Flag 0
General purpose flag usable by microcontroller software. This bit is battery backed up, even
when RGO turns off.
5:4
RESERVED
Reserved for future expansion
Bit 3
AO3
Bit 2
AO2
Bit 1
AO1
Bit 0
AO0
0
0
0
0
No Output (low power state)
0
0
0
1
VCELL1
0
0
1
0
VCELL2
0
0
1
1
VCELL3
0
1
0
0
VCELL4
0
1
0
1
VCELL5
0
1
1
0
VCELL6
0
1
1
1
VCELL7
1
0
0
0
External Temperature
1
0
0
1
Internal Temperature
1
x
1
x
RESERVED
1
1
x
x
RESERVED
15
Output Voltage
FN6446.0
February 16, 2007
ISL9208
Configuration Registers
The device is configured for specific application
requirements using the Configuration Registers. The
configuration registers consist of SRAM memory.
This memory is powered by the RGO output. In a sleep
condition, an internal switch converts power for the contents
of these registers from RGO to the VCELL1 input.
TABLE 6. FET CONTROL REGISTER (ADDR: 04H)
BIT
FUNCTION
DESCRIPTION
7
SLEEP
Force Sleep
Setting this bit to “1” forces the device to go into a sleep condition. This turns off both FET
outputs, the cell balance outputs and the voltage regulator. This also resets the CFET, DFET,
and CB7ON:CB1ON bits. The SLEEP bit is automatically reset to “0” when the device wakes
up. This bit does not reset the AO3:AO0 bits.
6
LDMONEN
Turn on VMON connection
Writing a “1” to this bit turns on the VMON circuit. Writing a “0” to this bit turns off the VMON
circuit. As such, the microcontroller has full control of the operation of this circuit.
5:2
RESERVED
1
CFET
Setting this bit to “1” turns on the charge FET.
Setting this bit to “0” turns off the charge FET.
This bit is automatically reset in the event of a charge overcurrent condition, unless the
automatic response is disabled by the DENOCC bit.
0
DFET
Setting this bit to “1” turns on the discharge FET.
Setting this bit to “0” turns off the discharge FET.
This bit is automatically reset in the event of a discharge overcurrent or discharge short circuit
condition, unless the automatic response is disabled by the DENOCD or DENSCD bits.
Reserved for future expansion.
TABLE 7. DISCHARGE SET CONFIG REGISTER (ADDR: 05H)
SETTING
FUNCTION
When set to ‘0’, a discharge overcurrent condition automatically turns off the FETs.
When set to ‘1’, a discharge overcurrent condition will not automatically turn off the FETs.
In either case, this condition sets the DOC bit, which also turns on the TEMP3V output.
Bit 7
DENOCD
Turn off automatic OC
discharge control
Bit 6
OCDV1
Bit 5
OCDV0
0
0
VOCD = 0.10V
0
1
VOCD = 0.12V
1
0
VOCD = 0.14V
VOCD = 0.16V
1
1
Bit 4
DENSCD
Turn off automatic SC
discharge control
Bit 3
SCDV1
Bit 2
SCDV0
Overcurrent Discharge Voltage Threshold
When set to ‘0’, a discharge short circuit condition turns off the FETs.
When set to ‘1’, a discharge short circuit condition will not automatically turn off the FETs.
In either case, the condition sets the SCD bit, which also turns on the TEMP3V output.
Short Circuit Discharge Voltage Threshold
0
0
VSCD = 0.20V
0
1
VSCD = 0.35V
1
0
VSCD = 0.65V
1
1
VSCD = 1.20V
Bit 1
OCDT1
Bit 0
OCDT0
Overcurrent Discharge Time-out
0
0
tOCD = 128ms (2ms if DTDIV=1)
0
1
tOCD = 256ms (4ms if DTDIV=1)
1
0
tOCD = 512ms (8ms if DTDIV=1)
1
1
tOCD = 1024ms (16ms if DTDIV=1)
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February 16, 2007
ISL9208
TABLE 8. CHARGE/TIME SCALE CONFIG REGISTER (ADDR: 06H)
SETTING
FUNCTION
When set to ‘0’, a charge overcurrent condition automatically turns off the FETs.
When set to ‘1’, a charge overcurrent condition will not automatically turn off the FETs.
In either case, this condition sets the COC bit, which also turns on the TEMP3V output.
Bit 7
DENOCC
Turn off automatic OC charge
control
Bit 6
OCCV1
Bit 5
OCCV0
0
0
VOCD = 0.10V
0
1
VOCD = 0.12V
1
0
VOCD = 0.14V
1
1
VOCD = 0.16V
Bit 4
SCLONG
Short circuit long delay
Bit 3
CTDIV
Divide charge time by 32
Bit 2
DTDIV
Divide discharge time by 64
Bit 1
OCCT1
Bit 0
OCCT0
0
0
tOCC = 64ms (2ms if CTDIV=1)
0
1
tOCC = 128ms (4ms if CTDIV=1)
1
0
tOCC = 256ms (8ms if CTDIV=1)
1
1
tOCC = 512ms (16ms if CTDIV=1)
Overcurrent Charge Voltage Threshold
When this bit is set to ‘0’, a short circuit needs to be in effect for 100us before a shutdown
begins. When this bit is set to ‘1’, a short circuit needs to be in effect for 8ms before a
shutdown begins.
When set to “1”, the charge overcurrent delay time is divided by 32.
When set to “0”, the charge overcurrent delay time is divided by 1.
When set to “1”, the discharge overcurrent delay time is divided by 64.
When set to “0”, the discharge overcurrent delay time is divided by 1.
Overcurrent Charge Time-out
TABLE 9. FEATURE SET CONFIGURATION REGISTER (ADDR: 07H)
BIT
FUNCTION
DESCRIPTION
7
ATMPOFF
When set to ‘1’ this bit disables the automatic temperature scan. When set to ‘0’, the temperature
Turn off automatic external temp scan is turned on for 4ms in every 512ms.
6
DIS3
Disable 3.3V reg
Setting this bit to “1” disables the internal 3.3V regulator. Setting this bit to “1” requires that there
be an external 3.3V regulator connected to the RGO pin.
5
TMP3ON
Turn on Temp 3.3V
Setting this bit to “1” turns ON the TEMP3V output to the external temperature sensor. The
output will remain on as long as this bit remains “1”.
4
DISXTSD
Disable external thermal shutdown
Setting this bit to “1” disables the automatic shutdown of the cell balance and power FETs in
response to an external over-temperature condition. While the automatic response is disabled,
the XOT flag is set so the microcontroller can initiate a shutdown based on the XOT flag.
3
DISITSD
Disable internal thermal shutdown
Setting this bit to “1” disables the automatic shutdown of the cell balance and power FETs in
response to an internal over-temperature condition. While the automatic response is disabled,
the IOT flag is set so the microcontroller can initiate a shutdown based on the IOT flag.
2
POR
Force POR
Setting this bit to “1” forces a POR condition. This resets all internal registers to zero.
1
DISWKUP
Disable WKUP pin
Setting this bit to “1” disables the WKUP pin function.
CAUTION: Setting this pin to ‘1’ prevents a wake up condition. If the device then goes to sleep,
it cannot be waken without a communication link that resets this bit, or by power cycling the
device.
0
WKPOL
Wake Up Polarity
Setting this bit to “1” sets the device to wake up on a rising edge at the WKUP pin.
Setting this bit to “0” sets the device to wake up on a falling edge at the WKUP pin.
17
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February 16, 2007
ISL9208
.
TABLE 10. WRITE ENABLE REGISTER (ADDR: 08H)
BIT
FUNCTION
DESCRIPTION
7
FSETEN
When set to “1”, allows writes to the Feature Set register. When set to “0”, prevents writes to the Feature
Enable discharge set writes Set register (Addr: 07H). Default on initial power up is “0”.
6
CHSETEN
Enable charge set writes
5
DISSETEN
When set to “1”, allows writes to the Discharge Set register (Addr: 05H). When set to “0”, prevents writes
Enable discharge set writes to the Feature Set register. Default on initial power up is “0”.
4
UFLG3
User Flag 3
General purpose flag usable by microcontroller software. This bit is battery backed up, even when RGO
turns off.
3
UFLG2
User Flag 3
General purpose flag usable by microcontroller software. This bit is battery backed up, even when RGO
turns off.
2
RESERVED
Reserved for future expansion.
1
RESERVED
Reserved for future expansion.
0
RESERVED
Reserved for future expansion.
When set to “1”, allows writes to the Charge Set register. When set to “0”, prevents writes to the Feature
Set register (Addr: 06H). Default on initial power up is “0”.
Device Description
System Power Up/Power Down
Design Theory
Instructed by the microcontroller, the ISL9208 performs cell
voltage monitoring and cell balancing operations,
overcurrent and short circuit monitoring with automatic pack
shutdown using built-in selectable time delays, and
automatic turn off of the power FETs and cell balancing FETs
in an over-temperature condition. All automatic functions of
the ISL9208 can be turned off and the microcontroller can
manage the operations through software.
Battery Connection
The ISL9208 supports packs of 5 to 7 series connected
Li-ion cells. Connection guidelines for each cell combination
are shown in Figure 1.
The ISL9208 powers up when the voltages on VCELL1,
VCELL2, VCELL3, and VCC all exceed their POR threshold.
At this time, the ISL9208 wakes up and turns on the RGO
output.
RGO provides a regulated 3.3VDC ±10% voltage at pin
RGO. It does this by using a control voltage on the RGC pin
to drive an external NPN transistor (See Figure 2.) The
transistor should have a beta of at least 70 to provide ample
current to the device and external circuits and should have a
VCE of greater than 30V (preferably 50V). The voltage at the
emitter of the NPN transistor is monitored and regulated to
3.3V volts by the control signal RGC. RGO also powers most
of the ISL9208 internal circuits. A 500Ω resistor is
recommended in the collector of the NPN transistor to
minimize initial current surge when the regulator turns on.
7 CELLS
6 CELLS
5 CELLS
VCELL7
VCELL7
VCELL7
CB7
VCELL6
CB7
VCELL6
CB7
VCELL6
CB6
VCELL5
CB6
VCELL5
CB6
VCELL5
CB5
VCELL4
CB5
VCELL4
CB5
VCELL4
CB4
VCELL3
CB4
VCELL3
CB4
VCELL3
CB3
VCELL2
CB3
VCELL2
CB3
VCELL2
CB2
VCELL1
CB2
VCELL1
CB2
VCELL1
RGC
CB1
VSS
CB1
VSS
CB1
VSS
RGO
Once powered up, the device remains in a wake up state
until put to sleep by the microcontroller (typically when the
cells drop too low in voltage) or until the VCELL1, VCELL2,
VCELL3, or VCC voltages drop below their POR threshold.
VCC
500
3.3V
VSS
Note: Multiple cells can be connected in parallel
GND
FIGURE 1. BATTERY CONNECTION OPTIONS
FIGURE 2. VOLTAGE REGULATOR CIRCUITS
18
FN6446.0
February 16, 2007
ISL9208
WKUP Pin Operation
There are two ways to design a wake up of the ISL9208. In
an active LOW connection (WKPOL = “0” - default), the
device wakes up when a charger is connected to the pack.
This pulls the WKUP pin low when compared to a reference
based on the VCELL1 voltage. In an active HIGH connection
(WKPOL = ‘1’) the device wakes up when the WKUP pin is
pulled high by a connection through an external switch.
ISL9208
WKUP
WKUP
(STATUS)
5V
230k*
WAKE UP
CIRCUITS
WKPOL
(CONTROL)
VCELL1
VSS
* Internal resistor
only connected when
WKPOL=1.
FIGURE 3. WAKE UP CONTROL CIRCUITS
Protection Functions
In the default recommended condition, the ISL9208
automatically responds to discharge overcurrent, discharge
short circuit, charge overcurrent, internal over-temperature,
and external over-temperature conditions. The designer can
set optional over-ride conditions that allow the response to
be dictated by the microcontroller. These are discussed
below.
OVERCURRENT SAFETY FUNCTIONS
The ISL9208 continually monitors the discharge current by
monitoring the voltage at the CSENSE and DSENSE pins. If
that voltage exceeds a selected value for a time exceeding a
selected delay, then the device enters an overcurrent or short
circuit protection mode. In these modes, the ISL9208
automatically turns off both power FETs and hence prevents
current from flowing through the terminals P+ and P-.
The voltage thresholds and the response times of the
overcurrent protection circuits are selectable for discharge
overcurrent, charge overcurrent, and discharge short circuit
conditions. The specific settings are determined by bits in
the “DISCHARGE SET CONFIG REGISTER (ADDR: 05H)”
on page 16, and “CHARGE/TIME SCALE CONFIG
REGISTER (ADDR: 06H)” on page 17. (See also
“REGISTERS” on page 13.)
19
In an overcurrent condition, the ISL9208 automatically turns off
the voltage on CFET and DFET pins. The DFET output drives
the discharge FET gate low, turning off the FET quickly. The
CFET output turns off and allows the gate of the charge FET to
be pulled low through a resistor.
By turning off the FETs the ISL9208 prevents damage to the
battery pack caused by excessive current into or out of to the
cells (as in the case of a faulty charger or short circuit
condition).
When the ISL9208 detects a discharge overcurrent condition,
both power FETs are turned off and the DOC bit is set. (When
the FETs are turned off, the DFET and CFET bits are also
reset.) The automatic response to overcurrent during discharge
is prevented by setting the DENOCD bit to “1”. The external
microcontroller can turn on the FETs at any time to recover from
this condition, but it would usually turn on the load monitor
function (by setting the LDMONEN bit) and monitor the LDFAIL
bit to detect that the overcurrent condition has been removed.
When the ISL9208 detects a discharge short circuit condition,
both power FETs are turned off and DSC bit is set. (When the
FETs are turned off, the DFET and CFET bits are also reset.)
The automatic response to short circuit during discharge is
prevented by setting the DENSCD bit to “1”. The external
microcontroller can turn on the FETs at any time to recover from
this condition, but it would usually turn on the load monitor
function (by setting the LDMONEN bit) and monitor the LDFAIL
bit to detect that the overcurrent condition has been removed.
When the ISL9208 detects a charge overcurrent condition, both
power FETs are turned off and COC bit is set. (When the FETs
are turned off, the DFET and CFET bits are also reset.) The
automatic response to overcurrent during discharge is
prevented by setting the DENOCC bit to “1”. The external
microcontroller can turn on the FETs at any time to recover from
this condition, but it would usually wait to do this until the cell
voltages are not over charged and that the overcurrent
condition has been removed. Or, the microcontroller could wait
until the pack is removed from the charger and then
re-attached.
An alternative method of providing the protection function, if
desired by the designer, is to turn off the automatic safety
response. In this case, the ISL9208 devices still monitor the
conditions and set the status bits, but take no action in
overcurrent or short circuit conditions. Safety of the pack
depends, instead, on the microcontroller to send commands to
the ISL9208 to turn off the FETs.
To facilitate a microcontroller response to an overcurrent
condition, especially if the microcontroller is in a low power
state, a charge overcurrent flag (COC), a discharge overcurrent
flag (DOC), or the short circuit flag (DSC) being set causes the
ISL9208 TEMP3V output to turn on and pull high. (See
Figure 5.) This output can be used as an external interrupt by
the microcontroller to wake-up quickly to handle the overcurrent
condition.
FN6446.0
February 16, 2007
ISL9208
P+
VSS
RL
combination of the load resistor, an external adjustment
resistor (R1), and the internal load monitor resistor form a
voltage divider. R1 is chosen so that when the load is
released to a sufficient level, the LDFAIL condition is reset.
OPEN
OVER-TEMPERATURE SAFETY FUNCTIONS
P-
POWER FETs
R1
ISL9208
VMON
VREF
External Temperature Monitoring
The external temperature is monitored by using a voltage
divider consisting of a fixed resistor and a thermistor. This
divider is powered by the ISL9208 TEMP3V output. This
output is normally controlled so it is on for only short periods
to minimize current consumption.
Without microcontroller intervention, and in the default state,
the ISL9208 provides an automatic temperature scan. This
scan circuit repeatedly turns on TEMP3V output (and the
external temperature monitor) for 4ms out of every 512ms.
In this way, the external temperature is monitored even if the
microcontroller is asleep.
LDFAIL
= 1 if VMON >VVMONH
= 0 if VMON ≤ VVMONL
LDMONEN
VSS
FIGURE 4. LOAD MONITOR CIRCUIT
LOAD MONITORING
The load monitor function in the ISL9208 (see Figure 4) is
used primarily to detect that the load has been removed
following an overcurrent or short circuit condition during
discharge. This can be used in a control algorithm to prevent
the FETs from turning on while the overload or short circuit
condition remains.
The load monitor can also be used by the microcontroller
algorithms after an undervoltage condition on any cells
causes the FETs to turn off. Use of the load monitor prevents
the FETs from turning on while the load is still present. This
minimizes the possible “oscillations” that can occur when a
load is applied in a low capacity pack. It can also be part of a
system protection mechanism to prevent the load from
turning on automatically - i.e. some action must be taken
before the pack is again turned on.
The load monitor circuit can be turned on or off by the
microcontroller. It is normally turned off to minimize current
consumption. It must be activated by the external
microcontroller for it to operate. The circuit works by
internally connecting the VMON pin to VSS through a
resistor. The circuit operates shown as in Figure 4.
In a typical pack operation, when an overcurrent or short
circuit event happens, the DFET turns off, opening the
battery circuit to the load. At this time, the RL is small and
the load monitor is initially off. In this condition, the voltage at
VMON rises to nearly the pack voltage.
Once the power FETs turn off, the microcontroller activates
the load monitor by setting the LDMONEN bit. This turns on
an internal FET that adds a pull down resistor to the load
monitor circuit. While still in the overload condition the
20
When the TEMP3V output turns on, the ISL9208 waits 1ms
for the temperature reading to stabilize, then compares the
external temperature voltage with an internal voltage divider
that is set to TEMP3V/13. When the thermistor voltage is
below the reference threshold after the delay, an external
temperature fail condition exists. To set the external overtemperature limit, set the value of RX resistor to the 12 times
the resistance of the thermistor at the over-temp threshold.
The TEMP3V output pin also turns on when the
microcontroller sets the AO3:AO0 bits to select that the
external temperature voltage. This causes the TEMPI
voltage to be placed on AO and activates (after 1ms) the
over-temperature detection. As long as the AO3:AO0 bits
point to the external temperature, the TEMP3V output
remains on.
Because of the manual scan of the temperature, it may be
desired to turn off the automatic scan, although they can be
used at the same time without interference. To turn off the
automatic scan, set the ATMPOFF bit.
The microcontroller can over-ride both the automatic
temperature scan and the microcontroller controlled
temperature scan by setting the TEMP3ON configuration bit.
This turns on the TEMP3V output to keep the temperature
control voltage on all the time, for a continuous monitoring of
an over-temperature condition. This likely will consume a
significant amount of current, so this feature is usually used
for special or test purposes.
Protection
As a default, when the ISL9208 detects an internal or
external over-temperature condition, the FETs are turned off,
the cell balancing function is disabled, and the IOT bit or
XOT bit (respectively) is set.
FN6446.0
February 16, 2007
ISL9208
4ms
TMP3ON
RGO
AO3:AO0
TO
µC
DECODE
EXT TEMP
12R
TEMP3V
VSS (ON)
MUX
AO
RX
TEMPI
1ms
DELAY
Analog Multiplexer Selection
The ISL9208 devices can be used to externally monitor
individual battery cell voltages and temperatures. Each
quantity can be monitored at the analog output pin (AO). The
desired voltage is selected using the I2C interface and the
AO3:AO0 bits. See Figure 6.
ATMPOFF
R
The automatic response to an internal over-temperature is
prevented by setting the DISITSD bit to “1”. The automatic
response to an external over-temperature is prevented by
setting the DISXTSD bit to “1”. In either case, it is important
for the microcontroller to monitor the internal and external
temperature to protect the pack and the electronics in an
over-temperature condition.
CHARGE OC
DISCHARGE OC
DISCHARGE SC
In the event of an automatic over-temperature condition, cell
balancing is prevented and FETs are held off until the
temperature drops back below the temperature recovery
threshold. During this temperature shutdown period, the
microcontroller can monitor the internal temperature through
the analog output pin (AO), but any writes to the CFET bit,
DFET bit, or cell balancing bits are ignored
OSC
ISL9208
I2C
OVERCURRENT
PROTECTION CIRCUITS
508ms
I2C
REGISTERS
Turning off the FETs in the event of an over-temperature
condition prevents continued discharge or charge of the cells
when they are over heated. Turning off the cell balancing in
the event of an over-temperature condition prevents damage
to the IC in the event too many cells are being balanced,
causing too much power dissipation in the ISL9208.
EXTERNAL
TEMP
MONITOR
XOT
VSS
TEMP FAIL
INDICATOR
FIGURE 5. EXTERNAL TEMPERATURE MONITORING
AND CONTROL
VOLTAGE MONITORING
Since the voltage on each of the Li-ion Cells are normally
higher than the regulated supply voltage, and since the
voltages on the upper cells is much higher than is tolerated
by a microcontroller, it is necessary to both level shift and
divide the voltage before it can be monitored by the
microcontroller or an external A/D converter. To get into the
voltage range required by the external circuits, the voltage
level shifter divides the cell voltage by 2 and references it to
VSS. Therefore, a Li-ion cell with a voltage of 4.2V becomes
a voltage of 2.1V on the AO pin.
SCL
SDA
I2C
A similar operation occurs when monitoring the internal
temperature through the AO output, except there is no
external “calibration” of the voltage associated with the
internal temperature. For the internal temperature
monitoring, the voltage at the output is linear with respect to
temperature. (See the Operating Specifications for
information about the output voltage at +25°C and the output
slope relative to temperature.).
21
VC7/VCC
LEVEL
SHIFT
VCELL6
LEVEL
SHIFT
VCELL2
LEVEL
SHIFT
VCELL1
REGS
AO3:AO0
DECODE
TEMPERATURE MONITORING
The voltage representing the external temperature applied at
the TEMPI terminal is directed to the AO terminal through a
MUX, as selected by the AO control bits (see Figures 5 and
6.) The external temperature voltage is not divided by 2 as
are the cell voltages. Instead it is a direct reflection of the
voltage at the TEMPI pin.
LEVEL
SHIFT
AO
2
MUX
VSS
EXT TEMP.
TEMPI
MUX
INT
TEMP
FIGURE 6. ANALOG OUTPUT MONITORING DIAGRAM
FN6446.0
February 16, 2007
ISL9208
Cell Balancing
differential between the minimum pack voltage and
maximum charger voltage does not exceed 22V.
OVERVIEW
A typical ISL9208 Li-ion battery pack consists of five to
seven cells in series, with one or more cells in parallel. This
combination gives both the voltage and power necessary for
power tool, e-bikes, electric wheel chairs, portable medical
equipment, and battery powered industrial applications.
While the series/parallel combination of Li-ion cells is
common, the configuration is not as efficient as it could be,
because any capacity mismatch between series-connected
cells reduces the overall pack capacity. This mismatch is
greater as the number of series cells and the load current
increase. Cell balancing techniques increase the capacity,
and the operating time, of Li-ion battery packs.
DEFINITION OF CELL BALANCING
Cell balancing is defined as the application of differential
currents to individual cells (or combinations of cells) in a
series string. Normally, of course, cells in a series string
receive identical currents. A battery pack requires additional
components and circuitry to achieve cell balancing. For the
ISL9208 devices, the only external components required are
balancing resistors.
CELL BALANCE OPERATION
Cell balancing is accomplished through a microcontroller
algorithm. This algorithm compares the cell voltages (a
representation of the pack capacity) and turns on balancing
for the cells that have the higher voltages. There are many
parameters that should be considered when writing this
algorithm. An example cell balancing algorithm is available
in the ISL9208EVAL1Z evaluation kit.
The microcontroller turns on the specific cell balancing by
setting a bit in the Cell Balance Register. Each bit in the
register corresponds to one cell’s balancing control. When
the bit is set, an internal cell balancing FET turns on. This
shorts an external resistor across the specified cell. The
maximum current that can be drawn from (or bypassed
around) the cell is 200mA. This current is set by selecting
the value of the external resistor. Figure 7 shows an example
with a 200mA (maximum) balancing current.
With lower balancing current, more balancing FETs can be
turned on at once, without exceeding the device power
dissipation limits or generating excessive balancing current
that will heat the external resistor.
External VMON/CFET protection mechanisms
When there is a single charge/discharge path, a blocking
diode is recommended in the VMON to P- path in ISL9208
solution. See D1 in Figure 8. This diode is to protect against
a negative voltage on the VMON pin that can occur when the
FETs are off and the charger connects to the pack. This
diode is not needed when there is a separate charge and
discharge path, because the voltages on P- (discharge) are
likely always positive. The diode also is not needed if the
22
When the pack is designed with a single set of
charge/discharge FETs, the ISL9208 CFET pin should be
protected in the event of an over-current or short circuit
shutdown. When this happens, the FET opens suddenly.
The flyback voltage from the motor windings could exceed
the maximum input voltage on the CFET pin. So, it is
recommended that an additional external series diode be
placed between the CFET pin of the ISL9208 and the gate of
the Charge FET. See Diode D3 in Figure 8. This will reduce
the CFET gate voltage, but not significantly.
Finally, to protect the Charge FET itself in the event of a
large negative voltage on the Pack- pin, zener diode D4 is
added. The large negative voltage can occur when the P- pin
goes significantly negative, while the CFET pin is being
internally clamped at VSS. The zener voltage of D4 should
be less than the VGS(max) specification of the FET.
VC7/VCC
ISL9208
21Ω
1W
CB7
200mA
CELL
BALANCE
CONTROL
(REG 02H)
7 6 5 4 3 2 1
VCELL1
21Ω
1W
CB1
VSS
FIGURE 7. CELL BALANCING CONTROL EXAMPLE WITH
200mA BALANCING CURRENT
PACK+
PACKD1
VMON
10M
ISL9208
D4
1M
D3
CFET
DFET
FIGURE 8. USE OF A DIODES FOR PROTECTING THE CFET
AND VMON PINS.
FN6446.0
February 16, 2007
ISL9208
User Flags
The ISL9208 contains four flags in the register area that the
microcontroller can use for general purpose indicators.
These bits are designated UFLG3, UFLG2, UFLG1, and
UFLG0. The microcontroller can set or reset these bits by
writing into the appropriate register.
The user flag bits are battery backed up, so the contents
remain even after exiting a sleep mode. However, if the
microcontroller sets the POR bit to force a power on reset, all
of the user flags will also be reset. In addition, if the voltage
on cell1 ever drops below the POR voltage, the contents of
the user flags (as well as all other register values) could be
lost.
Serial Interface
The device responds with an acknowledge after recognition
of a start condition and the correct slave byte. If a write
operation is selected, the device responds with an
acknowledge after the receipt of each subsequent eight bits.
The device acknowledges all incoming data and address
bytes, except for the slave byte when the contents do not
match the device’s internal slave address.
In the read mode, the device transmits eight bits of data,
releases the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the device will
continues to transmit data. The device terminates further
data transmissions if an acknowledge is not detected. The
master must then issue a stop condition to return the device
to Standby mode and place the device into a known state
INTERFACE CONVENTIONS
The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the slave.
The master always initiates data transfers, and provides the
clock for both transmit and receive operations. Therefore,
the ISL9208 devices operate as slaves in all applications.
When sending or receiving data, the convention is the most
significant bit (MSB) is sent first. So, the first address bit sent
is bit 7.
SCL
SDA
DATA
STABLE
DATA
CHANGE
DATA
STABLE
FIGURE 9. VALID DATA CHANGES ON I2C BUS
.
CLOCK AND DATA
Data states on the SDA line can change only while SCL is
LOW. SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions. See Figure 9.
SCL
SDA
START CONDITION
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
start condition and will not respond to any command until
this condition has been met. See Figure 10.
START
STOP
FIGURE 10. I2C START AND STOP BITS
STOP CONDITION
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA when SCL is
HIGH. The stop condition is also used to place the device
into the Standby power mode after a read sequence. A stop
condition is only issued after the transmitting device has
released the bus. See Figure 10.
ACKNOWLEDGE
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM
TRANSMITTER
DATA OUTPUT
FROM RECEIVER
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, releases the bus after transmitting eight
bits. During the ninth clock cycle, the receiver pulls the SDA
line LOW to acknowledge that it received the eight bits of
data. See Figure 11.
23
START
ACKNOWLEDGE
FIGURE 11. ACKNOWLEDGE RESPONSE FROM
RECEIVER
FN6446.0
February 16, 2007
ISL9208
WRITE OPERATIONS
Register Protection
For a write operation, the device requires a slave byte and
an address byte. The slave byte specifies the particular
device on the I2C bus that the master is writing to. The
address specifies one of the registers in that device. After
receipt of each byte, the device responds with an
acknowledge, and awaits the next eight bits from the master.
After the acknowledge, following the transfer of data, the
master terminates the transfer by generating a stop
condition. See Figure 12.
The Discharge Set, Charge Set, and Feature Set
configuration registers are write protected on initial power
up. In order to write to these registers it is necessary to set a
bit to enable each one. These write enable bits are in the
Write Enable register (Address 08H).
Read operations are initiated in the same manner as write
operations with the exception that the last bit of the slave
byte is set to one. After the device acknowledges the register
address, it sends out one bit of data for each master clock.
After sending eight bits to the master, the master sends a
NACK (Not acknowledge) to the device, then sends a stop
bit. See Figure 13.
After sending the eighth data bit to the master, the device
automatically increments its internal address pointer. So the
master, instead of sending the stop bit, can send additional
clocks to read the contents of the next register-without
sending another slave and address byte. After reading from
address 9, the device address wraps around to 0, so
continued master clocks would allow an indefinite number of
reads from the device.
The microcontroller can reset these bits back to zero to
prevent inadvertent writes that change the operation of the
pack.
Operation State Machine
Figure 14 shows a device state machine which defines how
the ISL9208 responds to various conditions.
SIGNALS
FROM THE
MASTER
Read Operations
Write the DISSETEN bit (Addr 8:bit 5) to “1” to enable
changes to the data in the Feature Set register (Address 5).
SDA BUS
SLAVE
BYTE
REGISTER
ADDRESS
S
T
O
P
DATA
0 1 0 1 0 0 0 0
A
C
K
A
C
K
A
C
K
ISL9208: SLAVE BYTE = 50H
FIGURE 12. WRITE SEQUENCE
SDA BUS
SIGNALS
FROM THE
SLAVE
.
S
T
A
R
T
SIGNALS
FROM THE
SLAVE
After receiving the acknowledge after the data byte, the
device automatically increments the address. So, before
sending the stop bit, the master may send additional data to
the device without re-sending the slave and address bytes.
After writing to address 0AH, the address “wraps around” to
address 0. Do not continue to write to addresses higher than
address 08H, since these addresses access registers that
are reserved. Writing to these locations can result in
unexpected device operation.
Write the CHSETEN bit (Addr 8:bit 6) to “1” to enable
changes to the data in the Feature Set register (Address 6).
SIGNALS
FROM THE
MASTER
When receiving data from the master, the value in the data
byte is transferred into the register specified by the address
byte on the falling edge of the clock following the 8th data bit.
Write the FSETEN bit (Addr 8:bit 7) to “1” to enable changes
to the data in the Feature Set register (Address 7).
S
T
A
R
T
SLAVE
BYTE
N
A
C
K
REGISTER
ADDRESS
S
T
O
P
0 1 0 1 0 0 0 1
A
C
K
A
C
K
DATA
ISL9208: SLAVE BYTE = 51H
FIGURE 13. READ SEQUENCE
24
FN6446.0
February 16, 2007
ISL9208
POWER FAILS AND ONE OR MORE OF THE SUPPLIES, VCC, VCELL1, VCELL2,
AND VCELL3 DO NOT MEET MINIMUM VOLTAGE REQUIREMENTS
POWER DOWN STATE
I2C INTERFACE IS DISABLED. BIASING IS
DISABLED. ALL REGISTERS SET TO DEFAULT
VALUES (ALL “0”)
Power is applied and all of the supplies, VCC, VCELL1, VCELL2,
and VCELL3 meet minimum voltage requirements
POWER UP STATE
I2C INTERFACE IS ENABLED. BIASING IS
ENABLED. VOLTAGE REGULATOR IS
ENABLED.
MAIN OPERATING STATE
SLEEP STATE
VOLTAGE REGULATOR IS ON
VOLTAGE REGULATOR IS OFF
LOGIC AND REGISTERS ARE POWERED
BY RGO
BIASING IS OFF
SLEEP bit is set to ‘1’
CFET, DFET, CELL BALANCING OUTPUTS
ARE ALL OFF. (REQUIRE AN EXTERNAL
COMMAND TO TURN ON)
CHARGE AND DISCHARGE CURRENT
PROTECTION CIRCUITS AND
TEMPERATURE PROTECTION CIRCUITS
ARE ACTIVE (DEFAULT). OVERCURRENT
CONDITIONS FORCE POWER FETS TO
TURN OFF. OVER-TEMPERATURE
CONDITIONS FORCE POWER FETS AND
CELL BALANCE OUTPUTS TO TURN OFF.
LOGIC AND REGISTERS ARE POWERED
BY VCELL1
CFET, DFET, CELL BALANCING OUTPUTS
ARE ALL OFF.
WKUP goes above or below
threshold (edge triggered).
Or, SLEEP bit is set to ‘0’
CHARGE AND DISCHARGE CURRENT
PROTECTION CIRCUITS ALL OFF.
VOLTAGE AND TEMPERATURE
MONITORING CIRCUITS ARE OFF.
I2C COMMUNICATION IS ACTIVE (IF
VCELL1 VOLTAGE IS HIGH ENOUGH TO
OPERATE WITH THE EXTERNAL DEVICE.)
VOLTAGE AND TEMPERATURE
MONITORING CIRCUITS ARE AWAITING
EXTERNAL CONTROL.
FIGURE 14. DEVICE OPERATION STATE MACHINE
25
FN6446.0
February 16, 2007
ISL9208
Applications Circuits
Also refer to the ISL9208, ISL9216, ISL9217 application
guide for additional circuit design guidelines.
The following application circuits are ideas to consider when
developing a battery pack implementation. There are many
more ways that the pack can be designed.
P+
ISL9208
500
1.2M
0.1µF
VC7/VCC
10M
CB7
VCELL6
SCL
CB6
VCELL5
SDA
WKUP
CB5
RGC
VCELL4
RGO
CB4
VCELL3
TEMP3V
THERM
TEMPI
CB3
VCELL2
AO
CB2
VCELL1
VMON
CFET
CB1
MINIMIZE LENGTH
VSS
DSREF
CSENSE
MAXIMIZE GAUGE
DFET
µC
VCC
RESET
GP
I/O
SCL
SDA
INT
A/D INPUT
I/O
OPTIONAL
LEDS
RESISTORS
CHRG
100
3.6V
ONE-WIRE INTERFACE
NOT NEEDED DURING
DISCHARGE
DSENSE
4.7µF
1µF
200k
16V (<CFET VGSMAX)
PB-
FIGURE 15. 7-CELL APPLICATION CIRCUIT INTEGRATED CHARGE/DISCHARGE
26
FN6446.0
February 16, 2007
ISL9208
ISL9208
500
1.2M
0.1µF
VC7/VCC
CB7
10M
VCELL6
SCL
CB6
VCELL5
SDA
WKUP
CB5
RGC
VCELL4
RGO
CB4
VCELL3
TEMP3V
THERM
TEMPI
CB3
VCELL2
AO
CB2
VCELL1
4.7µF
DSENSE
CSENSE
DFET
DSREF
VCC
RESET
GP
I/O
OPTIONAL
LEDS
RESISTORS
SCL
SDA
INT
A/D INPUT
I/O
CHRG
100
3.6V
CFET
MINIMIZE LENGTH
VSS
µC
VMON
CB1
MAXIMIZE GAUGE
1µF
ONE-WIRE INTERFACE
NOT NEEDED DURING
DISCHARGE
200k
OPTIONAL
16V
OPTIONAL
CHG
P-
B-
FIGURE 16. 7-CELL APPLICATION CIRCUIT SEPARATE CHARGE/DISCHARGE
27
FN6446.0
February 16, 2007
ISL9208
ISL9208
825k
0.1µF
SW
VC7/VCC
TRIGGER
IN ONE
OF THESE
LOCATIONS
500
10V
CB7
VCELL6
SCL
CB6
VCELL5
SDA
WKUP
CB5
RGC
VCELL4
RGO
CB4
VCELL3
TEMP3V
THERM
TEMPI
CB3
VCELL2
AO
CB2
VCELL1
4.7µF
1µF
µC
VCC
RESET
GP
I/O
SCL
SDA
INT
A/D INPUT
I/O
VMON
MINIMIZE LENGTH
DSREF
OPTIONAL
DSENSE
DFET
VSS
CSENSE
MAXIMIZE GAUGE
CHRG
100
3.6V
ONE-WIRE
INTERFACE
NOT NEEDED DURING
DISCHARGE
CFET
CB1
OPTIONAL
LEDS
RESISTORS
OPTIONAL
16V
CHG
P-
B-
FIGURE 17. 7-CELL APPLICATION CIRCUIT WITH SWITCH WAKE-UP AND SEPARATE CHARGE/DISCHARGE
28
FN6446.0
February 16, 2007
ISL9208
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L32.5x5B
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
-
-
0.05
-
A2
-
-
1.00
A3
b
0.18
D
0.23
9
0.30
5,8
5.00 BSC
D1
D2
9
0.20 REF
-
4.75 BSC
3.15
3.30
9
3.45
7,8
E
5.00 BSC
-
E1
4.75 BSC
9
E2
3.15
e
3.30
3.45
7,8
0.50 BSC
-
k
0.25
-
-
-
L
0.30
0.40
0.50
8
L1
-
-
0.15
10
N
32
2
Nd
8
3
Ne
8
3
P
-
-
0.60
9
θ
-
-
12
9
Rev. 1 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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29
FN6446.0
February 16, 2007