MD1711 High Speed, Integrated Ultrasound Driver IC Features General Description Drives two ultrasound transducer channels Generates 5-level waveform Drives 12 high voltage MOSFETs ±2.0A source and sink peak current Up to 20MHz output frequency 12V/ns slew rate ±3ns matched delay times Second harmonic is less than -40dB Two separate gate drive voltages 1.8V to 3.3V CMOS logic interface The Supertex MD1711 is an IC for a two-channel, 5level, high voltage and high-speed transmitter driver. It is designed for medical ultrasound imaging applications but can also be used for metal flaw detection, nondestructive evaluation, and driving piezoelectric transducers. The MD1711 is a two-channel logic controller circuit with low impedance MOSFET gate drivers. There are two sets of control logic inputs, one for channel A and one for Channel B. Each channel consists of three pairs of MOSFET gate drivers. These drivers are designed to match the drive requirements of the Supertex TC6320. The MD1711 drives six TC6320s. Each pair an N-channel and a P-channel MOSFET. They are designed to have the same impedance and can provide peak currents of over 2.0 amps. Applications Medical ultrasound imaging Piezoelectric transducer drivers Metal flaw detection Nondestructive evaluation Sonar Transmitter Typical Application Circuit (1 of 2 Channels) +5 V 0.22 µF +1 0 V 0.22 µF +1 0 V -1 0 V 0.22µF 0.22 µF +10V 40 36 35 FB 6 DVDD2 AVDD1 33 45 DGND DVSS DVDD1 TC6320 0.22 µF 43 42 31 +100V DVDD1 30 DGND DGND VPP1 1µF DV DD2 0.1µF OUTPA1 EN SEL POSA / POS1A NEGA / NEG1A HVEN1A / POS2A HVEN2A / NEG2A ClampA +3 . 3 V 39 47 Control Logic & Level Translator 13 1 10nF DV DD2 OUTNA1 37 10nF VNN 1 2 1µF -100V 3 +50V VPP2 4 DV DD1 1µF 5 46 OUTPA2 MD1711 VL L 41 (1/2 of I/O) 0.1 µF 10nF DV DD1 OUTNA2 34 48 10nF AV S S VNN2 -50V 0.1 µF 1µF Transducer 0V 0.1 µF 14 15 AV S S SU B OUTPA3 AV SS VSS 44 DV DD 1 OU TNA3 32 -10V DGND AGND 7 0 DVDD1 18 19 DVSS DVDD 2 16 21 DVDD1 DGND 28 DVDD 2 0V 26 25 0.22µF +10V -10V +10V +5V 1 0 Rev.12 011005 MD1711 Ordering Information Thermal Resistance θJA Package Option 48-Lead LQFP/TQFP (1.4mm) MD1711FG MD1711FG-G 50°C/W* * 10z. 4-layer 3x4inch PCB -G indicates package is RoHS “Green” compliant Absolute Maximum Ratings* VLL, Logic Supply AVDD1, DVDD1, Positive Gate Drive Supply DVDD2, Positive Gate Drive Supply AVSS, DVSS Negative Gate Drive Supply Storage temperature Junction temperature Power Dissipation -0.5V to +5.5V -0.5V to +15V -0.5V to +15V -15V to +0.5V -65°C to 150°C 125°C 1.2W *Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Operating Supply Voltages and Currents (Over operating conditions unless otherwise specified, AVDD1 = DVDD1 = DVDD2 = 10V, AVSS = DVSS = -10V, VLL = 3.3V, TA = 25°C) Sym Parameter Min Typ Max Units VLL Logic Supply +1.8 +3.3 +5.5 V AVDD1 Positive Drive Bias Supply +8.0 +10 +12.6 V DVDD1 Positive Gate Drive Supply +4.75 +12.6 V DVDD2 Positive Gate Drive Supply +4.75 +12.6 V AVSS, DVSS Negative Gate Drive and Bias Supply -12.0 -8.0 V IVLL Logic Supply Current 2.0 mA IAVDD1 Positive Bias Current 5.0 mA IAVSS & IDVSS Negative Drive and Bias Supply Current 20 mA IDVDD1 Positive Drive Current 1 55 mA IDVDD2 Positive Drive Current 2 13 mA IAVDD1Q VAVDD1 quiescent current 2.0 mA IAVSSQ VAVSS quiescent current 0.75 mA IDVDD1Q VDVDD1 quiescent current 10 µA IDVDD2Q VDVDD2 quiescent current 10 µA IVLLQ Logic Supply Current -10 Note All channel on at 5.0Mhz, No load 1.0 mA 2 DVDD2 = 5.0V, All channel on at 5.0Mhz, No load EN = low, All inputs low or high. MD1711 DC Electrical Characteristics (Over operating conditions unless otherwise specified, AVDD1 = DVDD1 = DVDD2 = 10V, AVSS = DVSS = -10V, VLL = 3.3V, TA = 0 to 70°C) P-Channel Gate Driver Outputs Sym RSINK Parameter Output sink resistance Min Typ Max 6.0 Units Ω RSOURCE Output source resistance 6.0 Ω ISINK Peak output sink current 2.0 A ISOURCE Peak output source current 2.0 A Conditions ISINK = 100mA ISOURCE = 100mA N-Channel Gate Driver Outputs Sym RSINK Parameter Output sink resistance Min Typ Max 10 Units Ω Conditions ISINK = 100mA RSOURCE Output source resistance 10 Ω ISOURCE = 100mA ISINK Peak output sink current 1.5 A ISOURCE Peak output source current 1.5 A Logic Inputs Sym VIH Parameter Input logic high voltage Min 0.8VLL VIL Input logic low voltage 0 IIH Input logic high current IIL Input logic low current Typ Max VLL Units V 0.2VLL V 1.0 µA -1.0 Conditions µA AC Electrical Characteristics (Over operating conditions unless otherwise specified, AVDD1 = DVDD1 = DVDD2 = 10V, AVSS = DVSS = -10V, VLL = 3.3V, TA = 0 to 70°C) Sym Parameter fOUT tr Output frequency range Propagation delay when output is from low to high Propagation delay when output is from high to low Output rise time tf Output fall time tPH tPL ∆tdm ∆tDLAY SR HD2 Min Typ Max Units 20 MHz 19 ns No load, See timing diagram 19 ns No load, See timing diagram 8.0 ns 1000pF load, see timing diagram 8.0 ns 1000pF load, see timing diagram ns No load, From device to device Standard deviation of td samples (1k) Delay time matching ±3.0 Output jitter 30 ps Output slew rate 12 V/ns -40 dB nd 2 harmonic distortion Conditions Measured at TC6320 output with 100Ω Load Power-Up Sequence 1 AVSS , DVSS Negative Gate Drive Supply and Substrate Bias 2 VLL, AVDD1, DVDD1 & DVDD2 Logic Supply, Positive Gate Drive Supply and Bias 3 MD1711 Truth Table for Channels A and B (For SEL = L) Logic Control Inputs SEL EN HVEN1/ POS2 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 0 X HVEN2/ NEG2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X Clamp 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X POS/ POS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X NEG/ NEG1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X VPP1 to VNN1 Output VPP2 to VNN2 Output HVOUTP1 HVOUTN1 HVOUTP2 HVOUT N2 OFF OFF OFF OFF OFF OFF ON OFF OFF OFF OFF OFF ON OFF 4 VPP3 to VNN3 Output HVOUT P3 HVOUTN3 ON ON ON OFF OFF OFF ON OFF OFF ON OFF OFF OFF OFF OFF ON OFF OFF OFF ON ON ON OFF ON OFF OFF OFF OFF ON OFF OFF OFF ON OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF MD1711 Truth Table for Channels A and B (For SEL = H) Logic Control Inputs SEL EN Clamp 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X HVEN1/ POS2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X HVEN2/ NEG2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X POS/ POS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X NEG/ NEG1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X VPP1 to VNN1 Output HVOUTP1 HVOUTN1 OFF OFF ON ON OFF OFF ON ON OFF OFF ON ON OFF OFF ON ON OFF OFF ON ON OFF OFF ON ON OFF OFF ON ON OFF OFF ON ON OFF VPP2 to VNN2 Output HVOUTP2 HVOUTN2 OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF VPP3 to VNN3 Output HVOUTP3 HVOUTN3 OFF OFF OFF OFF ON OFF ON OFF OFF ON ON OFF OFF OFF ON OFF ON ON ON OFF ON ON ON ON OFF OFF OFF Test Circuit for Channel A 1/2 of MD1711 3x TC6320 VPP1 DVDD2 Out-PA 1 +10V 10nF +100 V GP A1 HV OUTPA1 AV DD1 +10V DV DD1 +10V DV DD2 DV DD2 Out-NA1 10nF HVout A HV OUTNA1 GNA 1 +3.3V VLL VNN1 RLOAD -100V 100 EN PO SA / POS1A NEGA / NEG1A HVEN1A / POS2A HVEN2 A / NEG2A Channel A Control Logic and Level Translation VPP2 DVDD1 Out-PA 2 10nF +50 V GP A2 HV OUTPA2 DVDD1 Out-NA2 Clam pA 10nF GNA 2 SEL HV OUTNA2 VNN2 -50V AG nd DG nd Out-PA 3 -10V AV SS DV SS GP A3 HV OUTPA3 DV SS DVDD1 GNA 3 Out-NA3 HV OUTNA3 Note: Only one of the two circuit channels is shown. 5 MD1711 Timing Diagram (EN = H, SEL = ClampA = L) VLL HVEN1A / POS2A 0V VLL HVEN2A / NEG2A 0V VLL POSA / POS1A 0V VLL NEGA / NEG1A 0V fout VPP1 HVOUT A VPP2 0V VNN2 VNN1 tr, rise time from 0.9VNN1 to 0.9VPP1 tr, rise time from 0.9VNN2 to 0.9VPP2 tf, fall time from 0.9VPP1 to 0.9VNN1 3.3V IN 50% 50% 0V tPH tPL 10V OUT 0V 90% 90% 10 % 10% tr tf 6 tf, fall time from 0.9VPP2 to 0.9VNN2 MD1711 Block Diagram / Typical Application Circuit +100V 1 F DV DD2 10nF DV 1 DD DV DD2 DV 2 DD 10nF -100V AV 1 DD 1 F +100V 1 F DV DD 1 Piezoelectric Transducer A 10nF DV DD 1 POSA / POS1A 10nF -100V NEGA / NEG1A 1 F HVEN1A / POS2A HVEN2A / NEG2A ClampA V SS DV DD1 V LL SEL EN Control Logic and Level Translate +100V 1 F DV DD2 10nF DV DD2 POSB / POS1B 10nF -100V NEGB / NEG1B 1 F HVEN1B / POS2B +100V HVEN2B / NEG2B 1 F DV DD1 ClampB 10nF DV DD1 10nF -100V 1 F AV SS DV SS AGND V SS DGND DV DD1 Supertex TC6320 Supertex MD1711 7 Piezoelectric Transducer B MD1711 MD1711: Pin Description VLL AVDD1 DVDD1 DVDD2 DVSS AVSS DGND AGND POSA / POS1A NEGA / NEG1A HVEN1A / POS2A HVEN2A / NEG2A CLAMPA Out-PA1, Out-PA2, Out-PA3 Out-NA1, Out-NA2, Out-NA3 POSB / POS1B NEGB / NEG1B HVEN1B / POS2B HVEN2B / NEG2B CLAMPB SEL EN Out-PB1, Out-PB2, Out-PB3 Out-NB1, Out-NB2, Out-NB3 Logic supply voltage. Supplies analog circuitry portion of the gate driver. Should be at the same potential as DVDD1. Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and the main output stage for Out-PA2, Out-NA2, OutNA3, Out-PB2, Out-NB2, and Out-NB3. Should be at the same potential as AVDD1. Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and the main output stage for Out-PA1, Out-NA1, OutPB1, and Out-NB1. Can be at a different potential than DVDD1. Gate drive supply voltage for Out-PA3 and Out-PB3. Supplies digital circuitry portion and the main output stage. Should be at the same potential as AVSS. Negative driver supply for Out-PA3, Out-PB3 and bias circuits. They are also connected to the IC substrate. They are required to connect to the most negative potential of voltage supplies. Digital Ground. Analog Ground. Logic input control for channel A. When SEL = L, the pin is POSA. When SEL = H, the pin is POS1A. Logic input control for channel A. When SEL = L, the pin is NEGA. When SEL = H, the pin is NEG1A. Logic input control for channel A. When SE L= L, the pin is HVEN1A. When SEL = H, the pin is POS2A. Logic input control for channel A. When SEL = L, the pin is HVEN2A. When SEL = H, the pin is NEG2A. Used with SEL = H. Logic input control for Out-PA3 and Out-NA3. Connect to ground when SEL = L. Output P-Channel gate drivers for channel A Output N-Channel gate drivers for channel A Logic input control for channel B. When SEL = L, the pin is POSB. When SEL = H, the pin is POS1B. Logic input control for channel B. When SEL = L, the pin is NEGB. When SEL = H, the pin is NEG1B. Logic input control for channel B. When SEL = L, the pin is HVEN1B. When SEL = H, the pin is POS2B. Logic input control for channel B. When SEL = L, the pin is HVEN2B. When SEL = H, the pin is NEG2B. Used with SEL = H. Logic input control for Out-PB3 and Out-NB3. Connect to ground when SEL = L. Logic input select. See truth tables for SEL = L and SEL = H. Logic input enable control. When EN = L, all P-channel output drivers are high and all N-channel output drivers are low. Output P-Channel gate driver for channel B Output N-Channel gate driver for channel B 8 MD1711 Pin Configuration 48-Lead LQFP/TQFP (1.4mm) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Function POSA/POS1A NEGA/NEG1A HVEN1A/POS2A HVEN2A/NEG2A CLAMPA AVDD1 AGND CLAMPB HVEN2B/NEG2B HVEN1B/POS2B NEGB/NEG1B POSB/POS1B SEL AVSS AVSS DVSS Out-PB3 DGND DVDD1 Out-PB2 DVDD2 Out-PB1 N/C Out-NB1 Pin 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Function DVDD2 DGND Out-NB2 DVDD1 Out-NB3 DGND DVDD1 Out-NA3 DVDD1 Out-NA2 DGND DVDD2 Out-NA1 N/C Out-PA1 DVDD2 Out-PA2 DVDD1 DGND Out-PA3 DVSS VLL EN AVSS Doc. # DSFP-MD1711 A062806 9 Package Outline 48-Lead LQFP/TQFP Package Outline (FG) 7x7x1.4mm body, 0.50mm pitch D D1 E E1 Note 1 (Index Area D1/4 x E1/4) Gauge Plane L2 48 L 1 Seating Plane θ L1 b e Top View View B View B A A2 Seating Plane A1 Side View Note 1: A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. Symbol MIN Dimension (mm) A A1 A2 b D D1 E E1 1.40 0.05 1.35 0.17 8.80 6.80 8.80 6.80 NOM - - 1.40 0.22 9.00 7.00 9.00 7.00 MAX 1.60 0.15 1.45 0.27 9.20 7.20 9.20 7.20 JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001. Drawings not to scale. Doc. #: DSPD-48LQFPFG B032607 e L L1 L2 1.00 REF 0.25 BSC 0O 0.45 0.50 BSC 0.60 0.75 θ 3.5O 7O