LTC6102/LTC6102HV Precision Zero Drift Current Sense Amplifier FEATURES DESCRIPTION n The LTC®6102/LTC6102HV are versatile, high voltage, high-side current sense amplifiers. Their high supply voltage rating allows their use in almost any application, while the low drift and offset ensure accuracy across a wide range of operating conditions. n n n n n n n n n Supply Range: 4V to 60V, 70V Absolute Maximum (LTC6102) 5V to 100V, 105V Absolute Maximum (LTC6102HV) ±10μV Input Offset Maximum ±50nV/°C Input Offset Drift Maximum Fast Response: 1μs Step Response Gain Configurable with Two Resistors Low Input Bias Current: 3nA Maximum PSRR 130dB Minimum Output Currents up to 1mA Operating Temperature Range: –40°C to 125°C Available in 8-Lead MSOP and 3mm × 3mm DFN Packages The LTC6102/LTC6102HV monitor current via the voltage across an external sense resistor (shunt resistor). Internal circuitry converts input voltage to output current, allowing a small sense signal on a large common mode voltage to be translated to a ground-referred signal. Low DC offset allows the use of very low shunt resistor values and large gain-setting resistors. As a result, power loss in the shunt is reduced. The wide operating supply and high accuracy make the LTC6102/LTC6102HV ideal for a large array of applications from automotive to industrial and power management. A maximum input sense voltage of 2V allows a wide range of currents and voltages to be monitored. Fast response makes the LTC6102/LTC6102HV the perfect choice for load current warnings and shutoff protection control. APPLICATIONS n n n n n n n Current Shunt Measurement Battery Monitoring Remote Sensing Power Management Load Protection Motor Control Automotive Controls The LTC6102/LTC6102HV are available in 8-lead MSOP and 3mm × 3mm DFN packages. L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION 10A Current Sense with 10mA Resolution and 100mW Maximum Dissipation VSENSE – + 110 1mΩ* RIN 20Ω +IN 100 5V TO 105V L O A D V– –INF + – 0.1μF V+ LTC6102HV 1μF 5V VREG OUT VOUT 80 70 RSENSE = 10μΩ Max VSENSE = 100μV 60 50 40 30 ROUT 4.99k RSENSE = 100mΩ Max VSENSE = 1V 90 –INS DYNAMIC RANGE (dB) ILOAD Dynamic Range vs Maximum Power Dissipation in RSENSE at 10A LTC2433-1 DYNAMIC RANGE RELATIVE TO 10μV MINIMUM VSENSE ISENSE = 10A TO μP 20 0.001 0.01 0.1 1 MAXIMUM POWER DISSIPATION (W) 10 6102 TA01b 6102 TA01 VOUT = ROUT • VSENSE = 249.5VSENSE RIN *PROPER SHUNT SELECTION COULD ALLOW MONITORING OF CURRENTS IN EXCESS OF 1000A 6102fb 1 LTC6102/LTC6102HV ABSOLUTE MAXIMUM RATINGS (Note 1) Total Supply Voltage (V+ to V–): LTC6102................................................................70V LTC6102HV .........................................................105V Input Voltage Range (–INF, –INS) ............................. (V+ – 4V to V+ + 0.3V) (+IN) ......................................... (V+ – 20V to V+ + 1V) Output Voltage Range (OUT) ....................................... (V– – 0.3V to V– + 9V) Input Current (–INF, –INS) .....................................................±10mA (+IN) ................................................................–10mA Output Current .......................................(+1mA, –10mA) Output Short Circuit Duration........................... Indefinite Operating Temperature Range: (Note 2) LTC6102C/LTC6102HVC ....................... –40°C to 85°C LTC6102I/LTC6102HVI ......................... –40°C to 85°C LTC6102H/LTC6102HVH .................... –40°C to 125°C Specified Temperature Range: (Note 2) LTC6102C/LTC6102HVC ........................... 0°C to 70°C LTC6102I/LTC6102HVI ......................... –40°C to 85°C LTC6102H/LTC6102HVH .................... –40°C to 125°C Storage Temperature Range................... –65°C to 150°C PIN CONFIGURATION TOP VIEW –INS 1 8 +IN –INF 2 7 V+ V– 3 9 OUT 4 TOP VIEW –INS –INF V– OUT 6 VREG 5 V– DD PACKAGE 8-LEAD (3mm × 3mm) PLASTIC DFN TJMAX = 150°C, θJA = 60°C/W EXPOSED PAD (PIN 9) IS V–, MUST BE SOLDERED TO PCB 1 2 3 4 8 7 6 5 +IN V+ VREG V– MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 150°C, θJA = 300°C/W ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC6102CDD#PBF LTC6102CDD#TRPBF LCKH 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LTC6102IDD#PBF LTC6102IDD#TRPBF LCKH 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LTC6102HDD#PBF LTC6102HDD#TRPBF LCKH 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LTC6102HVCDD#PBF LTC6102HVCDD#TRPBF LCVC 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LTC6102HVIDD#PBF LTC6102HVIDD#TRPBF LCVC 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LTC6102HVHDD#PBF LTC6102HVHDD#TRPBF LCVC 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LTC6102CMS8#PBF LTC6102CMS8#TRPBF LTCKJ 8-Lead Plastic MSOP –40°C to 85°C LTC6102IMS8#PBF LTC6102IMS8#TRPBF LTCKJ 8-Lead Plastic MSOP –40°C to 85°C LTC6102HMS8#PBF LTC6102HMS8#TRPBF LTCKJ 8-Lead Plastic MSOP –40°C to 125°C LTC6102HVCMS8#PBF LTC6102HVCMS8#TRPBF LTCVB 8-Lead Plastic MSOP –40°C to 85°C LTC6102HVIMS8#PBF LTC6102HVIMS8#TRPBF 8-Lead Plastic MSOP –40°C to 85°C LTC6102HVHMS8#PBF LTC6102HVHMS8#TRPBF LTCVB 8-Lead Plastic MSOP –40°C to 125°C LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC6102CDD LTC6102CDD#TR LCKH 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LTC6102IDD LTC6102IDD#TR LCKH 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LTC6102HDD LTC6102HDD#TR LCKH 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LTCVB 6102fb 2 LTC6102/LTC6102HV ORDER INFORMATION LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC6102HVCDD LTC6102HVCDD#TR LCVC 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LTC6102HVIDD LTC6102HVIDD#TR LCVC 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LTC6102HVHDD LTC6102HVHDD#TR LCVC 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LTC6102CMS8 LTC6102CMS8#TR LTCKJ 8-Lead Plastic MSOP –40°C to 85°C LTC6102IMS8 LTC6102IMS8#TR LTCKJ 8-Lead Plastic MSOP –40°C to 85°C LTC6102HMS8 LTC6102HMS8#TR LTCKJ 8-Lead Plastic MSOP –40°C to 125°C LTC6102HVCMS8 LTC6102HVCMS8#TR LTCVB 8-Lead Plastic MSOP –40°C to 85°C LTC6102HVIMS8 LTC6102HVIMS8#TR LTCVB 8-Lead Plastic MSOP –40°C to 85°C LTC6102HVHMS8 LTC6102HVHMS8#TR LTCVB 8-Lead Plastic MSOP –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS (LTC6102) The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. RIN = 10Ω, ROUT = 10k, VSENSE+ = V+ (see Figure 1 for details), V+ = 12V, V– = 0V unless otherwise noted. SYMBOL PARAMETER V+ Supply Voltage Range VOS Input Offset Voltage (Note 3) Input Offset Voltage (Note 4) ΔVOS/ΔT IB PSRR CONDITIONS VSENSE = 100μV 6V ≤ V+ ≤ 60V V+ = 4V 6V ≤ V+ ≤ 60V V+ = 4V Input Offset Voltage Drift (Note 3) VSENSE = 100μV LTC6102C, LTC6102I LTC6102H l l Input Bias Current (Note 5) RIN = 40k, VSENSE = 2mV LTC6102C, LTC6102I LTC6102H l l Power Supply Rejection Ratio VSENSE(MAX) Input Sense Voltage Full Scale (V+ – VIN+) Maximum Output Voltage VSENSE = 100μV V+ = 6V to 60V UNITS 60 V 3 5 3 5 10 25 35 50 μV μV μV μV 25 25 50 75 nV/°C nV/°C 3 20 pA nA nA 60 l Error <1%, RIN = 10k, ROUT = 10k 6V ≤ V+ ≤ 60V V+ = 4V l l 2 0.8 V V VSENSE = 2mV, ROUT = 100k 12V ≤ V+ ≤ 60V V+ = 6V V+ = 4V l l l 8 3 1 V V V 6V ≤ V+ ≤ 60V, RIN = 1k, ROUT = 1k, VSENSE = 1.1V V+ = 4V, RIN = 10Ω, ROUT = 1k, VSENSE = 11mV l l 1 0.5 Maximum Output Current tr Input Step Response (to 2.5V on ΔVSENSE = 100mV Transient, 6V ≤ V+ ≤ 60V, RIN = 100Ω, a 5V Output Step) ROUT = 4.99k, IOUT = 100μA V+ = 4V Signal Bandwidth MAX 130 125 120 115 IOUT BW TYP 4 V+ = 4V to 60V VOUT MIN IOUT = 200μA, RIN = 100Ω, ROUT = 4.99k IOUT = 1mA, RIN = 100Ω, ROUT = 4.99k l 150 140 dB dB dB dB mA mA 1 μs 1.5 μs 140 200 kHz kHz 6102fb 3 LTC6102/LTC6102HV ELECTRICAL CHARACTERISTICS (LTC6102HV) The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. RIN = 10Ω, ROUT = 10k, VSENSE+ = V+ (see Figure 1 for details), V+ = 12V, V– = 0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS eN Input Noise Voltage 0.1Hz to 10Hz Supply Current V+ = 4V, I IS OUT = 0, RIN = 10k, ROUT = 100k V+ = 6V, IOUT = 0, RIN = 10k, ROUT = 100k V+ = 12V, IOUT = 0, RIN = 10k, ROUT = 100k V+ = 60V, IOUT = 0, RIN = 10k, ROUT = 100k LTC6102C, LTC6102I LTC6102H fS Sampling Frequency V+ Supply Voltage Range VOS Input Offset Voltage (Note 3) ΔVOS/ΔT IB PSRR VSENSE = 100μV 6V ≤ V+ ≤ 100V V+ = 5V Input Offset Voltage 6V ≤ V+ ≤ 100V (Note 4) V+ = 5V Input Offset Voltage Drift (Note 3) VSENSE = 100μV LTC6102HVC, LTC6102HVI LTC6102HVH Input Bias Current (Note 5) RIN = 40k, VSENSE = 2mV LTC6102HVC, LTC6102HVI LTC6102HVH Power Supply Rejection Ratio VSENSE = 100μV V+ = 6V to 100V eN Error <1%, RIN = 10k, ROUT = 10k 6V ≤ V+ ≤ 100V V+ = 5V Maximum Output Voltage VSENSE = 2mV, ROUT = 100k 12V ≤ V+ ≤ 100V V+ = 5V Maximum Output Current 6V ≤ V+ ≤ 100V, RIN = 1k, ROUT = 1k, VSENSE = 1.1V V+ = 5V, RIN = 10Ω, ROUT = 1k, VSENSE = 11mV Input Step Response (to 2.5V on a ΔVSENSE = 100mV Transient, 6V ≤ V+ ≤ 100V, 5V Output Step) RIN = 100Ω, ROUT = 4.99k, IOUT = 100μA V+ = 5V Signal Bandwidth IOUT = 200μA, RIN = 100Ω, ROUT = 4.99k IOUT = 1mA, RIN = 100Ω, ROUT = 4.99k Input Noise Voltage 0.1Hz to 10Hz IS Supply Current tr BW V+ = 5V, IOUT = 0, RIN = 10k, ROUT = 100k V+ = 6V, IOUT = 0, RIN = 10k, ROUT = 100k V+ = 12V, IOUT = 0, RIN = 10k, ROUT = 100k V+ = 100V, IOUT = 0, RIN = 10k, ROUT = 100k LTC6102HVC, LTC6102HVI LTC6102HVH fS Sampling Frequency MAX UNITS 2 μVP-P 290 l 300 l 420 l l μA μA μA μA μA μA μA μA μA 400 475 425 500 450 525 575 650 675 275 l 10 VSENSE(MAX) Input Sense Voltage Full Scale (V+ – V+IN) IOUT TYP 5 V+ = 5V to 100V VOUT MIN l l l l kHz 100 V 3 5 3 5 10 25 35 50 μV μV μV μV 25 25 60 50 75 nV/°C nV/°C pA nA nA 3 20 l 130 125 120 115 l l 2 1 V V l l 8 3 1 0.5 1 V V mA mA μs 1.5 140 200 2 μs kHz kHz μVP-P l l l l l l l l 150 dB dB dB dB 140 275 280 290 420 10 400 475 425 500 450 525 575 650 675 μA μA μA μA μA μA μA μA μA kHz 6102fb 4 LTC6102/LTC6102HV ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. In addition to the Absolute Maximum Ratings, the output current of the LTC6102 must be limited to ensure that the power dissipation in the LTC6102 does not allow the die temperature to exceed 150°C. See the Applications Information “Output Current Limitations Due to Power Dissipation” for further information. Note 2: The LTC6102C/LTC6102HVC are guaranteed to meet specified performance from 0°C to 70°C. The LTC6102C/LTC6102HVC are designed, characterized and expected to meet specified performance from –40°C to 85°C but are not tested or QA sampled at these temperatures. LTC6102I/ LTC6102HVI are guaranteed to meet specified performance from –40°C to 85°C. The LTC6102H/LTC6102HVH are guaranteed to meet specified performance from –40°C to 125°C. Note 3: These Parameters are guaranteed by design and are not 100% tested. Thermocouple effects preclude measurements of these voltage levels during automated testing. Note 4: Limits are fully tested. Limit is determined by high speed automated test capability. Note 5: IB specification is limited by practical automated test resolution. Please refer to the Typical Performance Characteristics section for more information regarding actual typical performance. For tighter specifications, please contact LTC Marketing. TYPICAL PERFORMANCE CHARACTERISTICS Input VOS vs Supply Voltage 15 15 10 10 VS = 4V 5 0 VS = 12V –5 0 –5 –10 –15 –15 0 20 40 60 80 100 120 TEMPERATURE (°C) TA = –40°C TA = 0°C TA = 25°C TA = 70°C TA = 85°C TA = 125°C –20 1.0 0 0 20 40 60 80 VSUPPLY (V) VS = 100V VS = 12V VS = 6V VS = 5V –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 6102 G05 120 LTC6102: IOUT Maximum vs Temperature MAXIMUM IOUT (mA) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 –40 100 6102 G03 LTC6102HV: VOUT Maximum vs Temperature MAXIMUM VOUT (V) MAXIMUM VOUT (V) 1.5 6102 G02 LTC6102: VOUT Maximum vs Temperature 6102 G04 2.0 0.5 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 SUPPLY VOLTAGE (V) 6102 G01 15 14 13 VS = 60V 12 11 VS = 12V 10 9 8 7 VS = 6V 6 5 4 VS = 4V 3 2 VS = 5V 1 0 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) TA = 25°C 2.5 5 –10 –20 –40 –20 Input Sense Range 3.0 MAXIMUM VSENSE (V) 20 INPUT OFFSET (μV) INPUT OFFSET (μV) Input VOS vs Temperature 20 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 –40 VS = 12V VS = 60V VS = 6V VS = 5V VS = 4V –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 6102 G06 6102fb 5 LTC6102/LTC6102HV TYPICAL PERFORMANCE CHARACTERISTICS LTC6102 Output Error Due to Typical Input Offset vs Input Voltage 100 VIN = 10μV 35 VS = 12V 10 VS = 6V VS = 5V 1 25 GAIN (dB) VS = 100V 0.1 0.01 0 20 40 60 80 100 120 TEMPERATURE (°C) 0.001 0.01 0.1 1 INPUT VOLTAGE (V) 100 LTC6102HV: Supply Current vs Supply Voltage 600 TA = 85°C TA = 85°C TA = 70°C TA = 125°C 400 300 200 TA = 25°C TA = –40°C 0 20 40 60 80 TEMPERATURE (°C) 100 120 TA = 0°C 300 0 Step Response 100mV V+ VSENSE– V+ – 20mV V+ – 100mV 0.5V 1V 5V VOUT 0.5V TA = 25°C V+ = 12V RIN = 100Ω ROUT = 4.99k VSENSE+ = V+ 6102 G13 VSENSE– CLOAD = 10pF CLOAD = 1000pF 0V VOUT TIME (10μs/DIV) TIME (10μs/DIV) 8 16 24 32 40 48 56 64 72 80 88 96 SUPPLY VOLTAGE (V) 6102 G12 V+ – 10mV 0V VIN = 0 RIN = 2M 6102 G11 V+ – 10mV TA = 25°C V+ = 12V RIN = 100Ω ROUT = 4.99k VSENSE+ = V+ TA = –40°C TA = 0°C 0 Step Response 10mV to 20mV VSENSE– TA = 25°C 200 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 SUPPLY VOLTAGE (V) Step Response 0mV to 10mV V+ TA = 125°C 400 100 VIN = 0 RIN = 2M 0 6102 G10 TA = 70°C 500 100 10 –40 –20 10M 6102 G09 LTC6102: Supply Current vs Supply Voltage 500 1000 100k 1M FREQUENCY (Hz) 6102 G08 SUPPLY CURRENT (μA) 10000 IOUT = 200μA DC 10 TA = 25°C V+ = 12V –5 RIN = 100Ω ROUT = 4.99k –10 10k 1k 600 VS = 100V VS = 60V VS = 12V VS = 6V VS = 5V 15 0 0.0001 0.00001 0.0001 Input Bias Current vs Temperature 100000 20 5 0.001 –20 IOUT = 1mA DC 30 FOR A 500μΩ SHUNT VIN = 100mV, ISHUNT = 200A ERROR DUE TO VOS IS 6mA 6102 G07 BIAS CURRENT (pA) Gain vs Frequency 40 SUPPLY CURRENT (μA) 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 –40 OUTPUT ERROR (%) MAXIMUM IOUT (mA) LTC6102HV: IOUT Maximum vs Temperature TA = 25°C V+ = 12V RIN = 100Ω ROUT = 4.99k VSENSE+ = V+ VOUT TIME (10μs/DIV) 6102 G14 6102 G15 6102fb 6 LTC6102/LTC6102HV TYPICAL PERFORMANCE CHARACTERISTICS Step Response Rising Edge Step Response Falling Edge PSRR vs Frequency 160 VSENSE– = 100mV 5.5V 5V 5.5V 5V 0.5V 0V VOUT 120 TA = 25°C V+ = 12V RIN = 100Ω ROUT = 4.99k VSENSE+ = V+ VOUT TA = 25°C V+ = 12V RIN = 100Ω ROUT = 4.99k VSENSE+ = V+ IOUT = 0 140 PSRR (dB) VSENSE– = 100mV IOUT = 100μA IOUT = 100μA 100 80 60 IOUT = 0 40 0.5V 0V TIME (500ns/DIV) V+ = 12V RIN = 100Ω ROUT = 4.99k AV = 49.9 IOUT = 500μA 20 0.1 TIME (500ns/DIV) 6102 G17 1 6102 G18 10 100 1k 10k 100k FREQUENCY (Hz) 1M 6102 G19 Input Referred Noise 0.1Hz to 10Hz 5 3 2 VOLTAGE NOISE DENSITY (μV/√Hz) TA = 25°C V+ = 12V RIN = 10Ω ROUT = 1k VSENSE = 2mV 4 NOISE (μV) Noise Spectral Density 2 1 0 –1 –2 –3 1 –4 –5 0 1 2 3 4 5 6 TIME (s) 7 8 9 10 6102 G20 0 100 1k 10k 100k FREQUENCY (Hz) 1M 6102 G21 PIN FUNCTIONS –INS (Pin 1): Amplifier Inverting Input. When tied to –INF, the internal sense amplifier will drive –INS to the same potential as +IN. –INF (Pin 2): Force Input. This pin carries the input current from RIN and must be tied to –INS near RIN. A resistor (RIN) tied from V+ to –INF sets the output current IOUT = VSENSE/RIN. VSENSE is the voltage across the external RSENSE. V– (Pins 3, 5): Negative Supply. OUT (Pin 4): Open-Drain Current output. OUT will source a current that is proportional to the sense voltage into an ex- ternal resistor. IOUT is the same current that enters –INF. VREG (Pin 6): Internal Regulated Supply. A 0.1μF (or larger) capacitor should be tied from VREG to V+. VREG is not designed to drive external circuits. V+ (Pin 7): Positive Supply. Supply current is drawn through this pin. +IN (Pin 8): Amplifier Non-Inverting Input. Must be tied to the system load end of the sense resistor. Exposed Pad (Pin 9, DFN Only): V–. The Exposed Pad must be soldered to PCB. 6102fb 7 LTC6102/LTC6102HV BLOCK DIAGRAM ILOAD – VSENSE VBATTERY + 0.1μF RSENSE RIN L O A D V+ 10V –INF –INS 10V 5V 5V VREG – 5k +IN + LTC6102/LTC6102HV IOUT 10V OUT 5k V – V– 6102 BD VOUT = VSENSE x ROUT RIN ROUT Figure 1. LTC6102/LTC6102HV Block Diagram and Typical Connection APPLICATIONS INFORMATION The LTC6102 high side current sense amplifier (Figure 1) provides accurate monitoring of current through a userselected sense resistor. The sense voltage is amplified by a user-selected gain and level shifted from the positive power supply to a ground-referred output. The output signal is analog and may be used as is or processed with an output filter. Theory of Operation An internal sense amplifier loop forces –INS to have the same potential as +IN. Connecting an external resistor, RIN, between –INS and V+ forces a potential across RIN that is the same as the sense voltage across RSENSE. A corresponding current, VSENSE/RIN, will flow through RIN. The high impedance inputs of the sense amplifier will not conduct this input current, so it will flow through the –INF pin and an internal MOSFET to the output pin. The output current can be transformed into a voltage by adding a resistor from OUT to V–. The output voltage is then VO = V– + IOUT • ROUT. Useful Gain Configurations GAIN RIN ROUT VSENSE AT VOUT = 5V 200 49.9Ω 10k 25mV 500 20Ω 10k 10mV 1000 10Ω 10k 5mV 4990 1Ω 4.99k 1mV Selection of External Current Sense Resistor The external sense resistor, RSENSE, has a significant effect on the function of a current sensing system and must be chosen with care. First, the power dissipation in the resistor should be considered. The system load current will cause both heat dissipation and voltage loss in RSENSE. As a result, the sense resistor should be as small as possible while still providing the input dynamic range required by the measurement. Note that input dynamic range is the difference between the maximum input signal and the minimum accurately reproduced signal, and is limited primarily by input DC offset of the internal amplifier of the LTC6102. In addition, RSENSE must be small enough that VSENSE does not exceed the maximum sense voltage specified by the LTC6102 or the sense resistor, even under peak load conditions. As an example, an application may require that the maximum sense voltage be 100mV. If this application is expected to draw 20A at peak load, RSENSE should be no more than 5mΩ. Once the maximum RSENSE value is determined, the minimum sense resistor value will be set by the resolution or dynamic range required. The minimum signal that can be accurately represented by this sense amp is limited by the input offset. As an example, the LTC6102 has a typical input offset of 3μV. If the minimum current is 1mA, a sense resistor of 3mΩ will set VSENSE to 3μV. 6102fb 8 LTC6102/LTC6102HV APPLICATIONS INFORMATION Dynamic Range vs Maximum Power Dissipation in RSENSE This is the same value as the input offset. A larger sense resistor will reduce the error due to offset by increasing the sense voltage for a given load current. Peak dissipation is 2W. If a 0.5mΩ sense resistor is employed, then the effective current error is 6mA (0.03% of full-scale), while the peak sense voltage is reduced to 10mV at 20A, dissipating only 200mW. The low offset and corresponding large dynamic range of the LTC6102 make it more flexible than other solutions in this respect. The 3μV typical offset gives 100dB of dynamic range for a sense voltage that is limited to 300mV max, and over 116dB of dynamic range if a maximum of 2V is allowed. The previous example assumes that a large output dynamic range is required. For circuits that do not require large dynamic range, the wide input range of the LTC6102 may be used to reduce the size of the sense resistor, reducing power loss and increasing reliability. For example, in a 100A circuit requiring 60dB of dynamic range, the input offset and drift of most current-sense solutions will require that the shunt be chosen so that the sense voltage is at least 100mV at full scale so that the minimum input is greater than 100μV. This will cause power dissipation in excess of 10W at full scale! That much power loss can put a significant load on the power supply and create thermal design headaches. In addition, heating in the sense resistor can reduce its accuracy and reliability. In contrast, the large dynamic range of the LTC6102 allows the use of a much smaller sense resistor. The LTC6102 allows the minimum sense voltage to be reduced to less than 10μV. The peak sense voltage would then be 10mV, dissipating only 1W at 100A in a 100μΩ sense resistor! With a specialized sense resistor, the same system would allow peak currents of more than 1000A without exceeding the input range of the LTC6102 or damaging the shunt. 100 RSENSE = 100mΩ RSENSE = 10mΩ RSENSE = 1Ω 90 DYNAMIC RANGE (dB) For this example, choosing a 5mΩ RSENSE will maximize the dynamic range and provide a system that has 100mV across the sense resistor at peak load (20A), while input offset causes an error equivalent to only 0.6mA of load current. 110 80 100dB: MAX VSENSE = 1V 70 40dB: MAX VSENSE = 1mV 60 50 RSENSE = 10μΩ 40 30 RSENSE = 100μΩ RSENSE = 1mΩ 20 0.001 0.01 0.1 1 10 100 MAXIMUM POWER DISSIPATION (W) DYNAMIC RANGE RELATIVE TO 10μV, MINIMUM VSENSE MAX ISENSE = 1A MAX ISENSE = 10A MAX ISENSE = 100A 6102 F10 Sense Resistor Connection Kelvin connection of +IN and –INS to the sense resistor should be used in all but the lowest power applications. Solder connections and PC board interconnections that carry high current can cause significant error in measurement due to their relatively large resistances. One 10mm × 10mm square trace of one-ounce copper is approximately 0.5mΩ. A 1mV error can be caused by as little as 2A flowing through this small interconnect. This will cause a 1% error in a 100mV signal. A 10A load current in the same interconnect will cause a 5% error for the same 100mV signal. An additional error is caused by the change in copper resistance over temperature, which is in excess of 0.4%/°C. By isolating the sense traces from the high-current paths, this error can be reduced by orders of magnitude. A sense resistor with integrated Kelvin sense terminals will give the best results. Figure 2 illustrates the recommended method. Note that the LTC6102 has a Kelvin input structure such that current flows into –INF. The –INS and –INF pins should be tied as close as possible to RIN. This reduces the parasitic series resistance so that RIN may be as low as 1Ω, allowing high gain settings to be used with very little gain error. 6102fb 9 LTC6102/LTC6102HV APPLICATIONS INFORMATION Selection of External Input Resistor, RIN The external input resistor, RIN, controls the transconductance of the current sense circuit, IOUT = VSENSE/RIN. For example, if RIN = 100, then IOUT = VSENSE/100 or IOUT = 1mA for VSENSE = 100mV. V+ Care should be taken when designing the PC board layout for RIN, especially for small RIN values. All trace and interconnect impedances will increase the effective RIN value, causing a gain error. It is important to note that the large temperature drift of copper resistance will cause a change in gain over temperature if proper care is not taken to reduce this effect. TIE AS CLOSE TO RIN AS POSSIBLE RIN– RSENSE +IN RIN+ –INS + – –INF LOAD V– another way, such as with a Schottky diode across RSENSE (Figure 3). This will reduce the high current measurement accuracy by limiting the result, while increasing the low current measurement resolution. This approach can be helpful in cases where occasional large burst currents may be ignored. V+ 0.1μF VREG OUT VOUT LTC6102 V+ RSENSE ROUT DSENSE 6102 F03 LOAD Figure 3. Shunt Diode Limits Maximum Input Voltage to Allow Better Low Input Resolution Without Overranging RSENSE* V+ LOAD RIN– RIN+ CREG V– OUTPUT LTC6102 ROUT V– *VISHAY VCS1625 SERIES WITH 4 PAD KELVIN CONNECTION 6102 F02 Figure 2. Kelvin Input Connection Preserves Accuracy with Large Load Current and Large Output Current RIN should be chosen to provide the required resolution while limiting the output current. At low supply voltage, IOUT may be as much as 1mA. By setting RIN such that the largest expected sense voltage gives IOUT = 1mA, then the maximum output dynamic range is available. Output dynamic range is limited by both the maximum allowed output current (Note 1) and the maximum allowed output voltage, as well as the minimum practical output signal. If less dynamic range is required, then RIN can be increased accordingly, reducing the output current and power dissipation. If small sense currents must be resolved accurately in a system that has very wide dynamic range, a smaller RIN may be used if the max current is limited in To further limit the effect of trace resistance on gain, maximizing the accuracy of these circuits, the LTC6102 has been designed with a Kelvin input. The inverting terminal (–INS) is separate from the feedback path (–INF). During operation, these two pins must be connected together. The design of the LTC6102 is such that current into –INS is input bias current only, which is typically 60pA at 25°C. Almost all of the current from RIN flows into –INF, through the LTC6102, and into ROUT via the OUT pin. In order to minimize gain error, –INS should be routed in a separate path from –INF to a point as close to RIN as possible. In addition, the higher potential terminal of RIN should be connected directly to the positive terminal of RSENSE (or any input voltage source). For the highest accuracy, RIN should be a four-terminal resistor if it is less than 10Ω. Selection of External Output Resistor, ROUT The output resistor, ROUT, determines how the output current is converted to voltage. VOUT is simply IOUT • ROUT. In choosing an output resistor, the max output voltage must first be considered. If the circuit that is driven by the output does not have a limited input voltage, then ROUT 6102fb 10 LTC6102/LTC6102HV APPLICATIONS INFORMATION must be chosen such that the max output voltage does not exceed the LTC6102 max output voltage rating. If the following circuit is a buffer or ADC with limited input range, then ROUT must be chosen so that IOUT(MAX) • ROUT is less than the allowed maximum input range of this circuit. In addition, the output impedance is determined by ROUT. If the circuit to be driven has high enough input impedance, then almost any output impedance will be acceptable. However, if the driven circuit has relatively low input impedance, or draws spikes of current, such as an ADC might do, then a lower ROUT value may be required in order to preserve the accuracy of the output. As an example, if the input impedance of the driven circuit is 100 times ROUT, then the accuracy of VOUT will be reduced by 1% since: VOUT =IOUT • ROUT • RIN(DRIVEN) ROUT + RIN(DRIVEN) =IOUT • ROUT • 100 = 0.99 •IOUT • ROUT 101 Error Sources The current sense system uses an amplifier and resistors to apply gain and level shift the result. The output is then dependent on the characteristics of the amplifier, such as gain and input offset, as well as resistor matching. Ideally, the circuit output is: Output Error, EOUT, Due to the Bias Currents, IB(+) and IB(–) The input bias current of the LTC6102 is vanishingly small. However, for very high resolution, or at high temperatures where IB increases due to leakage, the current may be significant. The bias current IB(+) flows into the positive input of the internal op amp. IB(–) flows into the negative input. EOUT(IBIAS) = ROUT((IB(+) • (RSENSE/RIN) – IB(–)) Since IB(+) ≈ IB(–) = IBIAS, if RSENSE << RIN then, EOUT(IBIAS) ≈ –ROUT • IBIAS For instance if IBIAS is 1nA and ROUT is 10k, the output error is –10μV. Note that in applications where RSENSE ≈ RIN, IB(+) causes a voltage offset in RSENSE that cancels the error due to IB(–) and EOUT(IBIAS) ≈ 0. In applications where RSENSE < RIN, the bias current error can be similarly reduced if an external resistor RIN(+) = (RIN – RSENSE) is connected as shown in Figure 4. Under both conditions: EOUT(IBIAS) = ± ROUT • IOS; IOS = IB(+) – IB(–) Adding RIN+ as described will maximize the dynamic range of the circuit. For less sensitive designs, RIN+ is not necessary. V+ R VOUT = VSENSE • OUT ;VSENSE = RSENSE •ISENSE RIN In this case, the only error is due to resistor mismatch, which provides an error in gain only. Output Error, EOUT, Due to the Amplifier DC Offset Voltage, VOS RIN– RSENSE RIN+ –INS +IN + – V– V+ 0.1μF VREG EOUT(VOS) = VOS • (ROUT/RIN) The DC offset voltage of the amplifier adds directly to the value of the sense voltage, VSENSE. This error is very small (3μV typ) and may be ignored for reasonable values of RIN. For very high dynamic range, this offset can be calibrated in the system due to its extremely low drift. –INF LOAD LTC6102 OUT VOUT ROUT RIN+ = RIN– – RSENSE 6102 F04 Figure 4. Second Input R Minimizes Error Due to Input Bias Current 6102fb 11 LTC6102/LTC6102HV APPLICATIONS INFORMATION Clock Feedthrough, Input Bias Current The LTC6102 uses auto-zeroing circuitry to achieve an almost zero DC offset over temperature, sense voltage, and power supply voltage. The frequency of the clock used for auto-zeroing is typically 10kHz. The term clock feedthrough is broadly used to indicate visibility of this clock frequency in the op amp output spectrum. There are typically two types of clock feedthrough in auto zeroed amps like the LTC6102. The first form of clock feedthrough is caused by the settling of the internal sampling capacitor and is input referred; that is, it is multiplied by the internal loop gain of the amp. This form of clock feedthrough is independent of the magnitude of the input source resistance or the magnitude of the gain setting resistors. The LTC6102 has a residue clock feedthrough of less then 1μVRMS input referred at 10kHz. The second form of clock feedthrough is caused by the small amount of charge injection occurring during the sampling and holding of the amp’s input offset voltage. The current spikes are multiplied by the impedance seen at the input terminals of the amp, appearing at the output multiplied by the internal loop gain of the internal op amp. To reduce this form of clock feedthrough, use smaller valued gain setting resistors and minimize the source resistance at the input. Input bias current is defined as the DC current into the input pins of the op amp. The same current spikes that cause the second form of clock feedthrough described above, when averaged, dominate the DC input bias current of the op amp below 70°C. As temperature increases, the leakage of the ESD protection diodes on the inputs increases the input bias currents of both inputs in the positive direction, while the current caused by the charge injection stays relatively constant. At temperatures above 70°C, the leakage current dominates and both the negative and positive pins’ input bias currents are in the positive direction (into the pins). Output Current Limitations Due to Power Dissipation The LTC6102 can deliver more than 1mA continuous current to the output pin. This current flows through RIN and enters the current sense amp via the –INF pin. The power dissipated in the LTC6102 due to the output current is: POUT = (V–INF – VOUT) • IOUT Since V–INF ≈ V+, POUT ≈ (V+ – VOUT) • IOUT There is also power dissipated due to the quiescent supply current: PQ = IS • V+ The total power dissipated is the output current dissipation plus the quiescent dissipation: PTOTAL = POUT + PQ At maximum supply and maximum output current, the total power dissipation can exceed 100mW. This will cause significant heating of the LTC6102 die. In order to prevent damage to the LTC6102, the maximum expected dissipation in each application should be calculated. This number can be multiplied by the θJA value listed in the package section on page 2 to find the maximum expected die temperature. This must not be allowed to exceed 150°C or performance may be degraded. As an example, if an LTC6102 in the MSOP package is to be biased at 55V ±5V supply with 1mA output current at 80°C: PQ(MAX) = IDD(MAX) • V+(MAX) = 39mW POUT(MAX) = IOUT • V+(MAX) = 60mW TRISE = θJA • PTOTAL(MAX) TMAX = TAMBIENT + TRISE TMAX must be < 125°C PTOTAL(MAX) ≈ 99mW and the max die temp will be 110°C If this same circuit must run at 125°C, the max die temp will increase to 155°C. (Note that supply current, and therefore PQ, is proportional to temperature. Refer to Typical Performance Characteristics section.) In this condition, the maximum output current should be reduced to avoid device damage. Note that the DD package has a smaller θJA than the MSOP package, which will substantially reduce the die temperature at similar power levels. 6102fb 12 LTC6102/LTC6102HV APPLICATIONS INFORMATION The LTC6102HV can be used at voltages up to 105V. This additional voltage requires that more power be dissipated for a given level of current. This will further limit the allowed output current at high ambient temperatures. It is important to note that the LTC6102 has been designed to provide at least 1mA to the output when required, and can deliver more depending on the conditions. Care must be taken to limit the maximum output current by proper choice of sense and input resistors and, if input fault conditions are likely, an external clamp. VBAT RSENSE RIN +IN –INS + – –INF LOAD + – 2V) TO V+ (V V– V+ V+ 0.1μF VREG LTC6102 OUT VOUT ROUT Output Filtering 6102 F05 The output voltage, VOUT, is simply IOUT • ZOUT. This makes filtering straightforward. Any circuit may be used which generates the required ZOUT to get the desired filter response. For example, a capacitor in parallel with ROUT will give a low pass response. This will reduce unwanted noise from the output, and may also be useful as a charge reservoir to keep the output steady while driving a switching circuit such as a mux or ADC. This output capacitor in parallel with an output resistor will create a pole in the output response at: f –3dB = 1 Useful Equations Input Voltage: VSENSE =ISENSE • RSENSE Current Gain: VOUT ROUT = VSENSE RIN IOUT ISENSE Transconductance: Transimpedance: = RSENSE RIN IOUT 1 = VSENSE RIN VOUT ISENSE = RSENSE • Input Sense Range The inputs of the LTC6102 can function from V+ to (V+ – 2V). Not only does this allow a wide VSENSE range, it also allows the input reference to be separate from the positive supply (Figure 5). Note that the difference between VBAT and V+ must be no more than the input sense voltage range listed in the Electrical Characteristics table. Monitoring Voltages Above V+ and Level Translation 2 • • ROUT • COUT Voltage Gain: Figure 5. V+ Powered Separately from Load Supply (VBAT) ROUT RIN The LTC6102 may be configured to monitor voltages that are higher than its supply, provided that the negative terminal of the input voltage is within the input sense range of the LTC6102. Figure 6 illustrates a circuit in which the LTC6102 has its supply pin tied to the lower potential terminal of the sense resistor instead of the higher potential terminal. The operation of the LTC6102 is such that the –INS and –INF pins will servo to within a few microvolts of +IN, which is shorted to V+. Since the input sense range of the LTC6102 includes V+, the circuit will operate properly. The voltage across RSENSE will be held across RIN by the LTC6102, causing current VSENSE/RIN to flow to ROUT. In this case, the supply current of the LTC6102 is also monitored, as it flows through RSENSE. 6102fb 13 LTC6102/LTC6102HV APPLICATIONS INFORMATION VBAT RSENSE RIN –INS +IN + – V– LOAD –INF V+ VREG OUT LTC6102 0.1μF VOUT ROUT 6102 F06 Figure 6. LTC6102 Supply Current Monitored with Load Because the voltage across RSENSE is not restricted to the sense range of the LTC6102 in this circuit, VSENSE can be large compared to the allowed sense voltage. This facilitates the sensing of very large voltages, provided that RIN is chosen so that VSENSE/RIN does not exceed the allowed output current. The gain is still controlled by ROUT/RIN, so either gain or attenuation may be applied to the input signal as it is translated to the output. Finally, the input may be a voltage source rather than a sense resistor, as shown in Figure 7. This circuit allows the translation of a wide variety of input signals across the entire supply range of the LTC6102 with only a tiny offset error while retaining simple gain control set by ROUT/RIN. Again, very large voltages may be sensed as long as RIN is chosen so that IOUT does not exceed the allowed output current. For example, VIN may be as large as 1V with RIN = 1k, or as large as 10V with RIN = 10k. For a 10V maximum input and a 5V maximum output, RIN = 10k and ROUT = 5k will allow the LTC6102HV to translate VIN to VOUT with a common mode voltage of up to 100V. For the case where a large input resistor is used, a similar resistor in series with +IN will reduce error due to input bias current. Reverse Supply Current Some applications may be tested with reverse-polarity supplies due to an expectation of this type of fault during operation. The LTC6102 is not protected internally from external reversal of supply polarity. To prevent damage that may occur during this condition, a Schottky diode should be added in series with V– (Figure 8). This will limit the reverse current through the LTC6102. Note that this diode will limit the low voltage performance of the LTC6102 by effectively reducing the supply voltage to the part by VD. RSENSE +IN L O A D V– –INS + – VIN RIN LTC6102 –INS +IN + VCM – D1 –INF –INF V+ VREG V+ R1 100 VBATT 0.1μF OUT R2 4.99k 6102 F08 V– V+ VREG 0.1μF Figure 8. Schottky Prevents Damage During Supply Reversal LTC6102 OUT VOUT ROUT 6102 F07 VOUT = VIN • ROUT RIN In addition, if the output of the LTC6102 is wired to a device that will effectively short it to high voltage (such as through an ESD protection clamp) during a reverse supply condition, the LTC6102’s output should be connected through a resistor or Schottky diode (Figure 9). Figure 7. Voltage Level-Shift Circuit 6102fb 14 LTC6102/LTC6102HV APPLICATIONS INFORMATION Bandwidth RSENSE +IN L O A D –INS + – V– D1 VBATT –INF V+ VREG LTC6102 R1 100 OUT 0.1μF R3 1k ADC R2 4.99k 6102 F09 Figure 9. Additional Resistor R3 Protects Output During Supply Reversal Response Time The LTC6102 is designed to exhibit fast response to inputs for the purpose of circuit protection or signal transmission. This response time will be affected by the external circuit in two ways, delay and speed. If the output current is very low and an input transient occurs, there may be a delay before the output voltage begins changing. This can be reduced by increasing the minimum output current, either by increasing RSENSE or decreasing RIN. The effect of increased output current is illustrated in the step response curves in the Typical Performance Characteristics section of this datasheet. Note that the curves are labeled with respect to the initial output currents. The speed is also affected by the external circuit. In this case, if the input changes very quickly, the internal amplifier will slew the gate of the internal output FET (Figure 1) in order to close the internal loop. This results in current flowing through RIN and the internal FET. This current slew rate will be determined by the amplifier and FET characteristics as well as the input resistor, RIN. Using a smaller RIN will allow the output current to increase more quickly, decreasing the response time at the output. This will also have the effect of increasing the maximum output current. Using a larger ROUT will also decrease the response time, since VOUT = IOUT • ROUT. Reducing RIN and increasing ROUT will both have the effect of increasing the voltage gain of the circuit. For applications that require higher bandwidth from the LTC6102, care must be taken in choosing RIN. For a general-purpose op-amp, the gain-bandwidth product is used to determine the speed at a given gain. Gain is determined by external resistors, and the gain-bandwidth product is an intrinsic property of the amplifier. The same is true for the LTC6102, except that the feedback resistance is determined by an internal FET characteristic. The feedback impedance is approximately 1/gm of the internal MOSFET. The impedance is reduced as current into –INF is increased. At 1mA, the impedance of the MOSFET is on the order of 10kΩ. RIN sets the closed-loop gain of the internal loop as 1/(RIN • gm). The bandwidth is then limited to GBW • (RIN • gm), with a maximum bandwidth of around 2MHz. This is illustrated in the characteristic curves, where gain vs frequency for two input conditions is shown. The exact impedance of the MOSFET is difficult to determine, as it is a function of input current, process, and capacitance, and has a very different characteristic for low currents vs high currents. However, it is clear that smaller values of RIN and smaller values of IOUT will generally result in lower closed-loop bandwidth. VSENSE and RIN should be chosen to maximize both IOUT and closed-loop gain for highest speed. Theoretically, maximum bandwidth would be achieved for the case where VIN = 10VDC and RIN = 10k, giving IOUT = 1mA and a closed-loop gain near 1. However, this may not be possible in a practical application. Note that the MOSFET gm is determined by the average or DC value of IOUT, not the peak value. Adding DC current to a small AC input will help increase the bandwidth. VREG Bypassing The LTC6102 has an internally regulated supply near V+ for internal bias. It is not intended for use as a supply or bias pin for external circuitry. A 0.1μF capacitor should be connected between the VREG and V+ pins. This capacitor should be located very near to the LTC6102 for the best performance. In applications which have large supply transients, a 6.8V zener diode may be used in parallel with this bypass capacitor for additional transient suppression. 6102fb 15 LTC6102/LTC6102HV TYPICAL APPLICATIONS Bidirectional Current Sense Circuit with Separate Charge/Discharge Output IDISCHARGE ICHARGE RSENSE CHARGER RIN C 100 RIN D 100 +IN L O A D RIN D 100 –INS –INF + – V– RIN C 100 –INS –INF V+ – + V+ 0.1μF VREG 0.1μF OUT LTC6102 +IN VREG OUT + ROUT D 4.99k + LTC6102 ROUT C 4.99k VOUT D VOUT C – VBATT V– – 6102 TA02 DISCHARGING: VOUT D = IDISCHARGE • RSENSE CHARGING: VOUT C = ICHARGE • RSENSE ( ( ) ROUT D WHEN IDISCHARGE ≥ 0 RIN D ) ROUT C WHEN ICHARGE ≥ 0 RIN C LTC6102 Monitors Its Own Supply Current ILOAD RSENSE R1 100 +IN L O A D V– ISUPPLY –INS –INF + – V+ VBATT 0.1μF VREG OUT LTC6102 + R2 4.99k VOUT – 6102 TA03 ( ) VOUT = 49.9 • RSENSE ILOAD + ISUPPLY 6102fb 16 LTC6102/LTC6102HV TYPICAL APPLICATIONS 16-Bit Resolution Unidirectional Output into LTC2433 ADC ILOAD VSENSE – + +IN L O A D RIN 100Ω –INS –INF + – V– V+ 0.1μF VREG 4 IN+ REF+ 1 VCC 5 IN– REF– GND 3 ROUT VOUT = • VSENSE = 49.9VSENSE RIN 9 SCK LTC2433-1 ROUT 4.99k 1μF 5V 2 OUT VOUT LTC6102 4V TO 60V 6 8 SDD TO μP 7 CC FO 10 ADC FULL-SCALE = 2.5V 6102 TA05 Intelligent High-Side Switch with Current Monitor 10μF 63V VLOGIC 14V 47k FAULT OFF ON 3 4 0.1μF 100Ω 1% 8 OUT LTC6102 6 2 VREG –INS –INF RS LT1910 V+ 100Ω 1μF 1 VO +IN 4.99k V– 5 SUB85N06-5 L O A D VO = 49.9 • RS • IL IL FOR RS = 5mΩ, VO = 2.5V AT IL = 10A (FULL SCALE) 6102 TA06 6102fb 17 LTC6102/LTC6102HV TYPICAL APPLICATIONS 48V Supply Current Monitor with Isolated Output and 105V Survivability ISENSE VSENSE + VS 48V – LOAD RSENSE RIN –INS +IN –INF – + V+ 0.1μF V– V– 0V VREG LTC6102HV OUT VLOGIC ROUT VOUT ANY OPTOISOLATOR V– N = OPTOISOLATOR CURRENT GAIN R VOUT = VLOGIC – ISENSE • SENSE • N • ROUT RIN 6102 TA07 Simple 500V Current Monitor DANGER! Lethal Potentials Present — Use Caution ISENSE VSENSE – 500V + RSENSE +IN L O A D V– –INS RIN 100Ω –INF + – DANGER!! HIGH VOLTAGE!! V+ VREG 0.1μF OUT LTC6102 51V BZX884-C51 M1 BAT46 VOUT M1 AND M2 ARE FQD3P50 TM ROUT VOUT = • VSENSE = 49.9 VSENSE RIN M2 ROUT 4.99k 2M 6102 TA08 6102fb 18 LTC6102/LTC6102HV PACKAGE DESCRIPTION DD Package 8-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1698) R = 0.115 TYP 5 0.38 ± 0.10 8 0.675 ±0.05 3.5 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) 1.65 ± 0.10 (2 SIDES) 3.00 ±0.10 (4 SIDES) PACKAGE OUTLINE PIN 1 TOP MARK (NOTE 6) (DD) DFN 1203 0.75 ±0.05 0.200 REF 0.25 ± 0.05 4 0.25 ± 0.05 0.50 BSC 2.38 ±0.05 (2 SIDES) 1 0.50 BSC 2.38 ±0.10 (2 SIDES) 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660 Rev F) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 0.254 (.010) 8 7 6 5 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 4.90 ± 0.152 (.193 ± .006) DETAIL “A” 0.52 (.0205) REF 0° – 6° TYP GAUGE PLANE 0.42 ± 0.038 (.0165 ± .0015) TYP 0.65 (.0256) BSC 1 0.53 ± 0.152 (.021 ± .006) RECOMMENDED SOLDER PAD LAYOUT DETAIL “A” 1.10 (.043) MAX 2 3 4 0.86 (.034) REF 0.18 (.007) SEATING PLANE NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.22 – 0.38 (.009 – .015) TYP 0.65 (.0256) BSC 0.1016 ± 0.0508 (.004 ± .002) MSOP (MS8) 0307 REV F 6102fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC6102/LTC6102HV TYPICAL APPLICATION Remote Current Sense with Simple Noise Filter V+ RSENSE TIE AS CLOSE TO RIN AS POSSIBLE RIN– +IN –INS – + fC = 1 2 • π • ROUT • COUT –INF LOAD V– V+ VREG OUT LTC6102 6102 TA09 0.1μF LONG WIRE ADC ROUT COUT REMOTE ADC RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1636 Rail-to-Rail Input/Output, Micropower Op Amp VCM Extends 44V above VEE, 55μA Supply Current, Shutdown Function LT1637/LT1638/ LT1639 Single/Dual/Quad, Rail-to-Rail, Micropower Op Amp VCM Extends 44V above VEE, 0.4V/μs Slew Rate, >1MHz Bandwidth, <250μA Supply Current per Amplifier LT1787/LT1787HV Precision, Bidirectional, High Side Current Sense Amplifier 2.7V to 60V Operation, 75μV Offset, 60μA Current Draw LTC1921 Dual –48V Supply and Fuse Monitor ±200V Transient Protection, Drives Three Optoisolators for Status LT1990 High Voltage, Gain Selectable Difference Amplifier ±250V Common Mode, Micropower, Pin Selectable Gain = 1, 10 LT1991 Precision, Gain Selectable Difference Amplifier 2.7V to ±18V, Micropower, Pin Selectable Gain = –13 to 14 LTC2050/LTC2051/ Single/Dual/Quad Zero-Drift Op Amp LTC2052 3μV Offset, 30nV/°C Drift, Input Extends Down to V– LTC4150 Coulomb Counter/Battery Gas Gauge Indicates Charge Quantity and Polarity LT6100 Gain-Selectable High Side Current Sense Amplifier 4.1V to 48V Operation, Pin-Selectable Gain: 10, 12.5, 20, 25, 40, 50V/V LTC6101/ LTC6101HV High Voltage High Side Current Sense Amplifier in SOT-23 4V to 60V/5V to 100V Operation, External Resistor Set Gain LTC6103 Dual High Side Precision Current Sense Amplifier 4V to 60V, Gain Configurable, 8-Pin MSOP LTC6104 Bidirectional High Side Precision Current Sense Amplifier 4V to 60V, Gain Configurable, 8-Pin MSOP LTC6106 Low Cost, High Side Precision Current Sense Amplifier 2.7V to 36V, Gain Configurable, SOT23 6102fb 20 Linear Technology Corporation LT 1007 REV B • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2007