Data Sheet No. PD60259 ADVANCE INFORMATION IRS2453D(S)PbF SELF-OSCILLATING FULL-BRIDGE DRIVER IC Features Integrated 600V Full-Bridge Gate Driver CT, RT programmable oscillator 15.6V Zener Clamp on VCC Micropower Startup Logic Level Latched Shutdown Pin Non-latched shutdown on CT pin (1/6th VCC) Description The IRS2453D is based on the popular IR2153 self-oscillating half-bridge gate driver IC, and incorporates a high voltage fullbridge gate driver with a front end oscillator similar to the industry standard CMOS 555 timer. HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The output driver features a high pulse current buffer stage designed for minimum driver cross-conduction. Noise immunity is achieved with low di/dt peak of the gate drivers, and with a undervoltage lockout hysteresis greater than 1.5V. The IRS2453D also includes latched and non-latched shutdown pins. Internal bootstrap FETs Excellent Latch Immunity on All Inputs & Outputs ESD Protection on All Pins 14-lead SOIC or PDIP package 1.0 usec (typ.) internal deadtime Package 14 Lead PDIP IRS2453DPbF 14 Lead SOIC (Narrow Body) IRS2453DSPbF Typical Connection Diagram + AC rectified line 1 VCC VB1 14 2 COM HO1 13 3 CT 4 RT 5 SD 6 LO1 7 LO2 IRS2453D 15V VS1 12 NC 11 VB2 10 HO2 9 VS2 8 LOAD - AC rectified line * Please note that this datasheet contains advanced information which could change before the product is released to production. 1 IRS2453DPbF Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Parameter Definition Symbol Min. Max. Units -0.3 625 V High Side Floating Supply Offset Voltage VB - 25 VB + 0.3 V VHO1, VHO2 High-Side Floating Output Voltage VS - 0.3 VB + 0.3 V VLO1, VLO2 Low-Side Output Voltage -0.3 VCC + 0.3 V VRT RT Pin Voltage -0.3 VCC + 0.3 V VCT CT Pin Voltage -0.3 VCC + 0.3 V VSD SD Pin Voltage -0.3 VCC + 0.3 V IRT RT Pin Current -5 5 mA ICC Supply Current (Note 1) --- 25 mA dVS/dt PD Allowable Offset Voltage Slew Rate -50 50 V/ns Maximum Power Dissipation @ TA ≤ +25ºC, 8-Pin DIP --- 1.0 W PD Maximum Power Dissipation @ TA ≤ +25ºC, 8-Pin SOIC --- 0.625 W RθJA Thermal Resistance, Junction to Ambient, 8-Pin DIP --- 125 ºC/W RθJA Thermal Resistance, Junction to Ambient, 8-Pin SOIC --- 200 ºC/W TJ Junction Temperature -55 150 TS Storage Temperature -55 150 TL Lead Temperature (Soldering, 10 seconds) --- 300 VB1, VB2 High Side Floating Supply Voltage VS1, VS2 ºC Note 1: This IC contains a zener clamp structure between the chip VCC and COM which has a nominal breakdown voltage of 15.6V. Please note that this supply pin should not be driven by a DC, low impedance power source greater than the VCLAMP specified in the Electrical Characteristics section. 2 IRS2453DPbF Recommended Operating Conditions For proper operation the device should be used within the recommended conditions. Parameter Definition Symbol Min. Max. Units VCC - 0.7 VCLAMP V -3.0 (Note 2) 600 V Supply Voltage VCCUV+ VCLAMP V ICC Supply Current (Note 3) 5 mA TJ Junction Temperature -25 125 ºC VBS1, VBS2 High Side Floating Supply Voltage VS1, VS2 Steady State High Side Floating Supply Offset Voltage VCC Note 2: Care should be taken to avoid output switching conditions where the VS node flies inductively below ground by more than 5V. Note 3: Enough current should be supplied to the VCC pin of the IC to keep the internal 15.6V zener diode clamping the voltage at this pin. Recommended Component Values Parameter Component Symbol Min. Max. Units RT Timing Resistor Value 1 --- kΩ CT CT Pin Capacitor Value 330 --- pF VBIAS (VCC, VBS) = 14V, VS=0V and TA = 25°C, CLO1=CLO2 = CHO1=CHO2 = 1nF. IRS2453D Frequency vs. RT 1000000 CT Values Frequency (Hz) 100000 330pf 470pF 10000 1nF 2.2nF 1000 4.7nF 10nF 100 10 1000 10000 100000 1000000 RT (Ohm) 3 IRS2453DPbF Electrical Characteristics VBIAS (VCC, VBS) = 14V, CT = 1 nF and TA = 25°C unless otherwise specified. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO. CLO1=CLO2=CHO1=CHO2=1nF. Symbol Definition Min Typ Max Units Test Conditions Low Voltage Supply Characteristics VCCUV+ Rising VCC Undervoltage Lockout Threshold 10.0 11.0 12.0 VCCUV- Falling VCC Undervoltage Lockout Threshold 8.0 9.0 10.0 VCC Undervoltage Lockout Hysteresis 1.6 2.0 2.4 Micropower Startup VCC Supply Current --- 140 200 µA Quiescent VCC Supply Current --- 1.3 2.0 mA 14.6 15.6 16.6 V ICC = 5mA VCC ≤ VCCUV-, VCC = VBS VCCUVHYS IQCCUV IQCC VCLAMP VCC Zener Clamp Voltage V VCC ≤ VCCUV- Floating Supply Characteristics IQBS1UV, Micropower Startup VBS Supply Current --- 3 10 µA IQBS2UV IQBS1, Quiescent VBS Supply Current --- 60 100 µA VBS Supply Undervoltage Positive Going Threshold 8.0 9.0 10.0 V VBS Supply Undervoltage negative Going Threshold 7.0 8.0 9.0 Offset Supply Leakage Current --- --- 50 µA VB = VS = 600V 19.6 20.2 20.8 kHz RT = 36.5kΩ 89 95 101 RT Pin Duty Cycle 48 50 52 % CT Pin Current --- 0.05 1.0 µA ICTUV UV-Mode CT Pin Pulldown Current 1 5 --- mA VCT+ Upper CT Ramp Voltage Threshold --- 9.1 --- VCT- Lower CT Ramp Voltage Threshold --- 4.8 --- VRT+ High-Level RT Output Voltage, VCC - VRT --- 10 50 mV IRT = 100µA --- 100 300 mV IRT = 1mA --- 10 50 mV IRT = 100µA --- 100 300 mV IRT = 1mA --- 0 100 mV VCC ≤ VCCUV- IQBS2 VBS1UV+, VBS2UV+ VBS1UV-, VBS2UV-, ILK1, ILK2 Oscillator I/O Characteristics fOSC d ICT VRTVRTUV Oscillator Frequency Low-Level RT Output Voltage UV-Mode RT Output Voltage RT = 7.15kΩ fo < 100kHz VCC = 7V V 4 IRS2453DPbF Electrical Characteristics VBIAS (VCC, VBS) = 14V, CT = 1 nF and TA = 25°C unless otherwise specified. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO. CLO1=CLO2=CHO1=CHO2=1nF. Symbol Definition Min Typ Max Units Test Conditions Gate Driver Output Characteristics VOH High-Level Output Voltage, VBIAS - VO --- VCC --- IO = 0A VOL Low-Level Output Voltage, VO --- COM --- IO = 0A VOL_UV UV-Mode Output Voltage, VO --- COM --- tr Output Rise Time --- 120 220 tf Output Fall Time --- 50 100 tsd Shutdown Propagation Delay --- 275 --- td Output Deadtime (HO or LO) 0.75 1.0 1.50 IO+ Output source current --- 180 --- IO- Output sink current --- 260 --- IO = 0A, VCC ≤ VCCUV- nsec µsec mA Shutdown VSD Shutdown Threshold at SD pin (latched) --- 2.0 --- V VCTSD CT Voltage Shutdown Threshold (non latched) --- 2.3 --- V --- 10 50 --- 100 300 --- 13.7 --- 30 55 --- VRTSD SD-Mode RT Output Voltage, VCC - VRT mV IRT = 100µA, VCT = 0V mV IRT = 1mA, VCT = 0V Bootstrap FET Characteristics VB1_ON VB when the bootstrap FET is on VB2_ON IB1_CAP VB source current when FET is on IB2_CAP IB1_10V IB2_10V VB source current when FET is on V CBS=0.1uF mA 8 12 --- VB=10V 5 IRS2453DPbF Lead Assignment VB1 14 2 COM HO1 13 3 CT 4 RT 5 SD 6 LO1 IRS2453D 1 VCC VS1 12 NC 11 VB2 10 HO2 9 VS2 8 7 LO2 Lead Definitions Lead Pin Symbol Description 1 VCC Logic and internal gate drive supply voltage 2 COM IC power and signal ground 3 CT Oscillator timing capacitor input 4 RT Oscillator timing resistor input 5 SD Shutdown input 6 LO1 Low-side gate driver output 7 LO2 Low-side gate driver output 8 VS2 High voltage floating supply return 9 HO2 High-side gate driver output 10 VB1 High side gate driver floating supply 11 NC No connect 12 VS1 High voltage floating supply return 13 HO1 High-side gate driver output 14 VB1 High side gate driver floating supply 6 IRS2453DPbF Functional Block Diagram RT 4 14 VB1 R Q HV Level Shift + R R + - S Q DEAD TIME 13 HO1 R PULSE FILTER S 12 VS1 PULSE GEN BOOTSTRAP DRIVE Q R/2 + - CT 3 R/2 SD 5 S Q R1 R2 Q S 2.0V DEAD TIME DELAY 6 LO1 10 VB2 Q R HV Level Shift PULSE GEN UV DETECT Q PULSE FILTER R 9 HO2 S 8 VS2 BOOTSTRAP DRIVE 15.4V DELAY 1 VCC 7 LO2 2 COM All values are typical. 7 IRS2453DPbF Timing Diagram VCCUV+ VCC Fault mode VCT<1/6*VCC 2/3 VCC 1/3 VCC 1/6 VCC VCC LO1 VCC DT LO2 VCC HO1 DT VCC DT HO2 VCC VRT 1mA IRT -1mA 8 IRS2453DPbF Functional Description Under-voltage Lock-Out Mode (UVLO) The under-voltage lockout mode (UVLO) is defined as the state the IC is in when VCC is below the turn-on threshold of the IC. The IRS2453D under voltage lock-out is designed to maintain an ultra low supply current of less than 150uA, and to guarantee the IC is fully functional before the high and low side output drivers are activated. During under voltage lock-out mode, the high and low-side driver outputs LO1, LO2, HO1, HO2 are all low. With VCC above the VCCUV+ threshold, the IC turns on and the output begin to oscillate. Normal operating mode Latched Shutdown When the SD pin is brought above 2V, the IC goes into fault mode and all outputs are low. VCC has to be recycled below VCCUV- to restart the IC. The SD pin can be used for overcurrent or over-voltage protection using appropriate external circuitry. 50% HO1 f ≈ 1 1.453 × RT × CT td_LO1 td_HO1 LO1 50% Once VCC reaches the start-up threshold VCCUV+, the MOSFET M1 opens, RT increases to approximately VCC (VCCVRT+) and the external CT capacitor starts charging. Once the CT voltage reaches VCT- (about 1/3 of VCC), established by an internal resistor ladder, LO1 and HO2 turn on with a delay equivalent to the deadtime td. Once the CT voltage reaches VCT+ (approximately 2/3 of VCC), LO1 and HO2 go low, RT goes down to approximately ground (VRT-), the CT capacitor starts discharging and the deadtime circuit is activated. At the end of the deadtime, LO2 and HO1 go high. Once the CT voltage reaches VCT-, LO2 and HO1 go low, RT goes to high again, the deadtime is activated. At the end of the deadtime, LO1 and HO2 go high and the cycle starts over again. The frequency is best determined by the graph, Frequency vs. RT, Page 3, for different values of CT. A first order approximate of the oscillator frequency can also be calculated by the following formula:: 50% 50% ton_LO 50% Deadtime Waveform Definitions Deadtime waveform tr tf 90% HO LO 10% Rise and fall time waveform This equation can vary slightly from actual measurements due to internal comparator over- and under-shoot delays. Bootstrap MOSFET The internal bootstrap FET and supply capacitor (CBOOT) comprise the supply voltage for the high side driver circuitry. The internal boostrap FET only turns on when the corresponding LO is high. To guarantee that the high-side supply is charged up before the first pulse on HO1 and HO2, LO1 and LO2 are both on when CT ramps between zero and 1/3*VCC. LO1 and LO2 are also on when CT is grounded below 1/6*VCC to ensure that the bootstrap capacitor is charged when CT is brought back over 1/3*VCC. Non-latched Shutdown If CT is pulled down below VCTSD (approximately 1/6 of VCC) by an external circuit, CT doesn’t charge up and oscillation stops. All outputs are held low and the bootstrap FETs are off. Oscillation will resume once CT is able to charge up again to VCT-. 9 IRS2453DPbF IRS2453D IRS2453DS 10 IRS2453DPbF Part number Sxxxxx Date code YWW? Pin 1 Identifier ? P MARKING CODE Lead Free Released Non-Lead Free Released IR logo ?XXXX Lot Code (Prod mode - 4 digit SPN code) Assembly site code Per SCOP 200-002 ORDER INFORMATION 8-lead PDIP: order IRS2453DPbF 8-lead SOICN: order IRS2453DSPbF 8-lead SOICN tape & reel: order IRS2453DSTRPbF Qualification: Industrial, MSL3, lead-free WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. 3/27/2006 11