Sanyo LC87F7LC8A Cmos ic from 128k byte, ram 4096 byte on-chip 8-bit 1-chip microcontroller Datasheet

Ordering number : ENA0835
LC87F7LC8A
CMOS IC
FROM 128K byte, RAM 4096 byte on-chip
8-bit 1-chip Microcontroller
Overview
The SANYO LC87F7LC8A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle
time of 83.3ns, integrates on a single chip a number of hardware features such as 128K-byte flash ROM (onboard
programmable), 4096-byte RAM, an on-chip debugger, a LCD controller/driver, sophisticated 16-bit timer/counter
(may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs),
four 8-bit timers with a prescaler, a 16-bit timer with a prescaler (may be divided into 8-bit timers), a base timer serving
as a time-of-day clock, a day and time counter, a synchronous SIO interface (with automatic block transmission/
reception capabilities), an asynchronous/synchronous SIO interface, a UART interface (full duplex), an 8-bit 15-channel
AD converter, two 12-bit PWM channels, a high-speed clock counter, a system clock frequency divider, a small signal
detector, ROM correction function, remote control receive function, and a 28-source 10-vector interrupt feature.
Features
„Flash ROM
• Capable of on-board-programming with wide range, 3.0 to 5.5V, of voltage source
• Block-erasable in 128byte units
• 131072 × 8 bits (LC87F7LC8A)
„RAM
• 4096 × 9 bits (LC87F7LC8A)
„Minimum Bus Cycle Time
• 83.3ns (12MHz)
VDD=3.0 to 5.5V
• 125ns (8MHz)
VDD=2.5 to 3.0V
• 250ns (4MHz)
VDD=2.2 to 2.5V
Note: The bus cycle time here refers to the ROM read speed.
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by
SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
Ver.0.92
82907HKIM 20070330-S00001 No.A0835-1/25
LC87F7LC8A
„Minimum Instruction Cycle Time (tCYC)
• 250ns (12MHz)
VDD=3.0 to 5.5V
• 375ns (8MHz)
VDD=2.5 to 3.0V
• 750ns (4MHz)
VDD=2.2 to 2.5V
„Ports
• Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1 bit units 27(P1n, P30 to P35, P70 to P73, P8n, XT2)
Ports whose I/O direction can be designated in 4 bit units 8(P0n)
• Normal withstand voltage input port
1(XT1)
• LCD ports
Segment output
48(S00 to S47)
Common output
4(COM0 to COM3)
Bias terminals for LCD driver
3(V1 to V3)
Other functions
Input/output ports
48(PAn, PBn, PCn, PDn, PEn, PFn)
Input ports
7(PLn)
• Dedicated oscillator ports
2(CF1, CF2)
• Reset pin
1(RES)
• Power supply
6(VSS1 to VSS3,VDD1 to VDD3)
„LCD Controller
1) Seven display modes are available (static, 1/2, 1/3, 1/4 duty ×1/2, 1/3 bias)
2) Segment output and common output can be switched to general purpose input/output ports
„Small Signal Detection (MIC signals etc)
1) Counts pulses with the level which is greater than a preset value
2) 2-bit counter
„Timers
• Timer 0: 16-bit timer/counter with two capture registers.
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) × 2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) + 8-bit counter
(with two 8-bit capture registers)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers)
Mode 3: 16-bit counter (with two 16-bit capture registers)
• Timer1: 16-bit timer/counter that supports PWM/toggle outputs
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter with an 8-bit prescaler
(with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from the lower-order 8 bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.)
• Timer4: 8-bit timer with 6-bit prescaler
• Timer5: 8-bit timer with 6-bit prescaler
• Timer6: 8-bit timer with 6-bit prescaler (with toggle output)
• Timer7: 8-bit timer with 6-bit prescaler (with toggle output)
• Timer8: 16-bit timer
Mode 0: 8-bit timer with an 8-bit prescaler ×2 channels (with toggle output)
Mode 1: 16-bit timer with an 8-bit prescaler (with toggle output)
• Base Timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts programmable in 5 different time schemes
• Day and time counter
1) Using with a base timer, it can be used as 65000 day + minute + second counter.
No.A0835-2/25
LC87F7LC8A
„High-speed Clock Counter
1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz).
2) Can generate output real-time.
„SIO
• SIO0: 8-bit synchronous serial interface
1) LSB first/MSB first is selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle=4/3tCYC)
3) Automatic continuous data transmission (1 to 256 bits specifiable in 1 bit units, suspension and resumption of
data transmission possible in 1 byte units)
• SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
„UART
1) Full duplex
2) 7/8/9 bit data bits selectable
3) 1 stop bit (2-bit in continuous data transmission)
4) Built-in baudrate generator
„AD Converter
• 8 bits × 15 channels
„PWM
• Multi frequency 12-bit PWM × 2 channels
„Remote Control Receiver Circuit
1) Noise rejection function (Units of noise rejection filter: about 120μs, when selecting a 32.768kHz
crystal oscillator as a clock)
2) Supporting reception formats with a guide-pulse of half-clock/clock/none.
3) Determines a end of reception by detecting a no-signal periods (No carrier).
(Supports same reception format with a different bit length.)
4) X’tal HOLD mode release function
„Watchdog Timer
1) External RC watchdog timer
2) Interrupt and reset signals selectable
„Clock Output Function
1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock.
2) Able to output oscillation clock of sub clock.
No.A0835-3/25
LC87F7LC8A
„Interrupts
• 28 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests
of the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest
level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest
vector address takes precedence.
No.
Vector Address
Level
Interrupt Source
1
00003H
X or L
INT0
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L/INT4/remote control receiver
4
0001BH
H or L
INT3/base timer/INT5
5
00023H
H or L
T0H/INT6
6
0002BH
H or L
T1L/T1H/INT7
7
00033H
H or L
SIO0/UART1 receive/T8L/T8H
8
0003BH
H or L
SIO1/UART1 transmit
9
00043H
H or L
ADC/MIC/T6/T7/PWM4,5
10
0004BH
H or L
Port 0/T4/T5
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
• IFLG (List of interrupt source flag function)
1) Shows a list of interrupt source flags that caused a branching to a particular vector address (shown in the
diagram above).
„Subroutine Stack Levels
• 2048 levels (the stack is allocated in RAM)
„High-speed Multiplication/Division Instructions
• 16-bits × 8-bits
(5 tCYC execution time)
• 24-bits × 16-bits
(12 tCYC execution time)
• 16-bits ÷ 8-bits
(8 tCYC execution time)
• 24-bits ÷ 16-bits
(12 tCYC execution time)
„Oscillation Circuits
• RC oscillation circuit (internal): For system clock
• CF oscillation circuit:
For system clock, with internal Rf, external Rd
• Crystal oscillation circuit:
For low-speed system clock, with internal Rf, external Rd
• Frequency variable RC oscillation circuit (internal): For system clock
1) Adjustable in ±4% (typ.) step from a selected center frequency.
2) Measures oscillation clock using a input signal from XT1 as a reference.
„System Clock Divider Function
• Can run on low current.
• The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, and
76.8μs (at a main clock rate of 10MHz).
No.A0835-4/25
LC87F7LC8A
„Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
(Some parts of the serial transfer function stops operation.)
1) Oscillation is not halted automatically.
2) Canceled by a system reset or occurrence of an interrupt
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, X’tal, and frequency variable RC oscillators automatically stop operation.
2) There are three ways of resetting the HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer
and the remote control receiver circuit.
1) The CF, RC, and frequency variable RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are five ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established in the base timer circuit
(5) Having an interrupt source established in the remote control receiver circuit
„ROM Correction Function
• Executes the correction program on detection of a match with the program counter value.
• Correction program area size: 128 bytes
„On-chip Debugger
• Supports software debugging with the IC mounted on the target board.
„Package Form
• QIP100E(14×20):
• ΤQFP100(14×14):
Lead-free type
Lead-free type
„Development Tools
• On-chip Debugger: TCB87-TypeA or TCB87-TypeB + LC87F7LC8A
„Flash ROM Programming boards
Package
Programming Boards
QIP100E(14×20)
W87FQ100
TQFP100(14×14)
W87FSQ100
„Flash ROM Programmer
Maker
Flash Support Group, Inc.
(Single)
Model
Supported version (Note)
Device
After 02.54
LC87F75C8A
AF9708/AF9709/AF9709B
(including product of
Ando Electric Co., Ltd.)
AF9723 (Main body)
(including product of
Flash Support Group, Inc.
Ando Electric Co., Ltd.)
(Gang)
AF9833 (Unit)
(including product of
After 02.03D
LC87F5JC8A
After 01.82G
Ando Electric Co., Ltd.)
Application Version
SANYO
SKK (SANYO FWS)
1.03
Chip Data Version
LC87F7LC8A
2.05
Note: Please check the latest version.
No.A0835-5/25
LC87F7LC8A
Package Dimensions
unit : mm (typ)
3151A
23.2
0.8
20.0
51
50
100
31
14.0
81
1
17.2
80
30
0.65
0.15
0.3
0.1
3.0max
(2.7)
(0.58)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Pin Assignment
V3/PL6/AN14/DBGP2
S47/PF7
S46/PF6
S45/PF5
S44/PF4
S43/PF3
S42/PF2
S41/PF1
S40/PF0
S39/PE7
S38/PE6
S37/PE5
S36/PE4
S35/PE3
S34/PE2
S33/PE1
S32/PE0
S31/PD7
S30/PD6
S29/PD5
S28/PD4
S27/PD3
S26/PD2
S25/PD1
S24/PD0
VSS2
VDD2
S23/PC7
S22/PC6
S21/PC5
SANYO : QIP100E(14X20)
LC87F7LC8A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P06/T6O
P07/T7O
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
P16/T1PWML
P17/T1PWMH/BUZ
RES
XT1/AN10
XT2/AN11
VSS1
CF1
CF2
VDD1
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7/MICIN
P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
P72/INT2/T0IN/NKIN
P73/INT3/T0IN/RMIN
S0/PA0
V2/PL5/AN13/DBGP1
V1/PL4/AN12/DBGP0
COM0/PL0
COM1/PL1
COM2/PL2
COM3/PL3
P30/INT4/T1IN/INT6/T0LCP1/PWM4
P31/INT4/T1IN/PWM5
VSS3
VDD3
P32/INT4/T1IN/UTX1
P33/INT4/T1IN/URX1
P34/INT5/T1IN/INT7/T0HCP1
P35/INT5/T1IN
P00
P01
P02/T8LO
P03/T8HO
P04
P05/CKO
S20/PC4
S19/PC3
S18/PC2
S17/PC1
S16/PC0
S15/PB7
S14/PB6
S13/PB5
S12/PB4
S11/PB3
S10/PB2
S9/PB1
S8/PB0
S7/PA7
S6/PA6
S5/PA5
S4/PA4
S3/PA3
S2/PA2
S1/PA1
Top view
SANYO: QIP100E(14×20) “Lead-free Type”
No.A0835-6/25
LC87F7LC8A
Package Dimensions
unit : mm (typ)
3274
75
0.5
16.0
14.0
51
50
100
26
14.0
16.0
76
1
0.5
0.2
25
0.125
1.2max
0.1
(1.0)
(1.0)
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Pin Assignment
S46/PF6
S45/PF5
S44/PF4
S43/PF3
S42/PF2
S41/PF1
S40/PF0
S39/PE7
S38/PE6
S37/PE5
S36/PE4
S35/PE3
S34/PE2
S33/PE1
S32/PE0
S31/PD7
S30/PD6
S29/PD5
S28/PD4
S27/PD3
S26/PD2
S25/PD1
S24/PD0
VSS2
VDD2
SANYO : TQFP100(14X14)
LC87F7LC8A
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
S23/PC7
S22/PC6
S21/PC5
S20/PC4
S19/PC3
S18/PC2
S17/PC1
S16/PC0
S15/PB7
S14/PB6
S13/PB5
S12/PB4
S11/PB3
S10/PB2
S9/PB1
S8/PB0
S7/PA7
S6/PA6
S5/PA5
S4/PA4
S3/PA3
S2/PA2
S1/PA1
S0/PA0
P73/INT3/T0IN/RMIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
P16/T1PWML
P17/T1PWMH/BUZ
RES
XT1/AN10
XT2/AN11
VSS1
CF1
CF2
VDD1
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7/MICIN
P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
P72/INT2/T0IN/NKIN
S47/PF7
V3/PL6/AN14/DBGP2
V2/PL5/AN13/DBGP1
V1/PL4/AN12/DBGP0
COM0/PL0
COM1/PL1
COM2/PL2
COM3/PL3
P30/INT4/T1IN/INT6/T0LCP1/PWM4
P31/INT4/T1IN/PWM5
VSS3
VDD3
P32/INT4/T1IN/UTX1
P33/INT4/T1IN/URX1
P34/INT5/T1IN/INT7/T0HCP1
P35/INT5/T1IN
P00
P01
P02/T8LO
P03/T8HO
P04
P05/CKO
P06/T6O
P07/T7O
P10/SO0
Top view
SANYO: TQFP100(14×14) “Lead-free Type”
No.A0835-7/25
LC87F7LC8A
System Block Diagram
Interrupt control
IR
PLA
ROM correct
Standby control
Flash ROM
RC
VMRC
Clock
generator
CF
PC
X’tal
SIO0
Bus interface
ACC
SIO1
Port 0
B register
Timer 0
(High speed clockcounter)
Port 1
C register
Timer 1
Port 3
ALU
Base timer
Port 7
LCD controller
Port 8
PSW
INT0 to 7
Noise rejection filter
ADC
RAR
Timer 4
Small signal
detector
RAM
Timer 5
Timer 6
Stack pointer
UART1
Timer 7
Watchdog timer
PWM4/5
Timer 8
On-chip debugger
Remote control
receiver circuit
Day and time
counter
No.A0835-8/25
LC87F7LC8A
Pin Description
Pin Name
VSS1
VSS2
VSS3
VDD1
I/O
Description
Option
-
- power supply pin
No
-
+ power supply pin
No
• 8-bit I/O port
Yes
VDD2
VDD3
Port 0
I/O
• I/O specifiable in 4-bit units
P00 to P07
• Pull-up resistors can be turned on and off in 4-bit units.
• Input for HOLD release
• Input for port 0 interrupt
• Shared pins
P02: Timer 8L toggle output
P03: Timer 8H toggle output
P05: Clock output (system clock/can selected from sub clock)
P06: Timer 6 toggle output
P07: Timer 7 toggle output
Port 1
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
P10 to P17
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins
P10: SIO0 data output
P11: SIO0 data input/bus I/O
P12: SIO0 clock I/O
P13: SIO1 data output
P14: SIO1 data input/bus I/O
P15: SIO1 clock I/O
P16: Timer 1PWML output
P17: Timer 1PWMH output/beeper output
Port 3
P30 to P35
I/O
Yes
• 6-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins
P30 to P33: INT4 input/HOLD release input/timer 1 event input/timer 0L capture input/
timer 0H capture input
P34 to P35: INT5 input/HOLD release input/timer 1 event input/timer 0L capture input/
timer 0H capture input
P30: PWM4 output/INT6 input/timer 0L capture 1 input
P31: PWM5 output
P32: UART1 transmit
P33: UART1 receive
P34: INT7 input/timer 0H capture 1 input
Interrupt acknowledge type
Rising
Falling
INT4
enable
enable
INT5
enable
enable
INT6
enable
INT7
enable
Rising &
H level
L level
enable
disable
disable
enable
disable
disable
enable
enable
disable
disable
enable
enable
disable
disable
Falling
Continued on next page.
No.A0835-9/25
LC87F7LC8A
Continued from preceding page.
Pin Name
Port 7
I/O
I/O
Description
Option
No
• 4-bit I/O port
• I/O specifiable in 1-bit units
P70 to P73
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins
P70: INT0 input/HOLD release input/timer 0L capture input/watchdog timer output
P71: INT1 input/HOLD release input/timer 0H capture input
P72: INT2 input/HOLD release input/timer 0 event input/timer 0L capture input/
high speed clock counter input
P73: INT3 input (with noise filter)/timer 0 event input/timer 0H capture input/
remote control receiver input
AD converter input ports: AN8 (P70), AN9 (P71)
Interrupt acknowledge type
Port 8
I/O
Rising
Falling
INT0
enable
enable
INT1
enable
enable
INT2
enable
INT3
enable
Rising &
H level
L level
disable
enable
enable
disable
enable
enable
enable
enable
disable
disable
enable
enable
disable
disable
Falling
• 8-bit I/O port
No
• I/O specifiable in 1-bit units
P80 to P87
• Shared pins
AD converter input ports: AN0 (P80) to AN7 (P87)
Small signal detector input port: MICIN (P87)
S0/PA0 to
I/O
S7/PA7
S8/PB0 to
I/O
I/O
I/O
I/O
I/O
• Segment output for LCD
No
• Segment output for LCD
No
• Segment output for LCD
No
• Can be used as general-purpose I/O port (PF)
I/O
COM3/PL3
V1/PL4 to
No
• Can be used as general-purpose I/O port (PE)
S47/PF7
COM0/PL0 to
• Segment output for LCD
• Can be used as general-purpose I/O port (PD)
S39/PE7
S40/PF0 to
No
• Can be used as general-purpose I/O port (PC)
S31/PD7
S32/PE0 to
• Segment output for LCD
• Can be used as general-purpose I/O port (PB)
S23/PC7
S24/PD0 to
No
• Can be used as general-purpose I/O port (PA)
S15/PB7
S16/PC0 to
• Segment output for LCD
• Common output for LCD
No
• Can be used as general-purpose input port (PL)
I/O
V3/PL6
• LCD output bias power supply
No
• Can be used as general-purpose input port (PL)
• Shared pins
AD converter input ports: AN12 (V1) to AN14 (V3)
On-chip debugger pins: DBGP0 (V1) to DBGP2 (V3)
RES
Input
Reset pin
No
XT1
Input
• 32.768kHz crystal oscillator input pin
No
• Shared pins
General-purpose input port
Must be connected to VDD1 if not to be used.
AD converter input port: AN10
XT2
I/O
• 32.768kHz crystal oscillator output pin
No
• Shared pins
General-purpose I/O port
Must be set for oscillation and kept open if not to be used.
AD converter input port: AN11
CF1
Input
CF2
Output
Ceramic resonator input pin
No
Ceramic resonator output pin
No
No.A0835-10/25
LC87F7LC8A
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode
Port Name
P00 to P07
P10 to P17
P30 to P35
Option Selected
in Units of
each bit
each bit
each bit
Option Type
Output Type
Pull-up Resistor
1
CMOS
Programmable (Note)
2
Nch-open drain
No
1
CMOS
Programmable
2
Nch-open drain
Programmable
1
CMOS
Programmable
2
Nch-open drain
Programmable
Programmable
P70
-
No
Nch-open drain
P71 to P73
-
No
CMOS
Programmable
P80 to P87
-
No
Nch-open drain
No
S0/PA0 to S47/PF7
-
No
CMOS
Programmable
COM0/PL0 to
-
No
Input only
No
No
COM3/PL3
V1/PL4 to V3/PL6
-
No
Input only
XT1
-
No
Input for 32.768kHz crystal
No
oscillator (Input only)
XT2
-
No
Output for 32.768kHz crystal oscillator
(Nch-open drain when in general-purpose
No
output mode)
Note 1: Programmable pull-up resistors for port 0 are controlled in 4 bit units (P00 to 03, P04 to 07).
*1: Connect the IC as shown below to minimize the noise input to the VDD1 pin.
Be sure to electrically short the VSS1, VSS2, and VSS3 pins.
LSI
VDD1
Power
supply
For backup *2
VDD2
VDD3
VSS1 VSS2
VSS3
*2: The internal memory is sustained by VDD1. If none of VDD2 and VDD3 are backed up, the high level output at
the ports are unstable in the HOLD backup mode, allowing through current to flow into the input buffer and thus
shortening the backup time.
Make sure that the port outputs are held at the low level in the HOLD backup mode.
No.A0835-11/25
LC87F7LC8A
Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
Maximum supply
VDD max
VDD1, VDD2, VDD3
VDD1=VDD2=VDD3
V1/PL4, V2/PL5,
VDD1=VDD2=VDD3
voltage
supply voltage for
VLCD
LCD
V3/PL6
Input voltage
VI(1)
Port L
XT1, CF1, RES
Input/output voltage
VIO(1)
min
typ
max
-0.3
+6.5
-0.3
VDD
-0.3
VDD+0.3
-0.3
VDD+0.3
unit
V
Ports 0, 1, 3, 7, 8
Ports A, B, C, D, E, F
XT2
Peak output
IOPH(1)
Ports 0, 1, 32 to 35
current
• CMOS output selected
• Current at each pin
IOPH(2)
Ports 30, 31
• CMOS output selected
High level output current
• Current at each pin
Mean output
-20
IOPH(3)
Ports 71 to 73
Current at each pin
-5
IOPH(4)
Ports A, B, C, D, E, F
Current at each pin
-5
IOMH(1)
Ports 0, 1, 32 to 35
• CMOS output selected
current
(Note 1-1)
-10
• Current at each pin
IOMH(2)
Ports 30, 31
• CMOS output selected
• Current at each pin
-7.5
-15
IOMH(3)
Ports 71 to 73
Current at each pin
IOMH(4)
Ports A, B, C, D, E, F
Current at each pin
Total output
ΣIOAH(1)
Ports 0, 1, 32 to 35
Total of all pins
-25
current
ΣIOAH(2)
Ports 30, 31
Total of all pins
-25
ΣIOAH(3)
Ports 0, 1, 3
Total of all pins
-45
ΣIOAH(4)
Ports 71 to 73
Total of all pins
-5
ΣIOAH(5)
Ports A, B, C
Total of all pins
-25
ΣIOAH(6)
Ports D, E, F
Total of all pins
-25
ΣIOAH(7)
Ports A, B, C, D, E, F
Total of all pins
-45
Peak output
IOPL(1)
Ports 0, 1, 32 to 35
Current at each pin
20
current
IOPL(2)
Ports 30, 31
Current at each pin
30
IOPL(3)
Ports 7, 8
Current at each pin
-3
-3
10
XT2
Low level output current
mA
IOPL(4)
Ports A, B, C, D, E, F
Current at each pin
10
Mean output
IOML(1)
Ports 0, 1, 32 to 35
Current at each pin
15
current
IOML(2)
Ports 30, 31
Current at each pin
20
Ports 7, 8
Current at each pin
(Note 1-1)
IOML(3)
7.5
XT2
IOML(4)
Ports A, B, C, D, E, F
Current at each pin
7.5
Total output
ΣOAL(1)
Ports 0,1,32 to 35
Total of all pins
45
current
ΣIOAL(2)
Ports 30, 31
Total of all pins
45
ΣIOAL(3)
Ports 0, 1, 3
Total of all pins
80
ΣIOAL(4)
Ports 7, 8
Total of all pins
20
XT2
Power dissipation
Operating ambient
ΣIOAL(5)
Ports A, B, C
Total of all pins
45
ΣIOAL(6)
Ports D, E, F
Total of all pins
45
ΣIOAL(7)
Ports A, B, C, D, E, F
Total of all pins
Pd max
QIP100E(14×20)
Ta=-20 to +70°C
461
TQFP100(14×14)
Ta=-20 to +70°C
331
Topr
temperature
Storage ambient
Tstg
temperature
80
-20
+70
-55
+125
mW
°C
Note 1-1: The mean output current is a mean value measured over 100ms.
No.A0835-12/25
LC87F7LC8A
Allowable Operating Conditions at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
Operating
supply voltage
(Note 2-1)
Memory
VDD(1)
VDD1=VDD2=VDD3
0.237μs≤tCYC≤200μs
min
3.0
typ
max
unit
5.5
VDD(2)
0.356μs≤tCYC≤200μs
2.5
5.5
VDD(3)
0.712μs≤tCYC≤200μs
2.2
5.5
2.0
5.5
0.3VDD
VDD
VHD
VDD1
sustaining
RAM and register contents
sustained in HOLD mode.
supply voltage
High level input
VIH(1)
voltage
Ports 0, 3, 8
Output disabled
Ports A, B, C, D, E, F
2.2 to 5.5
Port L
VIH(2)
Port 1
• Output disabled
Ports 71 to 73
• When INT1VTSL=0
P70 port input/
(P71 only)
2.2 to 5.5
+0.7
0.3VDD
VDD
+0.7
interrupt side
VIH(3)
P71 interrupt side
• Output disabled
• When INT1VTSL=1
VIH(4)
P87 small signal
Output disabled
input side
VIH(5)
P70 watchdog timer
Output disabled
side
VIH(6)
Low level input
VIL(1)
voltage
XT1, XT2, CF1, RES
Ports 0, 3, 8
Output disabled
Ports A, B, C, D, E, F
Port L
VIL(2)
Port 1
• Output disabled
Ports 71 to 73
• When INT1VTSL=0
P70 port input/
(P71 only)
interrupt side
VIL(3)
P71 interrupt side
• Output disabled
• When INT1VTSL=1
VIL(4)
P87 small signal
Output disabled
input side
VIL(5)
P70 watchdog timer
Output disabled
side
VIL(6)
Instruction cycle
XT1, XT2, CF1, RES
tCYC
time
(Note 2-2)
External system
clock frequency
FEXCF(1)
CF1
2.2 to 5.5
0.85VDD
VDD
2.2 to 5.5
0.75VDD
VDD
2.2 to 5.5
0.9VDD
VDD
2.2 to 5.5
0.75VDD
4.0 to 5.5
VSS
2.2 to 4.0
VSS
4.0 to 5.5
VSS
2.2 to 4.0
VSS
0.2VDD
2.2 to 5.5
VSS
0.45VDD
2.2 to 5.5
VSS
0.25VDD
2.2 to 5.5
VSS
2.2 to 5.5
VSS
0.25VDD
3.0 to 5.5
0.237
200
2.5 to 5.5
0.356
200
V
VDD
0.15VDD
+0.4
0.2VDD
0.1VDD
+0.4
0.8VDD
-1.0
2.2 to 5.5
0.712
200
• CF2 pin open
3.0 to 5.5
0.1
12
• System clock frequency
2.5 to 5.5
0.1
8
2.2 to 5.5
0.1
4
μs
division ratio=1/1
• External system clock
MHz
duty=50±5%
• CF2 pin open
3.0 to 5.5
0.2
24.4
• System clock frequency
2.5 to 5.5
0.2
16
2.2 to 5.5
0.2
8
division ratio=1/2
Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a
division ratio of 1/2.
Continued on next page.
No.A0835-13/25
LC87F7LC8A
Continued from preceding page.
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
Oscillation
FmCF(1)
CF1, CF2
frequency range
(Note 2-3)
• 12MHz ceramic oscillation
• See Fig. 1.
FmCF(2)
CF1, CF2
• 8MHz ceramic oscillation
• See Fig. 1.
FmCF(3)
CF1, CF2
• 4MHz ceramic oscillation
• See Fig. 1.
FmRC
Internal RC oscillation
FmVMRC(1)
• Frequency variable RC
min
typ
max
3.0 to 5.5
12
2.5 to 5.5
8
2.2 to 5.5
4
2.2 to 5.5
0.3
1.0
unit
2.0
source oscillation
MHz
• When
VMRAJ2 to 0=4,
2.2 to 5.5
10
2.2 to 5.5
4
2.2 to 5.5
32.768
VMFAJ2 to 0=0,
VMSL4M=0
FmVMRC(2)
• Frequency variable RC
source oscillation
• When
VMRAJ2 to 0=4,
VMFAJ2 to 0=0,
VMSL4M=1
FsX’tal
XT1, XT2
• 32.768kHz crystal oscillation
• See Fig. 2.
Frequency
OpVMRC(1)
When VMSL4M=0
variable RC
OpVMRC(2)
When VMSL4M=1
oscillation
kHz
2.2 to 5.5
8
10
12
2.2 to 5.5
3.5
4
4.5
2.2 to 5.5
8
24
64
2.2 to 5.5
1
4
8
MHz
usable range
Frequency
VmADJ(1)
Each step of VMRAJn
variable RC
oscillation
(Wide range)
VmADJ(2)
%
Each step of VMFAJn
adjustment
(Small range)
range
Note 2-3: See Tables 1 and 2 for the oscillation constants.
Electrical Characteristics at Ta = -20°C to +70°C, VSS1 = VSS2= VSS3= 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
High level input
IIH(1)
current
Ports 0, 1, 3, 7, 8
• Output disabled
Ports A, B, C, D, E,
• Pull-up resistor off
F
• VIN=VDD (Including output Tr's
Port L
typ
max
unit
2.2 to 5.5
1
2.2 to 5.5
1
2.2 to 5.5
1
15
off leakage current)
IIH(2)
RES
VIN=VDD
IIH(3)
XT1, XT2
• For input port specification
• VIN=VDD
Low level input
min
IIH(4)
CF1
VIN=VDD
2.2 to 5.5
IIH(5)
P87 small signal
4.5 to 5.5
4.2
8.5
15
input side
VIN=VBIS+0.5V
(VBIS: Bias voltage)
2.2 to 4.5
1.5
5.5
10
Ports 0, 1, 3, 7, 8
• Output disabled
Ports A, B, C, D, E,
• Pull-up resistor off
F
• VIN=VSS (Including output Tr's
2.2 to 5.5
-1
2.2 to 5.5
-1
2.2 to 5.5
-1
IIL(1)
current
Port L
off leakage current)
IIL(2)
RES
VIN=VSS
IIL(3)
XT1, XT2
• For input port specification
• VIN=VSS
IIL(4)
CF1
VIN=VSS
2.2 to 5.5
-15
IIL(5)
P87 small signal
VIN=VBIS-0.5V
(VBIS: Bias voltage)
4.5 to 5.5
-15
-8.5
-4.2
2.2 to 4.5
-10
-5.5
-1.5
input side
μA
Continued on next page.
No.A0835-14/25
LC87F7LC8A
Continued from preceding page.
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
High level output
VOH(1)
voltage
min
typ
IOH=-1mA
4.5 to 5.5
VDD-1
VOH(2)
IOH=-0.4mA
3.0 to 5.5
VDD-0.4
VOH(3)
IOH=-0.2mA
2.2 to 5.5
VDD-0.4
IOH=-10mA
4.5 to 5.5
VDD-1.5
VOH(5)
IOH=-1.6mA
3.0 to 5.5
VDD-0.4
VOH(6)
IOH=-1mA
2.2 to 5.5
VDD-0.4
IOH=-0.4mA
3.0 to 5.5
VDD-0.4
IOH=-0.2mA
2.2 to 5.5
VDD-0.4
VOH(4)
VOH(7)
Ports 0, 1, 32 to 35
Ports 30, 31
Ports 71 to 73
VOH(8)
VOH(9)
Ports A, B, C, D, E,
IOH=-1mA
4.5 to 5.5
VDD-1
VOH(10)
F
IOH=-0.4mA
3.0 to 5.5
VDD-0.4
VDD-0.4
max
IOH=-0.2mA
2.2 to 5.5
Low level output
VOL(1)
Ports 0, 1, 32 to 35
IOL=10mA
4.5 to 5.5
1.5
voltage
VOL(2)
Ports 30, 31
IOL=1.6mA
3.0 to 5.5
0.4
IOL=1mA
2.2 to 5.5
0.4
IOL=30mA
4.5 to 5.5
1.5
VOH(11)
VOL(3)
output mode)
VOL(4)
Port 30, 31
VOL(5)
(Port function
VOL(6)
LCD output voltage
(PWM function
output mode)
IOL=5mA
3.0 to 5.5
0.4
IOL=2.5mA
2.2 to 5.5
0.4
VOL(7)
Ports 7, 8
IOL=1.6mA
3.0 to 5.5
0.4
VOL(8)
XT2
IOL=1mA
2.2 to 5.5
0.4
VOL(9)
Ports A, B, C, D, E,
IOL=1.6mA
3.0 to 5.5
0.4
VOL(10)
F
IOL=1mA
2.2 to 5.5
0.4
VODLS
S0 to S47
• IO=0mA
regulation
• VLCD, 2/3VLCD, 1/3VLCD
level output
2.2 to 5.5
0
±0.2
2.2 to 5.5
0
±0.2
unit
V
• See Fig. 8.
VODLC
COM0 to COM3
• IO=0mA
• VLCD, 2/3VLCD, 1/2VLCD,
1/3VLCD level output
• See Fig. 8.
LCD bias resistor
RLCD(1)
Resistance per
See Fig. 8.
one bias resister
RLCD(2)
Resistance per
2.2 to 5.5
60
2.2 to 5.5
30
See Fig. 8.
one bias resister
kΩ
1/2R mode
Resistance of
Rpu(1)
Ports 0, 1, 3, 7
pull-up MOS Tr.
Rpu(2)
Ports A, B, C, D, E,
VOH=0.9VDD
F
Hysterisis voltage
VHYS(1)
Ports 1, 7
RES
VHYS(2)
P87 small signal
CP
All pins
15
35
80
2.2 to 5.5
18
50
150
2.2 to 5.5
0.1VDD
2.2 to 5.5
0.1VDD
2.2 to 5.5
10
V
input side
Pin capacitance
4.5 to 5.5
• For pins other than that under test:
VIN=VSS
• f=1MHz
pF
• Ta=25°C
Input sensitivity
Vsen
P87 small signal
input side
2.2 to 5.5
0.12VDD
Vp-p
No.A0835-15/25
LC87F7LC8A
Serial I/O Characteristics at Ta = -20°C to +70°C, VSS1 = VSS2= VSS3= 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Parameter
Symbol
Pin/Remarks
Specification
Conditions
Input clock
VDD[V]
Frequency
tSCK(1)
Low level
tSCKL(1)
SCK0(P12)
See Fig. 6.
tSCKH(1)
2.2 to 5.5
pulse width
tSCKHA(1)
tCYC
4
• (Note 4-1-2)
Frequency
tSCK(2)
SCK0(P12)
• CMOS output selected
4/3
• See Fig. 6.
Output clock
Low level
tSCKL(2)
1/2
pulse width
High level
tSCK
tSCKH(2)
2.2 to 5.5
pulse width
tSCKHA(2)
1/2
• Continuous data
transmission/reception mode
tSCKH(2)
• CMOS output selected
+2tCYC
• See Fig. 6.
Data setup time
Serial input
unit
1
• Continuous data
transmission/reception mode
tsDI(1)
SB0(P11),
SI0(P11)
tSCKH(2)
+(10/3)
tCYC
tCYC
• Must be specified with
respect to rising edge of
2.2 to 5.5
0.03
2.2 to 5.5
0.03
SIOCLK.
Data hold time
Input clock
Output
• See Fig. 6.
thDI(1)
tdD0(1)
delay time
SO0(P10),
SB0(P11)
• Continuous data
transmission/reception mode
2.2 to 5.5
• (Note 4-1-3)
tdD0(2)
• Synchronous 8-bit mode
• (Note 4-1-3)
tdD0(3)
Output clock
Serial output
max
1
• See Fig. 6.
Serial clock
typ
2
pulse width
High level
min
2.2 to 5.5
(1/3)tCYC
+0.05
μs
1tCYC
+0.05
(Note 4-1-3)
2.2 to 5.5
(1/3)tCYC
+0.05
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is
"H" to the first negative edge of the serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of
output state change in open drain output mode. See Fig. 6.
No.A0835-16/25
LC87F7LC8A
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Parameter
Symbol
Pin/Remarks
Specification
Conditions
Input clock
Frequency
tSCK(3)
Low level
tSCKL(3)
SCK1(P15)
See Fig. 6.
Frequency
SCK1(P15)
• CMOS output selected
tSCKL(4)
1
2
2.2 to 5.5
pulse width
High level
1/2
tSCK
tSCKH(4)
1/2
pulse width
Serial input
Data setup time
tsDI(2)
SB1(P14),
SI1(P14)
• Must be specified with
respect to rising edge of
2.2 to 5.5
0.03
2.2 to 5.5
0.03
SIOCLK.
Data hold time
Output delay time
• See Fig. 6.
thDI(2)
tdD0(4)
SO1(P13),
SB1(P14)
Serial output
unit
1
• See Fig. 6.
Low level
max
tCYC
tSCKH(3)
tSCK(4)
typ
2
2.2 to 5.5
pulse width
High level
min
pulse width
Output clock
Serial clock
VDD[V]
• Must be specified with
μs
respect to falling edge of
SIOCLK.
• Must be specified as the
time to the beginning of
2.2 to 5.5
(1/3)tCYC
+0.05
output state change in
open drain output mode.
• See Fig. 6.
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
No.A0835-17/25
LC87F7LC8A
Pulse Input Conditions at Ta = -20°C to +70°C, VSS1 = VSS2= VSS3= 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
High/low
tPIH(1)
INT0(P70),
• Interrupt source flag can be set.
level pulse
tPIL(1)
INT1(P71),
• Event inputs for timer 0 or 1 are
width
INT2(P72),
min
typ
max
unit
enabled.
INT4(P30 to P33),
2.2 to 5.5
1
2.2 to 5.5
2
2.2 to 5.5
64
2.2 to 5.5
256
2.2 to 5.5
1
2.2 to 5.5
4
INT5(P34 to P35),
INT6(P30),
INT7(P34)
tPIH(2)
INT3(P73) when noise filter
• Interrupt source flag can be set.
tPIL(2)
time constant is 1/1
• Event inputs for timer 0 are enabled.
tPIH(3)
INT3(P73) when noise filter
• Interrupt source flag can be set.
tPIL(3)
time constant is 1/32
• Event inputs for timer 0 are enabled.
tPIH(4)
INT3(P73) when noise filter
• Interrupt source flag can be set.
tPIL(4)
time constant is 1/128
• Event inputs for timer 0 are enabled.
tPIH(5)
MICIN(P87)
tPIL(5)
tPIH(6)
Condition that signal is accepted to
small signal detection counter.
RMIN(P73)
tPIL(6)
tCYC
Condition that signal is accepted to
remote control receiver circuit.
RMCK
(Note
5-1)
tPIL(7)
RES
Resetting is enabled.
2.2 to 5.5
μs
200
Note 5-1: RMCK is an unit for the base clock (40tCYC/50tCYC/Sub-Clock) of remote control receiver circuit.
AD Converter Characteristics at Ta = -20°C to +70°C, VSS1 = VSS2= VSS3= 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
Resolution
N
AN0(P80) to
Absolute
ET
AN7(P87),
Conversion
(Note 6-1)
AN8(P70),
accuracy
tCAD
time
typ
AN9(P71),
AD conversion time=32×tCYC
AN10(XT1),
(When ADCR2=0) (Note 6-2)
4.5 to 5.5
AN12(V1),
AN13(V2),
3.0 to 5.5
AN14(V3)
AD conversion time=64×tCYC
(When ADCR2=1) (Note 6-2)
4.5 to 5.5
3.0 to 5.5
VAIN
3.0 to 5.5
voltage range
Analog port
IAINH
VAIN=VDD
3.0 to 5.5
input current
IAINL
VAIN=VSS
3.0 to 5.5
max
unit
8
3.0 to 5.5
AN11(XT2),
Analog input
min
3.0 to 5.5
bit
±1.5
15.20
100.80
(tCYC=
(tCYC=
0.475µs)
3.15µs)
22.78
100.80
(tCYC=
(tCYC=
0.712µs)
3.15µs)
18.24
100.80
(tCYC=
(tCYC=
0.285µs)
1.57µs)
45.56
100.80
(tCYC=
(tCYC=
0.712µs)
1.57µs)
VSS
VDD
1
LSB
μs
V
μA
-1
Note 6-1: The quantization error (±1/2 LSB) is excluded from the absolute accuracy value.
Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till
the complete digital value corresponding to the analog input value is loaded in the required register.
No.A0835-18/25
LC87F7LC8A
Consumption Current Characteristics at Ta = -20°C to +70°C, VSS1 = VSS2= VSS3= 0V
Parameter
Symbol
Pin/
Remarks
VDD[V]
• FmCF=12MHz ceramic oscillation mode
consumption
VDD1
=VDD2
current
=VDD3
• System clock set to 12MHz side
Normal mode
(Note 7-1)
IDDOP(1)
IDDOP(2)
Specification
Conditions
• FmX’tal=32.768kHz crystal oscillation mode
min
typ
max
4.5 to 5.5
8.7
22
3.0 to 3.6
5
12.5
4.5 to 5.5
6.6
16.5
3.0 to 3.6
3.8
9.6
2.5 to 3.0
2.5
7.4
4.5 to 5.5
2.5
6.3
3.0 to 3.6
1.4
3.5
2.2 to 3.0
0.9
2.7
4.5 to 5.5
0.75
3.1
3.0 to 3.6
0.4
1.7
2.2 to 3.0
0.28
1.35
4.5 to 5.5
8
20
3.0 to 3.6
4.7
12
4.5 to 5.5
4.5
11.5
3.0 to 3.6
2.6
6.6
2.2 to 3.0
1.7
5
4.5 to 5.5
35
115
3.0 to 3.6
18
65
2.2 to 3.0
12
46
unit
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
IDDOP(3)
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
IDDOP(4)
• System clock set to 8MHz side
• Internal RC oscillation stopped.
IDDOP(5)
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
IDDOP(6)
• FmCF=4MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
IDDOP(7)
• System clock set to 4MHz side
• Internal RC oscillation stopped.
IDDOP(8)
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
IDDOP(9)
• FmCF=0Hz (oscillation stopped)
mA
• FmX’tal=32.768kHz crystal oscillation mode
IDDOP(10)
IDDOP(11)
• System clock set to internal RC oscillation
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
IDDOP(12)
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768 kHz crystal oscillation mode
• Internal RC oscillation stopped.
IDDOP(13)
• System clock set to 10MHz wifh frequency
variable RC oscillation
• 1/1 frequency division ratio
IDDOP(14)
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
IDDOP(15)
• Internal RC oscillation stopped.
• System clock set to 4MHz wifh frequency
IDDOP(16)
variable RC oscillation
• 1/1 frequency division ratio
IDDOP(17)
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
IDDOP(18)
• System clock set to 32.768kHz side
• Internal RC oscillation stopped.
IDDOP(19)
μA
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
Continued on next page.
No.A0835-19/25
LC87F7LC8A
Continued from preceding page.
Parameter
Symbol
Pin/
VDD[V]
HALT mode
consumption
VDD1
=VDD2
current
=VDD3
• FmX’tal=32.768kHz crystal oscillation mode
HALT mode
(Note 7-1)
IDDHALT(1)
Specification
Conditions
Remarks
• FmCF=12MHz ceramic oscillation mode
min
typ
max
4.5 to 5.5
3.6
8.2
3.0 to 3.6
2
4.6
4.5 to 5.5
2.6
5.9
3.0 to 3.6
1.4
3.3
2.5 to 3.0
1
2.5
4.5 to 5.5
1.15
2.65
3.0 to 3.6
0.6
1.5
2.2 to 3.0
0.4
1.1
unit
• System clock set to 12MHz side
IDDHALT(2)
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
HALT mode
IDDHALT(3)
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
IDDHALT(4)
• System clock set to 8 MHz side
• Internal RC oscillation stopped.
IDDHALT(5)
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
HALT mode
IDDHALT(6)
• FmCF=4MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
IDDHALT(7)
• System clock set to 4MHz side
• Internal RC oscillation stopped.
IDDHALT(8)
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
HALT mode
IDDHALT(9)
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
IDDHALT(10)
• System clock set to internal RC oscillation
mA
4.5 to 5.5
0.37
1.3
3.0 to 3.6
0.2
0.75
2.2 to 3.0
0.13
0.54
4.5 to 5.5
3.6
8.2
3.0 to 3.6
2
4.6
4.5 to 5.5
1.7
4
3.0 to 3.6
1
2.5
2.2 to 3.0
0.7
1.8
4.5 to 5.5
18.5
68
3.0 to 3.6
10
38
2.2 to 3.0
6.5
26
4.5 to 5.5
0.05
20
12
• Frequency variable RC oscillation stopped.
IDDHALT(11)
• 1/2 frequency division ratio
IDDHALT(12)
HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• Internal RC oscillation stopped.
IDDHALT(13)
• System clock set to 10MHz with frequency
variable RC oscillation
• 1/1 frequency division ratio
HALT mode
IDDHALT(14)
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
IDDHALT(15)
• Internal RC oscillation stopped.
• System clock set to 4MHz with frequency
IDDHALT(16)
variable RC oscillation
• 1/1 frequency division ratio
HALT mode
IDDHALT(17)
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
IDDHALT(18)
• System clock set to 32.768kHz side
• Internal RC oscillation stopped.
IDDHALT(19)
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
HOLD mode
IDDHOLD(1)
consumption
IDDHOLD(2)
current
IDDHOLD(4)
mode
IDDHOLD(5)
current
IDDHOLD(6)
HOLD mode
• CF1=VDD or open
3.0 to 3.6
0.03
2.2 to 3.0
0.02
8
Timer HOLD mode
4.5 to 5.5
16
58
• CF1=VDD or open
3.0 to 3.6
8.5
32
2.2 to 3.0
5
20
(External clock mode)
IDDHOLD(3)
Timer HOLD
consumption
VDD1
VDD1
μA
(External clock mode)
• FmX’tal=32.768kHz crystal oscillation mode
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
No.A0835-20/25
LC87F7LC8A
F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = VSS2= VSS3= 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
Onboard
IDDFW(1)
VDD1
programming
min
typ
max
unit
• 128-byte programming
• Erasing current included
3.0 to 5.5
25
40
mA
3.0 to 5.5
22.5
45
ms
current
Programming
tFW(1)
• 128-byte programming
time
• Erasing current included
• Time for setting up 128-byte data is
excluded.
UART (Full Duplex) Operating Conditions at Ta = +20°C to +70°C, VSS1 = VSS2= VSS3= 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
Transfer rate
UBR
UTX(S32),
2.2 to 5.5
URX(S33)
min
typ
16/3
max
unit
8192/3
tCYC
Data length: 7/8/9 bits (LSB first)
Stop bits:
1 bit (2-bit in continuous data transmission)
Parity bits: None
Example of 8-bit Data Transmission Mode Processing (Transmit Data=55H)
Start bit
Start of
transmission
Stop bit
Transmit data (LSB first)
End of
transmission
UBR
Example of 8-bit Data Reception Mode Processing (Receive Data=55H)
Stop bit
Start bit
Start of
reception
Receive data (LSB first)
End of
reception
UBR
No.A0835-21/25
LC87F7LC8A
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a
SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values
with which the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Nominal
Frequency
12MHz
8MHz
4MHz
Circuit Constant
Vendor Name
MURATA
MURATA
MURATA
Oscillator Name
Operating
Oscillation
Voltage
Stabilization Time
Remarks
C1
C2
Rf1
Rd1
Range
typ
max
[pF]
[pF]
[Ω]
[Ω]
[V]
[ms]
[ms]
CSTCE12M0G52-R0
(10)
(10)
Open
470
3.0 to 5.5
0.05
0.15
CSTCE8M00G52-R0
(10)
(10)
Open
2.2k
2.7 to 5.5
0.05
0.15
Internal
CSTLS8M00G53-B0
(15)
(15)
Open
680
2.5 to 5.5
0.05
0.15
C1, C2
Internal
C1, C2
CSTCR4M00G53-R0
(15)
(15)
Open
3.3k
2.2 to 5.5
0.05
0.15
Internal
CSTLS4M00G53-B0
(15)
(15)
Open
3.3k
2.2 to 5.5
0.05
0.15
C1, C2
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD
goes above the operating voltage lower limit (see Fig. 4).
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with
which the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillation Circuit with a Crystal Oscillation
Nominal
Frequency
32.768kHz
Vendor Name
SEIKO EPSON
Circuit Constant
Oscillator
Name
MC-306
Operating
Oscillation
Voltage
Stabilization Time
C3
C4
Rf2
Rd2
Range
typ
max
[pF]
[pF]
[Ω]
[Ω]
[V]
[s]
[s]
18
18
Open
560k
2.2 to 5.5
1.4
3.0
Remarks
Applicable
CL value=12.5pF
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the
oscillation to get stabilized after the HOLD mode is reset (see Fig. 4).
Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible
because they are vulnerable to the influences of the circuit pattern.
CF1
XT1
CF2
XT2
Rf2
Rf1
Rd1
C1
C2
C3
Rd2
C4
X’tal
CF
Figure 1 CF Oscillator Circuit
Figure 2 XT Oscillator Circuit
0.5VDD
Figure 3 AC Timing Measurement Point
No.A0835-22/25
LC87F7LC8A
VDD
Operating VDD
lower limit
0V
Power supply
Reset time
RES
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
Operating mode
Unpredictable
Reset
Instruction execution
Reset Time and Oscillation Stabilizing Time
HOLD reset signal
HOLD reset signal
absent
HOLD reset signal VALID
Internal RC oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
State
HOLD
HALT
HOLD Release Signal and Oscillation Stable Time
Figure 4 Oscillation Stabilizing Times
No.A0835-23/25
LC87F7LC8A
VDD
RRES
Note:
Determine the value of CRES and RRES so that the reset
signal is present for a period of 200μs after the supply
voltage goes beyond the lower limit of the IC's operating
voltage.
RES
CRES
Figure 5 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DI7
DI8
DO7
DO8
Data RAM
transfer period
(SIO0 only)
tSCK
tSCKH
tSCKL
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Data RAM
transfer period
(SIO0 only)
tSCKL
tSCKHA
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Figure 6 Serial I/O Waveforms
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
No.A0835-24/25
LC87F7LC8A
VDD
SW: ON/OFF (programmable)
RLCD
RLCD
SW: ON (VLCD=VDD)
RLCD
RLCD
VLCD
RLCD
RLCD
2/3 VLCD
RLCD
1/2 VLCD
RLCD
1/3 VLCD
RLCD
RLCD
GND
Figure 8 LCD bias resistor
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
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Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
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intellctual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of March, 2007. Specifications and information herein are subject
to change without notice.
PS No.A0835-25/25