MK2308-2 ZERO DELAY, LOW SKEW BUFFER Description Features The MK2308-2 is a low jitter, low skew, high performance Phase-Lock Loop (PLL) based zero delay buffer for high speed applications. Based on ICS’ proprietary low jitter PLL techniques, the device provides eight low skew outputs at speeds up to 160 MHz at 3.3 V. The MK2308-2 includes a bank of four outputs running at 1/2X. In the zero delay mode, the rising edge of the input clock is aligned with the rising edges of all eight outputs. Compared to competitive CMOS devices, the MK2308-2 has the lowest jitter. • • • • • • • Packaged in 16-pin SOIC Zero input-output delay Four 1X outputs plus four 1/2X outputs Output to output skew is less than 250 ps Output clocks up to 160 MHz at 3.3 V Ability to generate 2X the input Full CMOS outputs with 18 mA output drive capability at TTL levels at 3.3 V • Spread SmartTM technology works with spread spectrum clock generators • Advanced, low power, sub micron CMOS process • Operating voltage of 3.3 V or 5 V Block Diagram VDD 2 CLKA1 FBIN CLKA2 PLL CLKIN CLKA3 BANK A CLKA4 /2 CLKB1 CLKB2 S2, S1 2 Control Logic CLKB3 BANK B CLKB4 2 GND 1 MDS 2308-2 B I n t e gra te d C i r c u i t S y s t e m s ● 525 Race Stre et, San Jo se, CA 9 5126 Revision 111103 ● te l (40 8) 2 97-12 01 ● w w w. i c st . c o m MK2308-2 ZERO DELAY, LOW SKEW BUFFER Pin Assignment Feedback Configuration Table CLKIN 1 16 FBIN CLKA1 2 15 CLKA4 CLKA2 3 14 CLKA3 VDD 4 13 VDD GND 5 12 GND CLKB1 6 11 CLKB4 CLKB2 7 10 CLKB3 S2 8 9 Feedback From Bank A Bank B CLKA1:A4 CLKIN 2XCLKIN CLKB1:B4 CLKIN/2 CLKIN S1 16-pin (150 mil) SOIC Output Clock Mode Select Table S2 0 0 1 1 S1 0 1 0 1 Clocks A1:A4 Tri-state (high impedance) Running Running Running Clocks B1:B4 Tri-state (high impedance) Tri-state (high impedance) Running Running Internet Generation None PLL Buffer only (no zero delay) PLL PLL Status On On Off On Pin Descriptions Pin Number Pin Name Pin Type 1 CLKIN Input 2-3 CLKA1:A4 Output Clock A bank of four outputs. 4 VDD Power Power supply. Connect pin to same voltage as pin 13 (either 3.3 V or 5 V). 5 GND Power Connect to ground. 6-7 CLKB1:B4 Output Clock B bank of four outputs. These are low skew divide by two of bank A. 8 S2 Input Select input 2. Selects mode for outputs per table above. 9 S1 Input Select input 1. Selects mode for outputs per table above. 10 - 11 CLKB1:B4 Output Clock B bank of four outputs. These are low skew divide by two of bank A. 12 GND Power Connect to ground. 13 VDD Power Power supply. Connect pin to same voltage as pin 4 (either 3.3 V or 5 V). 14 - 15 CLKA1:A4 Output Clock A bank of four outputs. 16 FBIN Input Clock input. Connect to input clock source. Feedback input. Determines outputs per table above. 2 MDS 2308-2 B In te grated Circuit Systems Pin Description ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 111103 ● tel (4 08) 297-1 201 ● w w w. i c s t . c o m MK2308-2 ZERO DELAY, LOW SKEW BUFFER External Components The MK2308-2 requires a minimum number of external components for proper operation. Decoupling capacitors of 0.1µF should be connected between VDD and GND, as close to the part as possible. A 33Ω series terminating resistor should be used on each clock output to reduce reflections. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK2308-2. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature 0 to +70 °C Storage Temperature -65 to +150 °C Junction Temperature 175 °C Soldering Temperature 260 °C Recommended Operation Conditions Parameter Min. Max. Units 0 +70 °C +3.0 +5.5 V Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Typ. DC Electrical Characteristics VDD=3.3 V ±10%, Temp 0 to +70° /-40 to +85° C Parameter Symbol Conditions Operating Voltage VDD Input High Voltage VIH CLKIN pin only Input Low Voltage VIL CLKIN pin only Input High Voltage VIH Input Low Voltage VIL Output High Voltage VOH IOH = -18 mA Output Low Voltage VOL IOL = 18 mA Output High Voltage VOH IOH = -5 mA Typ. 3.0 (VDD/2)+1 ● Max. Units 5.5 V VDD/2 VDD/2 V (VDD/2)-1 2 0.8 525 Ra ce Street, San Jose, CA 9512 6 V V 2.4 V V 0.4 VDD-0.4 V V 3 MDS 2308-2 B In te grated Circuit Systems Min. Revision 111103 ● tel (4 08) 297-1 201 ● w w w. i c s t . c o m MK2308-2 ZERO DELAY, LOW SKEW BUFFER Parameter Symbol Conditions Operating Supply Current 100 MHz, CLKIN IDD No Load S1=S2=1 Short Circuit Current IOS Input Capacitance CIN Min. Typ. Max. Units 44 mA Each output ± 65 mA S1, S1, FBIN 7 pF AC Electrical Characteristics VDD = 3.3V ±10%, Temp 0 to +70°/ -40 to +85° C Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency FBIN to CLKA1 S1=S2=1 20 160 MHz Output Frequency FBIN to CLKA1 S1=S2=1 20 160 MHz Output Rise Time tOR 0.8 to 2.0 V, CL=30 pF 1.5 ns Output Fall Time tOF 0.8 to 2.0 V, CL=30 pF 1.5 ns 60 % Output Clock Duty Cycle at 1.4V 40 Device to Device skew, equally loaded rising edges at VDD/2 700 ps Output to Output skew, equally loaded rising edges at VDD/2 200 ps Maximum Absolute Jitter 50 300 Cycle to Cycle Jitter ps 30 pF loads 66.67 MHz outputs 400 ps 15 pF loads 66.67 MHz outputs 400 ps Skew from Output Bank A to Output Bank B All outputs equally loaded 400 ps Delay CLKIN Rising Edge to FBIN Rising Edge measured at VDD/2 ±250 ps 1 ms PLL Lock Time tLOCK Stable power supply, valid clocks on CLKIN, FBIN Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Conditions Min. Typ. Max. Units θJA Still air 120 °C/W θJA 1 m/s air flow 115 °C/W θJA 3 m/s air flow 105 °C/W 58 °C/W θJC 4 MDS 2308-2 B In te grated Circuit Systems Symbol ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 111103 ● tel (4 08) 297-1 201 ● w w w. i c s t . c o m MK2308-2 ZERO DELAY, LOW SKEW BUFFER Package Outline and Package Dimensions (16-pin SOIC, 150 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 16 Symbol E Min A A1 B C D E e H h L α H INDEX AREA 1 2 D A Inches Max Min 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0° 8° Max .0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .3859 .3937 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0° 8° h x 45 A1 C -Ce SEATING PLANE B L .10 (.004) C Ordering Information Part / Order Number Marking Shipping packaging Package Temperature MK2308S-2 MK2308S-2 Tubes 16-pin SOIC 0 to 70° C MK2308S-2T MK2308S-2T Tape and Reel 16-pin SOIC 0 to 70° C MK2308S-2I MK2308S-2I Tubes 16-pin SOIC -40 to +85° C MK2308S-2IT MK2308S-2IT Tape and Reel 16-pin SOIC -40 to +85° C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 5 MDS 2308-2 B In te grated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 111103 ● tel (4 08) 297-1 201 ● w w w. i c s t . c o m