Infineon HYB25D128323CL-3.6 128 mbit ddr sgram Datasheet

Data Sheet, V1.7, July 2003
HYB25D128323C[-3/-3.3]
HYB25D128323C[-3.6/L3.6]
HYB25D128323C[-4.5/L4.5]
HYB25D128323C-5
128 Mbit DDR SGRAM
Memory Products
N e v e r
s t o p
t h i n k i n g .
Edition 2003-07
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2003.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet, V1.7, July 2003
HYB25D128323C[-3/-3.3]
HYB25D128323C[-3.6/L3.6]
HYB25D128323C[-4.5/L4.5]
HYB25D128323C-5
128 Mbit DDR SGRAM
Memory Products
N e v e r
s t o p
t h i n k i n g .
HYB25D128323C[-3/-3.3], HYB25D128323C[-3.6/L3.6], HYB25D128323C[-4.5/L4.5], HYB25D128323C-5
Revision History:
V1.7
2003-07
Previous Version:
V1.51
2002-07
Page
Subjects (major changes since last revision)
all
new data sheet template
43
AC Operation Conditions: Input Slew Rate added
46
Timing Parameters for speed sorts –3, –3.3, –3.6, –4.5, and –5: Write DQS High/Low added
48
Timing Parameters for speed sorts L3.6 and L4.5: Write DQS High/Low added
Previous Version:
9, 13, 42, 46,
48
V1.51
2002-07
extended VDD range for –3.6 and L3.6
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
[email protected]
Template: mp_a4_v2.0_2003-06-06.fm
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
3.1
3.2
3.3
3.3.1
3.4
3.4.1
3.4.2
3.4.3
3.4.3.1
3.4.3.2
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.5.6
3.5.7
3.5.8
3.5.9
3.5.10
3.5.11
3.5.12
3.5.13
3.5.14
3.5.15
3.5.16
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.6.6
3.7
3.8
3.9
Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Mode Register Setup (EMRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal and Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Special Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Inputs and Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Strobe and Data Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation at Burst Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation at Burst Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description of Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Register Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Mode Register Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bank Activation Command (ACT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Precharge Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Auto Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Burst Read Operation: (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Burst Write Operation (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Burst Stop Command (BST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Mask (DMx) Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Autoprecharge Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read with Autoprecharge (READA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write with Autoprecharge (WRITEA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Burst Interruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Interrupted by a Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Interrupted by a Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Interrupted by a Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Interrupted by a Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Interrupted by a Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Interrupted by a Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operations and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Function Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DDR SGRAM Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Data Sheet
5
15
15
16
16
16
17
17
17
17
17
18
20
20
20
20
21
21
22
23
23
24
24
25
26
27
28
28
30
31
31
32
33
33
34
34
35
36
41
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Data Sheet
Ball Out 128Mbit DDR SGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Register Bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Mode Register Bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command and Address Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DQS Timing for Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DQS and DM Timing at Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DQS Pre/Postamble at Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Up Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Register Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Activate to Read or Write Command Timing (one bank) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Activate Bank A to Activate Bank B Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Precharge Command Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Self Refresh timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Autorefresh timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Down Mode timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Burst Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Burst Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Burst Stop for Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Mask Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Burst with Autoprecharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Burst with Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read interrupted by Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read interrupted by Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read interrupted by Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write interrupted by Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write interrupted by Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write interrupted by Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DDR SGRAM Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
11
14
15
16
17
18
19
19
20
20
21
21
22
23
23
24
25
26
27
28
29
30
31
32
32
33
33
34
35
41
43
52
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Data Sheet
7
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Data Sheet
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Signal and Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
IO Driver Strength and Interface Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Mapping of DQSx and DMx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Precharge Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Burst Mode and Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Concurrent Read Auto Precharge Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Concurrent Write Auto Precharge Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Command Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Function Truth Table I. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Function Truth Table for CKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Power & DC Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
AC Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Timing Parameters for speed sorts –3, –3.3, –3.6, –4.5, and –5 . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Timing Parameters for speed sorts L3.6 and L4.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
HYB25D128323C–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
HYB25D128323C–3.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
HYB25D128323C–3.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
HYB25D128323C–4.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
HYB25D128323C–5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
HYB25D128323CL3.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
HYB25D128323CL4.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8
V1.7, 2003-07
128 Mbit DDR SGRAM
1
Overview
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
HYB25D128323C[-3/-3.3]
HYB25D128323C[-3.6/L3.6]
HYB25D128323C[-4.5/L4.5]
HYB25D128323C-5
Maximum clock frequency up to 333 MHz
Maximum data rate up to 666 Mbps/pin
Data transfer on both edges of clock
Programmable CAS latency of 2, 3 and 4 clocks
Programmable burst length of 2, 4 and 8
Integrated DLL to align DQS and DQ transitions with CLK
Data transfer signals are synchronized with byte wise bidirectional Data Strobe
Data Strobe signal edge-aligned with data for Read operations
Data Strobe signal center aligned with data for Write operations
Differential clock inputs (CLK and CLK)
Data mask for masking write data, one DM per byte
Organization 1024K × 32 × 4 banks
4096 rows and 256 columns per bank
4K Refresh (32ms)
Refresh Interval 7.8 µsec
Autorefresh and Self Refresh available
Standard JEDEC TF-XBGA 128 package
Self-mirrored, symmetrical ball out
Matched Impedance Mode interface (Z0=60Ω)
SSTL-2 JEDEC Weak Mode interface (Z0=34Ω)
IO voltage VDDQ = 2.5 V
VDD power supply memory core:
– Speed sorts –3 and –3.3: 2.5 V < VDD < 2.9 V
– Speed sorts L4.5, –4.5, and –5: VDD = 2.5 V
– Speed sorts L3.6 and –3.6 support both VDD modes
Table 1
Performance
Part Number Speed Code
CAS Latency 4
CAS Latency 3
Data Out Window
DQS-DQ Skew
1.2
tCK4min.
fCK4max.
tCK3min.
fCK3max.
tQH
tDQSQ
–3
–3.3
–3.6
–4.5
–5.0
L3.6
L4.5
Unit
3
3.3
3.6
4.5
5.0
3.6
4.5
ns
333
300
278
222
200
278
222
MHz
4.0
4.0
4.2
4.5
5.0
4.2
4.5
ns
250
250
238
222
200
238
222
MHz
1.05
1.15
1.26
1.58
1.75
1.26
1.58
ns
0.30
0.30
0.33
0.45
0.5
0.33
0.45
ns
Description
The Infineon 128Mbit DDR SGRAM is a ultra high performance graphics memory device, designed to meet all
requirements for high bandwidth intensive applications like PC graphics systems.
The 128Mbit DDR SGRAM uses a double-data-rate DRAM architecture organized as 4 banks × 4096 rows × 256
columns × 32 bits. The double-data-rate architecture is essentially a 2n prefetch architecture, with an interface
designed to transfer two data words per clock cycle at the I/O pins. A single Read or Write access to the DDR
Data Sheet
9
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Overview
SGRAM consists of a single 64-bit wide, one clock cycle data transfer at the internal DRAM core and two
corresponding 32-bit wide, one-half clock cycle data transfers at the I/O pins. The result is a data rate of 666 Mbits
/ sec per pin. The external data interface is 32 bit wide and achieves at 333 MHz system clock a peak bandwidth
of 2.66 Gigabytes/sec.
The device is supplied with 2.5 V resp. within the range of 2.5 V - 2.9 V for the memory core and 2.5 V for the
output drivers. Two drivers strengths are available: 2.5 V Matched Impedance Mode and SSTL2 Weak Mode. The
“Matched Impedance Mode” interface is optimized for high frequency digital data transfers and matches the
impedance of graphics board systems (60Ohm).
Auto Refresh and Self Refresh operations are both supported.
A standard JEDEC TF-XBGA 128 package is used which enables ultra high speed clock and data transfer rates.
The signals are mapped symmetrically to the balls in order to enable mirrored mounting in application.
The chip is fabricated in Infineon technologies advanced 256M process technology.
Data Sheet
10
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Pin Configuration
2
Pin Configuration
1
Figure 1
2
3
4
5
6
7
8
9
10
11
12
A
DQS0
DM0
VSSQ
DQ3
DQ2
DQ0
DQ31
DQ29
DQ28
VSSQ
DM3
DQS3
B
DQ4
VDDQ
NC
VDDQ
DQ1
VDDQ
VDDQ
DQ30
VDDQ
NC
VDDQ
DQ27
C
DQ6
DQ5
VSSQ
VSSQ
VSSQ
VDD
VDD
VSSQ
VSSQ
VSSQ
DQ26
DQ25
D
DQ7
VDDQ
VDD
VSS
VSSQ
VSS
VSS
VSSQ
VSS
VDD
VDDQ
DQ24
E
DQ17
DQ16
VDDQ
VSSQ
VSSQ
VDDQ
DQ15
DQ14
F
DQ19
DQ18
VDDQ
VSSQ
TOP VIEW
128 BALL XBGA
VSSQ
VDDQ
DQ13
DQ12
G
DQS2
DM2
NC
VSSQ
4 Banks x 4096 Rows
x 256 Columns x 32 Bits
VSSQ
NC
DM1
DQS1
H
DQ21
DQ20
VDDQ
VSSQ
VSSQ
VDDQ
DQ11
DQ10
J
DQ22
DQ23
VDDQ
VSSQ
VSS
VSS
VSS
VSS
VSSQ
VDDQ
DQ9
DQ8
K
CAS# WE#
VDD
VSS
A10
VDD
VDD
RFU
VSS
VDD
NC
NC
L
RAS#
NC
NC
BA1
A2
A11
A9
A5
RFU
CLK
CLK#
MCL
M
CS#
NC
BA0
A0
A1
A3
A4
A6
A7
A8/AP
CKE
VREF
Ball Out 128Mbit DDR SGRAM
Note: The inner matrix of 4 × 4 balls will be used as thermal VSS contacts ncluding the thermal VSS contacts, the
total amount of balls is 144
Data Sheet
11
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Pin Configuration
Table 2
Signal and Pin Description
Pin
IO Type Detailed Function
CLK, CLK
Input
Clock: CLK and CLK# are differential clock inputs. All address and command inputs
are latched on the crossing of the positive edge of CLK and the negative edge of CLK.
Output data (DQ’s and DQS) is referenced to the crossing of CLK and CLK.
CKE
Input
Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock,
input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWERDOWN and SELF REFRESH operations (all banks idle), or ACTIVE POWER-DOWN
(row active in any bank). CKE is synchronous for POWER-DOWN entry and exit, and
for SELF REFRESH entry. CKE is asynchronous for SELF-REFRESH exit. CKE must
be maintained HIGH trough out READ and WRITE accesses. Input buffers (excluding
CLK, CLK) are disabled during POWER-DOWN. Input buffers (excluding CKE) are
disabled during SELF REFRESH. CKE is an SSTL2 input but will detect an LVCMOS
LOW level after VDD is applied.
CS
Input
Chip Select: CS# enables the command decoder when low and disables it when high.
When the command decoder is disabled, new commands are ignored, but internal
operations continue. CS# is considered part of the command code.
RAS, CAS, WE Input
Command Inputs: CAS, RAS, and WE (along with CS) define the command to be
executed.
BA1, BA0
Input
Bank Address Inputs: BA0 and BA1 select to which internal bank an ACTIVE, READ,
WRITE, or PRECHARGE command is being applied. They also define which mode
register (mode register or extended mode register) is loaded during a MODE
REGISTER SET command.
A11.. A0
Input
Address Inputs: During a Bank Activate command cycle, A0-A11 defines the row
address (RA0-RA11). During a Read or Write command cycle, A0-A7 defines the
column address (CA0-CA7).
In addition to the column address, A8/AP is used to invoke autoprecharge operation
at the end of the burst read or write cycle. If A8 is high, the active bank is precharged.
If A8 is low, the Autoprecharge function is disabled.
During a Precharge command cycle, A8/AP is used to determine, which bank(s) will
be precharged. If A8/AP is high, all four banks will be precharged regardless of the
state of BA0 and BA1. If A8/AP is low, BA0 and BA1 define the bank to be precharged.
The address inputs also provide the op-code during a MODE REGISTER SET
command.
DQS3.. DQS0
I/O
Data Strobes: The DQSx are the bidirectional strobe signals. At read cycles, the
DQSx signals are generated by the SGRAM and are edge-aligned to the data. At write
cycles, the DQS signals are generated by the controller. The rising or falling edge
indicates the center of the data valid window. Before and after a transfer cycle, DQSx
enters a preamble and a postamble state. The DQSx signals are mapped to the
following data bytes: DQS0 to DQ0.. DQ7, DQS1 to DQ8.. DQ15, DQS2 to
DQ16..DQ23, DQS3 to DQ24.. DQ31.
DQ31.. DQ0
I/O
Data Input/Output: The DQx signals form the 32 bit wide data bus. At READ cycles
the pins are outputs and during WRITE cycles inputs. The data is transferred at both
edges of the DQSx signals.
Data Sheet
12
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Pin Configuration
Table 2
Signal and Pin Description (cont’d)
Pin
IO Type Detailed Function
DM3.. DM0
Input
Input Data Mask: The DM signals are input mask signal for WRITE data. They mask
off a complete byte on the data bus. DMx = 1 prevents the corresponding byte from
being written. DM3 corresponds to DQ31..DQ24, DM2 to DQ23..DQ16, DM1 to
DQ15..DQ8, DM0 to DQ7..DQ0. DM signals are sampled on both edges of DQS.
Although DM pins are input-only, the DM loading is designed to match that of DQ and
DQS pins.
VREF
Input
Voltage Reference: VREF is the reference voltage input signal.
VDD, VSS
Supply
Power Supply: Power and Ground for the internal logic.
VDD = 2.5 V ± 5% for L4.5, –4.5, and -5
2.5 V – 5% < VDD < 2.9 V for –3.6 and L3.6
2.5 V < VDD < 2.9 V for –3 and –3.3
VDDQ, VSSQ
Supply
IO Power Supply: Isolated Power and Ground for the output buffers to provide
improved noise immunity. VDDQ = 2.5V ± 5%
NC, RFU
–
Please do not connect No Connect, Reserved for Future Use pins.
MCL
–
Must be connected to low
Data Sheet
13
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Pin Configuration
Row Addresses A11-A0, BA1-BA0
Column Address Buffer
Refresh Counter
Column Addresses A7-A0, AP
Row Address Buffer
4096 x 256
x 32 bit
Figure 2
Data Sheet
4096 x 256
x 32 bit
Control Logic & Timing Generator
DQS0
DM0
DQ7-DQ0
Data
DQ15-DQ8
Data
DM2
DQS2
DQ23-DQ16
Data
DQS3
DM3
Data
DQ31-DQ24
Bank 2
Row Decoder
Memory
Array
Bank 3
4096 x 256
x 32 bit
Output Buffers
DM1
Input Buffers
Memory
Array
Column Decoder
Bank 1
Row Decoder
Sense Amplifiers and Data Bus Buffer
Column Decoder
4096 x 256
x 32 bit
Memory
Array
Sense Amplifiers and Data Bus Buffer
Bank 0
Row Decoder
DQS1
Memory
Array
Column Decoder
Row Decoder
Sense Amplifiers and Data Bus Buffer
Column Decoder
Sense Amplifiers and Data Bus Buffer
Column Address Counter
CLK
CLK#
CKE
CS#
RAS#
CAS#
WE#
Vref
Functional blocks
14
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
3
Register Set
3.1
Mode Register
The mode register stores the data for controlling the various operating modes of the DDR SGRAM. It programs
CAS latency, addressing mode, burst length, test mode, DLL ON and various vendor specific options. The default
value of the mode register is not defined. Therefore the mode register must be written after power up to operate
the DDR SGRAM. The DDR SGRAM should be activated with CKE already high prior to writing into the Mode
Register. The Mode Register is written by using the MRS command. The state of the address signals registered
in the same cycle as MRS command is written in the mode register. The value can be changed as long as all banks
are in the idle state.
The mode register is divided into various fields depending on functionality. The burst length uses A2.. A0, CAS
latency (read latency from column address) uses A6.. A4. A7 is used for test mode, A8 is used for DLL Reset. A7,
A8 and BA1 must be set to low for normal DDR SGRAM operation. A9.. A11 is reserved for future use. BA0 selects
Extended Mode Register Setup operation when set to 1. Refer to the table for specific codes for various burst
length, addressing modes and CAS latencies.
BA1
BA0
A11
A10
A9
A8
A7
0
0
RFU
RFU
RFU
DLL
TM
Extended Mode
Register Access
BA0
A6
A5
A4
A3
CAS Latency
BT
A7
0
Mode Register
1
Extend. Mode Reg.
DLL Reset
A8
A1
A0
Address Bus
Mode Register
Burst Length
Burst Type
Testmode
Accessed Register
A2
mode
A3
Type
0
Normal
0
Sequential
1
Testmode
1
Reserved
CAS Latency
DLL Reset
A6
A5
A4
Latency
0
No
0
1
0
2
1
Yes
0
1
1
3
1
0
0
4
All other Reserved
Burst Length
A2
A1
A0
0
0
0
1
0
1
Length
Sequential
Interleave
1
2
2
0
4
4
1
8
8
All other Reserved
Figure 3
Data Sheet
Mode Register Bitmap
15
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
3.2
Extended Mode Register Setup (EMRS)
The Extended Mode Register is responsible for enabling / disabling the DLL in the HYB25D128323C and for
selecting the interface type for the IOs and input pins. The Extended Mode Register can be programmed by
performing a normal Mode Register Setup operation and setting the BA0 bit to high. All other bits of the EMRS
register are reserved and should be set to low.
The Bit A0 enables / disables the DLL.
The Bits A1 and A6 set the driver strength of the IOs. For detailed explanation, refer to the following table.
Table 3
IO Driver Strength and Interface Settings
A6
A1
Drive Strength
Strength/
Impedance
IO Power Supply
VDDQ
Comment
0
0
SSTL-2 weak
60% / 34Ohm
2.5V
replacement for strong mode
0
1
SSTL-2 weak
60% / 34Ohm
2.5V
–
1
0
RFU
RFU
RFU
Do not use
1
1
matched
impedance mode
30% / 60Ohm
2.5V
output driver matches line
impedance
Note: The combination A6=0 and A1=0 defines SSTL-2 strong mode in 32M DDR SGRAM which is not supported
in this device.
BA1
BA0
0
1
A11
A10
A9
A8
RFU must be set to "0"
A7
A6
A5
DS1
A4
A3
RFU must be set to "0"
A2
A1
A0
Address Bus
DS0
DLL
Extended Mode Register
Extended Mode
Register Access
BA0
Accessed Register
A6
A1
Drive Strength
A0
0
Mode Register
0
0
SSTL II-Weak Mode
0
Enable
1
Extend. Mode Reg.
0
1
SSTL II-Weak Mode
1
Disable
1
0
RFU
1
1
Matched Impedance 2.5V
Figure 4
Extended Mode Register Bitmap
3.3
Signal and Timing Description
3.3.1
General Description
DLL Enable
The 128Mbit DDR SGRAM is a 16MByte Synchronous Graphics DRAM. It consists of four banks. Each bank is
organized as 4096 rows × 256 columns × 32 bits.
Read and Write accesses are burst oriented. Accesses begin with the registration of an Activate command, which
is then followed by a Read or Write command. The address bits registered coincident with the Activate command
are used to select the bank and the row to be accessed. BA1 and BA0 select the bank, address bits A11.. A0 select
the row. Address bits A7.. A0 registered coincident with the Read or Write command are used to select the starting
column location for the burst access.
The regular Single Data Rate SGRAM read and write cycles only use the rising edge of the external clock input.
For the DDR SGRAM, the special signals DQSx (Data Strobe) are used to mark the data valid window. During
Data Sheet
16
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
read bursts, the data valid window coincides with the high or low level of the DQSx signals. During write bursts,
the DQSx signal marks the center of the valid data window. Data is available at every rising and falling edge of
DQSx, therefore the data transfer rate is doubled.
For Read accesses, the DQSx signals are aligned to the clock signal CLK.
3.4
Special Signal Description
3.4.1
Clock Signal
The DDR SGRAM operates with a differential clock (CLK and CLK#) input. CLK is used to latch the address and
command signals. Data input and DMx signals are latched with DQSx. The DDR SGRAM implements a Delay
Locked Loop circuit (DLL) which tracks both edges of the CLK input signal and aligns the DQS output edges with
the CLK input edges.
The minimum and maximum clock cycle time is defined by tCK. The maximum value for tCK is defined to provide a
lower bound for the operation frequency of the internal DLL circuit. The minimum and maximum clock duty cycle
are specified using the minimum clock high time tCH and the minimum clock low time tCL respectively.
The internal DLL circuit requires additional 200 clock cycles after DLL reset for internal clock stabilization.
3.4.2
Command Inputs and Addresses
Like single data rate SGRAMs, each combination of RAS#, CAS# and WE# input in conjunction with CS# input at
a rising edge of the clock determines a DDR SGRAM command.
VIH
CLK, CLK#
VIL
tIS
Address,
CS#, RAS#,
CAS#, WE#,
CKE
Valid
Valid
VIH
VTT
VIL
tIH
Figure 5
Command and Address Signal Timing
3.4.3
Data Strobe and Data Mask
3.4.3.1
Operation at Burst Reads
The Data Strobes provide a 3-state output signal to the receiver circuits of the controller during a read burst. The
data strobe signal goes tRPRE clock cycle low before data is driven by the DDR SGRAM and then toggles low to
high and high to low till the end of the burst. The CAS latency is specified to the first low to high transition. The
edges of the Output Data signals and the edges of the data strobe signals during a read are nominally coincident
with edges of the input clock. The tolerance of these edges is specified by the parameters tAC and tDQSCK and is
referenced to the crossing point of the CLK and CLK# signal. The tDQSQ timing parameter describes the skew
between the data strobe edge and the output data edge.
The following table summarizes the mapping of DQSx and DMx signals to the data bus.
Data Sheet
17
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
Table 4
Mapping of DQSx and DMx
data strobe signal
data mask signal
Controlled data bus
DQS0
DM0
DQ7 .. DQ0
DQS1
DM1
DQ8 .. DQ15
DQS2
DM2
DQ16 .. DQ23
DQS3
DM3
DQ24 .. DQ31
The minimum time during which the output data is valid is critical for the receiving device. This also applies to the
Data Strobe DQS during a read since it is tightly coupled to the output data. The parameters tQH and tDQSQ define
the minimum output data valid window.
Prior to a burst of read data, given that the device is not currently in burst read mode, the data strobe signals transit
from Hi-Z to a valid logic low. This is referred to as the data strobe “read preamble” tRPRE.
Once the burst of read data is concluded, given that no subsequent burst read operation is initiated, the data strobe
signals transit from a valid logic low to Hi-Z. This is referred to as the data strobe “read postamble” tRPST.
T0
CLK,
CLK#
T1
tCH
T2
tCL
tCK
T3
T4
tHP
VIH
VIL
tDQSCK
"Preamble"
tRPRE
DQS
"Postamble"
tRPST
VIH
VTT
VIL
tAC
DQx
D
D+1
D+2
D+3
VIH
VTT
VIL
tQH
tDQSQ
tQHS
Figure 6
DQS Timing for Read
3.4.3.2
Operation at Burst Write
During a write burst, control of the data strobe is driven by the memory controller. The DQSx signals are nominally
centered with respect to data and data mask. The tolerance of the data and data mask edges versus the data
strobe edges during writes are specified by the setup and hold time parameters of data (tQDQSS & tQDQSH) and data
mask (tDMDQSS & tDMDQSH). The input data is masked in the same cycle when the corresponding DMx signal is high
(i.e. the DMx mask to write latency is zero.)
Data Sheet
18
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
VIH
VTT
VIL
DQSx
tDMDQSS
DMx
tDMDQSS
tDMDQSH
tDMDQSH
tQDQSH
DQx
Q
VIH
VTT
VIL
tQDQSH
Q+1
tQDQSS
Q+2
Q+3
tQDQSS
Q+4
VIH
VTT
VIL
Input Data masked
Figure 7
DQS and DM Timing at Write
Prior to a burst of write data, given that the controller is not currently in burst write mode, the data strobe signal
(DQSx) transits from Hi-Z to a valid logic low. This is referred to as the data strobe “Write Preamble”. Once the
burst of write data is concluded, given that no subsequent burst write operation is initiated, the data strobe signal
(DQSx) transits from a valid logic low to Hi-Z. This is referred to as the data strobe “Write Postamble”, tWPST. For
DDR SGRAM, data is written with a delay which is defined by the parameter tDQSS (DDR write latency). This is
different than the single data rate SGRAM where data is written in the same cycle as the Write command is issued.
VIH
CLK,
CLK#
VIL
WR
tDQSS
tWPST
tWPREH
DQSx
VIH
VTT
VIL
"Preamble"
tWPRES
Q
DQx
Figure 8
Data Sheet
"Postamble"
Q+1
Q+2
Q+3
VIH
VTT
VIL
DQS Pre/Postamble at Write
19
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
3.5
Description of Timings
3.5.1
Power-Up Sequence
The following sequence is highly recommended for Power-Up:
1. Apply power and start clock. Maintain CKE=L and the other pins are in NOP conditions at the input
2. Apply VDD before or at the same time as VDDQ, apply VDDQ before or at the same time as VREF & VTT
3. Start clock, maintain stable conditions for 200 µs min.
4. Apply NOP and set CKE to high
5. Apply a Precharge All command
6. Issue EMRS (extended mode register set) command to enable the DLL
7. Issue a Mode Register Set command for “DLL reset“. 200 cycles of clock input are required to lock the DLL.
8. Issue Precharge commands for all banks of the device.
9. Issue two or more Auto-Refresh commands.
10. Issue a Mode Register Set command. (This step may also be taken as step 6)
Clock
Command
NOP
PREA
DLL
Reset
EMRS
tRP
tMRD
PREA
ARef
tRP
2 Clock
min.
ARef
tRFC
any
Comm.
MRS
tRFC
tMRD
200 Clock min.
Figure 9
Power-Up Sequence
3.5.2
Mode Register Set Timing
The DDR SGRAM should be activated with CKE already high prior to writing into the mode register. Two clock
cycles are required to complete the write operation in the mode register. The mode register contents can be
changed using the same command and clock cycle requirements during operation as long as all banks are in the
idle state.
Clk
Command
NOP
PREA
NOP
MRS
NOP
any
Comm.
NOP
tMRD
tRP
Figure 10
Mode Register Set Timing
3.5.3
Extended Mode Register Set Timing
The timing of the Extended Mode Register Setup operation is equivalent to the Mode Register Setup timing.
Data Sheet
20
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
3.5.4
Bank Activation Command (ACT)
The Bank Activation command is initiated by issuing an ACT command at the rising edge of the clock. The DDR
SGRAM has four independent banks which are selected by the two Bank select Addresses (BA0, BA1). The Bank
Activation command must be applied before any Read or Write operation can be executed. The delay from the
Bank Activation command to the first read or write command must meet or exceed the minimum of RAS to CAS
delay time (tRCDDC min. for read commands and tRCDWR min. for write commands). Once a bank has been activated,
it must be precharged before another Bank Activate command can be applied to the same bank. The minimum
time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank
activation delay time (tRRD min).
Clk
Command
ACT
READ
or
WRITE
NOP
PRE
ACT
tRCDRD for read
tRCDWR for write
Bank A
Row Add.
Addresses
Bank A
Col. Add.
Bank A
Row Add.
Bank A
tRC
Figure 11
Activate to Read or Write Command Timing (one bank)
Clk
Command
ACT
Addresses
Bank B
Row Add.
NOP
ACT
Bank A
Row Add.
tRRD
Figure 12
Activate Bank A to Activate Bank B Timing
3.5.5
Precharge Command
This command is used to precharge or close a bank that has been activated. Precharge is initiated by issuing a
Precharge command at the rising edge of the clock. The Precharge command can be used to precharge each
bank respectively or all banks simultaneously. The Bank addresses BA0 and BA1 select the bank to be
precharged. After a Precharge command, the analog delay tRP has to be met until a new Activate command can
be initiated to the same bank.
Data Sheet
21
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
Table 5
Precharge Control
A8/AP
BA1
BA0
Precharged
0
0
0
Bank A Only
0
0
1
Bank B Only
0
1
0
Bank C Only
0
1
1
Bank D Only
1
X
X
All Banks
Clk
Command
ACT
Addresses
Bank A
Row Add
PRE
NOP
NOP
Bank A
Row Add
Bank A
tRAS
ACT
tRP
tRC
Figure 13
Precharge Command Timing
3.5.6
Self Refresh
The self refresh mode can be used to retain the data in the DDR SGRAM if the chip is powered down. To set the
DDR SGRAM into a self refreshing mode, a Self Refresh command must be issued and CKE held low at the rising
edge of the clock. Once the self Refresh command is initiated, CKE must stay low to keep the device in Self
Refresh mode. During the Self refresh mode, all of the external control signals are disabled except CKE. The clock
is internally disabled during Self Refresh operation to reduce power. An internal timing generator guarantees the
self refreshing of the memory content. To exit the Self Refresh mode, a stable external clock is needed for the DLL
before returning CKE high. After the Power Down Exit time(tPDEX), a Deselect or NOP command is issued and CKE
is held high for longer than tSREX in order to lock the DLL.
Data Sheet
22
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
Clk
Command
NOP
SELF
REFRESH
NOP
DESEL
NOP
DESEL
NOP
DESEL
NOP
DESEL
Any
Comm.
CKE
tSREX
Figure 14
Self Refresh timing
3.5.7
Auto Refresh
The auto refresh function is initiated by issuing an Auto Refresh command at the rising edge of the clock. All banks
must be precharged and idle before the Auto Refresh command is applied. No control of the external address pins
is required once this cycle has started. All necessary addresses are generated in the device itself. When the
refresh cycle has completed, all banks will be in the idle state. A delay between the Auto Refresh command and
the next Activate Command or subsequent Auto Refresh Command must be greater than or equal to the tRFC(min).
Clk
Command
NOP
PRECHARGE
AUTO
REFRESH
Command
CKE
Command is
AUTOREFRESH
or ACT
tRP
Figure 15
Autorefresh timing
3.5.8
Power Down Mode
NOP
tRFC
The Power Down Mode is entered when CKE is set low and exited when CKE is set high. The CKE signal is
sampled at the rising edge of the clock. Once the Power Down Mode is initiated, all of the receiver circuits except
CLK, CKE and DLL circuits are gated off to reduce power consumption. All banks can be set to idle state or stay
activate during Power Down Mode, but burst activity may not be performed. After exiting from Power Down Mode,
at least one clock cycle of command delay must be inserted before starting a new command. During Power Down
Mode, refresh operations cannot be performed; therefore, the device cannot remain in Power Down Mode longer
than the refresh period (tREF) of the device.
Data Sheet
23
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
Clk
Command
PRE
NOP
NOP
DESEL
NOP
Any
Command
NOP
DESEL
CKE
Power Down
Mode entry
Figure 16
Power Down Mode timing
3.5.9
Burst Mode Operation
Power Down
Mode exit
tPDEX
Burst mode operation is used to provide a constant flow of data to the memory (write cycle) or from the memory
(read cycle). The burst length is programmable and set by address bits A0 - A3 during the Mode Register Setup
command. The burst length controls the number of words that will be output after a read command or the number
of words to be input after a write command. One word is 32 bits wide. The sequential burst length can be set to 2,
4 or 8 data words.
Table 6
Burst Mode and Sequence
Burst Length
Starting Column Address
A2
A1
A0
Type = Sequential
0
0-1
1
1-0
0
0
0-1-2-3
0
1
1-2-3-0
1
0
2-3-0-1
1
1
3-0-1-2
0
0
0
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
0
1
0
2-3-4-5-6-7-0-1
0
1
1
3-4-5-6-7-0-1-2
1
0
0
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
1
1
0
6-7-0-1-2-3-4-5
1
1
1
7-0-1-2-3-4-5-6
2
4
8
3.5.10
Order of Access within a Burst
Burst Read Operation: (READ)
The Burst Read operation is initiated by issuing a READ command at the rising edge of the clock after tRCD from
the bank activation. The address inputs (A7.. A0) determine the starting address for the burst. The burst length (2,
4 or 8) must be defined in the Mode Register. The first data after the READ command is available depending on
the CAS latency. The subsequent data is clocked out on the rising and falling edge of DQSx until the burst is
completed. The DQSx signal is generated by the DDR SGRAM during Burst Read Operations.
Data Sheet
24
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
CLK
Command
Read
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CL = 2
Read
Postamble
Read
Preamble
DQSx
CAS latency = 2
D-out
0
DQx
D-out
1
D-out
2
D-out
3
CL = 3
Burst length = 4
Read
Postamble
Read
Preamble
DQSx
CAS latency = 3
D-out
0
DQx
D-out
1
D-out
2
D-out
3
CL = 4
DQSx
Read
Postamble
Read
Preamble
CAS latency = 4
D-out
0
DQx
Figure 17
Burst Read Operation
3.5.11
Burst Write Operation (WRITE)
D-out
1
D-out
2
D-out
3
The Burst Write is initiated by issuing a WRITE command at the rising edge of the clock. The address inputs (A7..
A0) determine the starting column address. Data for the first burst write cycle must be applied on the DQ pins on
the first rising edge of DQSx following the WRITE command. The time between the WRITE command and the first
corresponding edge of the data strobe is tDQSS. The remaining data inputs must be supplied on each subsequent
rising and falling edge of the data strobe until the burst length is completed. When the burst has been finished,
any additional data supplied to the DQ pins will be ignored.
Data Sheet
25
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
CLK
WRITE
NOP
NOP
tDQSS
NOP
tWPST
DQSx
tWPRES
DQx
tWPREH
Data-in
0
Data-in
1
Data-in
2
Data-in
3
Burst length = 4
Figure 18
Burst Write Operation
3.5.12
Burst Stop Command (BST)
A Burst Stop is initiated by issuing a BURST STOP command at the rising edge of the clock. The Burst Stop
Command has the fewest restrictions, making it the easiest method to terminate a burst operation before it has
been completed. When the Burst Stop Command is issued during a burst read cycle, read data and DQSx go to
a high impedance state after a delay which is equal to the CAS Latency set in the Mode Register. The Burst Stop
latency is equal to the CAS latency CL.The Burst Stop command is not supported during a write burst operation.
Burst Stop is also illegal during Read with Auto-Precharge.
Data Sheet
26
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
CLK
Command
READ
BST
NOP
NOP
NOP
NOP
NOP
NOP
CL = 2
Burst Stop Latency = 2
DQSx
CAS latency = 2
D-out
0
DQx
D-out
1
CL = 3
Burst Stop Latency = 3
DQSx
CAS latency = 3
D-out
0
DQx
D-out
1
Burst Stop Latency = 4
DQSx
CAS latency = 4
D-out
0
DQx
D-out
1
Burst length = 4
Figure 19
Burst Stop for Read
3.5.13
Data Mask (DMx) Function
The DDR SGRAM has a Data Mask function that can be used only during write cycles. When the Data Mask is
activated (DMx high) during burst write, the write operation is masked immediately. The DMx to data-mask latency
is zero. DMx can be issued at the rising or falling edge of Data Strobe.
Data Sheet
27
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
CLK
Command
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQSx
D-in
0
DQx
D-in
1
D-in
2
D-in
3
D-in
4
D-in
5
D-in
6
D-in
7
DMx
Data is masked out
Figure 20
Data Mask Timing
3.5.14
Autoprecharge Operation
Burst length = 8
The Autoprecharge command is issued by setting column address A8 high when a Read or a Write command is
asserted to the DDR SGRAM. If A8 is low when Read or Write command is issued, a normal Read or Write burst
operation is executed and the bank remains active at the end of the burst sequence. When the Auto Precharge
command is activated, the active bank automatically begins to precharge at the earliest possible moment during
the Read or Write cycle after tRAS(min.) is satisfied.
3.5.15
Read with Autoprecharge (READA)
If a Read with Auto-precharge command is initiated, the DDR SGRAM automatically enters the precharge
operation BL/2 clock cycles after the READA command and tRAS(min.) is satisfied. If tRAS(min.) has not been satisfied
yet, an internal interlock will delay the precharge operation until it is satisfied. Once the precharge operation has
started, the bank cannot be reactivated and the new command can not be asserted until the Precharge time (tRP)
has been satisfied.
Data Sheet
28
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
CLK
Command
READA
NOP
NOP
NOP
NOP
NOP
NOP
ACT
CL = 2
DQSx
CAS latency = 2
D-out
0
DQx
D-out
1
D-out
2
D-out
3
D-out
0
D-out
1
CL = 3
DQSx
CAS latency = 3
DQx
D-out
2
D-out
3
CL = 4
DQSx
CAS latency = 4
D-out
0
DQx
Figure 21
Data Sheet
D-out
2
D-out
3
t
RP
BL / 2
Burst length = 4
D-out
1
Begin of
Autoprecharge
Bank can be activated after
completion of precharge
Read Burst with Autoprecharge
29
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
Burst length = 4
T0
CAS latency = 3
T1
T2
NOP
NOP
T3
T4
T5
T6
READ A
+ AP
NOP
NOP
T7
T8
CLK
BANK A
ACTIVATE
Command
NOP
NOP
NOP
t RCD(min)
t RAS(min)
t RP
Begin of
Auto Precharge
BL / 2
DQSx
CL = 3
D-out
0
DQx
Figure 22
Read Concurrent Auto Precharge
Table 7
Concurrent Read Auto Precharge Support
Asserted
Command
For same Bank
T4
T5
READ
NO
READ+AP
YES
ACTIVATE
PRECHARGE
D-out
1
D-out
2
D-out
3
For different Bank
T6
T4
T5
T6
NO
NO
NO
YES
YES
YES
NO
NO
YES
YES
NO
NO
NO
YES
YES
YES
YES
YES
NO
YES
YES
YES
Note: This table is for the case of Burst Length = 4, CAS Latency =3 and tWR=2 clocks
When READ with Auto Precharge is asserted, new commands can be asserted at T4,T5 and T6 as shown in
Table 7.
An Interrupt of a running READ burst with Auto Precharge i.e. at T4 and T5 to the same bank with another
READ+AP command is allowed, it will extend the begin of the internal Precharge operation to the last READ+AP
command.
Interrupts of a running READ burst with Auto Precharge i.e. at T4 are not allowed when doing concurrent
command to another active bank. ACTIVATE or PRECHARGE commands to another bank are always possible
while a READ with Auto Precharge operation is in progress.
3.5.16
Write with Autoprecharge (WRITEA)
If A8 is high when a Write command is issued, the Write with Auto-Precharge function is performed. The internal
precharge begins after the write recovery time tWR and tRAS(min.) are satisfied.
If a Write with Auto Precharge command is initiated, the DDR SGRAM automatically enters the precharge
operation at the first rising edge of CLK after the last valid edge of DQS (completion of the burst) plus the write
recovery time tWR. Once the precharge operation has started, the bank cannot be reactivated and the new
command can not be asserted until the Precharge time (tRP) has been satisfied. If tRAS(min.) has not been satisfied
yet, an internal interlock will delay the precharge operation until it is satisfied.
Data Sheet
30
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
Burst length = 4
T0
T1
T2
T3
T4
T5
T6
NOP
NOP
NOP
T7
T8
CLK
Command
BANK A
ACTIVATE
WRITE A
+ AP
NOP
NOP
NOP
NOP
t RAS(min)
t WR
t RP
BL / 2
Begin of
Auto Precharge
DQSx
D-in
0
DQx
Figure 23
D-in
1
D-in
2
D-in
3
Write Burst with Auto Precharge
Note: tWR starts at the first rising edge of clock after the last valid edge of the 4 DQSx.
Table 8
Concurrent Write Auto Precharge Support
Asserted
Command
For same Bank
For different Bank
T3
T4
T5
T6
T7
T8
T3
T4
T5
T6
T7
WRITE
NO
NO
NO
NO
NO
NO
NO
YES
YES
YES
YES
WRITE+AP
YES
NO
NO
NO
NO
NO
NO
YES
YES
YES
YES
READ
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
YES
READ+AP
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
YES
ACTIVATE
NO
NO
NO
NO
NO
NO
YES
YES
YES
YES
YES
PRECHARGE
NO
NO
NO
NO
NO
NO
YES
YES
YES
YES
YES
When Write with Auto Precharge is asserted, new commands can be asserted at T3.. T8 as shown in Table 8.
An Interrupt of a running WRITE burst with Auto Precharge i.e. at T3 to the same bank with another WRITE+AP
command is allowed as long as the burst is running, it will extend the begin of the internal Precharge operation to
the last WRITE+AP command.
Interrupts of a running WRITE burst with Auto Precharge i.e. at T3 are not allowed when doing concurrent
WRITE’s to another active bank. Consecutive WRITE or WRITE+AP bursts (T4.. T7) to other open banks are
possible. ACTIVATE or PRECHARGE commands to another bank are always possible while a WRITE with Auto
Precharge operation is in progress.
3.6
Burst Interruption
3.6.1
Read Interrupted by a Read
A Burst Read can be interrupted before completion of the burst by a new Read command given to any bank. When
the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst
length. The data from the first Read command continues to appear on the outputs until the CAS latency from the
Data Sheet
31
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
interrupting Read command is satisfied. At this point, the data from the interrupting Read command appears. Read
to Read interval (CAS#(a) to CAS#(b) Command period, tCCD) is minimum 1 CLK.
CLK
READ a
Command
READ b
NOP
NOP
NOP
NOP
tCCD
DQSx
D-out
a0
DQx
D-out
a1
D-out
b0
D-out
b1
D-out
b2
D-out
b3
Burst length = 4
CL = 2
Figure 24
Read interrupted by Read
3.6.2
Read Interrupted by a Write
To interrupt a burst read with a write command, a Burst Stop command must be asserted to avoid data contention
on the I/O bus by placing the DQ's (Output drivers) in a high impedance state at least one clock cycle before the
Write Command is initiated (Last Output to Write Command Latency). To insure that the DQs are tri-stated one
cycle before the write operation begins, the Burst Stop command must be applied at least 3 clock cycles for CL =
2, at least 4 clock cycles for CL = 3 or at least 5 clock cycles for CL = 4 before the Write command.
CLK
Command
READ
BST
NOP
NOP
WRITE
NOP
NOP
NOP
Burst Stop latency = CL
DQSx
D-out
0
DQx
D-out
1
D-in
0
Burst Stop to Write command latency
Figure 25
Data Sheet
D-in
1
D-in
2
D-in
3
Burst length = 4
CL = 2
Read interrupted by Write
32
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
3.6.3
Read Interrupted by a Precharge
A Burst Read operation can be interrupted by a Precharge of the same bank. The Read command to Precharge
time is minimum 1 clock cycle. The Precharge command disables the data output depending on the CAS latency.
Once the last data bit has been outputted, the output buffers are tristated. A new Bank Activate command may be
issued to the same bank after tRP.
CLK
Command
READ
NOP
PRE
NOP
NOP
ACT
Precharge latency = CL
NOP
First possible
ACT command
DQSx
D-out
0
DQx
D-out
1
D-out
2
D-out
3
Burst length = 8
CL = 2
tRP
Figure 26
Read interrupted by Precharge
3.6.4
Write Interrupted by a Write
A Burst Write can be interrupted before completion of the burst by a new Write Command. The minimum distance
between two different Write commands is one clock cycle. When the previous burst is interrupted, the remaining
addresses are overridden by the new address and data will be written into the device until the programmed burst
length is satisfied. The Write to Write interval (CAS a to CAS b command period) is defined by the parameter tCCD.
CLK
Command
WRITE a
WRITE b
NOP
NOP
NOP
tCCD
DQSx
DQx
D-in
a0
D-in
a1
D-in
b0
D-in
b1
D-in
b2
D-in
b3
Burst length = 4
Figure 27
Data Sheet
Write interrupted by Write
33
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
3.6.5
Write Interrupted by a Read
A Burst Write can be interrupted by a Read command sent to any bank. The DQs must be in the high impedance
state at least one clock cycle before the data of the interrupting read appears on the outputs to avoid data
contention. Before the Read Command is registered, any residual data from the burst write cycle must be masked
by DMx. Data that is presented on the DQ pins before the Read command is initiated, will actually be written to
the memory.
CLK
Command
Write
NOP
tDQSS
NOP
Last valid
data
Read
tWTR
NOP
NOP
NOP
CL = 2
DQSx
DQx
D-in
0
D-in
1
D-in
2
D-in
3
D-in
4
D-in
5
D-out
0
D-out
1
DMx
Data must be
masked
Figure 28
Write interrupted by Read
3.6.6
Write Interrupted by a Precharge
Data is masked
by Read
Burst length = 8
CL = 2
A Burst Write operation can be interrupted before completion of the burst by a Precharge of the same bank.
Random column access is allowed. A Write Recovery time (tWR) is required from the last data to Precharge
command. When Precharge command is asserted, any residual data from the burst write cycle must be masked
by DMx.
Data Sheet
34
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
CLK
Command
Write
bank A
NOP
NOP
NOP
Last valid
data
tDQSS
Write
bank B
PRE
NOP
NOP
tDQSS
tWR
DQSx
D-in
0
DQx
D-in
1
D-in
2
D-in
3
D-in
4
D-in
5
D-in
0
D-in
1
DMx
Data must be
masked
Figure 29
Write interrupted by Precharge
3.7
Operations and Functions
Table 9
Command Overview
Data is masked
by Precharge
Burst length = 8
Operation
Code
CKE
n-1
CKE
n
CS#
RAS# CAS# WE#
BA0
BA1
A8
A0-7
A9-11
Device Deselect
DESEL
H
X
H
X
X
X
X
X
X
X
No Operation
NOP
H
X
L
H
H
H
X
X
X
X
Mode Register Setup
MRS
H
X
L
L
L
L
0
0
OPCODE
Extended Mode Register MRS
Setup
H
X
L
L
L
L
1
0
OPCODE
Bank Activate
ACT
H
X
L
L
H
H
BA
BA
Row Address
Read
READ
H
X
L
L
H
H
BA
BA
L
Col.
Read with Auto
Precharge
READA
H
X
L
H
L
H
BA
BA
H
Col.
Write Command
WRITE
H
X
L
L
H
H
BA
BA
L
Col.
Write Command with
Auto Precharge
WRITEA
H
X
L
H
L
H
BA
BA
H
Col.
Burst Stop
BST
H
X
L
H
H
L
X
X
X
X
Precharge Single Bank
PRE
H
X
L
L
H
L
BA
BA
L
X
Precharge All Banks
PREAL
H
X
L
L
H
L
X
X
H
X
Auto Refresh
AREF
H
H
L
L
L
H
X
X
X
X
Self Refresh Entry
SREFEN
H
L
L
L
L
H
X
X
X
X
Self Refresh Exit
SREFEX
L
L
H
H
H
L
X
H
X
H
X
H
X
X
X
X
X
X
X
X
Data Sheet
35
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
Table 9
Command Overview (cont’d)
Operation
Code
CKE
n-1
CKE
n
CS#
RAS# CAS# WE#
BA0
BA1
A8
A0-7
A9-11
Power Down Mode Entry PWDNEN
(Note)
H
H
L
L
H
L
X
H
X
H
X
H
X
X
X
X
X
X
X
X
Power Down Mode Exit
L
H
H
L
X
valid
X
valid
X
valid
X
X
X
X
PWDNEX
Note: The Power Down Mode Entry command is illegal during Burst Read or Burst Write operations.
3.8
Function Truth Tables
Table 10 lists all abbreviations used in Table 11 and Table 12.
Table 10
Abbreviations
H
High Level
L
Low Level
X
Don’t Care
V
Valid Data Input
RA
Row Address
BA
Bank Address
PA
Precharge All
NOP
No Operation
CA
Column Address
Ax
Address Line x
Table 11
Function Truth Table I
Current State
Command
Address
Action
Notes
IDLE
DESEL
X
NOP
3)1)
3)
3)
Data Sheet
NOP
X
NOP
3)2)
BST
X
NOP
3)
READ / READA
BA,CA,A8
ILLEGAL
1)4)
1)
WRITE / WRITEA
BA,CA,A8
ILLEGAL
ACT
BA, RA
Bank Active
PRE / PREAL
BA, A8
NOP
AREF / SREF
X
AUTO-Refresh or Self-Refresh
MRS / EMRS
Op-Code
Mode Register Set or Extended Mode
Register Set
36
1)
1)
4)5)
4)
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
Table 11
Function Truth Table I (cont’d)
Current State
Command
Address
Action
ROW ACTIVE
DESEL
X
NOP
NOP
X
NOP
BST
X
NOP
READ / READA
BA, CA, A8
Begin Read, Determine Auto Precharge
9)6)
READ
Data Sheet
9)
WRITE / WRITEA
BA, CA, A8
Begin Write, Determine Auto Precharge
9)
ACT
BA, RA
ILLEGAL
1), 5)
6)7)
6)
7)
9)
1), 5)
PRE / PREAL
BA, A8
Precharge / Precharge All
AREF / SREF
X
ILLEGAL
MRS / EMRS
OP-Code
ILLEGAL
DESEL
X
Continue burst to end
NOP
X
Continue burst to end
BST
X
Terminate Burst
READ / READA
BA, CA, A8
Terminate burst, Begin New Read,
Determine Auto-Prechgarge
7)8)
WRITE / WRITEA
BA, CA, A8
ILLEGAL
2), 7)9)
1)
1)
ACT
BA, RA
ILLEGAL
PRE / PREAL
BA ,A8
Terminate Burst / Precharge
AREF / SREF
X
ILLEGAL
MRS / EMRS
Op-Code
ILLEGAL
X
Continue burst to end, Precharge
X
Continue burst to end, Precharge
BST
BA
ILLEGAL
READ / READA
BA, CA, A8
ILLEGAL
WRITE / WRITEA
BA, CA, A8
ILLEGAL
ACT
BA, RA
ILLEGAL
1)
1)
1)
1)
READ with
DESEL
Auto Precharge NOP
WRITE
Notes
PRE / PREAL
BA ,A8
ILLEGAL
AREF / SREF
X
ILLEGAL
MRS / EMRS
Op-Code
ILLEGAL
DESEL
X
Continue burst to end
NOP
X
Continue burst to end
BST
X
ILLEGAL
READ / READA
BA, CA, A8
Terminate Burst, Begin Read, Determine
Auto-Precharge.
7), 8)
WRITE / WRITEA
BA, CA, A8
Terminate Burst, Begin new Write,
Determine Auto-Precharge
2), 7)
ACT
BA, RA
ILLEGAL
1)
1)
8)
8)
PRE / PREAL
BA ,A8
Terminate Burst , Precharge
AREF / SREF
X
ILLEGAL
MRS / EMRS
OP-Code
ILLEGAL
37
2), 7)
7), 8)
2), 7)
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
Table 11
Function Truth Table I (cont’d)
Current State
Command
Address
Action
WRITE with
Autoprecharge
DESEL
X
Continue burst to end, Precharge
NOP
X
Continue burst to end, Precharge
BST
X
ILLEGAL
READ / READA
BA, CA, A8
ILLEGAL
ROW
ACTIVATING
WRITE / WRITEA
BA, CA, A8
ILLEGAL
ACT
BA, RA
ILLEGAL
1)
1)
1)
1)
PRE / PREAL
BA ,A8
ILLEGAL
AREF / SREF
X
ILLEGAL
MRS / EMRS
OP-Code
ILLEGAL
DESEL
X
NOP ( Row Active after tRCD)
NOP
X
NOP ( Row Active after tRCD)
BST
X
NOP ( Row Active after tRCD)
READ / READA
BA, CA, A8
ILLEGAL
1), 9)
WRITE / WRITEA
BA, CA, A8
ILLEGAL
1), 9)
ILLEGAL
1), 5)
1), 6)
ACT
PRECHARGE
BA, RA
1), 9)
1), 9)
1), 5)
PRE / PREAL
BA ,A8
ILLEGAL
AREF / SREF
X
ILLEGAL
MRS / EMRS
OP-Code
ILLEGAL
DESEL
X
NOP ( Row Idle after tRP)
NOP
X
NOP ( Row Idle after tRP)
BST
X
NOP ( Row Idle after tRP)
READ / READA
BA, CA, A8
ILLEGAL
1)
1)
ILLEGAL
1)
1)
ILLEGAL
1)
1)
1)
1)
2)
2)
2)
WRITE / WRITEA
ACT
BA, CA, A8
BA, RA
PRE / PREAL
BA ,A8
NOP ( Row Idle after tRP)
AREF / SREF
X
ILLEGAL
MRS / EMRS
OP-Code
ILLEGAL
X
NOP (Row Active after tWR)
WRITE
DESEL
RECOVERING NOP
Data Sheet
Notes
1), 6)
X
NOP (Row Active after tWR)
BST
X
NOP (Row Active after tWR)
READ / READA
BA, CA, A8
Begin Read, Determine Auto-Prechgarge
WRITE / WRITEA
BA, CA, A8
Begin Write, Determine Auto-Prechgarge
ACT
BA, RA
ILLEGAL
2)
1),10)
PRE / PREAL
BA ,A8
ILLEGAL
AREF / SREF
X
ILLEGAL
MRS / EMRS
OP-Code
ILLEGAL
38
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
Table 11
Function Truth Table I (cont’d)
Current State
Command
Address
Action
X
NOP (Precharge after tWR)
X
NOP (Precharge after tWR)
X
NOP (Precharge after tWR)
BA, CA, A8
ILLEGAL
1), 2)
WRITE / WRITEA
BA, CA, A8
ILLEGAL
1)
ACT
BA, RA
ILLEGAL
1)
PRE / PREAL
BA ,A8
ILLEGAL
1)
AREF / SREF
X
ILLEGAL
MRS / EMRS
OP-Code
ILLEGAL
DESEL
X
NOP (Idle after tRC)
NOP
X
NOP (Idle after tRC)
BST
X
NOP (Idle after tRC)
DESEL
WRITE
RECOVERING NOP
with AutoBST
precharge
READ / READA
REFRESH
(EXTENDED
MODE
REGISTER
SET)
READ / READA
BA, CA, A8
ILLEGAL
WRITE / WRITEA
BA, CA, A8
ILLEGAL
ACT
BA, RA
ILLEGAL
PRE / PREAL
BA ,A8
ILLEGAL
AREF / SREF
X
ILLEGAL
MRS / EMRS
OP-Code
ILLEGAL
DESEL
X
NOP (Idle after two clocks)
NOP
X
NOP (Idle after two clocks)
BST
X
NOP (Idle after two clocks)
READ / READA
BA, CA, A8
ILLEGAL
WRITE / WRITEA
BA, CA, A8
ILLEGAL
ACT
BA, RA
ILLEGAL
PRE / PREAL
BA ,A8
ILLEGAL
AREF / SREF
X
ILLEGAL
MRS / EMRS
OP-Code
ILLEGAL
Notes
11)
1) Illegal to bank specified states; function may be legal in the bank indicated by BAx, depending on the state of that bank
2) Must satisfy bus contention, bus turn around, write recovery requirements.
3) If both banks are idle, and CKE is inactive, the device will enter Power Down Mode. All input buffers except CKE, CLK and
CLK# will be disabled.
4) If both banks are idle, and CKE is deactivated coincidentally with an AutoRefresh command, the device will enter
SelfRefresh Mode. All input buffers except CKE will be disabled.
5) Illegal, if tRRD is not satisfied.
6) Illegal, if tRAS is not satisfied.
7) Must satisfy burst interrupt condition.
8) Must mask two preceding data bits with the DM pin.
9) Illegal, if tRCD is not satisfied.
10) Illegal, if tWR is not satisfied.
11) Illegal, if tRC is not satisfied.
Note: All entries assume the CKE was High during the preceding clock cycle
Data Sheet
39
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
Table 12
Function Truth Table for CKE
Current
State
CKE
n-1
CKE
n
CS#
RAS
#
CAS
#
WE#
Address Action
Notes
SELF
REFRESH
H
X
X
X
X
X
X
INVALID
1)
L
H
H
X
X
X
X
Exit Self-Refresh ( Idle after tSRX)
1)
L
H
L
H
H
H
X
Exit Self-Refresh ( Idle after tSRX)
1)
L
H
L
H
H
X
X
ILLEGAL
1)
L
H
L
H
H
X
X
ILLEGAL
1)
L
H
L
L
L
X
X
ILLEGAL
1)
L
L
X
X
X
X
X
NOP ( Maintain Self Refresh)
1)
H
X
X
X
X
X
X
INVALID
L
H
X
X
X
X
X
Exit Power Down ( Idle after tPDEX)
L
L
X
X
X
X
X
NOP ( Maintain Power Down)
H
H
X
X
X
X
X
Refer to Function Truth Table
2)
H
L
L
L
L
H
X
Enter Self Refresh
3)
H
L
H
X
X
X
X
Enter Power-Down
2)
H
L
L
H
H
H
X
Enter Power-Down
2)
H
L
L
H
H
L
X
ILLEGAL
2)
H
L
L
H
L
X
X
ILLEGAL
2)
H
L
L
L
X
X
X
ILLEGAL
2)
L
X
X
X
X
X
X
Refer to Power Down in this table
H
H
X
X
X
X
X
Refer to Funtion Truth Table
POWER
DOWN
ALL
BANKS
IDLE
All other
states
1) CKE low-to-high transition re-enables inputs asynchronously. A minimum setup time to CLK must be satisfied before any
commands other than EXIT are executed.
2) Power Down can be entered when all banks are idle (banks can be active or precharged)
3) Self Refresh can be entered only from the Precharge / Idle state.
Data Sheet
40
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
3.9
DDR SGRAM Simplified State Diagram
SELF
REFRESH
SREFEN
SREFEX
MODE
REGISTER
SET
MRS
AUTO
AREF
IDLE
REFRESH
CKEL
CKEH
ACT
CKEH
CKEL
ROW
ACTIVE
WRITE
READ
WRITEA
WRITE
POWER
DOWN
BST
READA
READ
READ
WRITEA
READA
READA
WRITEA
PRE
POWER
ON
READA
PRE
PRE
PRE
PRE
CHARGE
Automatic Sequence
Command Sequence
Figure 30
Data Sheet
DDR SGRAM Simplified State Diagram
41
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Electrical Characteristics
4
Electrical Characteristics
Table 13
Absolute Maximum Ratings
Parameter
Symbol
Voltage on I/O pins relative to VSS
VIN, VOUT
Values
Unit
min.
typ.
max.
Note/
Test Condition
–0.5
–
VDDQ + V
–
0.5
Voltage on Inputs relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating Temperature (Ambient)
Storage Temperature (Plastic)
Power Dissipation
Short Circuit Output Current
VIN
VDD
VDDQ
TA
TSTG
PD
IOUT
–0.5
–
+3.6
V
–
–0.5
–
+3.6
V
–
–0.5
–
+3.6
V
–
0
–
+70
°C
–
–55
–
+150
°C
–
–
1.4
–
W
–
–
50
–
mA
–
Attention: Stresses above those listed here may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Maximum ratings are absolute ratings; exceeding only one of these values may cause
irreversible damage to the integrated circuit.
Table 14
Power & DC Operation Conditions
Parameter
Symbol
Values
Unit Notes 1)
min.
typ. max.
VDD
2.38
2.5
2.63
V
L3.6, L4.52)
VDD
2.38
2.5
2.63
V
–3.6, –4.5, –5 2)
VDD
2.5
—
2.9
V
–3.6, L3.6 2)3)
VDD
2.5
—
2.9
V
–3, –3.3 2)
Power Supply Voltage for I/O Buffer
VDDQ
2.38
2.5
2.63
V
2) 4)
Reference Voltage
VREF
0.49 ×
VDDQ
1.25 0.51 ×
VDDQ
V
5) 6)
Termination Voltage
VTt
VREF - 0.04
VREF VREF + 0.04 V
Input leakage current
IIL
–5
—
5
µA
—
CLK Input leakage current
IILC
–5
—
5
µA
—
Output leakage current
IOL
–5
—
5
µA
—
Input logic high voltage, DC
VIH
VREF + 0.15 —
VDDQ + 0.3
V
8)
Input logic low voltage, DC
VIL
VSSQ - 0.3
—
VREF - 0.15
V
9)
Power Supply Voltage
7)
Output Levels: Matched Impedance Mode 2.5V
High Current at VOUT = VDDQ-0,373V
IOH
–5
—
—
mA
—
Low Current at VOUT = 0.373V
IOL
5
—
—
mA
—
High Current at VOUT = VDDQ – 0,373V
IOH
–5
—
—
mA
—
Low Current at VOUT = 0.373V
IOL
5
—
—
mA
—
Output Levels: SSTL2 Weak Mode 2.5V
Data Sheet
42
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Electrical Characteristics
1) TA = 0 to 70 ° C; VSS = 0 V
2) Under all conditions, VDDQ must be less than or equal to VDD
3) The speed sorts L3.6 and –3.6 support both VDD modes: 2.5V ± 5% and 2.5V – 2.9V
4) VDDQ = 2.5 V -/+5%
5) Typically the value of VREF is expected to be 0.5 * VDDQ of the transmitting device. VREF is expected to track variations in
VDDQ
6) Peak to peak AC noise on VREF may not exceed 2% VREF (DC)
7) VTT of the transmitting device must track VREF of the receiving device
8) Overshoots of VIH must be limited to a voltage < (VDDQ + 1.5 V) and a pulse width < 0.33 of the clock pulse
9) Undershoots of VIL must be limited to a voltage > -1.5 V and a pulse width < 0.33 of the clock pulse
Table 15
AC Operation Conditions
Parameter
Symbol
Values
Unit Notes
min.
typ. max.
VREF + 0.50
—
VDDQ + 0.3
V
L3.6, L4.5
VREF + 0.60
—
VDDQ + 0.3
V
–5.0
VREF + 0.50
—
VDDQ + 0.3
V
–3, –3.3, –3.6, –4.5
VSSQ - 0.3
—
VREF - 0.50
V
L3.6, L4.5
VSSQ - 0.3
—
VREF - 0.60
V
–5.0
VSSQ - 0.3
—
VREF - 0.50
V
–3, –3.3, –3.6, –4.5
1.2
—
VDDQ + 0.6
V
L4.5
1.0
—
VDDQ + 0.6
V
L3.6
1.2
—
VDDQ + 0.6
V
–4.5, –5.0
1.0
—
VDDQ + 0.6
V
–3, –3.3, –3.6, –4.5
VIX
VREF - 0.2
VREF VREF + 0.2
V
—
I/O Reference Voltage
VREF
0.49 × VDDQ —
0.51 × VDDQ V
—
Input Slew Rate
rI
1.0
—
Input logic high voltage
Input logic low voltage
Clock Differential Input Voltage
(CLK/CLK)
Clock Input Crossing Point (CLK/CLK)
VIH
VIL
VID
—
V/ns —
+ Vtt = 0.5xV DDQ
50 Ohm
Test point
DQ, DQS
15 pF
Figure 31
Output Test Circuit
Table 16
Pin Capacitances
Pin
min.
max.
Unit
A11.. A0, BA1, BA0, CKE, CS, CAS, RAS, WE
1.0
2.5
pF
CLK, CLK
1.0
2.5
pF
Data Sheet
43
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Electrical Characteristics
Table 16
Pin Capacitances
Pin
min.
max.
Unit
DQ0.. DQ31, DQS0 .. DQS3
1.0
3.0
pF
DM0.. DM3
1.0
3.0
pF
Table 17
Timing Parameters for speed sorts –3, –3.3, –3.6, –4.5, and –5
Part Number Extension
–3
–3.3
–3.6
–4.5
–5
Unit Note1)
Interface
MIM
MIM
MIM
WM/MIM
WM/MIM
—
Parameter
Symbol min. max. min. max. min. max. min. max. min. max. —
2)
—
Clock and Clock Enable
Clock Cycle Time
System frequency
Clock high level
width
tCK
tCK
fCK
fCK
tCH
Clock low level width tCL
Minimum clock half
period
tHP
3.0
5.0
3.3
5.0
3.6
5.0
4.5
5.5
5.0
5.5
ns
CL = 4
4.0
5.0
4.0
5.0
4.2
5.0
4.5
5.5
5.0
5.5
ns
CL = 3
200
333
200
300
200
278
183
222
183
200
MHz CL = 4
200
250
200
250
200
238
183
222
183
200
MHz CL = 3
0.45 0.55
0.45 0.55
0.45 0.55
0.45 0.55
0.45 0.55
tCK
—
0.45 0.55
0.45 0.55
0.45 0.55
0.45 0.55
0.45 0.55
tCK
—
tCH,
tCL
tCH,
tCL
tCH,
tCL
—
tCH,
tCL
—
tCH,
tCL
—
tCK
—
—
—
Command and Address Setup and Hold Times
tIS
0.65 —
0.65 —
0.75 —
1.0
—
1.0
—
ns
—
tIH
Address and
Command input hold
time
0.65 —
0.65 —
0.75 —
1.0
—
1.0
—
ns
—
tRC
tRFC
39
—
42.9 —
46.8 —
54
—
60
—
ns
—
45
—
49.5 —
54
63
—
70
—
ns
—
tRAS
tRAP
27
15.7k 29.7 15.7k 32.4 15.7k 36
15.7k ns
—
ns
—
Row Precharge
Time
tRP
12
—
13.2 —
14.4 —
18
—
20
—
ns
—
Activate(a) to
Activate(b)
Command period
tRRD
9.0
—
9.0
—
9.0
—
9.0
—
9.0
—
ns
—
CAS(a) to CAS(b)
Command period
tCCD
1
—
1
—
1
—
1
—
1
—
tCK
—
Last data in to Active tDAL
(tWR + tRP)
6
—
6
—
6
—
6
—
6
—
tCK
—
Address and
Command input
setup time
Common Parameters
Row Cycle Time
Row Cycle Time in
Auto Refresh
Row Active Time
ACTIVE to READ
with Auto precharge
command
Data Sheet
—
15.7k 40
tRAS (min.)- (burst length * tCK /2)
44
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Electrical Characteristics
Table 17
Timing Parameters for speed sorts –3, –3.3, –3.6, –4.5, and –5 (cont’d)
Part Number Extension
–3
–3.3
–3.6
–4.5
–5
Unit Note1)
Interface
MIM
MIM
MIM
WM/MIM
WM/MIM
—
Parameter
Symbol min. max. min. max. min. max. min. max. min. max. —
2)
—
Read Cycle Timing Parameters for Data and Data Strobe
Data Access Time
from Clock
tAC
-0.5
+0.5
-0.5
+0.5
-0.55 +0.55 -0.7
+0.7
-0.7
+0.7
ns
—
DQS edge to Clock
edge skew
tDQSCK
-0.5
+0.5
-0.5
+0.5
-0.55 +0.55 -0.7
+0.7
-0.7
+0.7
ns
—
DQS Read
Preamble
tRPRE
0.7
0.9
0.7
0.9
0.7
0.9
0.7
0.9
0.7
0.9
tCK
—
DQS Read
Postamble
tRPST
0.8
1.1
0.8
1.1
0.8
1.1
0.8
1.1
0.8
1.1
tCK
—
Row to Column
Delay Time for
Reads
tRCDDC
4
—
4
—
4
—
4
—
4
—
tCK
—
—
+0.3
—
+0.3
—
+0.33 —
+0.45 —
+0.5
ns
—
0.33
—
0.33
—
0.36
0.45
0.5
ns
—
DQS edge to output tDQSQ
data edge skew
Data hold skew
factor
tQHS
—
Data Output Hold
time from DQS
tQH
tHP-tQHS
tHP-tQHS
tHP-tQHS
—
—
tHP-tQHS
tHP-tQHS
ns
—
2
2
tCK
—
Write Cycle Timing Parameters for Data and Data Strobe
Row to Column
Delay Time for
Writes
tRCDWR
Clock to rising Edge tDQSS
DQS (Write Latency)
2
—
2
—
2
—
—
—
0.75 1.1
0.75 1.1
0.75 1.1
0.75 1.25
0.75 1.25
tCK
—
tQDQSS
0.40 —
0.40 —
0.40 —
0.6
—
0.6
—
ns
—
Data-in to DQS Hold tQDQSH
Time
0.40 —
0.40 —
0.40 —
0.6
—
0.6
—
ns
—
Data Mask to DQS
Setup Time
tDMDQSS 0.40 —
0.40 —
0.40 —
0.6
—
0.6
—
ns
—
Data Mask to DQS
Hold Time
tDMDQSH 0.40 —
0.40 —
0.40 —
0.6
—
0.6
—
ns
—
0
0
0
—
0
—
tCK
—
Data-in to DQS
Setup Time
Clock to DQS Write tWPRES
Preamb. Setup Time
0
Clock to DQS Write tWPREH
Preamble Hold Time
0.25 —
0.25 —
0.25 —
0.25 —
0.25 —
tCK
—
—
—
—
DQS Write
Postamble Hold
Time
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
—
Write Recovery
Time
tWR
2
—
2
—
2
—
2
—
2
—
tCK
3)
Data Sheet
45
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Electrical Characteristics
Table 17
Timing Parameters for speed sorts –3, –3.3, –3.6, –4.5, and –5 (cont’d)
Part Number Extension
–3
–3.3
–3.6
–4.5
–5
Unit Note1)
Interface
MIM
MIM
MIM
WM/MIM
WM/MIM
—
2)
Parameter
Symbol min. max. min. max. min. max. min. max. min. max. —
—
Internal WRITE to
READ command
delay
tWTR
1
tCK
—
Write DQS High
level Width
tDQSH
0.35 0.65
0.35 0.65
0.35 0.65
0.35 0.65
0.35 0.65
tCK
—
Write DQS Low level tDQSL
Width
0.35 0.65
0.35 0.65
0.35 0.65
0.35 0.65
0.35 0.65
tCK
—
—
1
—
1
—
1
—
1
—
Refresh Cycle
Refresh Period
(4096 cycles)
tREF
—
32
—
32
—
32
—
32
—
32
ms
—
Average periodic
refresh interval
tREFC
—
7.8
—
7.8
—
7.8
—
7.8
—
7.8
us
—
Refresh to Refresh
command interval
tREFC
—
15.7
—
15.7
—
15.7
—
15.7
—
15.7
µs
—
Mode Setup, Power Down & Self Refresh
Mode Register Set
cycle time
tMRD
2
—
2
—
2
—
2
—
2
—
tCK
—
Self Refresh Exit
time
tSREX
200
—
200
—
200
—
200
—
200
—
tCK
—
Power Down Exit
time
tPDEX
2*tCK —
+ tIS
1*tCK —
+ tIS
ns
—
2*tCK —
+ tIS
2*tCK —
+ tIS
1*tCK —
+ tIS
1) All parameters only valid for: TA = 0 to 70 °C; VSS = 0 V; 2.5 V < VDD < 2.9 V for –3 and –3.3; 2.375 V < VDD < 2.9 V for
–3.6; VDD = 2.5 V ± 0.125 V for –4.5 and –5; VDDQ = 2.5 V ± 0.125 V
2) Maximum clock rate is only guaranteed with the specified interface. The SSTL2-Weak Mode interface is limited to a
maximum speed of 250MHz.
3) The Write Recovery Time starts at the first rising edge of clock after the last valid (falling) DQS edge of the slowest DQS
signal.
Table 18
Timing Parameters for speed sorts L3.6 and L4.5
Part Number Extension
L3.6
L4.5
Unit Note 1)
Interface
MIM
WM/MIM
—
2)
Parameter
Symbol min.
max.
min.
max.
—
—
3.6
6.0
4.5
6.0
ns
CL = 4
4.2
10
4.5
10
ns
CL = 3
166
278
166
222
MHz CL = 4
100
238
100
222
MHz CL = 3
0.45
0.55
0.45
0.55
tCK
Clock and Clock Enable
Clock Cycle Time
System frequency
Clock high level width
Data Sheet
tCK
fCK
fCK
tCH
46
—
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Electrical Characteristics
Table 18
Timing Parameters for speed sorts L3.6 and L4.5 (cont’d)
Part Number Extension
L3.6
L4.5
Unit Note 1)
Interface
MIM
WM/MIM
—
2)
Parameter
Symbol min.
max.
min.
max.
—
—
Clock low level width
tCL
tHP
0.45
0.55
0.45
0.55
—
tCH, tCL
—
tCH, tCL
—
tCK
tCK
tIS
tIH
0.75
—
1.0
—
ns
—
0.75
—
1.0
—
ns
—
tRC
tRFC
tRAS
tRAP
tRP
tRRD
tCCD
tDAL
46.8
—
54
—
ns
—
54
—
63
—
ns
—
32.4
15.7k 36
15.7k ns
—
ns
—
Minimum clock half period
—
Command and Address Setup and Hold Times
Address and Command input setup time
Address and Command input hold time
Common Parameters
Row Cycle Time
Row Cycle Time in Auto Refresh
Row Active Time
ACTIVE to READ with Auto precharge command
Row Precharge Time
Activate(a) to Activate(b) Command period
CAS(a) to CAS(b) Command period
Last data in to Active (tWR + tRP)
tRAS (min.)- (burst length * tCK /2)
14.4
—
18
—
ns
—
9.0
—
9.0
—
ns
—
1
—
1
—
—
6
—
6
—
tCK
tCK
-0.55
+0.55 -0.7
+0.7
ns
—
-0.55
+0.55 -0.7
+0.7
ns
—
0.7
0.9
0.7
0.9
—
0.8
1.1
0.8
1.1
4
—
4
—
tCK
tCK
tCK
—
+0.33 —
+0.45 ns
—
—
0.36
0.45
ns
—
ns
—
—
—
Read Cycle Timing Parameters for Data and Data Strobe
Data Access Time from Clock
DQS edge to Clock edge skew
DQS Read Preamble
DQS Read Postamble
Row to Column Delay Time for Reads
DQS edge to output data edge skew
Data hold skew factor
Data Output Hold time from DQS
tAC
tDQSCK
tRPRE
tRPST
tRCDDC
tDQSQ
tQHS
tQH
tHP – tQHS
—
tHP – tQHS
—
—
Write Cycle Timing Parameters for Data and Data Strobe
Row to Column Delay Time for Writes
Clock to rising Edge DQS (Write Latency)
Data-in to DQS Setup Time
Data-in to DQS Hold Time
Data Mask to DQS Setup Time
Data Mask to DQS Hold Time
Clock to DQS Write Preamb. Setup Time
Clock to DQS Write Preamble Hold Time
DQS Write Postamble Hold Time
Write Recovery Time
Data Sheet
tRCDWR
tDQSS
tQDQSS
tQDQSH
tDMDQSS
tDMDQSH
tWPRES
tWPREH
tWPST
tWR
47
2
—
2
—
0.75
1.1
0.75
1.25
tCK
tCK
0.40
—
0.6
—
ns
—
0.40
—
0.6
—
ns
—
0.40
—
0.6
—
ns
—
0.40
—
0.6
—
ns
—
0
—
0
—
—
0.25
—
0.25
—
0.4
0.6
0.4
0.6
tCK
tCK
tCK
tCK
2
—
2
—
—
—
—
3)
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Electrical Characteristics
Table 18
Timing Parameters for speed sorts L3.6 and L4.5 (cont’d)
Part Number Extension
L3.6
L4.5
Unit Note 1)
Interface
MIM
WM/MIM
—
2)
Parameter
Symbol min.
max.
min.
max.
—
—
Internal WRITE to READ command delay
tWTR
tDQSH
tDQSL
1
—
1
—
—
0.35
0.65
0.35
0.65
0.35
0.65
0.35
0.65
tCK
tCK
tCK
tREF
tREFC
tREFC
—
32
—
32
ms
—
—
7.8
—
7.8
us
—
—
15.7
—
15.7
us
—
tMRD
tSREX
tPDEX
2
—
2
—
—
200
—
200
—
tCK
tCK
1*tCK+tIS —
ns
—
Write DQS High level Width
Write DQS Low level Width
—
—
Refresh Cycle
Refresh Period (4096 cycles)
Average periodic refresh interval
Refresh to Refresh command interval
Mode Setup, Power Down & Self Refresh
Mode Register Set cycle time
Self Refresh Exit time
Power Down Exit time
2*tCK+tIS —
—
1) All parameters only valid for: TA = 0 to 70 °C; VSS = 0 V; 2.375 V < VDD < 2.9 V for L3.6; VDD = 2.5 V ± 0.125 V for L4.5;
VDDQ = 2.5 V ± 0.125 V
2) Maximum clock rate is only guaranteed with the specified interface. The SSTL2-Weak Mode interface is limited to a
maximum speed of 250MHz.
3) The Write Recovery Time starts at the first rising edge of clock after the last valid (falling) DQS edge of the slowest DQS
signal.
Table 19
HYB25D128323C–3
Frequency / tCK
CAS latency
tRC
tRFC
tRAS
tRP
tWR
tRRD
tDAL
tRCDRD
tRCDWR
Units
333 MHz / 3.0 ns
4
13
15
9
4
2
3
6
4
2
tCK
300 MHz / 3.3 ns
4
13
15
9
4
2
3
6
4
2
tCK
278 MHz / 3.6 ns
4
13
15
9
4
2
3
6
4
2
tCK
250 MHz / 4.0 ns
3
12
14
8
4
2
3
6
3
2
tCK
222 MHz / 4.5 ns
3
10
12
7
3
2
2
5
3
2
tCK
200 MHz / 5.0 ns
3
9
11
6
3
2
2
5
3
2
tCK
Data Sheet
48
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Electrical Characteristics
Table 20
HYB25D128323C–3.3
Frequency / tCK
CAS latency
tRC
tRFC
tRAS
tRP
tWR
tRRD
tDAL
tRCDRD
tRCDWR
Units
300 MHz / 3.3 ns
4
13
15
9
4
2
3
6
4
2
tCK
278 MHz / 3.6 ns
4
13
15
9
4
2
3
6
4
2
tCK
250 MHz / 4.0 ns
3
12
14
8
4
2
3
6
3
2
tCK
222 MHz / 4.5 ns
3
10
12
7
3
2
2
5
3
2
tCK
200 MHz / 5.0 ns
3
9
11
6
3
2
2
5
3
2
tCK
Table 21
HYB25D128323C–3.6
Frequency / tCK
CAS latency
tRC tRFC
tRAS
tRP
tWR
tRRD
tDAL
tRCDRD
tRCDWR
Units
278 MHz / 3.6 ns
4
13
15
9
4
2
3
6
4
2
tCK
250 MHz / 4.0 ns
4
13
15
9
4
2
3
6
4
2
tCK
222 MHz / 4.5 ns
3
12
14
8
4
2
2
6
4
2
tCK
200 MHz / 5.0 ns
3
10
12
7
3
2
2
5
3
2
tCK
Table 22
HYB25D128323C–4.5
Frequency / tCK
CAS latency
tRC tRFC
tRAS
tRP
tWR
tRRD
tDAL
tRCDRD
tRCDWR
Units
222 MHz / 4.5 ns
3
12
14
8
4
2
2
6
4
2
tCK
200 MHz / 5.0 ns
3
12
14
8
4
2
2
6
4
2
tCK
183 MHz / 5.5 ns
3
12
14
8
4
2
2
6
4
2
tCK
Table 23
HYB25D128323C–5
Frequency / tCK
CAS latency
tRC tRFC
tRAS
tRP
tWR
tRRD
tDAL
tRCDRD
tRCDWR
Units
200 MHz / 5.0 ns
3
12
14
8
4
2
2
6
4
2
tCK
183 MHz / 5.5 ns
3
12
14
8
4
2
2
6
4
2
tCK
Data Sheet
49
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Electrical Characteristics
Table 24
HYB25D128323CL3.6
Frequency / tCK
CAS latency
tRC tRFC
tRAS
tRP
tWR
tRRD
tDAL
tRCDRD
tRCDWR
Units
278 MHz / 3.6 ns
4
13
15
9
4
2
3
6
4
2
tCK
250 MHz / 4.0 ns
4
13
15
9
4
2
3
6
4
2
tCK
222 MHz / 4.5 ns
3
12
14
8
4
2
2
6
4
2
tCK
200 MHz / 5.0 ns
3
10
12
7
3
2
2
5
3
2
tCK
166 MHz / 6.0 ns
3
9
11
6
3
2
2
5
3
2
tCK
Table 25
HYB25D128323CL4.5
Frequency / tCK
CAS latency
tRC tRFC
tRAS
tRP
tWR
tRRD
tDAL
tRCDRD
tRCDWR
Units
222 MHz / 4.5 ns
3
12
14
8
4
2
2
6
4
2
tCK
200 MHz / 5.0 ns
3
12
14
8
4
2
2
6
4
2
tCK
183 MHz / 5.5 ns
3
12
14
8
4
2
2
6
4
2
tCK
166 MHz / 6.0 ns
3
10
12
7
3
2
2
5
3
2
tCK
143 MHz / 7.0 ns
3
9
11
6
3
2
2
5
3
2
tCK
Table 26
Operating Currents
Parameter & Test Condition
Symbol
–3
–3.3 –3.6 –4.5 –5.0 L3.6 L4.5 Unit Notes
max.
typ.
typ.
OPERATING CURRENT: One bank; IDD0
Active-Precharge; tRC = tRC(min.);
tCK = tCK(min.); DQ, DM and DQS inputs
changing once per clock cycle;
Address and control inputs changing
once every two clock cycles
200
190
180
160
150
mA
OPERATING CURRENT: One bank; IDD1
Active-Read-Precharge; BL=4; CL=4;
tRCDDC = 4*tCK; tRC = tRC(min.);
tCK = tCK(min.); IOUT = 0mA; Address and
control inputs changing once per clock
cycle
230
220
110
190
180
mA
PRECHARGE POWER-DOWN
IDD2P
STANDBY CURRENT: All banks idle;
power-down mode; tCK = tCK(min.);
CKE=LOW
26
22
22
14
14
Data Sheet
50
10
7
1)
mA
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Electrical Characteristics
Table 26
Operating Currents (cont’d)
Parameter & Test Condition
Symbol
–3
–3.3 –3.6 –4.5 –5.0 L3.6 L4.5 Unit Notes
max.
IDD2F
typ.
typ.
130
120
110
100
100
mA
65
60
55
50
50
mA
IDD3N
130
120
110
100
100
mA
OPERATING CURRENT BURST
IDD4R
READ: BL=2; READS; Continuous
burst; one bank active; Address and
control inputs changing once per clock
cycle; tCK = tCK(min.); Iout=0mA; 50% of
data changing on every transfer
370
350
330
290
280
190
160
mA
OPERATING CURRENT BURST
IDD4W
WRITE: BL=2; WRITES; Continuous
burst; one bank active; Address and
control inputs changing once per clock
cycle; tCK = tCK(min.); DQ, DQS, and DM
changing twice per clock cycle; 50% of
data changing on every transfer
370
350
330
290
280
200
175
mA
IDLE STANDBY CURRENT:
CKE=HIGH; CS#=HIGH
(DESELECT); All banks idle;
tCK = tCK(min.); Address and control
inputs changing once per clock cycle;
VIN = VREF for DQ, DQS and DM
ACTIVE POWER-DOWN STANDBY IDD3P
CURRENT: one bank active; powerdown mode; CKE=LOW; tCK = tCK(min.);
ACTIVE STANDBY CURRENT:
CS#=HIGH; CKE=HIGH; one bank
active; tRC = tRC(max.); tCK = tCK(min.);
Address and control inputs changing
once per clock cycle; DQ, DQS, and
DM inputs changing twice per clock
cycle
AUTO REFRESH CURRENT:
tRC = tRFC(min.); tCK = tCK(min.)
IDD5
320
300
280
240
230
SELF REFRESH CURRENT: Self
Refresh Mode; CKE<=0.2V;
tCK = tCK(min.)
IDD6
20
16
16
10
10
430
400
370
320
300
IDD7
BURST OPERATING CURRENT 4
bank operation:
Four bank interleaving READs; BL=4;
with Auto Precharge; tRC = tRC(min.);
tCK = tCK(min.); Address and control
inputs change only during Active,
READ, or WRITE commands
mA
4
3
mA
mA
1)
1) Measured with output open.
Data Sheet
51
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Package Outlines
5
Package Outlines
Module Package
The package is conforming with JEDEC MO-205 Variation BD
General Tolerances according to ISO 8015
The inner matrix of 4 × 4 balls is reserved for thermal contacts
11.1
10.9
0.10
11.1
10.9
1.50
1.44
1.36
8.8
8.8
0.8
--
-0.85
0.8
--
8.8
8.8
MAX
All dimensions in mm. Notation is TYP or MAX or TYP
MIN
MIN
Figure 32
Data Sheet
Package Outlines
52
V1.7, 2003-07
www.infineon.com
Published by Infineon Technologies AG