LT1994 Low Noise, Low Distortion Fully Differential Input/ Output Amplifier/Driver U DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LT®1994 is a high precision, very low noise, low distortion, fully differential input/output amplifier optimized for 3V, single supply operation. The LT1994’s output common mode voltage is independent of the input common mode voltage, and is adjustable by applying a voltage on the VOCM pin. A separate internal common mode feedback path provides accurate output phase balancing and reduced even-order harmonics. This makes the LT1994 ideal for level shifting ground referenced signals for driving differential input, single supply ADCs. Fully Differential Input and Output Wide Supply Range: 2.375V to 12.6V Rail-to-Rail Output Swing Low Noise: 3nV/√Hz Low Distortion, 2VP-P, 1MHz: –94dBc Adjustable Output Common Mode Voltage Unity Gain Stable Gain-Bandwidth: 70MHz Slew Rate: 65V/μs Large Output Current: 85mA DC Voltage Offset <2mV MAX Open-Loop Gain: 100V/mV Low Power Shutdown 8-Pin MSOP or 3mm × 3mm DFN Package The LT1994 output can swing rail-to-rail and is capable of sourcing and sinking up to 85mA. In addition to the low distortion characteristics, the LT1994 has a low input referred voltage noise of 3nV/√Hz. This part maintains its performance for supply voltages as low as 2.375V. It draws only 13.3mA of supply current and has a hardware shutdown feature that reduces current consumption to 225µA. U APPLICATIO S ■ ■ ■ ■ Differential Input A/D Converter Driver Single-Ended to Differential Conversion Differential Amplification with Common Mode Translation Rail-to-Rail Differential Line Driver/Receiver Low Voltage, Low Noise, Differential Signal Processing The LT1994 is available in an 8-pin MSOP or 8-pin DFN package. , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. U ■ TYPICAL APPLICATIO LT1994 Driving an LTC1403A-1 1MHz Sine Wave, 8192 Point FFT Plot 499Ω 499Ω 3V 10µF 3V VIN 2VP-P 0.1µF – + VOCM LT1994 0.1µF + – 24.9Ω 24.9Ω VOCM = 1.5V AIN+ 47pF VDD SD0 CONV LTC1403A-1 AIN– SCK 50.4MHz GND VREF 10µF DIFFERENTIAL OUTPUT MAGNITUDE (dB) A/D Preamplifier: Single-Ended Input to Differential Output with Common Mode Level Shifting 0 FSAMPLE = 2.8Msps –10 F = 1.001MHz IN –20 INPUT = 2VP-P, SINGLE ENDED –30 SFDR = 93dB –40 –50 –60 –70 –80 –90 –100 –110 –120 499Ω 499Ω 1994 TA01 0 1.05 0.35 0.70 FREQUENCY (MHz) 1.40 1994 TA01b 1994fa 1 LT1994 W W U W ABSOLUTE AXI U RATI GS (Note 1) Total Supply Voltage (V+ to V–) ..............................12.6V Input Voltage (Note 2)...............................................±VS Input Current (Note 2)..........................................±10mA Input Current (VOCM, ⎯S⎯H⎯D⎯N) ................................±10mA VOCM, ⎯S⎯H⎯D⎯N .............................................................±VS Output Short-Circuit Duration (Note 3) ............ Indefinite Operating Temperature Range (Note 4) ... –40°C to 85°C Specified Temperature Range (Note 5) .... –40°C to 85°C Junction Temperature MS8 .................................................................. 150°C DFN8................................................................. 125°C Storage Temperature Range MS8 ................................................... –65°C to 150°C DFN8.................................................. –65°C to 125°C U W U PACKAGE/ORDER I FOR ATIO TOP VIEW IN– 1 VOCM 2 V+ 3 OUT+ 4 TOP VIEW 8 IN+ IN– 1 VOCM 2 V+ 3 OUT+ 4 7 SHDN 6 V – 5 OUT– 8 7 6 5 IN+ SHDN V– OUT– MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 150°C, θJA = 140°C/W DD PACKAGE 8-LEAD (3mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 160°C/W UNDERSIDE METAL CONNECTED TO V– ORDER PART NUMBER DD PART MARKING* ORDER PART NUMBER MS8 PART MARKING* LT1994CDD LT1994IDD LBQM LBQM LT1994CMS8 LT1994IMS8 LTBQN LTBQN Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3V, V– = 0V, VCM = VOCM = VICM = mid-supply, V⎯S⎯H⎯D⎯N = OPEN, RI = RF = 499Ω, RL = 800Ω to a mid-supply voltage (See Figure 1) unless otherwise noted. VS is defined (V+ – V–). VOUTCM is defined as (VOUT+ + VOUT–)/2. VICM is defined as (VIN+ + VIN–)/2. VOUTDIFF is defined as (VOUT+ – VOUT–). VINDIFF is defined as (VIN+ – VIN–). SYMBOL VOSDIFF PARAMETER Differential Offset Voltage (Input Referred) ΔVOSDIFF/ΔT Differential Offset Voltage Drift (Input Referred) IB Input Bias Current (Note 6) CONDITIONS VS = 2.375V, VICM = VS/4 VS = 3V VS = 5V VS = ±5V VS = 2.375V, VICM = VS/4 VS = 3V VS = 5V VS = ±5V VS = 2.375V, VICM = VS/4 VS = 3V VS = 5V VS = ±5V MIN TYP –45 –45 –45 –45 3 3 3 3 –18 –18 –18 –18 ● ● ● ● ● ● ● ● MAX ±2 ±2 ±2 ±3 –3 –3 –3 –3 UNITS mV mV mV mV μV/°C μV/°C μV/°C μV/°C μA μA μA μA 1994fa 2 LT1994 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3V, V– = 0V, VCM = VOCM = VICM = mid-supply, V⎯S⎯H⎯D⎯N = OPEN, RI = RF = 499Ω, RL = 800Ω to a mid-supply voltage (See Figure 1) unless otherwise noted. VS is defined (V+ – V–). VOUTCM is defined as (VOUT+ + VOUT–)/2. VICM is defined as (VIN+ + VIN–)/2. VOUTDIFF is defined as (VOUT+ – VOUT–). VINDIFF is defined as (VIN+ – VIN–). SYMBOL IOS PARAMETER Input Offset Current (Note 6) RIN Input Resistance CIN Input Capacitance en Differential Input Referred Noise Voltage f = 50kHz Density Input Noise Current Density f = 50kHz in enVOCM Input Referred Common Mode Output Noise Voltage Density Input Signal Common Mode Range VICMR (Note 7) CMRRI (Note 8) CMRRIO (Note 8) PSRR (Note 9) PSRRCM (Note 9) GCM Input Common Mode Rejection Ratio (Input Referred) ΔVICM/ΔVOSDIFF Output Common Mode Rejection Ratio (Input Referred) ΔVOCM/ΔVOSDIFF Differential Power Supply Rejection (ΔVS/ΔVOSDIFF) Output Common Mode Power Supply Rejection (ΔVS/ΔVOSOCM) Common Mode Gain (∆VOUTCM/ΔVOCM) BAL Common Mode Gain Error 100 • (GCM – 1) Output Balance (ΔVOUTCM/ΔVOUTDIFF) CONDITIONS VS = 2.375V, VICM = VS/4 VS = 3V VS = 5V VS = ±5V Common Mode Differential Mode Differential MIN ● ● ● ● f = 50kHz, VOCM Shorted to Ground VS = 3V VS = ±5V VS = 3V, ΔVICM = 0.75V ● ● TYP ±0.2 ±0.2 ±0.2 ±0.2 700 4.5 2 MAX ±2 ±2 ±3 ±4 UNITS μA μA μA μA kΩ kΩ pF 3 nV/√Hz 2.5 pA/√Hz 15 nV/√Hz ● 0 –5 55 85 V V dB VS = 5V, ΔVOCM = 2V ● 65 85 dB VS = 3V to ±5V ● 69 105 dB VS = 3V to ±5V ● 45 70 dB VS = ±2.5V ● 1 V/V VS = ±2.5V ● –0.15 ±1 % ● ● –65 –71 ±2.5 ±2.5 ±2.5 ±2.5 5 5 5 5 –46 –50 ±25 ±25 ±30 ±40 dB dB mV mV mV mV μV/°C μV/°C μV/°C μV/°C V ΔVOUTDIFF = 2V Single-Ended Input Differential Input VS = 2.375V, VICM = VS/4 VS = 3V VS = 5V VS = ±5V VS = 2.375V, VICM = VS/4 VS = 3V VS = 5V VS = ±5V VS = 3V, ±5V ● ● ● ● 1.75 3.75 VOSCM Common Mode Offset Voltage (VOUTCM – VOCM) ΔVOSCM/ΔT Common Mode Offset Voltage Drift VOUTCMR (Note 7) RINVOCM Output Signal Common Mode Range (Voltage Range for the VOCM Pin) Input Resistance, VOCM Pin ● 30 40 60 VMID Voltage at the VOCM Pin VS = 5V ● 2.45 2.5 2.55 V VOUT Output Voltage, High, Either Output Pin (Note 10) VS = 3V, No Load VS = 3V, RL = 800Ω VS = 3V, RL = 100Ω VS = ±5V, No Load VS = ±5V, RL = 800Ω VS = ±5V, RL = 100Ω ● ● ● 70 90 200 150 200 900 140 175 400 325 450 2400 mV mV mV mV mV mV ● ● ● ● V– + 1.1 V+ – 0.8 kΩ 1994fa 3 LT1994 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3V, V– = 0V, VCM = VOCM = VICM = mid-supply, V⎯S⎯H⎯D⎯N = OPEN, RI = RF = 499Ω, RL = 800Ω to a mid-supply voltage (See Figure 1) unless otherwise noted. VS is defined (V+ – V–). VOUTCM is defined as (VOUT+ + VOUT–)/2. VICM is defined as (VIN+ + VIN–)/2. VOUTDIFF is defined as (VOUT+ – VOUT–). VINDIFF is defined as (VIN+ – VIN–). SYMBOL PARAMETER Output Voltage, Low, Either Output Pin (Note 10) ISC Output Short-Circuit Current, Either Output Pin (Note 11) SR Slew Rate GBW Gain-Bandwidth Product (fTEST = 1MHz) Distortion tS Settling Time AVOL Large-Signal Voltage Gain VS Supply Voltage Range IS Supply Current I⎯S⎯H⎯D⎯N Supply Current in Shutdown VIL CONDITIONS VS = 3V, No Load VS = 3V, RL = 800Ω VS = 3V, RL = 100Ω VS = ±5V, No Load VS = ±5V, RL = 800Ω VS = ±5V, RL = 100Ω VS = 2.375V, RL = 10Ω VS = 3V, RL = 10Ω VS = 5V, RL = 10Ω VS = ±5V, VCM = 0V, RL = 10Ω VS = 5V, ΔVOUT+ = –ΔVOUT– = 1V VS = ±5V, VCM = 0V, ΔVOUT+ = –ΔVOUT– = 1.8V VS = 3V, TA = 25°C VS = ±5V, VCM = 0V, TA = 25°C VS = 3V, RL = 800Ω, fIN = 1MHz, VOUT+ – VOUT– = 2VP-P Differential Input 2nd Harmonic 3rd Harmonic Single-Ended Input 2nd Harmonic 3rd Harmonic VS = 3V, 0.01%, 2V Step VS = 3V, 0.1%, 2V Step VS = 3V MIN ● ● ±25 ±30 ±40 ±45 50 50 TYP 30 50 125 80 125 900 ±35 ±40 ±65 ±85 65 65 ● ● 58 58 70 70 MHz MHz –99 –96 dBc dBc –94 –108 120 90 100 dBc dBc ns ns dB ● ● ● ● ● ● ● ● ● ● ● 2.375 MAX 70 90 250 180 250 2400 85 85 12.6 UNITS mV mV mV mV mV mV mA mA mA mA V/μS V/μS V ● ● ● ⎯S⎯H⎯D⎯N Input Logic Low VS = 3V VS = 5V VS = ±5V VS = 3V VS = 5V VS = ±5V VS = 3V to ±5V VIH ⎯S⎯H⎯D⎯N Input Logic High VS = 3V to ±5V ● R⎯S⎯H⎯D⎯N ⎯S⎯H⎯D⎯N Pull-Up Resistor VS = 2.375V to ±5V tON Turn-On Time V⎯S⎯H⎯D⎯N 0.5V to 3V 1 μs tOFF Turn-Off Time V⎯S⎯H⎯D⎯N 3V to 0.5V 1 μs Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The inputs are protected by a pair of back-to-back diodes. If the differential input voltage exceeds 1V, the input current should be limited to less than 10mA. Note 3: A heat sink may be required to keep the junction temperature below the absolute maximum rating when the output is shorted indefinitely. ● ● ● 13.3 13.9 14.8 0.225 0.375 0.7 18.5 19.5 20.5 0.8 1.75 2.5 + V – 2.1 mA mA mA mA mA mA V 55 75 kΩ ● V+ – 0.6 40 V Note 4: The LT1994C/LT1994I are guaranteed functional over the operating temperature range –40°C to 85°C. Note 5: The LT1994C is guaranteed to meet specified performance from 0°C to 70°C. The LT1994C is designed, characterized, and expected to meet specified performance from –40°C to 85°C but is not tested or QA sampled at these temperatures. The LT1994I is guaranteed to meet specified performance from –40°C to 85°C. Note 6: Input bias current is defined as the average of the input currents flowing into Pin 1 and Pin 8 (IN– and IN+). Input Offset current is defined as the difference of the input currents flowing into Pin 8 and Pin 1 (IOS = IB+ – IB–). 1994fa 4 LT1994 ELECTRICAL CHARACTERISTICS Note 7: Input Common Mode Range is tested using the Test Circuit of Figure 1 (RF = RI) by applying a single ended 2VP-P, 1kHz signal to VINP (VINM = 0), and measuring the output distortion (THD) at the common mode Voltage Range limits listed in the Electrical Characteristics table, and confirming the output THD is better than –40dB. The voltage range for the output common mode range (Pin 2) is tested using the Test Circuit of Figure 1 (RF = RI) by applying a 0.5V peak, 1kHz signal to the VOCM Pin 2 (with VINP = VINM = 0) and measuring the output distortion (THD) at VOUTCM with VOCM biased 0.5V from the VOCM pin range limits listed in the Electrical Characteristics Table, and confirming the THD is better than –40dB. Note 8: Input CMRR is defined as the ratio of the change in the input common mode voltage at the pins IN+ or IN– to the change in differential input referred voltage offset. Output CMRR is defined as the ratio of the change in the voltage at the VOCM pin to the change in differential input referred voltage offset. Note 9: Differential Power Supply Rejection (PSRR) is defined as the ratio of the change in supply voltage to the change in differential input referred voltage offset. Common Mode Power Supply Rejection (PSRRCM) is defined as the ratio of the change in supply voltage to the change in the common mode offset, VOUTCM – VOCM. Note 10: Output swings are measured as differences between the output and the respective power supply rail. Note 11: Extended operation with the output shorted may cause junction temperatures to exceed the 150°C limit for the MSOP package (or 125°C for the DD package) and is not recommended. U W TYPICAL PERFOR A CE CHARACTERISTICS Common Mode Voltage Offset vs Temperature 7.5 COMMON MODE VOLTAGE OFFSET (mV) VS = 3V VCM = 1.5V VOCM = 1.5V 250 FOUR TYPICAL UNITS 0 –250 –500 –25 0 25 50 TEMPERATURE (°C) 75 100 IB, VS = ±5V 2.5 0 –15 0.5 IOS, VS = 3V –20 IOS, VS = ±5V 0 –25 –0.5 IB, VS = 3V –2.5 –50 –25 0 25 50 TEMPERATURE (°C) 75 1994 G01 100 –30 –50 –25 0 25 50 TEMPERATURE (°C) 75 1994 G02 72 2 –1.0 100 1994 G03 Frequency Response vs Supply Voltage Gain Bandwidth vs Temperature Frequency Response vs Load Capacitance 2 RF = RI = 499Ω RF = RI = 499Ω VS = 2.5V 71 VS = ±5V VS = 3V VS = 2.5V 1 1 VS = 5V 70 GAIN (dB) GAIN BANDWIDTH (MHz) 1.0 VS = 3V 69 GAIN (dB) –750 –50 5.0 –10 VS = 3V VCM = 1.5V VOCM = 1.5V FOUR TYPICAL UNITS INPUT OFFSET CURRENT (µA) DIFFERENTIAL VOS (µV) 500 Input Bias Current and Input Offset Current vs Temperature INPUT BIAS CURRENT (µA) Differential Input Referred Voltage Offset vs Temperature 0 VS = ±5V VS = 3V 0 68 –1 –1 5pF FROM EACH OUTPUT TO GROUND 25pF FROM EACH OUTPUT TO GROUND 67 66 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 1994 G04 –2 0.1 1 10 FREQUENCY (MHz) 100 1994 G05 –2 0.1 1 10 FREQUENCY (MHz) 100 1994 G06 1994fa 5 LT1994 U W TYPICAL PERFOR A CE CHARACTERISTICS Output Impedance vs Frequency 100 Differential Power Supply Rejection vs Frequency Output Balance vs Frequency –30 VS = 3V RF = RI = 499Ω 110 ∆VOUTCM ∆VOUTDIFF 1 90 DIFFERENTIAL PSRR (dB) OUTPUT BALANCE (dB) ZOUT OUT+, OUT– (Ω) –40 10 –50 –60 SINGLE ENDED INPUT –70 DIFFERENTIAL INPUT 80 –90 1 10 FREQUENCY (MHz) 50 40 30 10 VS = 3V 1k 100 0 10k 100k 1M FREQUENCY (Hz) 10M Input Common Mode Rejection vs Frequency 60 ∆VS ∆VOSOCM V– SUPPLY COMMON MODE PSRR (dB) 50 VS = ±5V 80 70 60 50 40 V+ SUPPLY 30 20 10 40 VS = 3V 0 0.1 30 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 1 10 FREQUENCY (MHz) 100 1995 G10 10M 2ND, VICM = 1.5V 2ND, VCM = V– 3RD, VCM = V– –100 100M 1995 G09 Input Noise vs Frequency 100 100 VS = 3V TA = 25°C 10 10 en in 1 10 100 1k 10k FREQUENCY (Hz) 100k 1 1M 1995 G12 –40 VS = 3V FIN = 1MHz RF = RI = 499Ω –70 R = 800Ω L VOCM = MID-SUPPLY DISTORTION HD2, HD3 (dB) DISTORTION HD2, HD3 (dB) 100k 1M FREQUENCY (Hz) Differential Distortion vs Input Common Mode Level –60 –90 10k 1995 G11 Differential Distortion vs Input Amplitude (Single Ended Input) –80 VS = 3V 1k INPUT CURRENT NOISE DENSITY (pA/√Hz) 90 INPUT CMRR (dB) Common Mode Output Power Supply Rejection vs Frequency ∆VICM ∆VOSDIFF VS = 3V 100M 1995 G08 1994 G07 100 V– SUPPLY 60 20 INPUT REFERRED VOLTAGE NOISE DENSITY (nV/√Hz) 0.1 V+ SUPPLY 70 –80 0.1 ∆VS ∆VOSDIFF 100 VS = 3V VIN = 2VP-P (SINGLE ENDED) –50 F = 1MHz IN RF = RI = 499Ω –60 RL = 800Ω VOCM = MID-SUPPLY –70 –80 –90 2ND –100 3RD, VICM = 1.5V –110 1 2 3 VIN (VP-P) 4 3RD 5 1994 G13 –110 0 2.5 0.5 1.5 2.0 1.0 INPUT COMMON MODE DC BIAS, IN– OR IN+ PINS (V) 1994 G14 1994fa 6 LT1994 U W TYPICAL PERFOR A CE CHARACTERISTICS Differential Distortion vs Frequency Slew Rate vs Temperature SLEW RATE (V/µs) 66 2ND –90 VS = 3V 64 VS = ±5V 62 –100 –110 100k 1M FREQUENCY (Hz) 10M 60 –50 +0.1% ERROR VOUT –0.1% ERROR VS = 3V RF = RI = 499Ω –25 0 25 50 TEMPERATURE (°C) 75 100 25ns/DIV 1994 G17 1994 G16 1994 G15 Small Signal Step Response 25pF LOAD Large Signal Step Response VS = 3V RF = RI = 499Ω VCM = V– OUT+ OUT+ 0.5V/DIV OUT+ 0.5V/DIV VS = 3V RF = RI = 499Ω VIN = 100mVP-P, SINGLE ENDED Output with Large Input Overdrive VS = 3V RF = RI = 499Ω 0pF LOAD 20mV/DIV DISTORTION (dB) –80 RF = RI = 499Ω SETTLE VOLTAGE ERROR (2mV/DIV) VS = 3V V = 2VP-P (SINGLE ENDED) –50 F IN = 1MHz IN RF = RI = 499Ω –60 RL = 800Ω VOCM = MID-SUPPLY –70 VICM = MID-SUPPLY 3RD 2V Step Response Settling VOUT = VOUT+ – VOUT– (0.5V/DIV) 68 –40 OUT– OUT– OUT– VIN = 3VP-P SINGLE ENDED VIN = 10VP-P SINGLE ENDED 100ns/DIV 20ns/DIV 1994 G18 2µs/DIV 1994 G19 1994 G20 1994fa 7 LT1994 U W TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs ⎯S⎯H⎯D⎯N Voltage SHDN PIN VOLTAGE = V+ TOTAL SUPPLY CURRENT (mA) TOTAL SUPPLY CURRENT (mA) 16 TA = 85°C 15 TA = –40°C TA = 0°C 10 TA = 25°C TA = 70°C 5 Supply Current vs ⎯S⎯H⎯D⎯N Voltage 16 VS = 5V TOTAL SUPPLY CURRENT (mA) Supply Current vs Supply Voltage 20 12 TA = –40°C 8 TA = 0°C TA = 25°C 4 TA = 85°C VS = 3V 12 TA = –40°C 8 TA = 85°C TA = 0°C TA = 70°C TA = 25°C 4 TA = 70°C 0 0 2.5 5.0 7.5 10.0 SUPPLY VOLTAGE (V) 12.5 0 0 1 2 3 4 SHDN PIN VOLTAGE (V) 1994 G21 SHUTDOWN SUPPLY CURRENT (µA) SHDN PIN CURRENT (µA) TA = 0°C TA = 25°C TA = 70°C TA = 85°C –20 0.5 1.5 2.0 2.5 1.0 SHDN PIN VOLTAGE (V) 3.0 1994 G23 750 TA = 25°C 500 TA = 85°C TA = –40°C 250 0 0 0.5 1000 TA = –40°C –30 0 Shutdown Supply Current vs Supply Voltage VS = 3V –10 0 1994 G22 ⎯S⎯H⎯D⎯N Pin Current vs ⎯S⎯H⎯D⎯N Pin Voltage 0 5 1.5 2.0 2.5 1.0 SHDN PIN VOLTAGE (V) 3.0 1994 G24 0 2.5 7.5 10.0 5.0 SUPPLY VOLTAGE (V) 12.5 1994 G25 1994fa 8 LT1994 U U U PI FU CTIO S IN+, IN– (Pins 1, 8): Non-Inverting and Inverting Input Pins of the Amplifier, respectively. For best performance, it is highly recommended that stray capacitance be kept to an absolute minimum by keeping printed circuit connections as short as possible, and if necessary, stripping back nearby surrounding ground plane away from these pins. VOCM (Pin 2): Output Common Mode Reference Voltage. The VOCM pin is the midpoint of an internal resistive voltage divider between the supplies, developing a (default) mid-supply voltage potential to maximize output signal swing. VOCM has a Thevenin equivalent resistance of approximately 40kΩ and can be overdriven by an external voltage reference. The voltage on VOCM sets the output common mode voltage level (which is defined as the average of the voltages on the OUT+ and OUT– pins). VOCM should be bypassed with a high quality ceramic bypass capacitor of at least 0.1μF (unless connected directly to a low impedance, low noise ground plane) to minimize common mode noise from being converted to differential noise by impedance mismatches both externally and internally to the IC. V+, V– (Pins 3, 6): Power Supply Pins. For single supply applications (Pin 6 grounded) it is recommended that high quality 1μF and 0.1µF ceramic bypass capacitors be placed from the positive supply pin (Pin 3) to the negative supply pin (Pin 6) with minimal routing. Pin 6 should be directly tied to a low impedance ground plane. For dual power supplies, it is recommended that high quality, 0.1μF ceramic capacitors are used to bypass Pin 3 to ground and Pin 6 to ground. It is also highly recommended that high quality 1µF and 0.1µF ceramic bypass capacitors be placed across the power supply pins (Pins 3 and 6) with minimal routing. OUT+, OUT– (Pins 4, 5): Output Pins. Each pin can drive approximately 100Ω to ground with a short circuit current limit of up to ±85mA. Each amplifier output is designed to drive a load capacitance of 25pF. This basically means the amplifier can drive 25pF from each output to ground or 12.5pF differentially. Larger capacitive loads should be decoupled with at least 25Ω resistors from each output. SHDN (Pin 7): When Pin 7 (⎯S⎯H⎯D⎯N) is floating or when Pin 7 is directly tied to V+, the LT1994 is in the normal operating mode. When Pin 7 is pulled a minimum of 2.1V below V+, the LT1994 enters into a low power shutdown state. Refer to the ⎯S⎯H⎯D⎯N pin section under Applications Information for description of the LT1994 output impedance in the shutdown state. 1994fa 9 LT1994 U W U U APPLICATIO S I FOR ATIO Functional Description The LT1994 is a small outline, wide band, low noise, and low distortion fully-differential amplifier with accurate output phase balancing. The LT1994 is optimized to drive low voltage, single-supply, differential input analog-to-digital converters (ADCs). The LT1994’s output is capable of swinging rail-to-rail on supplies as low as 2.5V, which makes the amplifier ideal for converting ground referenced, single-ended signals into VOCM referenced differential signals in preparation for driving low voltage, single-supply, differential input ADCs. Unlike traditional op amps which have a single output, the LT1994 has two outputs to process signals differentially. This allows for two times the signal swing in low voltage systems when compared to single-ended output amplifiers. The balanced differential nature of the amplifier also provides even-order harmonic distortion cancellation, and less susceptibility to common mode noise (like power supply noise). The LT1994 can be used as a single ended input to differential output amplifier, or as a differential input to differential output amplifier. The LT1994’s output common mode voltage, defined as the average of the two output voltages, is independent of the input common mode voltage, and is adjusted by applying a voltage on the VOCM pin. If the pin is left open, there is an internal resistive voltage divider, which develops a potential halfway between the V+ and V– pins. The VOCM pin will have an equivalent Thevenin equivalent resistance of 40kΩ, and a Thevenin equivalent voltage of half-supply. Whenever this pin is not hard tied to a low impedance ground plane, it is recommended that a high quality ceramic cap is used to bypass the VOCM pin to a low impedance ground plane (see Layout Considerations in this document). The LT1994’s internal common mode feedback path forces accurate output phase balancing to reduce even order harmonics, and centers each individual output about the potential set by the VOCM pin. VOUT + + VOUT – VOUTCM = VOCM = 2 The outputs (OUT+ and OUT–) of the LT1994 are capable of swinging rail-to-rail. They can source or sink up to approximately 85mA of current. Each output is rated to drive approximately 25pF to ground (12.5pF differentially). Higher load capacitances should be decoupled with at least 25Ω of series resistance from each output. Input Pin Protection The LT1994’s input stage is protected against differential input voltages that exceed 1V by two pairs of back-toback diodes that protect against emitter base breakdown of the input transistors. In addition, the input pins have steering diodes to either power supply. If the input pair is over-driven, the current should be limited to under 10mA to prevent damage to the IC. The LT1994 also has steering diodes to either power supply on the VOCM, and ⎯S⎯H⎯D⎯N pins (Pins 2 and 7) and if exposed to voltages that exceed either supply, they too should be current limited to under 10mA. ⎯S⎯H⎯D⎯N Pin If the ⎯S⎯H⎯D⎯N pin (Pin 7) is pulled 2.1V below the positive supply, an internal current is generated that is used to power down the LT1994. The pin will have the Thevenin equivalent impedance of approximately 55kΩ to V+. If the pin is left unconnected, an internal pull-up resistor of 120kΩ will keep the part in normal active operation. Care should be taken to control leakage currents at this pin to under 1μA to prevent leakage currents from inadvertently putting the LT1994 into shutdown. In shutdown, all biasing current sources are shut off, and the output pins OUT+ and OUT– will each appear as open collectors with a nonlinear capacitor in parallel, and steering diodes to either supply. Because of the non-linear capacitance, the outputs still have the ability to sink and source small amounts of transient current if exposed to significant voltage transients. The inputs (IN+, and IN–) have anti-parallel diodes that can conduct if voltage transients at the input exceed 1V. The inputs also have steering diodes to either supply. The turn-on and turn-off time between the shutdown and active states are on the order of 1μs but depends on the circuit configuration. General Amplifier Applications As levels of integration have increased and, correspondingly, system supply voltages decreased, there has been 1994fa 10 LT1994 U U W U APPLICATIO S I FOR ATIO a need for ADCs to process signals differentially in order to maintain good signal to noise ratios. These ADCs are typically supplied from a single supply voltage that can be as low as 2.5V and will have an optimal common mode input range near mid-supply. The LT1994 makes interfacing to these ADCs trivial, by providing both single ended to differential conversion as well as common mode level shifting. Figure 1 shows a general single supply application with perfectly matched feedback networks from OUT+ and OUT–. The gain to VOUTDIFF from VINM and VINP is: VOUTDIFF = VOUT + – VOUT – ≈ RF • (VINP – VINM ) RI Note from the above equation that the differential output voltage (VOUT+ – VOUT–) is completely independent of input and output common mode voltages, or the voltage at the common mode pin. This makes the LT1994 ideally suited pre-amplification, level shifting, and conversion of single ended signals to differential output signals in preparation for driving differential input ADCs. βAVG is defined as the average feedback factor (or gain) from the outputs to their respective inputs: 1 ⎛ RI2 RI1 ⎞ + β AVG = • ⎜ ⎟ 2 ⎝ RI2 + RF2 RI1 + RF1 ⎠ Δβ is defined as the difference in feedback factors: ∆β = RI2 RI1 – RI2 + RF2 RI1 + RF1 VICM is defined as the average of the two input voltages, VINP and VINM (also called the input common mode voltage): 1 VICM = • (VINP + VINM ) 2 and VINDIFF is defined as the difference of the input voltages: VINDIFF = VINP – VINM Effects of Resistor Pair Mismatch Figure 2 shows a circuit diagram that takes into consideration that real world resistors will not perfectly match. Assuming infinite open loop gain, the differential output relationship is given by the equation: VOUTDIFF = VOUT + – VOUT – ≅ where: RF is the average of RF1 and RF2, and RI is the average of RI1 and RI2. RF • VINDIFF + RI When the feedback ratios mismatch (Δβ), common mode to differential conversion occurs. Setting the differential input to zero (VINDIFF = 0), the degree of common mode to differential conversion is given ∆β ∆β • VICM – • VOCM, β AVG β AVG RI VIN– VOUT+ RF VIN– RF2 RI2 RL VOUT+ RL V+ 0.1µF VS RBAL VINM VINM 3 3 1 VOCM 2 8 VCM 0.1µF – + VOCM 1 4 0.1µF LT1994 – + VOCM VOUTCM 2 8 0.1µF 5 – VOCM VIN RBAL 0.1µF VSHDN RF V – SHDN 0.1µF 5 6 7 RI 4 LT1994 + 6 VINP + – VINP 7 VSHDNB VOUT– + Figure 1. Test Circuit 1994 F01 RL RI1 RF1 VIN VOUT– RL + 1994 F02 Figure 2. Real-World Application 1994fa 11 LT1994 U W U U APPLICATIO S I FOR ATIO by the equation: R1 should be chosen (see Figure 3): VOUTDIFF = VOUT + – VOUT – ≈ (VICM – VOCM ) • β∆β AVG VINDIFF = 0 In general, the degree of feedback pair mismatch is a source of common mode to differential conversion of both signals and noise. Using 1% resistors or better will provide about 28dB of common mode rejection. Using 0.1% resistors will provide about 48dB of common mode rejection. A low impedance ground plane should be used as a reference for both the input signal source and the VOCM pin. A direct short of VOCM to this ground plane or bypassing the VOCM with a high quality 0.1µF ceramic capacitor to this ground plane will further mitigate against common mode signals from being converted to differential. Input Impedance and Loading Effects The input impedance looking into the VINP or VINM input of Figure 1 depends on whether or not the sources VINP and VINM are fully differential. For balanced input sources (VINP = –VINM), the input impedance seen at either input is simply: R1 = RINM • RS RINM − RS According to Figure 3, the input impedance looking into the differential amp (RINM) reflects the single ended source case, thus: RINM = R2 is chosen to balance R1 || RS: R2 = R1 • RS R1 + RS Input Common Mode Voltage Range The LT1994’s input common mode voltage (VICM) is defined as the average of the two input voltages, VIN+, and VIN–. It extends from V– to approximately 1.25V below V+. The input common mode range depends on the circuit configuration (gain), VOCM and VCM (refer to Figure 4). For fully differential input applications, where VINP = –VINM, the common mode input is approximately: RINP = RINM = RI For single ended inputs, because of the signal imbalance at the input, the input impedance actually increases over the balanced differential case. The input impedance looking into either input is: RINP = RINM = RI ⎛ 1 ⎡ RF ⎤⎞ ⎜ 1– 2 • ⎢ R + R ⎥⎟ ⎝ ⎣ I F ⎦⎠ Input signal sources with non-zero output impedances can also cause feedback imbalance between the pair of feedback networks. For the best performance, it is recommended that the source’s output impedance be compensated for. If input impedance matching is required by the source, RI ⎛ 1 ⎡ RF ⎤⎞ ⎜ 1– 2 • ⎢ R + R ⎥⎟ ⎝ ⎣ I F ⎦⎠ VICM = ⎛ RI ⎞ VIN+ + VIN– ≈ VOCM • ⎜ ⎟+ ⎝ RI + RF ⎠ 2 ⎛ RF ⎞ VCM • ⎜ ⎟ ⎝ RF + RI ⎠ RINM RS VS RI RF R1 – + LT1994 R1 CHOSEN SO THAT R1 || RINM = RS R2 CHOSEN TO BALANCE R1 || RS + RI – RF 1994 F03 R2 = RS || R1 Figure 3. Optimal Compensation for Signal Source Impedance 1994fa 12 LT1994 U U W U APPLICATIO S I FOR ATIO RI VIN– VOUT+ RF RL VS VINM 3 1 VOCM 2 8 VCM – + VOCM 4 LT1994 – + SHDN 0.1µF 5 the input common mode voltage, it can be directly tied to the VOCM pin, but must be capable of driving a 40kΩ equivalent resistance that is tied to a mid-supply potential. If an external reference drives the VOCM pin, it should still be bypassed with a high quality 0.1μF capacitor to a low impedance ground plane to filter any thermal noise and to prevent common mode signals on this pin from being inadvertently converted to differential signals. 6 VINP Noise Considerations 7 VSHDNB RI RF VIN+ VOUT– RL 1994 F04 Figure 4. Circuit for Common Mode Range With singled ended inputs, there is an input signal component to the input common mode voltage. Applying only VINP (setting VINM to zero), the input common voltage is approximately: VICM ⎛ RI ⎞ VIN+ + VIN– = ≈ VOCM • ⎜ ⎟+ ⎝ RI + RF ⎠ 2 ⎛ RF ⎞ VINP ⎛ RF ⎞ VCM • ⎜ •⎜ ⎟ ⎟+ ⎝ RF + RI ⎠ 2 ⎝ RF + RI ⎠ Output Common Mode Voltage Range The output common mode voltage is defined as the average of the two outputs: V + + VOUT – VOUTCM = VOCM = OUT 2 The LT1994’s input referred voltage noise is on the order of 3nV/√Hz. Its input referred current noise is on the order of 2.5pA/√Hz. In addition to the noise generated by the amplifier, the surrounding feedback resistors also contribute noise. The output noise generated by both the amplifier and the feedback components is given by the equation: 2 e no = ⎛ ⎡ RF ⎤⎞ 2 ⎜ e ni • ⎢1+ R ⎥⎟ + 2 • (In • RF ) + ⎝ I ⎦⎠ ⎣ 2 ⎛ ⎡ R ⎤⎞ 2 • ⎜ e nRI • ⎢ F ⎥⎟ + 2 • e nRF2 ⎝ ⎣ RI ⎦⎠ A plot of this equation and a plot of the noise generated by the feedback components are shown in Figure 6. The LT1994’s input referred voltage noise contributes the equivalent noise of a 560Ω resistor. When the feedback enRI22 enRF22 RF2 in–2 The VOCM sets this average by an internal common mode feedback loop which internally forces VOUT+ = –VOUT–. The output common mode range extends from approximately 1.1V above V– to approximately 0.8V below V+. The VOCM pin sits in the middle of an 80kΩ to 80kΩ voltage divider that sets the default mid-supply open circuit potential. In single supply applications, where the LT1994 is used to interface to an ADC, the optimal common mode input range to the ADC is often determined by the ADC’s reference. If the ADC makes a reference available for setting RI2 VS/2 3 encm 2 1 2 8 in+2 – + VOCM 4 eno2 LT1994 – + 5 6 7 enRI1 2 RI1 eni2 –VS/2 RF1 enRF12 1994 F05 Figure 5. Noise Analysis 1994fa 13 LT1994 U W U U APPLICATIO S I FOR ATIO network is comprised of resistors whose values are less than this, the LT1994’s output noise is voltage noise dominant (See Figure 6): ⎛ R ⎞ e no ≈ e ni • ⎜ 1 + F ⎟ ⎝ RI ⎠ Feedback networks consisting of resistors with values greater than about 10kΩ will result in output noise which is amplifier current noise dominant. e no ≈ 2 • In • RF Lower resistor values always result in lower noise at the penalty of increased distortion due to increased loading of the feedback network on the output. Higher resistor values will result in higher output noise, but improved distortion due to less loading on the output. 100 OUTPUT NOISE (nV/√Hz) TOTAL (AMPLIFIER + FEEDBACK NETWORK) OUTPUT NOISE 10 FEEDBACK NETWORK NOISE ALONE 1 0.1 1 RF = RI (kΩ) 10 1994 F06 Figure 6. LT1994 Output Spot Noise vs Spot Noise Contributed by Feedback Network Alone Figure 6 shows the noise voltage that will appear differentially between the outputs. The common mode output noise voltage does not add to this differential noise. For optimum noise and distortion performance, use a differential output configuration. Power Dissipation Considerations The LT1994 is housed in either an 8-lead MSOP package (θJA = 140°C/W or an 8-lead DD package (θJA = 160°C/ W). The LT1994 combines high speed and large output current with a small die and small package so there is a need to be sure the die temperature does not exceed 150°C if housed in the 8-lead MSOP package, and 125°C if housed in the 8-lead DD package. In the 8-lead MSOP, LT1994 has its V– lead fused to the frame so it is possible to lower the package thermal impedance by connecting the V– pin to a large ground plane or metal trace. Metal trace and plated through holes can be used to spread the heat generated by the device to the backside of the PC board. For example, an 8-lead MSOP on a 3/32" FR-4 board with 540mm2 of 2oz. copper on both sides of the PC board tied to the V– pin can drop the θJA from 140°C/W to 110°C/W (see Table 1). The underside of the DD package has exposed metal (4mm2) from the lead frame where the die is attached. This provides for the direct transfer of heat from the die junction to the printed circuit board to help control the maximum operating junction temperature. The dual-inline pin arrangement allows for extended metal beyond the ends of the package on the topside (component side) of a circuit board. Table 1 summarizes for both the MSOP and DD packages, the thermal resistance from the die junction to ambient that can be obtained using various amounts of topside, and backside metal (2oz. copper). On multilayer boards, further reductions can be obtained using additional metal on inner PCB layers connected through vias beneath the package. In general, the die temperature can be estimated from the ambient temperature TA, and the device power dissipation PD: TJ = TA+ + PD • θJA 1994fa 14 LT1994 U W U U APPLICATIO S I FOR ATIO The power dissipation in the IC is a function of the supply voltage, the output voltage, and the load resistance. For fully differential output amplifiers at a given supply voltage (±VCC), and a given differential load (RLOAD), the worstcase power dissipation PD(MAX) occurs at the worst case quiescent current (IQ(MAX) = 20.5mA) and when the load current is given by the expression: ILOAD = Table 1. LT1994 MSOP and DD Package Thermal Resistivity LT1994 8-LEAD MSOP PACKAGE VCC RLOAD The worst case power dissipation in the LT1994 at V ILOAD = CC is: RLOAD ( ) PD(MAX) = 2 • VCC • ILOAD + IQ(MAX) – ILOAD2 • RLOAD To operate the device at higher ambient temperature, connect more copper to the V– pin to reduce the thermal resistance of the package as indicated in Table 1. Note that TJMAX for the 8-lead DD package is 125°C (as opposed to 150°C for the 8-lead MSOP), and the data for the equation above should be altered accordingly. V 2 = CC + 2 • VCC • IQ(MAX) RLOAD Example: A LT1994 is mounted on a circuit board in a MSOP-8 package (θJA = 140°C/W), and is running off of ±5V supplies driving an equivalent load (external load plus feedback network) of 75Ω. The worst-case power that would be dissipated in the device occurs when: VCC2 PD(MAX ) = + 2 • VCC • IQ(MAX ) = RLOAD 5V 2 + 2 • 5V • 17.5MA = 0.54W 75Ω The maximum ambient temperature the 8-lead MSOP is allowed to operate under these conditions is: LT1994 8-LEAD DD PACKAGE Copper Area Copper Area Thermal Topside Backside Resistance (mm2) (mm2) (Junction to Ambient) 0 0 140 Copper Area Topside (mm2) Thermal Resistance (Junction to Ambient) 4 160 30 0 135 16 135 100 0 130 32 110 100 100 120 64 95 540 540 110 130 70 Layout Considerations Because the LT1994 is a high speed amplifier, it is sensitive to both stray capacitance and stray inductance. Components connected to the LT1994 should be connected with as short and direct connections as possible. A low noise, low impedance ground plane is critical for the highest performance. In single supply applications, high quality surface mount 1μF and 0.1μF ceramic bypass capacitors with minimum PCB trace should be used directly across the power supplies V+ to V–. In split supply applications, high quality surface mount 1μF and 0.1μF ceramic bypass capacitors should be placed across the power supplies V+ to V–, and individual high quality surface mount 0.1μF bypass caps should be used from each supply to ground with direct (short) connections. TA = TJMAX – PD • θJA = 150°C – (0.54W) • (140°C/W) = 75°C 1994fa 15 LT1994 U U W U APPLICATIO S I FOR ATIO Any stray parasitic capacitance to ground at the summing junctions, IN+ and IN– should be kept to an absolute minimum even if it means stripping back the ground plane away from any trace attached to this node. This becomes especially true when the feedback resistor network uses resistor values >500Ω in circuits with RF = RI. Excessive peaking in the frequency response can be mitigated by adding small amounts of feedback capacitance around RF (2pF to 5pF). Always keep in mind the differential nature of the LT1994, and that it is critical that the output impedances seen by both outputs (stray or intended) should be as balanced and symmetric as possible. This will help preserve the natural balance of the LT1994, which minimizes the generation of even order harmonics, and preserves the rejection of common mode signals and noise. It is highly recommended that the VOCM pin be either hard tied to a low impedance ground plane (in split supply applications) or bypassed to ground with a high quality 0.1μF ceramic capacitor in single supply applications. This will help prevent thermal noise from the internal 80kΩ-80kΩ voltage divider (25nV/√Hz) and other external sources of noise from being converted to differential noise due to mismatches in the feedback networks. It is also recommended that the resistive feedback networks be comprised of 1% resistors (or better) to enhance the output common mode rejection. This will also prevent VOCM input referred common mode noise of the common mode amplifier path (which cannot be filtered) from being converted to differential noise, degrading the differential noise performance. W W SI PLIFIED SCHE ATIC V+ 120k SHUTDOWN CIRCUIT I1 V+ 55k I1 SHDN CM1 V+ CM2 V+ + BIAS ADJUST OUT– Q10 V– BIAS + BIAS ADJUST – – Gm2B Gm2A OUT+ Q12 V+ OUT+ +V I2 R1 4k V+ R2 4k Q2 D2 V+ D3 D4 Q3 Q4 V+ 80k Q8 VOCM 80k Q5 Q6 OUT– V– V+ I3 Q7 Q1 D1 V– V– V+ V+ IN– V+ Q11 Q9 V– V– V+ V– V– CM ADJUST I4A I4B V– IN+ 1994 SS01 V– 1994fa 16 LT1994 U TYPICAL APPLICATIO S Differential 1st Order Lowpass Filter Example: The specified –3dB frequency is 1MHz Gain = 4 Maximum –3dB frequency (f3dB) 5MHz 1. Using f3dB = 1000kHz, C11abs = 400pF Stopband attenuation: –6dB at 2 • f3dB and 14dB at 5 • f3dB 2. Nearest standard 5% value to 400pF is 390pF and C11 = C12 = 390pF C11 VIN– 3. Using f3dB = 1000kHz, C11 = 390pF and Gain = 4, R21 = R22 = 412Ω and R11 = R12 = 102Ω (nearest 1% value) R21 R11 V+ 0.1µF Differential 2nd Order Butterworth Lowpass Filter 3 1 – + 2 8 0.1µF 4 VOUT + LT1994 + – 6 5 VOUT– Maximum –3dB frequency (f3dB) 2.5MHz Stopband attenuation: –12dB at 2 • f3dB and –28dB at 5 • f3dB 7 R21 VIN+ R12 R22 VIN– R11 C21 R31 V+ 0.1µF C12 1994 TA03 3 1 Component Calculation: 2 C11 8 0.1µF R11 = R12, R21 = R22 – + 5MHz f3dB 4 • 105 C11abs = (C11abs in pF and f3dB in kHz) f3dB 2. Select a standard 5% capacitor value nearest the absolute value for C11 5 VOUT– 7 VIN+ R12 1. Calculate an absolute value for C11 (C11abs) using a specified –3dB frequency VOUT+ LT1994 + – 6 f3dB ≤ 5MHz and Gain ≤ 4 R32 R22 C22 1994 TA04 Component Calculation: R11 = R12, R21 = R22, R31 = R32, C21 = C22, C11 = 10 • C21, R1 = R11, R2 = R21, R3 = R31, C2 = C21 and C1 = C11 3. Calculate R11 and R21 using the standard 5% C11 value, f3dB and desired gain R11 and R21 equations (C11 in pF and f3dB in kHz) R21= 159.2 • 106 C11• f3dB R11= R21 Gain 1994fa 17 LT1994 U TYPICAL APPLICATIO S 1. Calculate an absolute value for C2 (C2abs) using a specified –3dB frequency Example: The specified –3dB frequency is 1MHz Gain = 1 4 • 105 (C2abs in pF and f3dB in kHz) (Note 2) f3dB 2. Nearest standard 5% value to 400pF is 390pF and C21 = C22 = 390pF and C11 = 3900pF 2. Select a standard 5% capacitor value nearest the absolute value for C2 (C1 = 10 • C2) 3. Using f3dB = 1000kHz, C2 = 390pF and Gain = 1, R1 = 549Ω, R2 = 549Ω and R3 = 15.4Ω (nearest 1% values). R11 = R21 = 549Ω, R21 = R22 = 549Ω and R31 = R32 = 15.4Ω. C2abs = 3. Calculate R3, R2 and R1 using the standard 5% C2 value, the specified f3dB and the specified passband gain (Gn) f3dB ≤ 2.5MHz and Gain ≤ 8.8 or Gain ≤ 2.5MHz f3dB R1, R2 and R3 equations (C2 in pF and f3dB in kHz) (1.121– R3 = R2 = R1= 1. Using f3dB = 1000kHz, C2abs = 400pF Note 1: The equations for R1, R2, R3 are ideal and do not account for the finite gain bandwidth product (GBW) of the LT1994 (70MHz). The maximum gain is set by the C1/C2 ratio (which for convenience is set equal to ten). Note 2: The calculated value of a capacitor is chosen to produce input resistors less than 600Ω. If a higher value input resistance is required then multiply all resistor values and divide all capacitor values by the same number. (1.131– 0.127 • Gn) ) • 108 (Note 1) (Gn + 1) • C2 • f3dB 1.266 • 1015 R3 • C22 • f3dB2 R2 Gn A Single Ended to Differential Voltage Conversion with Source Impedance Matching and Level Shifting RS = 50Ω 50Ω 374Ω 402Ω V+ VIN 0.1µF 54.9Ω V 3 1 V 1 2 8 0.1µF VIN – + –1 VOUT– VOCM LT1994 + – 6 0 4 5 VOUT+ VOCM + 0.25V VOCM VOUT+ VOCM – 0.25V VOUT– 0 t 7 t 1994 TA05 402Ω 402Ω 1994fa 18 LT1994 U PACKAGE DESCRIPTIO DD Package 8-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1698) R = 0.115 TYP 5 0.38 ± 0.10 8 0.675 ±0.05 3.5 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) 3.00 ±0.10 (4 SIDES) PACKAGE OUTLINE 1.65 ± 0.10 (2 SIDES) PIN 1 TOP MARK (NOTE 6) (DD8) DFN 1203 0.25 ± 0.05 4 0.25 ± 0.05 0.75 ±0.05 0.200 REF 0.50 BSC 2.38 ±0.05 (2 SIDES) 1 0.50 BSC 2.38 ±0.10 (2 SIDES) 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 0.254 (.010) 8 7 6 5 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 4.90 ± 0.152 (.193 ± .006) DETAIL “A” 0.52 (.0205) REF 0° – 6° TYP GAUGE PLANE 0.42 ± 0.038 (.0165 ± .0015) TYP 0.65 (.0256) BSC 1 0.53 ± 0.152 (.021 ± .006) RECOMMENDED SOLDER PAD LAYOUT DETAIL “A” 1.10 (.043) MAX 2 3 4 0.86 (.034) REF 0.18 (.007) SEATING PLANE NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.22 – 0.38 (.009 – .015) TYP 0.65 (.0256) BSC 0.127 ± 0.076 (.005 ± .003) MSOP (MS8) 0204 1994fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LT1994 U TYPICAL APPLICATIO RFID Receiver Front-End, 20kHz < –3dB BW < 5MHz (Baseband Gain = 2) 0.056µF 82pF 140Ω 402Ω 5V 0.1µF 3 1 5V VCC IOUT 0° RF– 270pF LT5516 LT1994 2 BPF RF+ 4 7 5V + 8 0.1µF 0.056µF IOUT 5 6 140Ω 402Ω IOUT– 82pF 270pF 5V LO INPUT 82pF 270pF LO+ QOUT 0.056µF + 140Ω 402Ω 0°/90° 5V 90° LO– 0.1µF QOUT– 1 270pF ENABLE 3 4 7 EN 5V 2 8 0.1µF 0.056µF LT1994 QOUT 5 6 140Ω 402Ω 82pF 1994 TA02 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1167 Precision, Instrumentation Amp Single Gain Set Resistor: G = 1 to 10,000 LT1806/LT1807 Single/Dual Low Distortion Rail-to-Rail Amp 325MHz, 140V/µs Slew Rate, 3.5nV/√Hz Noise LT1809/LT1810 Single/Dual Low Distortion Rail-to-Rail Amp 180MHz, 350V/µs Slew Rate, Shutdown LT1990 High Voltage Gain Selectable Differential Amp ±250V Common Mode, Micropower, Gain = 1, 10 LT1991 Precision Gain Selectable Differential Amp Micropower, Pin Selectable Gain = –13 to 14 LTC1992/LTC1992-x Fully Differential Input/Output Amplifiers Programmable Gain or Fixed Gain (G = 1, 2, 5, 10) LT1993-2/-4/-10 Low Distortion and Noise, Differential In/Out Fixed Gain (G = 2, 4, 10) LT1995 High Speed Gain Selectable Differential Amp 30MHz, 1000V/µs, Pin Selectable Gain = –7 to 8 LT1996 Precision, 100µA, Gain Selectable Differential Amp Pin Selectable Gain = 9 to 117 LT6600-2.5/-5/-10/-15/-20 Differential Amp and Lowpass, Chebyshev Filter Filter Cutoff = 2.5MHz, 5MHz, 10MHz, 15MHz or 20MHz 1994fa 20 Linear Technology Corporation LT 0306 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2005