Harris CA1394 Tv horizontal processor Datasheet

CA1391, CA1394
UCT
OBSOLETE PROD
REPLACEMENT
NO RECOMMENDED
ns 1-800-442-7747
Call Central Applicatio harris.com
or email: centapp@
May 1999
[ /Title
(CA13
91,
CA139
4)
/Subject
(TV
Horizontal
Processors)
/Autho
r ()
/Keywords
(Harris
Semiconductor,
TV
horizontal
processor,
horizontal
oscillator,
horizontal
driver,
phase
detector,
AFC
circuit,
AGC
circuit,
TV Horizontal Processors
Features
Description
• CA1391E - Positive Horizontal Sawtooth Input
The Harris CA1391E and CA1394E are monolithic
integrated circuits designed for use in the low-level
horizontal section of monochrome or color television
receivers. Functions include a phase detector, an oscillator,
a regulator, and a pre-driver.
• CA1394E - Negative Horizontal Sawtooth Input
• Internal Shunt Regulator
• Linear Balanced Phase Detector
The CA1391E and CA1394E are electrically equivalent and
pin compatible with industry types 1391 and 1394 in similar
packages.
• Preset Hold Control Capability
• Pull-In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±300Hz (Typ)
• Low Thermal Frequency Drift
Part Number Information
• Small Static Phase Error
PART NUMBER
TEMP.
RANGE (oC)
PKG.
NO.
PACKAGE
• Variable Output Duty Cycle
CA1391E
0 to 85
8 Ld PDIP
E8.3
• Adjustable DC Loop Gain
CA1394E
0 to 85
8 Ld PDIP
E8.3
Pinout
Functional Diagram
CA1391, CA1394
(PDIP)
TOP VIEW
OUT
1
GND
2
SYNC
IN
HORIZ
IN
3
4
MARKSPACE
RATIO
OSC
7
TIMING
PHASE
DETECTOR
OUTPUT
V+
OSCILLATOR
TIMING
5
6
7
8
PHASE
DETECTOR
OUT
6 V+
PHASE
5 DETECT
OUT
OSCILLATOR
MARK-SPACE
RATIO
8
REGULATOR
4
PHASE
DETECTOR
PREDRIVER
3
2
SYNC
INPUT
GROUND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1999
8-9
1
OUTPUT
HORIZONTAL
SAWTOOTH
INPUT
File Number
981.4
CA1391, CA1394
Absolute Maximum Ratings
Thermal Information
DC Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA
DC Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Sync Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5VP-P
Sawtooth Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5VP-P
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
120
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
(See Figure 1)
PARAMETER
TEST CONDITIONS
TEMP. (oC)
MIN
TYP
MAX
UNITS
Supply Voltage
S1, S5, S6 = 2; S2, S3, S4, S7, S8 = 1
Measure Terminal 6 to GND
25
8
-
9
V
Free Running
Frequency -1%
S1, S5, S6 = 2; S2, S3, S4, S7, S8 = 1
Counter to Terminal 1
25
14734
-
16734
Hz
Output Leakage
S2, S3, S6, S8 = 1; S1, S4, S5, S7 = 2
Measure Terminal 1 to 25V
25
-
10
-
mV
Output Saturation
S2, S3, S5, S6, S8 = 1; S1, S4, S7 = 2
Measure Terminal 1 to GND
25
-
60
-
mV
Phase Detector Bias
S2, S5, S6, S8 = 1; S1, S3, S4, S7 = 2
Measure Terminal 3 to GND
25
-
1.9
-
V
Phase Detector Leak
S5, S8 = 1; S1, S2, S3, S4, S6, S7 = 2
Measure Terminal 5 to +4V
25
-2
-
2
mV
Phase Detector Low
S1, S5, S8 = 1; S2, S3, S4, S6, S7 = 2
Measure Terminal 5 to +4V
25
-0.55
(Note 2)
-
-
V
Phase Detector High
S1, S5, S6, S8 = 1; S2, S3, S4, S7 = 2
Measure Terminal 5 to +4V
25
+0.55
(Note 2)
-
-
V
Phase Detector Balance VDET2 + VDET3
25
-100
-
100
mV
Sync Diode
S1, S2, S3, S4, S6, S7 = 1; S5, S8 = 2
25
0.3
-
1.2
V
Static Phase Error
See Figure 3
25
-
0.5
-
µs
Oscillator Pull In Range
-
±300
-
Hz
Oscillator Hold In Range
-
±900
-
Hz
NOTE:
2. Polarity reversed in the CA1391.
8-10
CA1391, CA1394
Test Circuit
+6V
620Ω
+25V
1W
1kΩ
200Ω
1
14kΩ
2
150Ω
S3
430Ω
2
150kΩ
1
6800pF
1
1µF
S5
100Ω
2
1.65kΩ
S7
150Ω
1.5kΩ
1
2
S4
8
7
6
5
3
4
CA1391/CA1394
1
2
S8
1
2.65kΩ
2 1
S2
S1
2
1
S6
2
1
2
5.6kΩ
+6V
FIGURE 1. DC TEST CIRCUIT
Schematic Diagram
OSC.
TIMING
7
PREDRIVER
V+
6
OSCILLATOR
REGULATOR
R31
560
R8
3.9K
R1
2.6K
PHASE
DETECTOR
Q6
R12
2.4K
R18
200
R16
1.1K
R29
1.5K
R24
40K
Q16
Q20
Q15
MARKSPACE
RATIO
R15
2.4K
Q7 Q8
Q4
8
R4
430
Q3
OUT
Q1
Q5
Q2
R9
1.3K
R6
400
R5
5.1K
R2
6.8K
R10
470
Q12
Q11
R13
1.5K
R7
1.8K
Q9
Z1
Z2
Q10
R17
6.2K
R22
Q13 3.3K
R20
820
5
PHASE
DET. OUT
CA1394E
4
R25
Q22 Q23
7.5K
R26
R23
6.8K
7.5K
Q18
Q17
R27
510
D1
R19
240
R11
3.6K
D2
3 SYNC INPUT
2 GND
NOTE: All resistances are in ohms.
8-11
Q21
Q19
Q14
R14
6.8K
R3
7.5K
1
R1
3K
R30
1.5K
R28
910
HORIZ
INPUT
4
CA1391E
CA1391, CA1394
Application Information
Circuit Operation (See Schematic Diagram)
Q20 and Q21 so that there is no net output current at Terminal 5
for balanced conditions. When a phase offset occurs, current
flows either in or out of Terminal 5. In circuit applications, this
terminal is connected to Terminal 7 through an external low
pass filter, thereby controlling the oscillator.
The CA1391 and CA1394 contain the oscillator, phase
detector, and predriver sections necessary for the television
horizontal oscillator and AFC loop.
The oscillator is an RC type with Terminal 7 used to control the
timing. If it is assumed that Q7 is initially off, then an external
capacitor connected from Terminal 7 to ground charges through
an external resistance connected between Terminals 6 and 7. As
soon as the voltage at Terminal 7 exceeds the potential set at the
base of Q8 by resistors R11 and R12, Q7 turns on, and Q6 supplies base current to Q5 and Q10. Transistor Q5 discharges the
capacitor through R4 until the base bias of Q7 falls below that of
Q8 at which time, Q7 turns off, and the cycle repeats.
Shunt regulation for the circuit is obtained by using a VBE
and zener multiplier. Resistors R13 and R14 multiply the VBE
of Q11, and the ratio of R15 and R16 multiplies the voltage of
the zener diode Z1.
VOLTAGE AT TERM. 8 (THROUGH 1kΩ)
The sawtooth generated at the base of Q4 appears across R3
and turns off Q3 whenever the sawtooth voltage rises to a value
that exceeds the bias set at Terminal 8. By adjusting the potential at Terminal 8, the duty cycle at the pre-drive output (Terminal 1) may be changed. The phase detector is isolated from the
remainder of the circuit by R31, Z2, Q15 and Q16. The phase
detector consists of the comparator Q22 and Q23, and the
gated current source Q18. Negative going sync pulses at Terminal 3 turn off Q17, and the current division between Q22 and
Q23 is then determined by the phase relationship of the sync
and the sawtooth waveform at Terminal 4, which is derived from
the horizontal flyback pulse. If there is no phase difference
between the sync and sawtooth, equal currents flow in the collectors of Q22 and Q23 during each half of the sync pulse
period. The current in Q22 is turned around by current mirror
TA = 25oC
FREE RUNNING FREQUENCY = 15734Hz
5.0
4.5
4.0
3.5
3.0
2.5
2.0
0
10
20
30
40
24V
620Ω
3kΩ
120kΩ
0.47µF
+150V
4kΩ
10W
470µF
14kΩ
2
2.7kΩ
2.4kΩ
8.2kΩ
0.01µF
150kΩ
0.001µF
8
7
1.5kΩ
6
5
3
4
CA1394
1
60
70
FIGURE 2. DUTY CYCLE AT THE PRE-DRIVE OUTPUT (TERMINAL
1) AS IT IS AFFECTED BY THE INPUT AT TERMINAL 8
V+
6800pF
50
POSITIVE PULSE WIDTH AT TERMINAL 1 (µs)
2
22Ω
470pF
270Ω
7.5kΩ
0.1µF
0.1µF
390kΩ
3.9kΩ
0.0027µF
SYNC
1.2kΩ
20VP-P
5µs
FIGURE 3. TYPICAL CIRCUIT APPLICATION
8-12
60VP-P
10µs
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