ON MC14174BDG Hex type d flip-flop Datasheet

MC14174B
Hex Type D Flip-Flop
The MC14174B hex type D flip−flop is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. Data on the D inputs which meets the setup time
requirements is transferred to the Q outputs on the positive edge of the
clock pulse. All six flip−flops share common clock and reset inputs.
The reset is active low, and independent of the clock.
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Features
•
•
•
•
•
•
•
Static Operation
All Inputs and Outputs Buffered
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
Functional Equivalent to TTL 74174
These Devices are Pb−Free and are RoHS Compliant
MARKING
DIAGRAMS
PDIP−16
P SUFFIX
CASE 648
Symbol
Value
Unit
VDD
−0.5 to +18.0
V
Vin, Vout
−0.5 to VDD
+ 0.5
V
Input or Output Current (DC or Transient)
per Pin
Iin, Iout
± 10
mA
Power Dissipation, per Package (Note 1)
PD
500
mW
Ambient Temperature Range
TA
−55 to +125
°C
−65 to +150
°C
260
°C
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Storage Temperature Range
Lead Temperature (8−Second Soldering)
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
© Semiconductor Components Industries, LLC, 2011
June, 2011 − Rev. 7
1
MC14174BCP
AWLYYWWG
1
1
SOIC−16
D SUFFIX
CASE 751B
MAXIMUM RATINGS (Voltages Referenced to VSS)
Parameter
16
1
A
WL
YY, Y
WW
G
16
14174BG
AWLYWW
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Package
Shipping†
MC14174BCPG
PDIP−16
(Pb−Free)
500 Units/Rail
MC14174BDG
SOIC−16
(Pb−Free)
48 Units/Rail
MC14174BDR2G
SOIC−16
(Pb−Free)
2500/Tape & Reel
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
MC14174B/D
MC14174B
R
1
16
VDD
Q0
2
15
Q5
D0
3
14
D5
D1
4
13
D4
Q1
5
12
Q4
D2
6
11
D3
Q2
7
10
Q3
VSS
8
9
C
Figure 1. Pin Assignment
TRUTH TABLE (Positive Logic)
Inputs
Clock
Reset
Q
0
1
X
X
1
1
1
0
0
1
Q
0
X
X = Don’t Care
2
Q1
5
D1
Q2
7
6
D2
Q3
10
11
D3
13
D4
Q4
12
14
D5
Q5
15
CLOCK
1
RESET
3
D0
4
VDD = PIN 16
VSS = PIN 8
Figure 2. Block Diagram
Output
Data
Q0
9
No
Change
Figure 3. Timing Diagram
Figure 4. Functional Block Diagram
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2
MC14174B
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
− 55_C
25_C
VDD
125_C
Symbol
Vdc
Min
Max
Min
Typ
(Note 2)
VOL
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
VOH
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
−
−
−
−
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
−
−
−
−
– 1.7
– 0.36
– 0.9
– 2.4
−
−
−
−
IOL
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
Input Current
Iin
15
−
± 0.1
−
± 0.00001
± 0.1
−
± 1.0
mAdc
Input Capacitance, (Vin = 0)
Cin
−
−
−
−
5.0
7.5
−
−
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mAdc
IT
5.0
10
15
Characteristic
Output Voltage
Vin = VDD or 0
Vin = 0 or VDD
“0” Level
“1” Level
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Source
Sink
Total Supply Current (Note 3, 4)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
VIL
VIH
IOH
Max
Min
Max
Unit
IT = (1.1 mA/kHz) f + IDD
IT = (2.3 mA/kHz) f + IDD
IT = (3.7 mA/kHz) f + IDD
Vdc
Vdc
mAdc
mAdc
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in mA (per package), CL in pF,
V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.003.
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3
MC14174B
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SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)
All Types
Characteristic
Symbol
VDD
Vdc
Min
Typ
(Note 6)
Max
5.0
10
15
−
−
−
100
50
40
200
100
80
5.0
10
15
−
−
−
210
85
65
400
160
120
5.0
10
15
−
−
−
250
100
75
500
200
150
Unit
Output Rise and Fall Time
tTLH, tTHL = (1.35 ns/pF) CL + 32 ns
tTLH, tTHL = (0.6 ns/pF) CL + 20 ns
tTLH, tTHL = (0.4 ns/pF) CL + 20 ns
tTLH, tTHL
Propagation Delay Time — Clock to Q
tPLH, tPHL = (0.9 ns/pF) CL + 165 ns
tPLH, tPHL = (0.36 ns/pF) CL + 64 ns
tPLH, tPHL = (0.26 ns/pF) CL + 52 ns
tPLH, tPHL
Propagation Delay Time — Reset to Q
tPHL = (0.9 ns/pF) CL + 205 ns
tPHL = (0.36 ns/pF) CL + 79 ns
tPHL = (0.26 ns/pF) CL + 62 ns
tPHL
Clock Pulse Width
tWH
5.0
10
15
150
90
70
75
45
35
−
−
−
ns
Reset Pulse Width
tWL
5.0
10
15
200
100
80
100
50
40
−
−
−
ns
fcl
5.0
10
15
−
−
−
7.0
12
15.5
2.0
5.0
6.5
mHz
tTLH, tTHL
5.0
10
15
−
−
−
−
−
−
15
5.0
4.0
ms
Data Setup Time
tsu
5.0
10
15
40
20
15
20
10
0
−
−
−
ns
Data Hold Time
th
5.0
10
15
80
40
30
40
20
15
−
−
−
ns
trem
5.0
10
15
250
100
80
125
50
40
−
−
−
ns
Clock Pulse Frequency
Clock Pulse Rise and Fall Time
Reset Removal Time
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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4
ns
ns
ns
MC14174B
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
−A−
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
SOLDERING FOOTPRINT
8X
6.40
16X
1
1.12
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
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5
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
MC14174B
PACKAGE DIMENSIONS
PDIP−16
CASE 648−08
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
16
9
1
8
B
F
C
L
S
−T−
H
SEATING
PLANE
K
G
D
M
J
16 PL
0.25 (0.010)
M
T A
M
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740 0.770
0.250 0.270
0.145 0.175
0.015 0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
0_
10 _
0.020 0.040
MILLIMETERS
MIN
MAX
18.80 19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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