Ultralow Noise,
150 mA CMOS Linear Regulator
ADP150
TYPICAL APPLICATION CIRCUITS
VIN = 2.3V
CIN
1µF
ON
1
VIN
2
GND
3
EN
VOUT = 1.8V
VOUT 5
COUT
1µF
NC 4
OFF
NC = NO CONNECT
Figure 1. 5-Lead TSOT with Fixed Output Voltage, 1.8 V
VIN = 2.3V
CIN
1µF
2
VIN
VOUT
VOUT = 1.8V
A
TOP VIEW
(Not to Scale)
ON
OFF
1
EN
GND
B
COUT
1µF
08343-002
Ultra low noise: 9 μV rms, independent of VOUT
No additional noise bypass capacitor required
Stable with 1 μF ceramic input and output capacitors
Maximum output current: 150 mA
Input voltage range: 2.2 V to 5.5 V
Low quiescent current
IGND = 10 μA with zero load
Low shutdown current: <1 μA
Low dropout voltage: 105 mV @ 150 mA load
Initial output voltage accuracy: ±1%
Up to 14 fixed output voltage options: 1.8 V to 3.3 V
PSRR performance of 70 dB at 10 kHz
Current limit and thermal overload protection
Logic-controlled enable
5-lead TSOT package
4-ball, 0.8 mm × 0.8 mm, 0.4 mm pitch WLCSP
08343-001
FEATURES
Figure 2. 4-Ball WLCSP with Fixed Output Voltage, 1.8 V
APPLICATIONS
Mobile phones
Digital camera and audio devices
Portable and battery-powered equipment
Post dc-to-dc regulation
Portable medical devices
RF, PLL, VCO, and clock power supplies
GENERAL DESCRIPTION
The ADP150 is an ultralow noise (9 μV), low dropout, linear
regulator that operates from 2.2 V to 5.5 V and provides up to
150 mA of output current. The low 105 mV dropout voltage at
150 mA load improves efficiency and allows operation over a
wide input voltage range.
Using an innovative circuit topology, the ADP150 achieves ultralow
noise performance without the necessity of an additional noise
bypass capacitor, making it ideal for noise sensitive analog and
RF applications. The ADP150 also achieves ultralow noise
performance without compromising PSRR or line and load
transient performance. The ADP150 offers the best combination
of ultralow noise and quiescent current consumption to maximize
battery life in portable applications.
The ADP150 is specifically designed for stable operation with
tiny 1 μF ± 30% ceramic input and output capacitors to meet
the requirements of high performance, space-constrained
applications.
The ADP150 is available in 14 fixed output voltage options,
ranging from 1.8 V to 3.3 V.
Short-circuit and thermal overload protection circuits prevent
damage in adverse conditions. The ADP150 is available in tiny
5-lead TSOT and 4-ball, 0.4 mm pitch WLCSP packages for the
smallest footprint solution to meet a variety of portable power
applications.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
ADP150
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................7
Applications ....................................................................................... 1
Theory of Operation ...................................................................... 11
Typical Application Circuits............................................................ 1
Applications Information .............................................................. 12
General Description ......................................................................... 1
Capacitor Selection .................................................................... 12
Revision History ............................................................................... 2
Undervoltage Lockout ............................................................... 13
Specifications..................................................................................... 3
Enable Feature ............................................................................ 13
Recommended Specifications: Input and Output Capacitor .. 4
Current Limit and Thermal Overload Protection ................. 13
Absolute Maximum Ratings............................................................ 5
Thermal Considerations............................................................ 14
Thermal Data ................................................................................ 5
PCB Layout Considerations ...................................................... 17
Thermal Resistance ...................................................................... 5
Outline Dimensions ....................................................................... 18
ESD Caution .................................................................................. 5
Ordering Guide .......................................................................... 19
Pin Configurations and Function Descriptions ........................... 6
REVISION HISTORY
10/09—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADP150
SPECIFICATIONS
VIN = (VOUT + 0.4 V) or 2.2 V, whichever is greater; EN = VIN, IOUT = 10 mA, CIN = COUT = 1 μF, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
INPUT VOLTAGE RANGE
OPERATING SUPPLY CURRENT
SHUTDOWN CURRENT
OUTPUT VOLTAGE ACCURACY
5-Lead TSOT
4-Ball WLCSP
REGULATION
Line Regulation
Load Regulation 1
5-Lead TSOT
4-Ball WLCSP
DROPOUT VOLTAGE 2
Symbol
VIN
IGND
Conditions
TJ = −40°C to +125°C
IOUT = 0 μA
IOUT = 0 μA, TJ = −40°C to +125°C
IOUT = 100 μA
IOUT = 100 μA, TJ = −40°C to +125°C
IOUT = 10 mA
IOUT = 10 mA, TJ = −40°C to +125°C
IOUT = 150 mA
IOUT = 150 mA, TJ = −40°C to +125°C
EN = GND
EN = GND, TJ = −40°C to +125°C
Min
2.2
IOUT = 10 mA
100 μA < IOUT < 150 mA, VIN = (VOUT + 0.4 V) to 5.5 V,
TJ = −40°C to +125°C
IOUT = 10 mA
100 μA < IOUT < 150 mA, VIN = (VOUT + 0.4 V) to 5.5 V,
TJ = −40°C to +125°C
∆VOUT/∆VIN
VIN = (VOUT + 0.4 V) to 5.5 V, TJ = −40°C to +125°C
∆VOUT/∆IOUT
IOUT = 100 μA to 150 mA
IOUT = 100 μA to 150 mA, TJ = −40°C to +125°C
IOUT = 100 μA to 150 mA
IOUT = 100 μA to 150 mA, TJ = −40°C to +125°C
IOUT = 10 mA
IOUT = 10 mA, TJ = −40°C to +125°C
IOUT = 150 mA
IOUT = 150 mA, TJ = −40°C to +125°C
VOUT = 3.3 V
IGND-SD
VOUT
VOUT
∆VOUT/∆IOUT
VDROPOUT
START-UP TIME 3
CURRENT LIMIT THRESHOLD 4
UNDERVOLTAGE LOCKOUT
Input Voltage Rising
Input Voltage Falling
Hysteresis
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
TSSD
TSSD-HYS
TJ rising
EN INPUT
EN Input Logic High
EN Input Logic Low
EN Input Leakage Current
VIH
VIL
VI-LEAKAGE
OUTPUT NOISE
OUTNOISE
2.2 V ≤ VIN ≤ 5.5 V
2.2 V ≤ VIN ≤ 5.5 V
EN = IN or GND
EN = IN or GND, TJ = −40°C to +125°C
10 Hz to 100 kHz, VIN = 5 V, VOUT = 3.3 V
10 Hz to 100 kHz, VIN = 5 V, VOUT = 2.5 V
10 Hz to 100 kHz, VIN = 5 V, VOUT = 1.8 V
TSTART-UP
ILIMIT
UVLO
UVLORISE
UVLOFALL
UVLOHYS
1.0
Unit
V
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
Rev. 0 | Page 3 of 20
Max
5.5
−1
−2.5
+1
+1.5
%
%
−1
−2.0
+1
+1.5
%
%
−0.05
+0.05
%/V
10
22
20
40
60
100
220
320
0.2
0.003
0.0075
0.002
0.006
10
35
105
160
190
TJ = −40°C to +125°C
TJ = −40°C to +125°C
TJ = −40°C to +125°C
Typ
150
260
400
1.96
%/mA
%/mA
%/mA
%/mA
mV
mV
mV
mV
μs
mA
115
V
V
mV
150
15
°C
°C
1.28
1.2
0.4
0.001
1
9
9
9
V
V
μA
μA
μV rms
μV rms
μV rms
ADP150
Parameter
POWER SUPPLY REJECTION RATIO
(VIN = VOUT + 0.5 V)
Symbol
PSRR
POWER SUPPLY REJECTION RATIO
(VIN = VOUT + 1 V)
Conditions
10 kHz, VIN = 3.8 V, VOUT = 3.3 V, IOUT = 10 mA
Min
Typ
70
Max
Unit
dB
10 kHz, VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA
100 kHz, VIN = 3.8 V, VOUT = 3.3 V, IOUT = 10 mA
100 kHz, VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA
10 kHz, VIN = 4.3 V, VOUT = 3.3 V, IOUT = 10 mA
70
55
55
70
dB
dB
dB
dB
100 kHz, VIN = 4.3 V, VOUT = 3.3 V, IOUT = 10 mA
55
dB
1
Based on an end-point calculation using 1 mA and 150 mA loads. See Figure 6 for typical load regulation performance for loads less than 1 mA.
Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 2.2 V.
3
Start-up time is defined as the time between the rising edges of EN to VOUT being at 90% of its nominal value.
4
Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V or 2.7 V.
2
RECOMMENDED SPECIFICATIONS: INPUT AND OUTPUT CAPACITOR
Table 2.
Parameter
INPUT AND OUTPUT CAPACITOR
Minimum Input and Output Capacitance 1
Capacitor ESR
1
Symbol
Conditions
Min
CMIN
RESR
TA = −40°C to +125°C
TA = −40°C to +125°C
0.7
0.001
Typ
Max
Unit
0.2
μF
Ω
The minimum input and output capacitance should be greater than 0.7 μF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R-type and X5R-type capacitors are
recommended, and Y5V and Z5U capacitors are not recommended for use with any LDO.
Rev. 0 | Page 4 of 20
ADP150
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN to GND
VOUT to GND
EN to GND
Storage Temperature Range
Operating Junction Temperature Range
Operating Ambient Temperature Range
Soldering Conditions
Rating
−0.3 V to +6.5 V
−0.3 V to VIN
−0.3 V to +6.5 V
−65°C to +150°C
−40°C to +125°C
−40°C to +85°C
JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP150 can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temperature
does not guarantee that TJ is within the specified temperature
limits. In applications with high power dissipation and poor
thermal resistance, the maximum ambient temperature may
have to be derated.
In applications with moderate power dissipation and low
printed circuit board (PCB) thermal resistance, the maximum
ambient temperature can exceed the maximum limit as long
as the junction temperature is within specification limits. The
junction temperature (TJ) of the device is dependent on the
ambient temperature (TA), the power dissipation of the device (PD),
and the junction-to-ambient thermal resistance of the package
(θJA).
Maximum junction temperature (TJ) is calculated from the
ambient temperature (TA) and power dissipation (PD) by
The junction-to-ambient thermal resistance (θJA) of the package
is based on modeling and a calculation using a 4-layer board.
The junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA can vary, depending on
PCB material, layout, and environmental conditions. The specified
values of θJA are based on a 4-layer, 4 inch × 3 inch circuit board.
Refer to JESD 51-7 and JESD 51-9 for detailed information
on the board construction. For additional information, see
the AN-617 Application Note, MicroCSP™ Wafer Level Chip
Scale Package.
ΨJB is the junction-to-board thermal characterization parameter
with units of °C/W. ΨJB of the package is based on modeling and
a calculation using a 4-layer board. The JESD51-12, Guidelines
for Reporting and Using Package Thermal Information, states that
thermal characterization parameters are not the same as thermal
resistances. ΨJB measures the component power flowing through
multiple thermal paths rather than a single path as in thermal
resistance, θJB. Therefore, ΨJB thermal paths include convection
from the top of the package as well as radiation from the package,
factors that make ΨJB more useful in real-world applications.
Maximum junction temperature (TJ) is calculated from the
board temperature (TB) and power dissipation (PD) by
TJ = TB + (PD × ΨJB)
Refer to JESD51-8 and JESD51-12 for more detailed information
about ΨJB.
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
5-Lead TSOT
4-Ball, 0.4 mm Pitch WLCSP
TJ = TA + (PD × θJA)
ESD CAUTION
Rev. 0 | Page 5 of 20
θJA
170
260
ΨJB
43
58
Unit
°C/W
°C/W
ADP150
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
5
VOUT
A
ADP150
EN 3
VIN
VOUT
TOP VIEW
(Not to Scale)
TOP VIEW
(Not to Scale)
4
NC = NO CONNECT
NC
08343-003
GND 2
2
B
EN
GND
08343-004
VIN 1
1
Figure 4. 4-Ball WLCSP Pin Configuration
Figure 3. 5-Lead TSOT Pin Configuration
Table 5. 5-Lead TSOT Pin Function Descriptions
Table 6. 4-Ball WLCSP Pin Function Descriptions
Pin No.
1
Mnemonic
VIN
Pin No.
A1
Mnemonic
VIN
2
3
GND
EN
A2
VOUT
B1
EN
B2
GND
4
5
NC
VOUT
Description
Regulator Input Supply. Bypass VIN to
GND with a 1 μF or greater capacitor.
Ground.
Enable Input. Drive EN high to turn on
the regulator; drive EN low to turn off
the regulator. For automatic startup,
connect EN to VIN.
No Connect. Not connected internally.
Regulated Output Voltage. Bypass VOUT
to GND with a 1 μF or greater capacitor.
Rev. 0 | Page 6 of 20
Description
Regulator Input Supply. Bypass VIN to
GND with a 1 μF or greater capacitor.
Regulated Output Voltage. Bypass VOUT
to GND with a 1 μF or greater capacitor.
Enable Input. Drive EN high to turn on
the regulator; drive EN low to turn off
the regulator. For automatic startup,
connect EN to VIN.
Ground.
ADP150
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 3.7 V, VOUT = 3.3 V, IOUT = 1 mA, CIN = COUT = 1 μF, TA = 25°C, unless otherwise noted.
3.315
300
IOUT = 150mA
3.310
250
GROUND CURRENT (µA)
3.305
3.295
3.290
3.285
IOUT = 0.1mA
IOUT = 1mA
IOUT = 10mA
IOUT = 50mA
IOUT = 100mA
IOUT = 150mA
3.275
3.270
3.265
–40
IOUT = 100mA
200
150
IOUT = 50mA
100
IOUT = 10mA
IOUT = 1mA
50
IOUT = 0.1mA
–5
25
85
0
125
JUNCTION TEMPERATURE (°C)
–40
–5
25
85
08343-008
3.280
08343-005
VOUT (V)
3.300
125
JUNCTION TEMPERATURE (°C)
Figure 5. Output Voltage (VOUT) vs. Junction Temperature
Figure 8. Ground Current vs. Junction Temperature
3.298
250
3.297
200
GROUND CURRENT (µA)
3.296
VOUT (V)
3.295
3.294
3.293
3.292
150
100
50
0.1
1
10
100
0
0.01
08343-006
3.290
0.01
1000
IOUT (mA)
1
10
100
1000
IOUT (mA)
Figure 6. Output Voltage (VOUT) vs. Load Current (IOUT)
Figure 9. Ground Current vs. Load Current (IOUT)
250
3.300
IOUT = 150mA
IOUT = 0.1mA
200
GROUND CURRENT (µA)
IOUT = 1mA
3.296
IOUT = 10mA
3.294
IOUT = 50mA
3.292
3.7
3.9
4.1
4.3
4.5
4.7
IOUT = 50mA
100
IOUT = 10mA
IOUT = 1mA
IOUT = 0.1mA
IOUT = 150mA
4.9
5.1
5.3
VIN (V)
5.5
0
3.5
08343-007
3.288
3.5
150
50
IOUT = 100mA
3.290
IOUT = 100mA
3.7
3.9
4.1
4.3
4.5
4.7
4.9
5.1
5.3
VIN (V)
Figure 7. Output Voltage (VOUT) vs. Input Voltage (VIN)
Figure 10. Ground Current vs. Input Voltage (VIN)
Rev. 0 | Page 7 of 20
5.5
08343-010
3.298
VOUT (V)
0.1
08343-009
3.291
ADP150
0.7
700
VIN = 3.6V
VIN = 3.8V
VIN = 4.2V
VIN = 4.4V
VIN = 5.0V
VIN = 5.2V
VIN = 5.4V
VIN = 5.5V
0.4
0.3
0.2
0.1
500
400
300
200
100
–25
0
25
50
75
100
0
3.05
08343-011
0
–50
125
TEMPERATURE (°C)
IOUT
IOUT
IOUT
IOUT
= 10mA
= 50mA
= 100mA
= 150mA
3.10
3.15
3.20
3.25
3.30
3.35
3.40
3.45
VIN (A)
08343-014
0.5
600
GROUND CURRENT (µA)
SHUTDOWN CURRENT (µA)
0.6
Figure 14. Ground Current vs. Input Voltage (VIN) in Dropout
Figure 11. Shutdown Current vs. Temperature at Various Input Voltages
80
–10
70
–20
–30
60
IOUT = 100µA
IOUT = 1mA
IOUT = 10mA
IOUT = 100mA
IOUT = 150mA
VIN = VOUT + 0.5V
VRIPPLE = 50mV
CIN = COUT = 1µF
DROPOUT (mA)
–40
PSRR (dB)
50
40
–50
–60
30
–70
20
–80
10
1
10
100
1000
IOUT (mA)
–100
10
08343-012
0
3.30
10k
100k
1M
10M
Figure 15. Power Supply Rejection Ratio (PSRR) vs. Frequency,
VOUT = 1.8 V, VIN = 2.3 V
–10
IOUT = 10mA
IOUT = 50mA
IOUT = 100mA
IOUT = 150mA
–20
–30
3.25
IOUT = 100µA
IOUT = 1mA
IOUT = 10mA
IOUT = 100mA
IOUT = 150mA
VIN = VOUT + 0.5V
VRIPPLE = 50mV
CIN = COUT = 1µF
–40
PSRR (dB)
VOUT (V)
1k
FREQUENCY (Hz)
Figure 12. Dropout Voltage vs. Load Current (ILOAD)
3.35
100
08343-015
–90
3.20
3.15
–50
–60
–70
3.10
–80
3.05
3.15
3.20
3.25
3.30
3.35
3.40
3.45
VIN (V)
–100
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 16. Power Supply Rejection Ratio (PSRR) vs. Frequency,
VOUT = 2.8 V, VIN=3.3 V
Figure 13. Output Voltage (VOUT) vs. Input Voltage (VIN) in Dropout
Rev. 0 | Page 8 of 20
08343-016
3.10
08343-013
3.00
3.05
–90
ADP150
–10
–20
–30
15
IOUT = 100µA
IOUT = 1mA
IOUT = 10mA
IOUT = 100mA
IOUT = 150mA
VIN = VOUT + 0.5V
VRIPPLE = 50mV
CIN = COUT = 1µF
13
11
RMS NOISE (µV)
–40
PSRR (dB)
VOUT = 3.3V
VOUT = 2.8V
VOUT = 1.8V
–50
–60
–70
9
7
5
–80
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
1
0.001
08343-017
–100
10
–30
PSRR (dB)
–40
10
100
0.501
VIN = VOUT + 0.5V
VRIPPLE = 50mV
CIN = COUT = 1µF
IOUT = 100µA
IOUT = 100µA
IOUT = 100µA
IOUT = 150mA
IOUT = 150mA
IOUT = 150mA
1
1k
Figure 20. Output RMS Noise vs. Load Current (IOUT) and
Output Voltage (VOUT), VIN = 5 V, COUT = 1 μF
VOUT = 1.8V
VOUT = 2.8V
VOUT = 3.3V
0.451
0.401
0.351
NOISE (µV/ Hz)
–20
VOUT = 1.8V,
VOUT = 2.8V,
VOUT = 3.3V,
VOUT = 1.8V,
VOUT = 2.8V,
VOUT = 3.3V,
0.1
IOUT (mA)
Figure 17. Power Supply Rejection Ratio (PSRR) vs. Frequency,
VOUT = 3.3 V, VIN = 3.8 V
–10
0.01
08343-021
3
–90
–50
–60
–70
0.301
0.251
0.201
0.151
–80
0.101
–90
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 18. Power Supply Rejection Ratio (PSRR) vs. Frequency
Various Output Voltages and Load Currents
–10
–20
–30
–40
VIN = 3.8V,
VIN = 4.3V,
VIN = 5.3V,
VIN = 3.8V,
VIN = 4.3V,
VIN = 5.3V,
0.001
10
100
10k
100k
Figure 21. Output Noise Spectrum, VIN = 5 V, ILOAD = 10 mA, COUT = 1 μF
T
VRIPPLE = 50mV
CIN = COUT = 1µF
IOUT = 1mA
IOUT = 1mA
IOUT = 1mA
IOUT = 150mA
IOUT = 150mA
IOUT = 150mA
1k
FREQUENCY (Hz)
IOUT
1mA TO 150mA LOAD STEP
–60
VOUT
2
–70
–80
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 19. Power Supply Rejection Ratio (PSRR) vs. Frequency with
Various Headroom Voltages (VIN − VOUT), VOUT = 3.3 V
CH1 100mA
CH2 50mV
M40µs
A CH1
T
117.560µs
112mA
Figure 22. Load Transient Response, COUT = 1 μF
Rev. 0 | Page 9 of 20
08343-022
VIN = 3.7V
VOUT = 3.3V
–90
08343-019
PSRR (dB)
1
–50
–100
10
08343-020
0.051
08343-018
–100
10
ADP150
T
T
IOUT
1mA TO 150mA LOAD STEP
VIN
3.7V TO 4.7V VOLTAGE STEP
OFFSET = 2.7V
1
1
VOUT
2
2
VOUT
CH2 50mV
M40µs
A CH1
T
118.000µs
108mA
CH1 1.00V
T
VIN
3.7V TO 4.7V VOLTAGE STEP
OFFSET = 2.7V
1
VOUT
M10µs
T
29.60µs
A CH1
4.60V
08343-024
2
CH2 10mV
M10µs
T
29.60µs
A CH1
4.60V
Figure 25. Line Transient Response, CIN, COUT =1 μF, ILOAD = 150 mA
Figure 23. Load Transient Response, COUT = 4.7 μF
CH1 1.00V
CH2 10mV
08343-125
CH1 100mA
08343-023
VIN = 3.7V
VOUT = 3.3V
Figure 24. Line Transient Response, CIN, COUT = 1 μF, ILOAD = 1mA
Rev. 0 | Page 10 of 20
ADP150
THEORY OF OPERATION
The ADP150 is an ultralow noise, low quiescent current, low
dropout linear regulator that operates from 2.2 V to 5.5 V and
can provide up to 150 mA of output current. Drawing a low 220 μA
of quiescent current (typical) at full load makes the ADP150 ideal
for battery-operated portable equipment. Shutdown current
consumption is typically 200 nA.
Using new innovative design techniques, the ADP150 provides
superior noise performance for noise sensitive analog and
RF applications without the need for a noise bypass capacitor.
The ADP150 is also optimized for use with small 1 μF ceramic
capacitors.
VIN
VOUT
R1
EN
SHORT CIRCUIT,
UVLO, AND
THERMAL
PROTECT
SHUTDOWN
VOLTAGE
REFERENCE
R2
The ADP150 is available in 14 output voltage options, ranging
from 1.8 V to 3.3 V. The ADP150 uses the EN pin to enable and
disable the VOUT pin under normal operating conditions. When
EN is high, VOUT turns on, and when EN is low, VOUT turns
off. For automatic startup, EN can be tied to VIN.
08343-025
GND
Internally, the ADP150 consists of a reference, an error amplifier,
a feedback voltage divider, and a PMOS pass transistor. Output
current is delivered via the PMOS pass device that is controlled
by the error amplifier. The error amplifier compares the reference
voltage with the feedback voltage from the output and amplifies
the difference. If the feedback voltage is lower than the reference
voltage, the gate of the PMOS device is pulled lower, allowing
more current to pass and increasing the output voltage. If the
feedback voltage is higher than the reference voltage, the gate of
the PMOS device is pulled higher, allowing less current to pass
and decreasing the output voltage.
Figure 26. Internal Block Diagram
Rev. 0 | Page 11 of 20
ADP150
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Input and Output Capacitor Properties
Output Capacitor
Any good quality ceramic capacitors can be used with the ADP150,
as long as they meet the minimum capacitance and maximum
ESR requirements. Ceramic capacitors are manufactured with a
variety of dielectrics, each with different behavior over temperature
and applied voltage. Capacitors must have a dielectric adequate to
ensure the minimum capacitance over the necessary temperature
range and dc bias conditions. X5R or X7R dielectrics with a
voltage rating of 6.3 V or 10 V are recommended. Y5V and Z5U
dielectrics are not recommended, due to their poor temperature
and dc bias characteristics.
The ADP150 is designed for operation with small, space-saving
ceramic capacitors but functions with most commonly used
capacitors as long as care is taken with regard to the effective
series resistance (ESR) value. The ESR of the output capacitor
affects the stability of the LDO control loop. A minimum of 1 μF
capacitance with an ESR of 1 Ω or less is recommended to
ensure the stability of the ADP150. The transient response to
changes in load current is also affected by output capacitance.
Using a larger value of output capacitance improves the transient
response of the ADP150 to large changes in the load current.
Figure 27 and Figure 28 show the transient responses for output
capacitance values of 1 μF and 4.7 μF, respectively.
T
IOUT
1mA TO 150mA LOAD STEP
Figure 29 depicts the capacitance vs. the voltage bias characteristic
of a 0402, 1 μF, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the X5R
dielectric is about ±15% over the −40°C to +85°C temperature
range and is not a function of package or voltage rating.
1.2
1
1.0
CAPACITANCE (µF)
2
VOUT
CH1 100mA
CH2 50mV
M1.0µs
A CH1
T
716.000µs
100mA
08343-126
VIN = 3.7V
VOUT = 3.3V
0.8
0.6
0.4
0.2
Figure 27. Output Transient Response, COUT = 1 μF
0
0
2
4
6
8
BIAS VOLTAGE (V)
IOUT
1mA TO 150mA LOAD STEP
10
08343-100
T
Figure 29. Capacitance vs. Voltage Bias Characteristic
Use Equation 1 to determine the worst-case capacitance,
accounting for capacitor variation over temperature, component
tolerance, and voltage.
1
2
CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL)
VOUT
where:
CBIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
CH2 50mV
M1.0µs
A CH1
T
240.000ns
108mA
08343-127
VIN = 3.7V
VOUT = 3.3V
CH1 100mA
(1)
Figure 28. Output Transient Response, COUT = 4.7 μF
Input Bypass Capacitor
Connecting a 1 μF capacitor from VIN to GND reduces the
circuit sensitivity to the PCB layout, especially when long input
traces or high source impedance is encountered. If greater than
1 μF of output capacitance is required, increase the input capacitor
to match the output capacitor.
In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
The tolerance of the capacitor (TOL) is assumed to be 10%, and
the CBIAS is 0.94 μF at 1.8 V, as shown in Figure 29.
Substituting these values in Equation 1 yields
CEFF = 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 μF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over temperature
and tolerance at the chosen output voltage.
Rev. 0 | Page 12 of 20
ADP150
To guarantee the performance of the ADP150, it is imperative
that the effects of the dc bias, temperature, and tolerances on
the behavior of the capacitors be evaluated for each.
UNDERVOLTAGE LOCKOUT
The ADP150 has an internal undervoltage lockout circuit that
disables all inputs and the output when the input voltage is less
than approximately 2.0 V. This ensures that the ADP150 inputs
and output behave in a predictable manner during power-up.
The ADP150 uses an internal soft start to limit the inrush current
when the output is enabled. The start-up time for the 3.3 V
option is approximately 150 μs from the time the EN active
threshold is crossed to when the output reaches 90% of its final
value. As shown in Figure 32, the start-up time is dependent on the
output voltage setting.
T
EN
ENABLE FEATURE
VOUT = 3.3V
The ADP150 uses the EN pin to enable and disable the VOUT
pin under normal operating conditions. As shown in Figure 30,
when a rising voltage on EN crosses the active threshold, VOUT
turns on. When a falling voltage on EN crosses the inactive
threshold, VOUT turns off.
VOUT = 2.8V
VOUT = 1.8V
1
1
3.5
CH1 1V
CH3 1V
2.5
CH2 1V
CH4 1V
M40.0µs
A CH1
T
240.000ns
3.24V
08343-128
3.0
VOUT
Figure 32. Typical Start-Up Time
2.0
CURRENT LIMIT AND THERMAL OVERLOAD
PROTECTION
1.5
1.0
0
0
0.2
0.4
0.6
0.8
VEN
1.0
1.2
1.4
1.6
08343-101
0.5
Figure 30. Typical EN Pin Operation
As shown in Figure 30, the EN pin has hysteresis built in. This
prevents on/off oscillations that can occur due to noise on the
EN pin as it passes through the threshold points.
The EN pin active/inactive thresholds are derived from the VIN
voltage; therefore, these thresholds vary with changing input
voltage. Figure 31 shows the typical EN active/inactive thresholds
when the input voltage varies from 2.2 V to 5.5 V.
1.1
1.0
0.8
FALLING
0.7
0.6
0.5
0.4
2.3
2.8
3.3
3.8
4.3
4.8
5.3
5.5
VIN (V)
08343-102
TYPICAL THRESHOLD (V)
RISING
0.9
The ADP150 is protected against damage due to excessive
power dissipation by current and thermal overload protection
circuits. The ADP150 is designed to limit current when the
output load reaches 260 mA (typical). When the output load
exceeds 260 mA, the output voltage is reduced to maintain a
constant current limit.
Thermal overload protection is included, which limits the junction
temperature to a maximum of 150°C (typical). Under extreme
conditions (that is, high ambient temperature and power dissipation)
when the junction temperature starts to rise above 150°C, the
output is turned off, reducing the output current to zero. When
the junction temperature drops below 135°C, the output is turned
on again and the output current is restored to its nominal value.
Consider the case where a hard short from VOUT to GND occurs.
At first, the ADP150 limits current so that only 260 mA is
conducted into the short. If self-heating of the junction is great
enough to cause its temperature to rise above 150°C, thermal
shutdown activates, turning off the output and reducing the
output current to zero. As the junction temperature cools and
drops below 135°C, the output turns on and conducts 260 mA
into the short, again causing the junction temperature to rise
above 150°C. This thermal oscillation between 135°C and 150°C
causes a current oscillation between 260 mA and 0 mA that
continues as long as the short remains at the output.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For reliable
operation, device power dissipation must be externally limited
so that the junction temperatures do not exceed 125°C.
Figure 31. Typical EN Pin Thresholds vs. Input Voltage (VIN)
Rev. 0 | Page 13 of 20
ADP150
When the junction temperature exceeds 150°C, the converter
enters thermal shutdown. It recovers only after the junction
temperature decreases below 135°C to prevent any permanent
damage. Therefore, thermal analysis for the chosen application is
very important to guarantee reliable performance over all conditions.
The junction temperature of the die is the sum of the ambient
temperature of the environment and the temperature rise of the
package due to the power dissipation, as shown in Equation 2.
To guarantee reliable operation, the junction temperature of
the ADP150 must not exceed 125°C. To ensure that the junction
temperature stays below 125°C, be aware of the parameters that
contribute to the junction temperature changes. These parameters
include ambient temperature, power dissipation in the power
device, and thermal resistances between the junction and
ambient air (θJA). The θJA number is dependent on the package
assembly compounds that are used and the amount of copper
used to solder the package GND pins to the PCB. Table 7 shows
typical θJA values of the 5-lead TSOT and 4-ball WLCSP packages
for various PCB copper sizes. Table 8 shows the typical ΨJB
value of the 5-lead TSOT and 4-ball WLCSP.
TJ = TA + {[(VIN − VOUT) × ILOAD] × θJA}
(3)
As shown in the previous equation, for a given ambient temperature,
input-to-output voltage differential, and continuous load current,
there exists a minimum copper size requirement for the PCB to
ensure that the junction temperature does not rise above 125°C.
Figure 33 to Figure 46 show the junction temperature calculations
for the different ambient temperatures, load currents, VIN-to-VOUT
differentials, and areas of PCB copper.
140
MAX JUNCTION TEMPERATURE
120
100
80
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
= 1mA
= 10mA
= 25mA
= 50mA
= 75mA
= 100mA
= 150mA
1.0
1.5
60
40
20
0
0.5
2.0
2.5
3.0
VIN – VOUT (V)
3.5
4.0
4.5
08343-228
In most applications, the ADP150 does not dissipate much heat
due to its high efficiency. However, in applications with high
ambient temperature and high supply voltage to output voltage
differential, the heat dissipated in the package is large enough
that it can cause the junction temperature of the die to exceed
the maximum junction temperature of 125°C.
Power dissipation due to ground current is quite small and can be
ignored. Therefore, the junction temperature equation simplifies to
JUNCTION TEMPERATURE, TJ (°C)
THERMAL CONSIDERATIONS
Figure 33. TSOT, 500 mm2 of PCB Copper, TA = 25°C
140
MAX JUNCTION TEMPERATURE
1
TSOT
170
152
146
134
131
θJA (°C/W)
WLCSP
260
159
157
153
151
Device soldered to minimum size pin traces.
Table 8. Typical ΨJB Values
TSOT
42.8
100
80
ILOAD = 1mA
ILOAD = 10mA
ILOAD = 25mA
ILOAD = 50mA
ILOAD = 75mA
ILOAD = 100mA
ILOAD = 150mA
60
40
20
0
0.5
ΨJB (°C/W)
WLCSP
58.4
1.0
1.5
2.0
2.5
3.0
VIN – VOUT (V)
3.5
4.0
Figure 34. TSOT, 100 mm2 of PCB Copper, TA = 25°C
Use Equation 2 to calculate the junction temperature.
TJ = TA + (PD × θJA)
120
(2)
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
PD = [(VIN − VOUT) × ILOAD] + (VIN × IGND)
where:
ILOAD is the load current.
IGND is the ground current.
VIN and VOUT are input and output voltages, respectively.
Rev. 0 | Page 14 of 20
4.5
08343-229
Copper Size (mm2)
01
50
100
300
500
JUNCTION TEMPERATURE, TJ (°C)
Table 7. Typical θJA Values
ADP150
140
140
40
20
0
0.5
1.0
1.5
2.0
2.5
3.0
VIN – VOUT (V)
3.5
4.0
4.5
80
60
40
ILOAD = 1mA
ILOAD = 10mA
ILOAD = 25mA
ILOAD = 50mA
20
0
0.5
Figure 35. TSOT, 0 mm2 of PCB Copper, TA = 25°C
JUNCTION TEMPERATURE, TJ (°C)
80
60
40
ILOAD = 1mA
ILOAD = 10mA
ILOAD = 25mA
ILOAD = 50mA
1.0
1.5
ILOAD = 75mA
ILOAD = 100mA
ILOAD = 150mA
2.0
2.5
3.0
VIN – VOUT (V)
3.5
4.0
4.5
Figure 36. TSOT, 500 mm2 of PCB Copper, TA = 50°C
4.5
100
80
ILOAD = 1mA
ILOAD = 10mA
ILOAD = 25mA
ILOAD = 50mA
ILOAD = 75mA
ILOAD = 100mA
ILOAD = 150mA
60
40
20
1.0
1.5
2.0
2.5
3.0
VIN – VOUT (V)
3.5
4.0
4.5
Figure 39. TSOT, 100 mm2 of PCB Copper, Board Temperature = 85°C
140
140
MAX JUNCTION TEMPERATURE
MAX JUNCTION TEMPERATURE
JUNCTION TEMPERATURE, TJ (°C)
120
100
80
60
40
ILOAD = 1mA
ILOAD = 10mA
ILOAD = 25mA
ILOAD = 50mA
1.0
1.5
ILOAD = 75mA
ILOAD = 100mA
ILOAD = 150mA
2.0
2.5
3.0
VIN – VOUT (V)
3.5
4.0
4.5
08343-232
JUNCTION TEMPERATURE, TJ (°C)
4.0
120
0
0.5
08343-231
JUNCTION TEMPERATURE, TJ (°C)
100
0
0.5
3.5
MAX JUNCTION TEMPERATURE
120
20
2.0
2.5
3.0
VIN – VOUT (V)
140
MAX JUNCTION TEMPERATURE
0
0.5
1.5
Figure 38. TSOT, 0 mm2 of PCB Copper, TA = 50°C
140
20
1.0
ILOAD = 75mA
ILOAD = 100mA
ILOAD = 150mA
08343-233
60
100
08343-248
80
ILOAD = 1mA
ILOAD = 10mA
ILOAD = 25mA
ILOAD = 50mA
ILOAD = 75mA
ILOAD = 100mA
ILOAD = 150mA
120
Figure 37. TSOT, 100 mm2 of PCB Copper, TA = 50°C
120
ILOAD = 1mA
ILOAD = 10mA
ILOAD = 25mA
ILOAD = 50mA
ILOAD = 75mA
ILOAD = 100mA
ILOAD = 150mA
100
80
60
40
20
0
0.5
1.0
1.5
2.0
2.5
3.0
VIN – VOUT (V)
3.5
4.0
Figure 40. WLCSP, 500 mm2 of PCB Copper, TA = 25°C
Rev. 0 | Page 15 of 20
4.5
08343-042
100
MAX JUNCTION TEMPERATURE
JUNCTION TEMPERATURE, TJ (°C)
120
08343-230
JUNCTION TEMPERATURE, TJ (°C)
MAX JUNCTION TEMPERATURE
ADP150
140
140
MAX JUNCTION TEMPERATURE
ILOAD = 1mA
ILOAD = 10mA
ILOAD = 25mA
ILOAD = 50mA
ILOAD = 75mA
ILOAD = 100mA
ILOAD = 150mA
80
60
40
20
0
0.5
1.0
1.5
2.0
2.5
3.0
VIN – VOUT (V)
3.5
4.0
4.5
100
80
60
40
0
0.5
Figure 41. WLCSP, 100 mm2 of PCB Copper, TA = 25°C
JUNCTION TEMPERATURE, TJ (°C)
100
80
60
40
0
0.5
1.0
1.5
3.5
4.0
4.5
ILOAD = 50mA
ILOAD = 75mA
2.0
2.5
3.0
VIN – VOUT (V)
ILOAD = 100mA
ILOAD = 150mA
3.5
4.0
4.5
120
100
80
60
40
20
0
0.5
Figure 42. WLCSP, 0 mm2 of PCB Copper, TA = 25°C
ILOAD = 1mA
ILOAD = 10mA
ILOAD = 25mA
ILOAD = 50mA
1.0
1.5
ILOAD = 75mA
ILOAD = 100mA
ILOAD = 150mA
2.0
2.5
3.0
VIN – VOUT (V)
3.5
4.0
4.5
Figure 45. WLCSP, 0 mm2 of PCB Copper, TA = 50°C
140
140
MAX JUNCTION TEMPERATURE
MAX JUNCTION TEMPERATURE
100
80
60
40
ILOAD = 1mA
ILOAD = 10mA
ILOAD = 25mA
ILOAD = 50mA
20
0
0.5
1.0
1.5
ILOAD = 75mA
ILOAD = 100mA
ILOAD = 150mA
2.0
2.5
3.0
VIN – VOUT (V)
3.5
4.0
Figure 43. WLCSP, 500 mm2 of PCB Copper, TA = 50°C
4.5
120
100
80
60
40
20
0
0.5
ILOAD = 1mA
ILOAD = 10mA
ILOAD = 25mA
ILOAD = 50mA
ILOAD = 75mA
ILOAD = 100mA
ILOAD = 150mA
1.0
1.5
2.0
2.5
3.0
VIN – VOUT (V)
3.5
4.0
4.5
08343-049
JUNCTION TEMPERATURE, TJ (°C)
120
08343-045
JUNCTION TEMPERATURE, TJ (°C)
2.0
2.5
3.0
VIN – VOUT (V)
MAX JUNCTION
TEMPERATURE
120
ILOAD = 1mA
ILOAD = 10mA
ILOAD = 25mA
1.5
140
MAX JUNCTION
TEMPERATURE
20
1.0
ILOAD = 75mA
ILOAD = 100mA
ILOAD = 150mA
Figure 44. WLCSP, 100 mm2 of PCB Copper, TA = 50°C
08343-044
JUNCTION TEMPERATURE, TJ (°C)
140
ILOAD = 1mA
ILOAD = 10mA
ILOAD = 25mA
ILOAD = 50mA
20
08343-047
100
120
08343-046
JUNCTION TEMPERATURE, TJ (°C)
120
08343-043
JUNCTION TEMPERATURE, TJ (°C)
MAX JUNCTION TEMPERATURE
Figure 46. WLCSP, 100 mm2 of PCB Copper, Board Temperature = 85°C
Rev. 0 | Page 16 of 20
ADP150
PCB LAYOUT CONSIDERATIONS
Heat dissipation from the package can be improved by
increasing the amount of copper attached to the pins of the
ADP150. However, as listed in Table 7, a point of diminishing
returns is reached eventually, beyond which an increase in the
copper size does not yield significant heat dissipation benefits.
08343-148
Place the input capacitor as close as possible to the VIN and
GND pins. Place the output capacitor as close as possible to the
VOUT and GND pins. Use of 0402 size or 0603 size capacitors
and resistors achieves the smallest possible footprint solution on
boards where area is limited.
08343-147
Figure 48. Example WLCSP PCB Layout
Figure 47. Example TSOT PCB Layout
Rev. 0 | Page 17 of 20
ADP150
OUTLINE DIMENSIONS
2.90 BSC
5
4
2.80 BSC
1.60 BSC
1
2
3
0.95 BSC
1.90
BSC
*1.00 MAX
0.10 MAX
0.50
0.30
0.20
0.08
SEATING
PLANE
8°
4°
0°
0.60
0.45
0.30
100708-A
*0.90 MAX
0.70 MIN
*COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH
THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
Figure 49. 5-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-5)
Dimensions show in millimeters
0.660
0.600
0.540
SEATING
PLANE
2
1
A
0.280
0.260
0.240
BALL A1
IDENTIFIER
B
0.40
BALL PITCH
TOP VIEW
(BALL SIDE DOWN)
0.230
0.200
0.170
BOTTOM VIEW
(BALL SIDE UP)
0.050 NOM
COPLANARITY
Figure 50.4-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-4-3)
Dimensions show in millimeters
Rev. 0 | Page 18 of 20
011509-A
0.430
0.400
0.370
0.800
0.760 SQ
0.720
ADP150
ORDERING GUIDE
Model
ADP150ACBZ-1.8-R7 2
ADP150ACBZ-2.5-R72
ADP150ACBZ-2.75R72
ADP150ACBZ-2.8-R72
ADP150ACBZ-2.85R72
ADP150ACBZ-3.0R72
ADP150ACBZ-3.3-R72
ADP150AUJZ-1.8-R72
ADP150AUJZ-2.5-R72
ADP150AUJZ-2.8-R72
ADP150AUJZ-3.0-R72
ADP150AUJZ-3.3-R72
ADP150CB-3.3-EVALZ2
ADP150UJ-3.3-EVALZ2
Temperature
Range (TJ)
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Output
Voltage (V) 1
1.8
2.5
2.75
2.8
2.85
3.0
3.3
1.8
2.5
2.8
3.0
3.3
3.3
3.3
Package Description
4-Ball Wafer Level Chip Scale Package [WLCSP]
4-Ball Wafer Level Chip Scale Package [WLCSP]
4-Ball Wafer Level Chip Scale Package [WLCSP]
4-Ball Wafer Level Chip Scale Package [WLCSP]
4-Ball Wafer Level Chip Scale Package [WLCSP]
4-Ball Wafer Level Chip Scale Package [WLCSP]
4-Ball Wafer Level Chip Scale Package [WLCSP]
5-Lead Thin Small Outline Transistor Package [TSOT]
5-Lead Thin Small Outline Transistor Package [TSOT]
5-Lead Thin Small Outline Transistor Package [TSOT]
5-Lead Thin Small Outline Transistor Package [TSOT]
5-Lead Thin Small Outline Transistor Package [TSOT]
Evaluation Board with WLCSP package
Evaluation Board with TSOT package
1
Package
Option
CB-4-3
CB-4-3
CB-4-3
CB-4-3
CB-4-3
CB-4-3
CB-4-3
UJ-5
UJ-5
UJ-5
UJ-5
UJ-5
Branding
36
3V
3X
46
3Y
47
48
LDS
LDZ
LE3
LE2
LEJ
Up to 14 fixed output voltage options from 1.8 V to 3.3 V are available. For additional voltage options, contact your local Analog Devices, Inc, sales or distribution
representative.
2
Z = RoHS Compliant Part.
Rev. 0 | Page 19 of 20
ADP150
NOTES
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08343-0-10/09(0)
Rev. 0 | Page 20 of 20