TI1 ISO7741-Q1 High-speed, robust-emc reinforced quad-channel digital isolator Datasheet

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ISO7740-Q1, ISO7741-Q1, ISO7742-Q1
SLLSEU0 – NOVEMBER 2016
ISO774x-Q1 High-Speed, Robust-EMC Reinforced Quad-Channel Digital Isolators
1 Features
3 Description
•
•
The ISO774x-Q1 devices are high-performance,
quad-channel digital isolators with 5000 VRMS (DW
package) and 2500 VRMS (DBQ package) isolation
ratings per UL 1577. This family of devices has
reinforced insulation ratings according to VDE, CSA,
TUV and CQC.
1
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature
– Device HBM ESD Classification Level 3A
– Device CDM ESD Classification Level C6
Signaling Rate: Up to 100 Mbps
Wide Supply Range: 2.25 V to 5.5 V
2.25-V to 5.5-V Level Translation
Default Output High and Low Options
Low Power Consumption, Typical 1.5 mA per
Channel at 1 Mbps
Low Propagation Delay: 10.7 ns Typical
(5-V Supplies)
High CMTI: ±100 kV/μs Typical
Robust Electromagnetic Compatibility (EMC)
– System-Level ESD, EFT, and Surge Immunity
– Low Emissions
Isolation Barrier Life: >40 Years
Wide-SOIC (DW-16) and QSOP (DBQ-16)
Package Options
Safety-Related Certifications:
– DIN V VDE V 0884-10 (VDE V 0884-10):
2006-12
– UL 1577 Component Recognition Program
– CSA Component Acceptance Notice 5A, IEC
60950-1 and IEC 60601-1 End Equipment
Standards
– CQC Approval per GB4943.1-2011
– TUV Certification according to EN 60950-1 and
EN 61010-1
– Certifications for DW Package Complete; All
Other Certifications are Planned
2 Applications
•
•
•
•
•
Hybrid Electric Vehicles
Motor Control
Power Supplies
Solar Inverters
Medical Equipment
The ISO774x-Q1 devices provide high
electromagnetic immunity and low emissions at low
power consumption, while isolating CMOS or
LVCMOS digital I/Os. Each isolation channel has a
logic input and output buffer separated by silicon
dioxide (SiO2) insulation barrier. This device comes
with enable pins which can be used to put the
respective outputs in high impedance for multi-master
driving applications and to reduce power
consumption. The ISO7740-Q1 device has all four
channels in the same direction, the ISO7741-Q1
device has three forward and one reverse-direction
channels, and the ISO7742-Q1 device has two
forward and two reverse-direction channels. If the
input power or signal is lost, default output is high for
devices without suffix F and low for devices with
suffix F. See the Device Functional Modes section for
further details.
Used in conjunction with isolated power supplies, this
device helps prevent noise currents on a data bus or
other circuits from entering the local ground and
interfering with or damaging sensitive circuitry.
Through innovative chip design and layout
techniques, electromagnetic compatibility of the
ISO774x-Q1 devices have been significantly
enhanced to ease system-level ESD, EFT, surge, and
emissions compliance. The ISO774x-Q1 devices are
available in 16-pin SOIC and QSOP packages.
Device Information(1)
PART NUMBER
PACKAGE
ISO7740-Q1
ISO7741-Q1
ISO7742-Q1
BODY SIZE (NOM)
SOIC (DW)
10.30 mm × 7.50 mm
SSOP (DBQ)
4.90 mm × 3.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
VCCI
Isolation
Capacitor
VCCO
INx
OUTx
ENx
GNDI
GNDO
VCCI and GNDI are supply and ground
connections respectively for the input
channels.
VCCO and GNDO are supply and ground
connections respectively for the output
channels.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO7740-Q1, ISO7741-Q1, ISO7742-Q1
SLLSEU0 – NOVEMBER 2016
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6.18
6.19 Typical Characteristics .......................................... 18
1
1
1
2
3
5
7
8
Parameter Measurement Information ................ 20
Detailed Description ............................................ 22
8.1
8.2
8.3
8.4
Absolute Maximum Ratings ...................................... 5
ESD Ratings ............................................................ 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Power Rating............................................................. 6
Insulation Specifications .......................................... 7
Safety-Related Certifications..................................... 8
Safety Limiting Values .............................................. 8
Electrical Characteristics—5-V Supply ..................... 9
Supply Current Characteristics—5-V Supply ........ 10
Electrical Characteristics—3.3-V Supply .............. 11
Supply Current Characteristics—3.3-V Supply ..... 12
Electrical Characteristics—2.5-V Supply .............. 13
Supply Current Characteristics—2.5-V Supply ..... 14
Switching Characteristics—5-V Supply................. 15
Switching Characteristics—3.3-V Supply.............. 15
Switching Characteristics—2.5-V Supply.............. 16
Insulation Characteristics Curves ......................... 16
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
22
22
23
24
Application and Implementation ........................ 25
9.1 Application Information............................................ 25
9.2 Typical Application .................................................. 25
10 Power Supply Recommendations ..................... 27
11 Layout................................................................... 28
11.1 Layout Guidelines ................................................. 28
11.2 Layout Example .................................................... 28
12 Device and Documentation Support ................. 29
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
29
29
29
29
29
29
29
13 Mechanical, Packaging, and Orderable
Information ........................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
November 2016
*
Initial release.
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5 Pin Configuration and Functions
ISO7740-Q1 DW and DBQ Packages
16-Pin SOIC-WB and QSOP
Top View
ISO7741-Q1 DW and DBQ Packages
16-Pin SOIC-WB and QSOP
Top View
1
16 VCC2
VCC1
1
16 VCC2
GND1 2
15 GND2
GND1 2
15 GND2
3
INB
4
INC
5
IND
6
11 OUTD
NC
7
10
ISOLATION
INA
14 OUTA
INA
3
13 OUTB
INB
4
12 OUTC
INC
5
GND1 8
14 OUTA
ISOLATION
VCC1
OUTD 6
EN2
EN1
9 GND2
7
GND1 8
13 OUTB
12 OUTC
11
IND
10
EN2
9 GND2
ISO7742-Q1 DW and DBQ Packages
16-Pin SOIC-WB and QSOP
Top View
1
16 VCC2
GND1 2
15 GND2
INA
3
INB
4
OUTC 5
OUTD 6
EN1
7
GND1 8
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14 OUTA
ISOLATION
VCC1
13 OUTB
12
INC
11
IND
10
EN2
9 GND2
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Pin Functions
PIN
NAME
I/O
DESCRIPTION
7
I
Output enable 1. Output pins on side 1 are enabled when EN1 is high
or open and in high-impedance state when EN1 is low.
10
10
I
Output enable 2. Output pins on side 2 are enabled when EN2 is high
or open and in high-impedance state when EN2 is low.
2
2
2
8
8
8
ISO7740-Q1
ISO7741-Q1
ISO7742-Q1
EN1
—
7
EN2
10
GND1
—
Ground connection for VCC1
—
Ground connection for VCC2
9
9
9
15
15
15
INA
3
3
3
I
Input, channel A
INB
4
4
4
I
Input, channel B
INC
5
5
12
I
Input, channel C
IND
6
11
11
I
Input, channel D
NC
7
—
—
—
Not connected
OUTA
14
14
14
O
Output, channel A
OUTB
13
13
13
O
Output, channel B
OUTC
12
12
5
O
Output, channel C
OUTD
11
6
6
O
Output, channel D
VCC1
1
1
1
—
Power supply, side 1
VCC2
16
16
16
—
Power supply, side 2
GND2
4
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6 Specifications
6.1 Absolute Maximum Ratings
See
(1)
VCC1, VCC2
Supply voltage (2)
MIN
MAX
–0.5
6
V
Voltage at INx, OUTx, ENx
–0.5
IO
Output current
–15
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
UNIT
V
VCCX + 0.5
–65
(3)
V
15
mA
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±6000
Charged-device model (CDM), per AEC Q100-011
±1500
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
NOM
UNIT
Supply voltage
VCC(UVLO+)
UVLO threshold when supply voltage is rising
VCC(UVLO-)
UVLO threshold when supply voltage is falling
1.7
1.8
V
VHYS(UVLO)
Supply voltage UVLO hysteresis
100
200
mV
IOH
IOL
2.25
MAX
VCC1, VCC2
High-level output current
Low-level output current
VIH
High-level input voltage
VIL
Low-level input voltage
DR
Data rate
TA
Ambient temperature
(1)
2
VCCO (1) = 5 V
–4
VCCO = 3.3 V
–2
VCCO = 2.5 V
–1
5.5
V
2.25
V
mA
VCCO = 5 V
4
VCCO = 3.3 V
2
VCCO = 2.5 V
1
0.7 × VCCI
mA
(1)
VCCI
V
0
0.3 × VCCI
V
0
-40
25
100
Mbps
125
°C
VCCI = Input-side VCC; VCCO = Output-side VCC.
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6.4 Thermal Information
ISO774x-Q1
THERMAL METRIC (1)
DW (SOIC)
DBQ (QSOP)
16 Pins
16 Pins
UNIT
83.4
109
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case(top) thermal resistance
46
54.4
°C/W
RθJB
Junction-to-board thermal resistance
48
51.9
°C/W
ψJT
Junction-to-top characterization parameter
19.1
14.2
°C/W
ψJB
Junction-to-board characterization parameter
47.5
51.4
°C/W
RθJC(bottom)
Junction-to-case(bottom) thermal resistance
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
6.5 Power Rating
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
200
mW
40
mW
160
mW
200
mW
50
mW
150
mW
200
mW
100
mW
100
mW
ISO7740-Q1
PD
Maximum power dissipation
PD1
Maximum power dissipation by side-1
PD2
Maximum power dissipation by side-2
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 50-MHz 50% duty cycle square wave
ISO7741-Q1
PD
Maximum power dissipation
PD1
Maximum power dissipation by side-1
PD2
Maximum power dissipation by side-2
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 50-MHz 50% duty cycle square wave
ISO7742-Q1
PD
Maximum power dissipation
PD1
Maximum power dissipation by side-1
PD2
Maximum power dissipation by side-2
6
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VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 50-MHz 50% duty cycle square wave
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6.6 Insulation Specifications
PARAMETER
VALUE
TEST CONDITIONS
DW-16
DBQ-16
UNIT
External clearance (1)
Shortest terminal-to-terminal distance through air
>8
>3.7
mm
CPG
External creepage (1)
Shortest terminal-to-terminal distance across the package
surface
>8
>3.7
mm
DTI
Distance through the insulation
Minimum internal gap (internal clearance)
>21
>21
μm
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112
>600
>600
V
Material group
According to IEC 60664-1
I
I
Rated mains voltage ≤ 300 VRMS
I-IV
I-III
Rated mains voltage ≤ 600 VRMS
I-IV
n/a
Rated mains voltage ≤ 1000 VRMS
I-III
n/a
CLR
Overvoltage category per IEC 60664-1
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 (2)
VIORM
VIOWM
Maximum repetitive peak isolation voltage
AC voltage (bipolar)
1414
566
VPK
Maximum isolation working voltage
AC voltage; Time dependent dielectric breakdown (TDDB)
Test
1000
400
VRMS
DC voltage
1414
566
VDC
8000
3600
VPK
8000
4000
VPK
Method a, After Input/Output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM, tm = 10 s
≤5
≤5
Method a, After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM, tm = 10 s
≤5
≤5
Method b1; At routine test (100% production) and
preconditioning (type test)
Vini = VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM, tm = 1 s
≤5
≤5
VIO = 0.4 × sin (2πft), f = 1 MHz
~1
~1
VIOTM
Maximum transient isolation voltage
VTEST = VIOTM
t = 60 s (qualification)
t= 1 s (100% production)
VIOSM
Maximum surge isolation voltage (3)
Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM (qualification)
Apparent charge (4)
qpd
Barrier capacitance, input to output (5)
CIO
Isolation resistance (5)
RIO
12
>10
VIO = 500 V, 100°C ≤ TA ≤ 125°C
>1011
>1011
9
>109
>10
pF
12
VIO = 500 V, TA = 25°C
VIO = 500 V at TS = 150°C
pC
>10
Pollution degree
2
2
Climatic category
55/125/21
55/125/21
5000
2500
Ω
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
Maximum withstanding isolation voltage
VTEST = VISO , t = 60 s (qualification),
VTEST = 1.2 × VISO , t = 1 s (100% production)
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-terminal device.
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6.7 Safety-Related Certifications
DW package devices certified. All other certifications are planned.
VDE
CSA
UL
Certified according to UL 1577
Component Recognition
Program
CQC
Certified according to DIN
V VDE V 0884-10 (VDE V
0884-10):2006-12
Certified under CSA Component
Acceptance Notice 5A, IEC
60950-1 and IEC 60601-1
Maximum transient
isolation voltage, 8000 VPK
(DW-16) and 3600 VPK
(DBQ-16);
Maximum repetitive peak
isolation voltage, 1414 VPK
(DW-16) and 566 VPK
(DBQ-16);
Maximum surge isolation
voltage, 8000 VPK (DW16) and 4000 VPK (DBQ16)
Reinforced insulation per CSA
60950-1-07+A1+A2 and IEC
60950-1 2nd Ed.,
800 VRMS (DW-16) and 370 VRMS
(DBQ-16) max working voltage
(pollution degree 2, material
group I);
2 MOPP (Means of Patient
Protection) per CSA 60601-1:14
and IEC 60601-1 Ed. 3.1, 250
VRMS (DW-16) max working
voltage
DW-16: Reinforced Insulation,
Altitude ≤ 5000 m, Tropical
DW-16: Single protection, 5000 Climate, 400 VRMS maximum
VRMS;
working voltage;
DBQ-16: Single protection,
DBQ-16: Basic Insulation,
2500 VRMS
Altitude ≤ 5000 m, Tropical
Climate, 250 VRMS maximum
working voltage
Certificate number:
40040142
Master contract number: 220991
File number: E181974
Certified according to GB
4943.1-2011
Certificate number:
CQC15001121716
TUV
Certified according to EN
61010-1:2010 (3rd Ed) and
EN 609501:2006/A11:2009/A1:2010/A
12:2011/A2:2013
5000 VRMS Reinforced
insulation per EN 610101:2010 (3rd Ed) up to
working voltage of 600 VRMS
(DW-16)
5000 VRMS Reinforced
insulation per EN 609501:2006/A11:2009/A1:2010/A
12:2011/A2:2013 up to
working voltage of 800 VRMS
(DW-16)
Client ID number: 77311
6.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
DW-16 PACKAGE
IS
Safety input, output, or supply
current
RθJA = 83.4 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 1
273
RθJA = 83.4 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 1
416
RθJA = 83.4 °C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see
Figure 1
545
PS
Safety input, output, or total power RθJA = 83.4 °C/W, TJ = 150°C, TA = 25°C, see Figure 3
TS
Maximum safety temperature
mA
1499
mW
150
°C
DBQ-16 PACKAGE
IS
Safety input, output, or supply
current
RθJA = 109 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 2
209
RθJA = 109 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 2
319
RθJA = 109 °C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see
Figure 2
417
PS
Safety input, output, or total power RθJA = 109 °C/W, TJ = 150°C, TA = 25°C, see Figure 4
TS
Maximum safety temperature
mA
1147
mW
150
°C
The maximum safety temperature is the maximum junction temperature specified for the device. The power
dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines
the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information is that of a
device installed on a High-K test board for leaded Surface Mount Packages. The power is the recommended
maximum input voltage times the current. The junction temperature is then the ambient temperature plus the
power times the junction-to-air thermal resistance
8
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6.9 Electrical Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH = –4 mA; see Figure 15
VOL
Low-level output voltage
IOL = 4 mA; see Figure 15
VCCO
(1)
MIN
TYP
– 0.4
4.8
VIT+(IN) Rising input voltage threshold
VIT-(IN) Falling input voltage threshold
VI(HYS)
Input threshold voltage
hysteresis
(1)
IIH
High-level input current
VIH = VCCI
IIL
Low-level input current
VIL = 0 V at INx or ENx
CMTI
Common-mode transient
immunity
VI = VCCI or 0 V, VCM = 1200 V; see
Figure 18
CI
Input Capacitance (2)
VI = VCC/ 2 + 0.4×sin(2πft), f = 1 MHz,
VCC = 5 V
(1)
(2)
MAX
UNIT
V
0.2
0.4
V
0.6 × VCCI
0.7 × VCCI
V
0.3 × VCCI
0.4 × VCCI
V
0.1 × VCCI
0.2 × VCCI
V
10
at INx or ENx
–10
40
μA
μA
100
2
kV/μs
pF
VCCI = Input-side VCC; VCCO = Output-side VCC.
Measured from input pin to ground.
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6.10 Supply Current Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted).
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISO7740-Q1
EN2 = 0 V; VI = VCC1 (ISO7740-Q1);
VI = 0 V (ISO7740-Q1 with F suffix)
ICC1
1.2
1.6
ICC2
0.3
0.5
EN2 = 0 V; VI = 0 V (ISO7740-Q1);
VI = VCC1 (ISO7740-Q1 with F suffix)
ICC1
5.5
7.8
ICC2
0.3
0.5
EN2 = VCC2; VI = VCC1 (ISO7740-Q1);
VI = 0 V (ISO7740-Q1 with F suffix)
ICC1
1.2
1.6
ICC2
2
3.2
EN2 = VCC2; VI = 0 V (ISO7740-Q1);
VI = VCC1 (ISO7740-Q1 with F suffix)
ICC1
5.5
7.8
ICC2
2.2
3.6
ICC1
3.3
4.7
ICC2
2.3
3.6
ICC1
3.4
4.8
ICC2
4.2
5.8
ICC1
3.8
5.7
ICC2
22.7
28
Supply current - Disable
Supply current - DC signal
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
mA
ISO7741-Q1
EN1 = EN2 = 0 V; VI = VCCI (1) (ISO7741-Q1);
VI = 0 V (ISO7741-Q1 with F suffix)
ICC1
1
1.5
ICC2
0.8
1.1
EN1 = EN2 = 0 V; VI = 0 V (ISO7741-Q1);
VI = VCCI (ISO7741-Q1 with F suffix)
ICC1
4.3
6.3
ICC2
1.8
2.7
EN1 = EN2 = VCCI; VI = VCCI (ISO7741-Q1);
VI = 0 V (ISO7741-Q1 with F suffix)
ICC1
1.5
2.3
ICC2
2
3
EN1 = EN2 = VCCI; VI = 0 V (ISO7741-Q1);
VI = VCCI (ISO7741-Q1 with F suffix)
ICC1
4.8
6.8
ICC2
3.2
4.9
ICC1
3.2
4.6
ICC2
2.8
4.1
ICC1
3.7
5.2
ICC2
4.2
5.7
ICC1
8.6
11.3
ICC2
18
22
EN1 = EN2 = 0 V; VI = VCCI (ISO7742-Q1);
VI = 0 V (ISO7742-Q1 with F suffix)
ICC1, ICC2
0.9
1.3
EN1 = EN2 = 0 V; VI = 0 V (ISO7742-Q1);
VI = VCCI (ISO7742-Q1 with F suffix)
ICC1, ICC2
3
4.6
EN1 = EN2 = VCCI; VI = VCCI (ISO7742-Q1);
VI = 0 V (ISO7742-Q1 with F suffix)
ICC1, ICC2
1.7
2.7
EN1 = EN2 = VCCI; VI = 0 V (ISO7742-Q1);
VI = VCCI (ISO7742-Q1 with F suffix)
ICC1, ICC2
4
5.9
1 Mbps
ICC1, ICC2
3
4.4
10 Mbps
ICC1, ICC2
4
5.5
100 Mbps
ICC1, ICC2
13.4
17
Supply current - Disable
Supply current - DC signal
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
mA
ISO7742-Q1
Supply current - Disable
Supply current - DC signal
Supply current - AC signal
(1)
10
All channels switching with square
wave clock input; CL = 15 pF
mA
VCCI = Input-side VCC
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6.11 Electrical Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCCO (1) – 0.3
3.2
VOH
High-level output voltage
IOH = –2 mA; see Figure 15
VOL
Low-level output voltage
IOL = 2 mA; see Figure 15
VIT+(IN)
Rising input voltage threshold
VIT-(IN)
Falling input voltage threshold
0.3 × VCCI
0.4 × VCCI
VI(HYS)
Input threshold voltage hysteresis
0.1 × VCCI
0.2 × VCCI
IIH
High-level input current
VIH = VCCI (1) at INx or ENx
IIL
Low-level input current
VIL = 0 V at INx or ENx
CMTI
Common-mode transient
immunity
VI = VCCI or 0 V, VCM = 1200 V; see Figure 18
(1)
MAX
V
0.1
0.3
V
0.6 × VCCI
0.7 × VCCI
V
V
V
10
–10
40
UNIT
μA
μA
100
kV/μs
VCCI = Input-side VCC; VCCO = Output-side VCC.
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6.12 Supply Current Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted).
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISO7740-Q1
EN2 = 0 V; VI = VCC1 (ISO7740-Q1);
VI = 0 V (ISO7740-Q1 with F suffix)
ICC1
1.2
1.6
ICC2
0.3
0.5
EN2 = 0 V; VI = 0 V (ISO7740-Q1);
VI = VCC1 (ISO7740-Q1 with F suffix)
ICC1
5.5
7.8
ICC2
0.3
0.5
EN2 = VCC2; VI = VCC1 (ISO7740-Q1);
VI = 0 V (ISO7740-Q1 with F suffix)
ICC1
1.2
1.6
ICC2
1.9
3.2
EN2 = VCC2; VI = 0 V (ISO7740-Q1);
VI = VCC1 (ISO7740-Q1 with F suffix)
ICC1
5.5
7.8
ICC2
2.2
3.6
ICC1
3.3
4.7
ICC2
2.2
3.6
ICC1
3.4
4.8
ICC2
3.6
5
ICC1
3.3
5.5
ICC2
17
20
Supply current - Disable
Supply current - DC signal
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
mA
ISO7741-Q1
EN1 = EN2 = 0 V; VI = VCCI (1) (ISO7741-Q1);
VI = 0 V (ISO7741-Q1 with F suffix)
ICC1
1
1.5
ICC2
0.8
1.1
EN1 = EN2 = 0 V; VI = 0 V (ISO7741-Q1);
VI = VCCI (ISO7741-Q1 with F suffix)
ICC1
4.3
6.3
ICC2
1.9
2.7
EN1 = EN2 = VCCI; VI = VCCI (ISO7741-Q1);
VI = 0 V (ISO7741-Q1 with F suffix)
ICC1
1.5
2.3
ICC2
2
3
EN1 = EN2 = VCCI; VI = 0 V (ISO7741-Q1);
VI = VCCI (ISO7741-Q1 with F suffix)
ICC1
4.8
6.8
ICC2
3.2
4.9
ICC1
3.2
4.6
ICC2
2.7
4.1
ICC1
3.5
5
ICC2
3.7
5.2
Supply current - Disable
Supply current - DC signal
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
ICC1
6.8
9.3
ICC2
13.7
16.4
EN1 = EN2 = 0 V; VI = VCCI (ISO7742-Q1);
VI = 0 V (ISO7742-Q1 with F suffix)
ICC1, ICC2
0.9
1.3
EN1 = EN2 = 0 V; VI = 0 V (ISO7742-Q1);
VI = VCCI (ISO7742-Q1 with F suffix)
ICC1, ICC2
3
4.6
EN1 = EN2 = VCCI; VI = VCCI (ISO7742-Q1);
VI = 0 V (ISO7742-Q1 with F suffix)
ICC1, ICC2
1.7
2.7
EN1 = EN2 = VCCI; VI = 0 V (ISO7742-Q1);
VI = VCCI (ISO7742-Q1 with F suffix)
ICC1, ICC2
4
5.9
1 Mbps
ICC1, ICC2
2.9
4.3
10 Mbps
ICC1, ICC2
3.6
5.1
100 Mbps
ICC1, ICC2
10.3
13
100 Mbps
mA
ISO7742-Q1
Supply current - Disable
Supply current - DC signal
Supply current - AC signal
(1)
12
All channels switching with square
wave clock input; CL = 15 pF
mA
VCCI = Input-side VCC
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6.13 Electrical Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCCO (1) – 0.2
2.45
VOH
High-level output voltage
IOH = –1 mA; see Figure 15
VOL
Low-level output voltage
IOL = 1 mA; see Figure 15
VIT+(IN)
Rising input voltage threshold
VIT-(IN)
Falling input voltage threshold
0.3 × VCCI
0.4 × VCCI
VI(HYS)
Input threshold voltage hysteresis
0.1 × VCCI
0.2 × VCCI
IIH
High-level input current
VIH = VCCI (1) at INx or ENx
IIL
Low-level input current
VIL = 0 V at INx or ENx
CMTI
Common-mode transient
immunity
VI = VCCI or 0 V, VCM = 1200 V; see Figure 18
(1)
MAX
UNIT
V
0.05
0.2
V
0.6 × VCCI
0.7 × VCCI
V
V
V
10
μA
–10
μA
40
100
kV/μs
VCCI = Input-side VCC; VCCO = Output-side VCC.
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6.14 Supply Current Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted).
PARAMETER
TEST CONDITIONS
SUPPLY
CURRENT
MIN
TYP
MAX
UNIT
ISO7740-Q1
EN2 = 0 V; VI = VCC1 (ISO7740-Q1);
VI = 0 V (ISO7740-Q1 with F suffix)
ICC1
1.2
1.6
ICC2
0.3
0.5
EN2 = 0 V; VI = 0 V (ISO7740-Q1);
VI = VCC1 (ISO7740-Q1 with F suffix)
ICC1
5.5
7.8
ICC2
0.3
0.5
EN2 = VCC2; VI = VCC1 (ISO7740-Q1);
VI = 0 V (ISO7740-Q1 with F suffix)
ICC1
1.2
1.6
ICC2
1.9
3.2
EN2 = VCC2; VI = 0 V (ISO7740-Q1);
VI = VCC1 (ISO7740-Q1 with F suffix)
ICC1
5.4
7.8
ICC2
2.2
3.6
ICC1
3.3
4.7
ICC2
2.2
3.5
ICC1
3.4
4.8
ICC2
3.2
4.7
ICC1
3.2
5.4
ICC2
13
17
Supply current - Disable
Supply current - DC signal
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
mA
ISO7741-Q1
EN1 = EN2 = 0 V; VI = VCCI (1) (ISO7741-Q1);
VI = 0 V (ISO7741-Q1 with F suffix)
ICC1
1
1.5
ICC2
0.8
1.1
EN1 = EN2 = 0 V; VI = 0 V (ISO7741-Q1);
VI = VCCI (ISO7741-Q1 with F suffix)
ICC1
4.3
6.3
ICC2
1.8
2.7
EN1 = EN2 = VCCI; VI = VCCI (ISO7741-Q1);
VI = 0 V (ISO7741-Q1 with F suffix)
ICC1
1.4
2.3
ICC2
2
3
EN1 = EN2 = VCCI; VI = 0 V (ISO7741-Q1);
VI = VCCI (ISO7741-Q1 with F suffix)
ICC1
4.7
6.8
ICC2
3.2
4.9
ICC1
3.1
4.6
ICC2
2.7
4
ICC1
3.4
4.9
ICC2
3.5
4.9
ICC1
5.6
8.3
ICC2
10.8
13.8
EN1 = EN2 = 0 V; VI = VCCI (ISO7742-Q1);
VI = 0 V (ISO7742-Q1 with F suffix)
ICC1, ICC2
0.9
1.3
EN1 = EN2 = 0 V; VI = 0 V (ISO7742-Q1);
VI = VCCI (ISO7742-Q1 with F suffix)
ICC1, ICC2
3
4.6
EN1 = EN2 = VCCI; VI = VCCI (ISO7742-Q1);
VI = 0 V (ISO7742-Q1 with F suffix)
ICC1, ICC2
1.7
2.7
EN1 = EN2 = VCCI; VI = 0 V (ISO7742-Q1);
VI = VCCI (ISO7742-Q1 with F suffix)
ICC1, ICC2
4
5.9
1 Mbps
ICC1, ICC2
2.9
4.3
10 Mbps
ICC1, ICC2
3.4
4.9
100 Mbps
ICC1, ICC2
8.3
11.5
Supply current - Disable
Supply current - DC signal
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
mA
ISO7742-Q1
Supply current - Disable
Supply current - DC signal
Supply current - AC signal
(1)
14
All channels switching with square
wave clock input; CL = 15 pF
mA
VCCI = Input-side VCC
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6.15 Switching Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
MIN
TYP
MAX
6
10.7
16
ns
0
4.9
ns
4
ns
4.4
ns
2.4
3.9
ns
2.4
3.9
ns
Disable propagation delay, high-to-high impedance output
9
20
ns
Disable propagation delay, low-to-high impedance output
9
20
ns
Enable propagation delay, high impedance-to-high output
for ISO774x-Q1
7
20
ns
3
8.5
μs
Enable propagation delay, high impedance-to-low output for
ISO774x-Q1
3
8.5
μs
Enable propagation delay, high impedance-to-low output for
ISO774x-Q1 with F suffix
7
20
ns
0.1
0.3
μs
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time (2)
tsk(pp)
Part-to-part skew time (3)
tr
Output signal rise time
tf
Output signal fall time
tPHZ
tPLZ
tPZH
tDO
Same-direction channels
See Figure 15
See Figure 16
Measured from the time VCC goes
below 1.7 V. See
Default output delay time from input power loss
tie
(3)
See Figure 15
Enable propagation delay, high impedance-to-high output
for ISO774x-Q1 with F suffix
tPZL
(1)
(2)
TEST CONDITIONS
16
Time interval error
2
0.8
– 1 PRBS data at 100 Mbps
UNIT
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.16 Switching Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
MIN
TYP
MAX
6
11
16
ns
0.1
5
ns
4.1
ns
4.5
ns
1.3
3
ns
1.3
3
ns
Disable propagation delay, high-to-high impedance output
17
30
ns
Disable propagation delay, low-to-high impedance output
17
30
ns
Enable propagation delay, high impedance-to-high output
for ISO774x-Q1
17
30
ns
3.2
8.5
μs
Enable propagation delay, high impedance-to-low output
for ISO774x-Q1
3.2
8.5
μs
Enable propagation delay, high impedance-to-low output
for ISO774x-Q1 with F suffix
17
30
ns
0.1
0.3
μs
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time (2)
tsk(pp)
Part-to-part skew time (3)
tr
Output signal rise time
tf
Output signal fall time
tPHZ
tPLZ
tPZH
tPZL
tDO
tie
(1)
(2)
(3)
TEST CONDITIONS
See Figure 15
Same-direction channels
See Figure 15
Enable propagation delay, high impedance-to-high output
for ISO774x-Q1 with F suffix
Default output delay time from input power loss
See Figure 16
Measured from the time VCC goes
below 1.7 V. See
16
Time interval error
2
0.9
– 1 PRBS data at 100 Mbps
UNIT
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.17 Switching Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time (2)
tsk(pp)
Part-to-part skew time (3)
tr
Output signal rise time
tf
Output signal fall time
tPHZ
tPLZ
tPZH
tDO
(1)
(2)
(3)
MAX
UNIT
18.5
ns
0.2
5.1
ns
4.1
ns
4.6
ns
1
3.5
ns
1
3.5
ns
Disable propagation delay, high-to-high impedance output
22
40
ns
Disable propagation delay, low-to-high impedance output
22
40
ns
Enable propagation delay, high impedance-to-high output
for ISO774x-Q1
18
40
ns
3.3
8.5
μs
Enable propagation delay, high impedance-to-low output
for ISO774x-Q1
3.3
8.5
μs
Enable propagation delay, high impedance-to-low output
for ISO774x-Q1 with F suffix
18
40
ns
0.1
0.3
μs
See Figure 15
Same-direction Channels
See Figure 15
See Figure 16
Measured from the time VCC goes
below 1.7 V. See
Default output delay time from input power loss
tie
7.5
TYP
12
Enable propagation delay, high impedance-to-high output
for ISO774x-Q1 with F suffix
tPZL
MIN
16
Time interval error
2
0.7
– 1 PRBS data at 100 Mbps
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.18 Insulation Characteristics Curves
450
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
500
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
400
Safety Limiting Current (mA)
Safety Limiting Current (mA)
600
400
300
200
100
350
300
250
200
150
100
50
0
0
0
50
100
150
Ambient Temperature (qC)
200
D001
Figure 1. Thermal Derating Curve for Safety Limiting
Current for
DW-16 Package
16
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0
50
100
150
Ambient Temperature (qC)
200
D002
Figure 2. Thermal Derating Curve for Safety Limiting
Current for
DBQ-16 Package
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1600
1400
1400
1200
Safety Limiting Power (mW)
Safety Limiting Power (mW)
Insulation Characteristics Curves (continued)
1200
1000
800
600
400
1000
800
600
400
200
200
0
0
0
50
100
150
Ambient Temperature (qC)
200
D003
Figure 3. Thermal Derating Curve for Safety Limiting Power
for DW-16 Package
Copyright © 2016, Texas Instruments Incorporated
0
50
100
150
Ambient Temperature (qC)
200
D004
Figure 4. Thermal Derating Curve for Safety Limiting Power
for DBQ-16 Package
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6.19 Typical Characteristics
9
25
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
15
7
Supply Current (mA)
Supply Current (mA)
20
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
8
10
6
5
4
3
2
5
1
0
0
0
25
TA = 25°C
50
Data Rate (Mbps)
75
0
100
CL = 15 pF
100
D006
CL = No Load
9
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
16
14
12
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
8
7
Supply Current (mA)
18
Supply Current (mA)
75
Figure 6. ISO7740-Q1 Supply Current vs Data Rate
(With No Load)
20
10
8
6
6
5
4
3
4
2
2
1
0
0
0
25
TA = 25°C
50
Data Rate (Mbps)
75
100
0
25
50
Data Rate (Mbps)
D007
CL = 15 pF
TA = 25°C
Figure 7. ISO7741-Q1 Supply Current vs Data Rate
(With 15-pF Load)
75
100
D008
CL = No Load
Figure 8. ISO7741-Q1 Supply Current vs Data Rate
(With No Load)
8
16
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
12
10
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
7
Supply Current (mA)
14
Supply Current (mA)
50
Data Rate (Mbps)
TA = 25°C
Figure 5. ISO7740-Q1 Supply Current vs Data Rate
(With 15-pF Load)
8
6
4
6
5
4
3
2
1
2
0
0
0
25
TA = 25°C
50
Data Rate (Mbps)
75
100
CL = 15 pF
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0
25
D009
Figure 9. ISO7742-Q1 Supply Current vs Data Rate
(With 15-pF Load)
18
25
D005
50
Data Rate (Mbps)
TA = 25°C
75
100
D010
CL = No Load
Figure 10. ISO7742-Q1 Supply Current vs Data Rate
(With No Load)
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Typical Characteristics (continued)
6
0.9
Low-Level Output Voltage (V)
High-Level Output Voltage (V)
0.8
5
4
3
2
VCC at 2.5 V
VCC at 3.3 V
VCC at 5 V
1
0
-15
0.7
0.6
0.5
0.4
0.3
0.2
VCC at 2.5 V
VCC at 3.3 V
VCC at 5 V
0.1
0
-10
-5
High-Level Output Current (mA)
0
0
TA = 25°C
15
D012
TA = 25°C
Figure 11. High-Level Output Voltage vs High-level Output
Current
Figure 12. Low-Level Output Voltage vs Low-Level Output
Current
2.10
14
2.05
Propagation Delay Time (ns)
Power Supply UVLO Threshold (V)
5
10
Low-Level Output Current (mA)
D011
2.00
1.95
1.90
1.85
1.80
VCC1 Rising
VCC1 Falling
VCC2 Rising
VCC2 Falling
1.75
1.70
1.65
-55
-5
45
Free-Air Temperature (qC)
95
125
D013
Figure 13. Power Supply Undervoltage Threshold vs FreeAir Temperature
Copyright © 2016, Texas Instruments Incorporated
13
12
11
10
tPHL at 2.5 V
tPLH at 2.5 V
tPHL at 3.3 V
9
8
-55
-25
5
35
65
Free-Air Temperature (qC)
tPLH at 3.3 V
tPHL at 5 V
tPLH at 5 V
95
125
D014
Figure 14. Propagation Delay Time vs Free-Air Temperature
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7 Parameter Measurement Information
Isolation Barrier
IN
Input
Generator
(See Note A)
VI
VCCI
VI
OUT
50%
50%
0V
tPLH
CL
See Note B
VO
50
tPHL
VO
VOH
90%
50%
50%
10%
VOL
tf
tr
Copyright © 2016, Texas Instruments Incorporated
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3ns, ZO = 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in
actual application.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 15. Switching Characteristics Test Circuit and Voltage Waveforms
VCCO
VCC
Isolation Barrier
IN
0V
VO
VI
tPZL
0V
tPLZ
VOH
EN
0.5 V
VO
50%
VOL
50
OUT
VCC
VO
VCC / 2
VCC / 2
VI
0V
EN
CL
See Note B
VI
VCC / 2
VCC / 2
VI
CL
See Note B
IN
Input
Generator
(See Note A)
±1%
OUT
Isolation Barrier
Input
Generator
(See Note A)
3V
RL = 1 k
tPZH
RL = 1 k
±1%
VOH
50%
VO
0.5 V
tPHZ
50
0V
Copyright © 2016, Texas Instruments Incorporated
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 10 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 16. Enable/Disable Propagation Delay Time Test Circuit and Waveform
20
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Parameter Measurement Information (continued)
VI See Note B
VCC
VCC
Isolation Barrier
IN = 0 V (Devices without suffix F)
IN = VCC (Devices with suffix F)
VI
IN
1.7 V
0V
OUT
VO
tDO
CL
See Note A
VO
default high
VOH
50%
VOL
default low
Copyright © 2016, Texas Instruments Incorporated
A.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B.
Power Supply Ramp Rate = 10 mV/ns
Figure 17. Default Output Delay Time Test Circuit and Voltage Waveforms
VCCI
VCCO
C = 0.1 µF ±1%
Pass-fail criteria:
The output must
remain stable.
Isolation Barrier
S1
IN
C = 0.1 µF ±1%
OUT
+
EN
CL
See Note A
GNDI
+
VCM ±
VOH or VOL
±
GNDO
Copyright © 2016, Texas Instruments Incorporated
A.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 18. Common-Mode Transient Immunity Test Circuit
Copyright © 2016, Texas Instruments Incorporated
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8 Detailed Description
8.1 Overview
The ISO774x-Q1 family of devices have an ON-OFF keying (OOK) modulation scheme to transmit the digital
data across a silicon dioxide based isolation barrier. The transmitter sends a high frequency carrier across the
barrier to represent one digital state and sends no signal to represent the other digital state. The receiver
demodulates the signal after advanced signal conditioning and produces the output through a buffer stage. If the
ENx pin is low then the output goes to high impedance. The ISO774x-Q1 devices also incorporate advanced
circuit techniques to maximize the CMTI performance and minimize the radiated emissions due the high
frequency carrier and IO buffer switching. The conceptual block diagram of a digital capacitive isolator, Figure 19,
shows a functional block diagram of a typical channel.
8.2 Functional Block Diagram
Transmitter
Receiver
EN
TX IN
OOK
Modulation
TX Signal
Conditioning
Oscillator
SiO2 based
Capacitive
Isolation
Barrier
RX Signal
Conditioning
Envelope
Detection
RX OUT
Emissions
Reduction
Techniques
Copyright © 2016, Texas Instruments Incorporated
Figure 19. Conceptual Block Diagram of a Digital Capacitive Isolator
Figure 20 shows a conceptual detail of how the ON-OFF keying scheme works.
TX IN
Carrier signal through
isolation barrier
RX OUT
Figure 20. On-Off Keying (OOK) Based Modulation Scheme
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8.3 Feature Description
Table 1 provides an overview of the device features.
Table 1. Device Features
PART NUMBER
CHANNEL DIRECTION
MAXIMUM DATA
RATE
DEFAULT
OUTPUT
ISO7740-Q1
4 Forward,
0 Reverse
100 Mbps
High
ISO7740-Q1 with F
suffix
4 Forward,
0 Reverse
100 Mbps
Low
ISO7741-Q1
3 Forward,
1 Reverse
100 Mbps
High
ISO7741-Q1 with F
suffix
3 Forward,
1 Reverse
ISO7742-Q1
2 Forward,
2 Reverse
ISO7742-Q1 with F
suffix
(1)
2 Forward,
2 Reverse
100 Mbps
100 Mbps
100 Mbps
Low
High
Low
PACKAGE
RATED ISOLATION (1)
DW-16
5000 VRMS / 8000 VPK
DBQ-16
2500 VRMS / 3600 VPK
DW-16
5000 VRMS / 8000 VPK
DBQ-16
2500 VRMS / 3600 VPK
DW-16
5000 VRMS / 8000 VPK
DBQ-16
2500 VRMS / 3600 VPK
DW-16
5000 VRMS / 8000 VPK
DBQ-16
2500 VRMS / 3600 VPK
DW-16
5000 VRMS / 8000 VPK
DBQ-16
2500 VRMS / 3600 VPK
DW-16
5000 VRMS / 8000 VPK
DBQ-16
2500 VRMS / 3600 VPK
See Safety-Related Certifications for detailed isolation ratings.
8.3.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO774xQ1 family of devices incorporates many chip-level design improvements for overall system robustness. Some of
these improvements include:
• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
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8.4 Device Functional Modes
Table 2 lists the functional modes for the ISO774x-Q1 devices.
Table 2. Function Table (1)
VCCI
VCCO
PU
(2)
(3)
OUTPUT
ENABLE
(ENx)
OUTPUT
(OUTx)
H
H or open
H
L
H or open
L
Open
H or open
Default
X
L
Z
PU
X
(1)
INPUT
(INx) (2)
PU
PD
PU
X
H or open
Default
X
PD
X
X
Undetermined
COMMENTS
Normal Operation:
A channel output assumes the logic state of its input.
Default mode: When INx is open, the corresponding channel output
goes to its default logic state. Default is High for ISO774x-Q1 and
Low for ISO774x-Q1 with F suffix.
A low value of output enable causes the outputs to be highimpedance.
Default mode: When VCCI is unpowered, a channel output assumes
the logic state based on the selected default option. Default is High
for ISO774x-Q1 and Low for ISO774x-Q1 with F suffix.
When VCCI transitions from unpowered to powered-up, a channel
output assumes the logic state of the input.
When VCCI transitions from powered-up to unpowered, channel output
assumes the selected default state.
When VCCO is unpowered, a channel output is undetermined (3).
When VCCO transitions from unpowered to powered-up, a channel
output assumes the logic state of the input.
VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 2.25 V); PD = Powered down (VCC ≤ 1.7 V); X = Irrelevant; H
= High level; L = Low level ; Z = High Impedance
A strongly driven input signal can weakly power the floating VCC through an internal protection diode and cause undetermined output.
The outputs are in undetermined state when 1.7 V < VCCI, VCCO < 2.25 V.
8.4.1 Device I/O Schematics
Input (Devices without F suffix)
VCCI
VCCI
VCCI
Input (Devices with F suffix)
VCCI
VCCI
VCCI
VCCI
1.5 M
985
985
INx
INx
1.5 M
Output
Enable
VCCO
VCCO
VCCO
VCCO
VCCO
2M
~20
1970
OUTx
ENx
Copyright © 2016, Texas Instruments Incorporated
Figure 21. Device I/O Schematics
24
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ISO774x-Q1 devices are high-performance, quad-channel digital isolators. These devices come with enable
pins on each side which can be used to put the respective outputs in high impedance for multi master driving
applications and reduce power consumption. The ISO774x-Q1 devices use single-ended CMOS-logic switching
technology. The voltage range is from 2.25 V to 5.5 V for both supplies, VCC1 and VCC2. When designing with
digital isolators, keep in mind that because of the single-ended design structure, digital isolators do not conform
to any specific interface standard and are only intended for isolating single-ended CMOS or TTL digital signal
lines. The isolator is typically placed between the data controller (that is, μC or UART), and a data converter or a
line transceiver, regardless of the interface type or standard.
9.2 Typical Application
Figure 22 shows the typical isolated CAN interface implementation.
VS
3.3 V
10 F
2
Vcc
D2
1:1.33
3
MBR0520L
1
D1
4
OUT
ISO 3.3V
5
TPS76333-Q1
SN6501-Q1
GND
IN
10 F 0.1 F
3
1
EN
GND
10 F
2
MBR0520L
GND
5
ISO Barrier
0.1 F
0.1 F
0.1 F
0.1 F 29,57
VDDIO
TMS320F28
035PAGQ
CANRXA
CANTXA
26
1
5
25
3
VCC1
VCC2
OUTC
INC
INA
OUTA
VSS
6,28
16
12
14
3
VCC
RS
CANH
R
4
SN65HVD231Q
D
CANL
1
Vref
GND
8
10
(optional)
7
6
10
(optional)
5
2
ISO774x-Q1
SM712
0.1 F
0.1 F 29,57
6
VDDIO
TMS320F28
035PAGQ
CANRXA
26
4
2,8
CANTXA
25
OUTD
IND
INB
OUTB
GND1
GND2
11
13
9,15
3
VCC
4.7 nF / 2 kV
RS 8 10
CANH
7
R
4
SN65HVD231Q
6 10
CANL
D
1
Vref 5
GND
(optional)
(optional)
SM712
2
VSS
6,28
4.7 nF / 2 kV
Copyright © 2016, Texas Instruments Incorporated
Figure 22. Typical Isolated CAN Application Circuit
Copyright © 2016, Texas Instruments Incorporated
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Typical Application (continued)
9.2.1 Design Requirements
To design with these devices, use the parameters listed in Table 3.
Table 3. Design Parameters
PARAMETER
VALUE
Supply voltage, VCC1 and VCC2
2.25 to 5.5 V
Decoupling capacitor between VCC1 and GND1
0.1 µF
Decoupling capacitor from VCC2 and GND2
0.1 µF
9.2.2 Detailed Design Procedure
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO774x-Q1 family of devices only require two external bypass capacitors to operate.
2 mm maximum
from VCC2
2 mm maximum
from VCC1
0.1 µF
0.1 µF
VCC2
VCC1
1
16
2
15
INA
3
14
OUTA
INB
4
13
OUTB
INC
5
12
OUTC
OUTD
6
11
IND
7
10
8
9
GND1
GND2
EN2
EN1
GND2
GND1
Figure 23. Typical ISO7741-Q1 Circuit Hook-up
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9.2.3 Application Curve
Ch4 = 1 V / div
Ch4 = 1 V / div
The following typical eye diagrams of the ISO774x-Q1 family of devices indicates low jitter and wide open eye at
the maximum data rate of 100 Mbps.
Time = 2.5 ns / div
Time = 2.5 ns / div
Figure 25. Eye Diagram at 100 Mbps PRBS 216 – 1, 3.3 V
and 25°C
Ch4 = 500 mV / div
Figure 24. Eye Diagram at 100 Mbps PRBS 216 – 1, 5 V and
25°C
Time = 2.5 ns / div
Figure 26. Eye Diagram at 100 Mbps PRBS 216 – 1, 2.5 V and 25°C
10 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins
as possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501-Q1.
For such applications, detailed power supply design and transformer selection recommendations are available in
SN6501-Q1 Transformer Driver for Isolated Power Supplies (SLLSEF3).
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11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 27). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/inch2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, refer to the Digital Isolator Design Guide (SLLA284).
11.1.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 UL94V-0 printed circuit boards. This PCB is preferred over cheaper
alternatives due to its lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and self-extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces, pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 27. Layout Example Schematic
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Digital Isolator Design Guide (SLLA284)
• Isolation Glossary (SLLA353)
• SN6501-Q1 Transformer Driver for Isolated Power Supplies (SLLSEF3)
• SN65HVD231Q-Q1 3.3-V CAN Transceivers (SGLS398)
• TMS320F28035 Piccolo™ Microcontrollers (SPRS584)
• TPS76333-Q1 Low-Power 150-mA Low-Dropout Linear Regulators (SGLS247)
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
ISO7740-Q1
Click here
Click here
Click here
Click here
Click here
ISO7741-Q1
Click here
Click here
Click here
Click here
Click here
ISO7742-Q1
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
Piccolo, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
DBQ0016A
SSOP - 1.75 mm max height
SCALE 2.800
SHRINK SMALL-OUTLINE PACKAGE
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
16
1
14X .0250
[0.635]
2X
.175
[4.45]
.189-.197
[4.81-5.00]
NOTE 3
8
9
B
16X .008-.012
[0.21-0.30]
.150-.157
[3.81-3.98]
NOTE 4
.007 [0.17]
C A
B
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
GAGE PLANE
.004-.010
[ 0.11 -0.25]
0 -8
.016-.035
[0.41-0.88]
DETAIL A
(.041 )
[1.04]
TYPICAL
4214846/A 03/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.
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EXAMPLE BOARD LAYOUT
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SEE
DETAILS
SYMM
1
16
16X (.016 )
[0.41]
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
LAND PATTERN EXAMPLE
SCALE:8X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
.002 MAX
[0.05]
ALL AROUND
METAL
.002 MIN
[0.05]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214846/A 03/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
32
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Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO7740-Q1 ISO7741-Q1 ISO7742-Q1
ISO7740-Q1, ISO7741-Q1, ISO7742-Q1
www.ti.com
SLLSEU0 – NOVEMBER 2016
EXAMPLE STENCIL DESIGN
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SYMM
1
16
16X (.016 )
[0.41]
SYMM
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X
4214846/A 03/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
Copyright © 2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: ISO7740-Q1 ISO7741-Q1 ISO7742-Q1
33
ISO7740-Q1, ISO7741-Q1, ISO7742-Q1
SLLSEU0 – NOVEMBER 2016
www.ti.com
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A
16X
7.6
7.4
NOTE 4
B
2.65 MAX
B
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
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Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO7740-Q1 ISO7741-Q1 ISO7742-Q1
ISO7740-Q1, ISO7741-Q1, ISO7742-Q1
www.ti.com
SLLSEU0 – NOVEMBER 2016
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
16X (1.65)
SEE
DETAILS
1
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
Copyright © 2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: ISO7740-Q1 ISO7741-Q1 ISO7742-Q1
35
ISO7740-Q1, ISO7741-Q1, ISO7742-Q1
SLLSEU0 – NOVEMBER 2016
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.3)
(9.75)
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
36
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO7740-Q1 ISO7741-Q1 ISO7742-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Dec-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ISO7740FQDWQ1
PREVIEW
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7740FQ
ISO7740FQDWRQ1
PREVIEW
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7740FQ
ISO7740QDWQ1
PREVIEW
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7740Q
ISO7740QDWRQ1
PREVIEW
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7740Q
ISO7741FQDWQ1
PREVIEW
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7741FQ
ISO7741FQDWRQ1
PREVIEW
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7741FQ
ISO7741QDWQ1
PREVIEW
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7741Q
ISO7741QDWRQ1
PREVIEW
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7741Q
ISO7742FQDWQ1
PREVIEW
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7742FQ
ISO7742FQDWRQ1
PREVIEW
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7742FQ
ISO7742QDWQ1
PREVIEW
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7742Q
ISO7742QDWRQ1
PREVIEW
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7742Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
9-Dec-2016
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ISO7740-Q1, ISO7741-Q1, ISO7742-Q1 :
• Catalog: ISO7740, ISO7741, ISO7742
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Dec-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ISO7740FQDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7740QDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7741FQDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7741QDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7742FQDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7742QDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Dec-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO7740FQDWRQ1
SOIC
DW
16
2000
367.0
367.0
38.0
ISO7740QDWRQ1
SOIC
DW
16
2000
367.0
367.0
38.0
ISO7741FQDWRQ1
SOIC
DW
16
2000
367.0
367.0
38.0
ISO7741QDWRQ1
SOIC
DW
16
2000
367.0
367.0
38.0
ISO7742FQDWRQ1
SOIC
DW
16
2000
367.0
367.0
38.0
ISO7742QDWRQ1
SOIC
DW
16
2000
367.0
367.0
38.0
Pack Materials-Page 2
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