NXP MK10FN1M0VLQ12 K10 sub-family Datasheet

NXP Semiconductors
Data Sheet: Technical Data
K10 Sub-Family
Document Number K10P144M120SF3
Rev. 7, 02/2018
K10P144M120SF3
Supports the following:
MK10FX512VLQ12,
MK10FN1M0VLQ12,
MK10FX512VMD12,
MK10FN1M0VMD12
Key features
• Operating Characteristics
– Voltage range: 1.71 to 3.6 V
– Flash write voltage range: 1.71 to 3.6 V
– Temperature range (ambient): -40 to 105°C
• Performance
– Up to 120 MHz Arm® Cortex®-M4 core with DSP
instructions delivering 1.25 Dhrystone MIPS per
MHz
• Memories and memory interfaces
– Up to 1024 KB program flash memory on nonFlexMemory devices
– Up to 512 KB program flash memory on
FlexMemory devices
– Up to 512 KB FlexNVM on FlexMemory devices
– 16 KB FlexRAM on FlexMemory devices
– Up to 128 KB RAM
– Serial programming interface (EzPort)
– FlexBus external bus interface
– NAND flash controller interface
• Clocks
– 3 to 32 MHz crystal oscillator
– 32 kHz crystal oscillator
– Multi-purpose clock generator
• System peripherals
– Multiple low-power modes to provide power
optimization based on application requirements
– Memory protection unit with multi-master
protection
– 32-channel DMA controller, supporting up to 128
request sources
– External watchdog monitor
– Software watchdog
– Low-leakage wakeup unit
• Security and integrity modules
– Hardware CRC module to support fast cyclic
redundancy checks
– 128-bit unique identification (ID) number per chip
• Human-machine interface
– Low-power hardware touch sensor interface (TSI)
– General-purpose input/output
• Analog modules
– Four 16-bit SAR ADCs
– Programmable gain amplifier (PGA) (up to x64)
integrated into each ADC
– Two 12-bit DACs
– Four analog comparators (CMP) containing a 6-bit
DAC and programmable reference input
– Voltage reference
• Timers
– Programmable delay block
– Two 8-channel motor control/general purpose/PWM
timers
– Two 2-channel quadrature decoder/general purpose
timers
– Periodic interrupt timers
– 16-bit low-power timer
– Carrier modulator transmitter
– Real-time clock
• Communication interfaces
– Two Controller Area Network (CAN) modules
– Three SPI modules
– Two I2C modules
– Six UART modules
– Secure Digital Host Controller (SDHC)
– Two I2S modules
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Table of Contents
1 Ordering parts.......................................................................................3
6.1.1
Debug trace timing specifications..................................21
1.1 Determining valid orderable parts............................................... 3
6.1.2
JTAG electricals.............................................................22
2 Part identification................................................................................. 3
6.2 System modules........................................................................... 25
2.1 Description...................................................................................3
6.3 Clock modules............................................................................. 25
2.2 Format.......................................................................................... 3
6.3.1
MCG specifications........................................................25
2.3 Fields............................................................................................3
6.3.2
Oscillator electrical specifications................................. 27
2.4 Example....................................................................................... 4
6.3.3
32 kHz oscillator electrical characteristics.....................29
3 Terminology and guidelines.................................................................4
6.4 Memories and memory interfaces................................................30
3.1 Definitions................................................................................... 4
6.4.1
Flash (FTFE) electrical specifications........................... 30
3.2 Examples......................................................................................4
6.4.2
EzPort switching specifications..................................... 34
3.3 Typical-value conditions..............................................................5
6.4.3
NAND flash controller specifications............................35
3.4 Relationship between ratings and operating requirements.......... 5
6.4.4
Flexbus switching specifications....................................38
3.5 Guidelines for ratings and operating requirements......................6
6.5 Security and integrity modules.................................................... 41
4 Ratings..................................................................................................6
6.6 Analog..........................................................................................41
4.1 Thermal handling ratings............................................................. 6
6.6.1
ADC electrical specifications.........................................41
4.2 Moisture handling ratings............................................................ 7
6.6.2
CMP and 6-bit DAC electrical specifications................49
4.3 ESD handling ratings................................................................... 7
6.6.3
12-bit DAC electrical characteristics............................. 51
4.4 Voltage and current operating ratings..........................................7
6.6.4
Voltage reference electrical specifications.....................54
5 General................................................................................................. 7
6.7 Timers.......................................................................................... 55
5.1 AC electrical characteristics........................................................ 8
6.8 Communication interfaces........................................................... 55
5.2 Nonswitching electrical specifications........................................ 8
6.8.1
CAN switching specifications........................................55
5.2.1
Voltage and current operating requirements.................. 8
6.8.2
DSPI switching specifications (limited voltage range)..56
5.2.2
LVD and POR operating requirements.......................... 9
6.8.3
DSPI switching specifications (full voltage range)........57
5.2.3
Voltage and current operating behaviors....................... 10
6.8.4
Inter-Integrated Circuit Interface (I2C) timing.............. 59
5.2.4
Power mode transition operating behaviors...................12
6.8.5
UART switching specifications..................................... 60
5.2.5
Power consumption operating behaviors....................... 13
6.8.6
SDHC specifications...................................................... 60
5.2.6
EMC radiated emissions operating behaviors................16
6.8.7
I2S/SAI switching specifications................................... 61
5.2.7
Designing with radiated emissions in mind................... 17
5.2.8
Capacitance attributes.................................................... 17
5.3 Switching specifications.............................................................. 17
6.9 Human-machine interfaces (HMI)...............................................68
6.9.1
TSI electrical specifications........................................... 68
7 Dimensions...........................................................................................69
5.3.1
Device clock specifications............................................17
7.1 Obtaining package dimensions.................................................... 69
5.3.2
General switching specifications....................................18
8 Pinout................................................................................................... 69
5.4 Thermal specifications................................................................. 19
8.1 Pins with active pull control after reset....................................... 69
5.4.1
Thermal operating requirements.................................... 19
8.2 K10 Signal Multiplexing and Pin Assignments...........................70
5.4.2
Thermal attributes.......................................................... 20
8.3 K10 pinouts..................................................................................76
6 Peripheral operating requirements and behaviors................................ 21
9 Revision History...................................................................................78
6.1 Core modules............................................................................... 21
K10 Sub-Family, Rev. 7, 02/2018
2
NXP Semiconductors
Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to nxp.com and perform a part number search for the
following device numbers: PK10 and MK10
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q K## A M FFF T PP CC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
K##
Kinetis family
• K10
A
Key attribute
• F = Cortex-M4 w/ DSP and FPU
M
Flash memory type
• N = Program flash only
• X = Program flash and FlexMemory
FFF
Program flash memory size
• 512 = 512 KB
• 1M0 = 1 MB
Table continues on the next page...
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NXP Semiconductors
3
Terminology and guidelines
Field
Description
Values
T
Temperature range (°C)
• V = –40 to 105
• C = –40 to 85
PP
Package identifier
• LQ = 144 LQFP (20 mm x 20 mm)
• MD = 144 MAPBGA (13 mm x 13 mm)
CC
Maximum CPU frequency (MHz)
• 12 = 120 MHz
N
Packaging type
• R = Tape and reel
• (Blank) = Trays
2.4 Example
This is an example part number:
MK10FN1M0VLQ12
3 Terminology and guidelines
3.1 Definitions
Key terms are defined in the following table:
Term
Rating
Definition
A minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent
chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic
begins to exceed one of its operating ratings.
Operating requirement
A specified value or range of values for a technical characteristic that you must guarantee during
operation to avoid incorrect operation and possibly decreasing the useful life of the chip
Operating behavior
A specified value or range of values for a technical characteristic that are guaranteed during
operation if you meet the operating requirements and any other specified conditions
Typical value
A specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Is representative of that characteristic during operation when you meet the typical-value
conditions or other specified conditions
NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed.
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NXP Semiconductors
Terminology and guidelines
3.2 Examples
EX
A
M
PL
E
Operating rating:
EX
AM
PL
E
Operating requirement:
EX
AM
PL
E
Operating behavior that includes a typical value:
3.3 Typical-value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Value
Unit
TA
Ambient temperature
25
°C
VDD
Supply voltage
3.3
V
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5
Ratings
3.4 Relationship between ratings and operating requirements
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Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- Possible decreased life
- Possible incorrect operation
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- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
Expected permanent failure
–∞
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Fatal range
Expected permanent failure
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Expected permanent failure
–∞
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Handling (power off)
3.5 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
4 Ratings
4.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
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NXP Semiconductors
General
4.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
-2000
+2000
V
1
VCDM
Electrostatic discharge voltage, charged-device model
-500
+500
V
2
Latch-up current at ambient temperature of 105°C
-100
+100
mA
3
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
4.4 Voltage and current operating ratings
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage1
–0.3
3.8
V
IDD
Digital supply current
—
300
mA
VDIO
Digital input voltage (except RESET, EXTAL0/XTAL0, and
EXTAL1/XTAL1) 2
–0.3
5.5
V
VAIO
Analog3, RESET, EXTAL0/XTAL0, and EXTAL1/XTAL1 input
voltage
–0.3
VDD + 0.3
V
Maximum current single pin limit (applies to all digital pins)
–25
25
mA
VDD – 0.3
VDD + 0.3
V
–0.3
3.8
V
ID
VDDA
Analog supply voltage
VBAT
RTC battery supply voltage
1. It applies for all port pins.
2. It covers digital pins.
3. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
5 General
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7
General
5.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
Input Signal
High
Low
VIH
80%
50%
20%
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 1. Input signal measurement reference
All digital I/O switching characteristics assume:
1. output pins
• have CL=30pF loads,
• are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
• are configured for high drive strength (PORTx_PCRn[DSE]=1)
2. input pins
• have their passive filter disabled (PORTx_PCRn[PFE]=0)
5.2 Nonswitching electrical specifications
5.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
VDD
Supply voltage
1.71
3.6
V
VDDA
Analog supply voltage
1.71
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
–0.1
0.1
V
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
0.1
V
1.71
3.6
V
0.7 × VDD
—
V
VBAT
VIH
RTC battery supply voltage
Notes
Input high voltage (digital pins)
Table continues on the next page...
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General
Table 1. Voltage and current operating requirements (continued)
Symbol
Description
Min.
Max.
Unit
0.75 × VDD
—
V
• 2.7 V ≤ VDD ≤ 3.6 V
—
0.35 × VDD
V
• 1.7 V ≤ VDD ≤ 2.7 V
—
0.3 × VDD
V
VHYS
Input hysteresis (digital pins)
0.06 × VDD
—
V
IICDIO
Digital pin negative DC injection current —
single pin
-5
—
mA
• 2.7 V ≤ VDD ≤ 3.6 V
Notes
• 1.7 V ≤ VDD ≤ 2.7 V
VIL
Input low voltage (digital pins)
1
• VIN < VSS-0.3V
IICAIO
Analog2, EXTAL0/XTAL0, and EXTAL1/
XTAL1 pin DC injection current — single pin
• VIN < VSS-0.3V (Negative current
injection)
• VIN > VDD+0.3V (Positive current
injection)
IICcont
Contiguous pin DC injection current —
regional limit, includes sum of negative
injection currents or sum of positive injection
currents of 16 contiguous pins
• Negative current injection
3
mA
-5
—
—
+5
-25
—
—
+25
mA
• Positive current injection
VODPU
Open drain pullup voltage level
VDD
VDD
V
VRAM
VDD voltage required to retain RAM
1.2
—
V
VPOR_VBAT
—
V
VRFVBAT
VBAT voltage required to retain the VBAT
register file
4
1. All 5 V tolerant digital I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode
connection to VDD. If VIN is less than VDIO_MIN, a current limiting resistor is required. If VIN greater than VDIO_MIN
(=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads. The negative DC injection
current limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IICDIO|.
2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Additionally, EXTAL and
XTAL are analog pins.
3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VAIO_MIN or greater
than VAIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as
R=(VAIO_MIN-VIN)/|IICAIO|. The positive injection current limiting resistor is calculated as R=(VIN-VAIO_MAX)/|IICAIO|. Select the
larger of these two calculated resistances if the pin is exposed to positive and negative injection currents.
4. Open drain outputs must be pulled to VDD.
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9
General
5.2.2 LVD and POR operating requirements
Table 2. LVD and POR operating requirements
Symbol
Description
Min.
Typ.
Max.
Unit
VPOR
Falling VDD POR detect voltage
0.8
1.1
1.5
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
2.62
2.70
2.78
V
2.72
2.80
2.88
V
2.82
2.90
2.98
V
2.92
3.00
3.08
V
—
±80
—
mV
1.54
1.60
1.66
V
1.74
1.80
1.86
V
1.84
1.90
1.96
V
1.94
2.00
2.06
V
2.04
2.10
2.16
V
—
±60
—
mV
VLVW1H
VLVW2H
VLVW3H
VLVW4H
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
Low-voltage inhibit reset/recover hysteresis —
high range
VLVDL
Falling low-voltage detect threshold — low range
(LVDV=00)
VLVW2L
VLVW3L
VLVW4L
VHYSL
1
• Level 4 falling (LVWV=11)
VHYSH
VLVW1L
Notes
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
1
• Level 4 falling (LVWV=11)
Low-voltage inhibit reset/recover hysteresis —
low range
VBG
Bandgap voltage reference
0.97
1.00
1.03
V
tLPO
Internal low power oscillator period
900
1000
1100
μs
factory trimmed
1. Rising thresholds are falling threshold + hysteresis voltage
Table 3. VBAT power operating requirements
Symbol
Description
VPOR_VBAT Falling VBAT supply POR detect voltage
Min.
Typ.
Max.
Unit
0.8
1.1
1.5
V
Notes
5.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol
VOH
Description
Min.
Typ.
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -9mA
VDD – 0.5
—
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA
VDD – 0.5
—
Output high voltage — high drive strength
Max.
Unit
Notes
—
—
V
V
Table continues on the next page...
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NXP Semiconductors
General
Table 4. Voltage and current operating behaviors (continued)
Symbol
Description
Min.
Typ.
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA
VDD – 0.5
—
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA
VDD – 0.5
—
Output high current total for all ports
—
—
100
mA
Output high current total for fast digital ports
—
—
100
mA
0.5
V
0.5
V
0.5
V
0.5
V
Output high voltage — low drive strength
IOHT
IOHT_io60
VOL
IOLT_io60
IINA
Unit
Notes
—
Output low voltage — high drive strength
—
V
V
—
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 10 mA
—
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 5 mA
—
—
Output low voltage — low drive strength
IOLT
Max.
—
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2 mA
—
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 1 mA
—
—
Output low current total for all ports
—
—
100
mA
Output low current total for fast digital ports
—
—
100
mA
Input leakage current, analog pins and digital
pins configured as analog inputs
1, 2
• VSS ≤ VIN ≤ VDD
• All pins except EXTAL32, XTAL32,
EXTAL, XTAL
• EXTAL (PTA18) and XTAL (PTA19)
• EXTAL32, XTAL32
IIND
—
0.002
0.5
μA
—
0.004
1.5
μA
—
0.075
10
μA
Input leakage current, digital pins
2, 3
• VSS ≤ VIN ≤ VIL
• All digital pins
—
0.002
0.5
μA
—
0.002
0.5
μA
—
0.004
1
μA
• VIN = VDD
• All digital pins except PTD7
• PTD7
IIND
Input leakage current, digital pins
2, 3, 4
• VIL < VIN < VDD
IIND
• VDD = 3.6 V
—
18
26
μA
• VDD = 3.0 V
—
12
19
μA
• VDD = 2.5 V
—
8
13
μA
• VDD = 1.7 V
—
3
6
μA
Input leakage current, digital pins
• VDD < VIN < 5.5 V
ZIND
2, 3
—
1
50
μA
Input impedance examples, digital pins
2, 5
—
—
48
kΩ
Table continues on the next page...
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11
General
Table 4. Voltage and current operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
• VDD = 3.6 V
—
—
55
kΩ
• VDD = 3.0 V
—
—
57
kΩ
• VDD = 2.5 V
—
—
85
kΩ
Notes
• VDD = 1.7 V
RPU
Internal pullup resistors
20
—
50
kΩ
6
RPD
Internal pulldown resistors
20
—
50
kΩ
7
1.
2.
3.
4.
5.
Analog pins are defined as pins that do not have an associated general purpose I/O port function.
Digital pins have an associated GPIO port function and have 5V tolerant inputs, except EXTAL and XTAL.
Internal pull-up/pull-down resistors disabled.
Characterized, not tested in production.
Examples calculated using VIL relation, VDD, and max IIND: ZIND=VIL/IIND. This is the impedance needed to pull a high
signal to a level below VIL due to leakage when VIL < VIN < VDD. These examples assume signal source low = 0 V. See
Figure 2.
6. Measured at VDD supply voltage = VDD min and Vinput = VSS
7. Measured at VDD supply voltage = VDD min and Vinput = VDD
Figure 2. 5 V Tolerant Input IIND Parameter
5.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
•
•
•
•
•
CPU and system clocks = 100 MHz
Bus clock = 50 MHz
FlexBus clock = 50 MHz
Flash clock = 25 MHz
MCG mode: FEI
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General
Table 5. Power mode transition operating behaviors
Symbol
tPOR
Description
Min.
Max.
After a POR event, amount of time from the point VDD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
Unit
Notes
1
• VDD slew rate ≥ 5.7 kV/s
• VDD slew rate < 5.7 kV/s
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
• LLS → RUN
• VLPS → RUN
• STOP → RUN
μs
—
300
—
1.7 V / (VDD
slew rate)
—
160
μs
—
114
μs
—
114
μs
—
5.0
μs
—
5
μs
—
4.8
μs
1. Normal boot (FTFE_FOPT[LPBOOT]=1)
5.2.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol
IDDA
IDD_RUN
IDD_RUN
Description
Analog supply current
Min.
Typ.
Max.
Unit
Notes
—
—
See note
mA
1
Run mode current — all peripheral clocks
disabled, code executing from flash
2
• @ 1.8V
—
49.28
73.85
mA
• @ 3.0V
—
49.08
73.93
mA
Run mode current — all peripheral clocks
enabled, code executing from flash
3
• @ 1.8V
—
74.43
99.97
mA
• @ 3.0V
—
74.28
100.41
mA
IDD_WAIT
Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
—
34.67
58.5
mA
2
IDD_WAIT
Wait mode reduced frequency current at 3.0 V —
all peripheral clocks disabled
—
18.03
41.91
mA
4
IDD_STOP
Stop mode current at 3.0 V
—
1.25
1.62
mA
—
2.93
4.39
mA
• @ –40 to 25°C
Table continues on the next page...
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General
Table 6. Power consumption operating behaviors (continued)
Symbol
Description
• @ 70°C
Min.
Typ.
Max.
Unit
—
7.08
10.74
mA
Notes
• @ 105°C
IDD_VLPR
Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
—
1.03
4.48
mA
5
IDD_VLPR
Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
—
1.58
4.96
mA
5
IDD_VLPW
Very-low-power wait mode current at 3.0 V
—
0.64
4.29
mA
5
IDD_VLPS
Very-low-power stop mode current at 3.0 V
• @ –40 to 25°C
—
0.22
0.38
mA
• @ 70°C
—
0.78
1.33
mA
• @ 105°C
—
2.18
3.56
mA
• @ –40 to 25°C
—
0.22
0.37
mA
• @ 70°C
—
0.78
1.33
mA
• @ 105°C
—
2.16
3.52
mA
• @ –40 to 25°C
—
4.09
5.58
μA
• @ 70°C
—
20.98
28.93
μA
• @ 105°C
—
84.95
111.15
μA
• @ –40 to 25°C
—
2.68
4.22
μA
• @ 70°C
—
8.8
10.74
μA
• @ 105°C
—
37.28
43.61
μA
• @ –40 to 25°C
—
2.46
4.02
μA
• @ 70°C
—
7.04
8.99
μA
• @ 105°C
—
30.68
37.04
μA
IDD_LLS
IDD_VLLS3
IDD_VLLS2
IDD_VLLS1
IDD_VBAT
Low leakage stop mode current at 3.0 V
Very low-leakage stop mode 3 current at 3.0 V
Very low-leakage stop mode 2 current at 3.0 V
Very low-leakage stop mode 1 current at 3.0 V
Average current when CPU is not accessing
RTC registers at 3.0 V
6
• @ –40 to 25°C
—
0.89
1.10
μA
• @ 70°C
—
1.28
1.85
μA
• @ 105°C
—
3.10
4.30
μA
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 120 MHz core and system clock, 60 MHz bus, 30 MHz FlexBus clock, and 20 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks disabled.
3. 120 MHz core and system clock, 60 MHz bus, 30 MHz FlexBus clock, and 20 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks enabled, but peripherals are not in active operation.
4. 25 MHz core and system clock, 25 MHz bus clock, and 12.5 MHz FlexBus and flash clock. MCG configured for FEI mode.
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General
5. 4 MHz core, system, 2 MHz FlexBus, and 2 MHz bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All
peripheral clocks disabled.
6. Includes 32kHz oscillator current and RTC operation.
5.2.5.1
Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at greater
than 50 MHz frequencies. MCG in PEE mode at greater than 100 MHz frequencies.
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFE
Figure 3. Run mode supply current vs. core frequency
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15
General
Figure 4. VLPR mode supply current vs. core frequency
5.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors for 256MAPBGA
Symbol
Description
Frequency
band (MHz)
Typ.
Unit
Notes
1, 2, 3
VRE1
Radiated emissions voltage, band 1
0.15–50
21
dBμV
VRE2
Radiated emissions voltage, band 2
50–150
24
dBμV
VRE3
Radiated emissions voltage, band 3
150–500
29
dBμV
VRE4
Radiated emissions voltage, band 4
500–1000
28
dBμV
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of
Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported
emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the
measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 72 MHz, fBUS = 72 MHz
3. Determined according to IEC Standard JESD78, IC Latch-Up Test
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NXP Semiconductors
General
5.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.nxp.com.
2. Perform a keyword search for “EMC design.”
5.2.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
Input capacitance: fast digital pins
—
9
pF
CIN_D_io60
5.3 Switching specifications
5.3.1 Device clock specifications
Table 9. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
Normal run mode
fSYS
System and core clock
—
120
MHz
fBUS
Bus clock
—
60
MHz
FlexBus clock
—
50
MHz
fFLASH
Flash clock
—
25
MHz
fLPTMR
LPTMR clock
—
25
MHz
FB_CLK
VLPR mode1
fSYS
System and core clock
—
4
MHz
fBUS
Bus clock
—
4
MHz
FlexBus clock
—
4
MHz
fFLASH
Flash clock
—
0.5
MHz
fLPTMR
LPTMR clock
—
4
MHz
FB_CLK
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
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17
General
5.3.2 General switching specifications
These general purpose specifications apply to all pins configured for:
• GPIO signaling
• Other peripheral module signaling not explicitly stated elsewhere
Table 10. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100
—
ns
3
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
16
—
ns
3
External reset pulse width (digital glitch filter disabled)
100
—
ns
3
2
—
Bus clock
cycles
Mode select (EZP_CS) hold time after reset
deassertion
Port rise and fall time (high drive strength)
4
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
—
14
ns
• 2.7 ≤ VDD ≤ 3.6V
—
8
ns
• 1.71 ≤ VDD ≤ 2.7V
—
36
ns
• 2.7 ≤ VDD ≤ 3.6V
—
24
ns
• Slew enabled
Port rise and fall time (low drive strength)
5
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
—
14
ns
• 2.7 ≤ VDD ≤ 3.6V
—
8
ns
• 1.71 ≤ VDD ≤ 2.7V
—
36
ns
• 2.7 ≤ VDD ≤ 3.6V
—
24
ns
• Slew enabled
tio50
Port rise and fall time (high drive strength)
6
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
—
7
ns
—
• 2.7 ≤ VDD ≤ 3.6V
—
3
ns
—
• 1.71 ≤ VDD ≤ 2.7V
—
28
ns
—
• 2.7 ≤ VDD ≤ 3.6V
—
14
ns
—
• Slew enabled
tio50
Port rise and fall time (low drive strength)
-1
• Slew disabled
Table continues on the next page...
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General
Table 10. General switching specifications (continued)
Symbol
Description
Min.
Max.
Unit
Notes
• 1.71 ≤ VDD ≤ 2.7V
—
18
ns
—
• 2.7 ≤ VDD ≤ 3.6V
—
9
ns
—
• 1.71 ≤ VDD ≤ 2.7V
—
48
ns
—
• 2.7 ≤ VDD ≤ 3.6V
—
24
ns
—
• Slew enabled
tio60
Port rise and fall time (high drive strength)
6
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
—
6
ns
—
• 2.7 ≤ VDD ≤ 3.6V
—
3
ns
—
• 1.71 ≤ VDD ≤ 2.7V
—
28
ns
—
• 2.7 ≤ VDD ≤ 3.6V
—
14
ns
—
• Slew enabled
tio60
Port rise and fall time (low drive strength)
-1
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
—
18
ns
—
• 2.7 ≤ VDD ≤ 3.6V
—
6
ns
—
• 1.71 ≤ VDD ≤ 2.7V
—
48
ns
—
• 2.7 ≤ VDD ≤ 3.6V
—
24
ns
—
• Slew enabled
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be
recognized in that case.
2. The greater synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and
VLLSx modes.
4. 75 pF load
5. 15 pF load
6. 25 pF load
5.4 Thermal specifications
5.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol
TJ
TA
Description
Min.
Max.
Unit
Die junction temperature
–40
125
°C
–40
105
°C
Ambient
temperature1
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General
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
determine TJ is:
TJ = TA + RθJA x chip power dissipation
5.4.2 Thermal attributes
Board type
Symbol
Description
144 LQFP
144 MAPBGA
Unit
Notes
Single-layer
(1s)
RθJA
Thermal
45
resistance,
junction to
ambient (natural
convection)
50
°C/W
1, 2
Four-layer
(2s2p)
RθJA
Thermal
36
resistance,
junction to
ambient (natural
convection)
30
°C/W
1,2, 3
Single-layer
(1s)
RθJMA
Thermal
36
resistance,
junction to
ambient (200 ft./
min. air speed)
41
°C/W
1,3
Four-layer
(2s2p)
RθJMA
Thermal
30
resistance,
junction to
ambient (200 ft./
min. air speed)
27
°C/W
1,3
—
RθJB
Thermal
resistance,
junction to
board
24
17
°C/W
4
—
RθJC
Thermal
resistance,
junction to case
9
10
°C/W
5
—
ΨJT
Thermal
2
characterization
parameter,
junction to
package top
outside center
(natural
convection)
2
°C/W
6
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions
—Natural Convection (Still Air) with the single layer board horizontal. Board meets JESD51-9 specification.
3. Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental Conditions
—Forced Convection (Moving Air) with the board horizontal.
4. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions
—Junction-to-Board.
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NXP Semiconductors
Peripheral operating requirements and behaviors
5. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material between
the top of the package and the cold plate.
6. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions
—Natural Convection (Still Air).
6 Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 Debug trace timing specifications
Table 12. Debug trace operating behaviors
Symbol
Description
Min.
Max.
Unit
Tcyc
Clock period
Frequency dependent
MHz
Twl
Low pulse width
2
—
ns
Twh
High pulse width
2
—
ns
Tr
Clock and data rise time
—
3
ns
Tf
Clock and data fall time
—
3
ns
Ts
Data setup
3
—
ns
Th
Data hold
2
—
ns
TRACECLK
Tr
Tf
Twh
Twl
Tcyc
Figure 5. TRACE_CLKOUT specifications
TRACE_CLKOUT
Ts
Th
Ts
Th
TRACE_D[3:0]
Figure 6. Trace data specifications
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Peripheral operating requirements and behaviors
6.1.2 JTAG electricals
Table 13. JTAG limited voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
TCLK frequency of operation
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
25
• Serial Wire Debug
0
50
1/J1
—
ns
• Boundary Scan
50
—
ns
• JTAG and CJTAG
20
—
ns
• Serial Wire Debug
10
—
ns
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
2.4
—
ns
J7
TCLK low to boundary scan output data valid
—
25
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1
—
ns
J11
TCLK low to TDO data valid
—
17
ns
J12
TCLK low to TDO high-Z
—
17
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
Table 14. JTAG full voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
TCLK frequency of operation
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
20
• Serial Wire Debug
0
40
1/J1
—
ns
50
—
ns
25
—
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
• Boundary Scan
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 14. JTAG full voltage range electricals (continued)
Symbol
Description
• JTAG and CJTAG
Min.
Max.
Unit
12.5
—
ns
• Serial Wire Debug
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
2.4
—
ns
J7
TCLK low to boundary scan output data valid
—
25
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1.4
—
ns
J11
TCLK low to TDO data valid
—
22.1
ns
J12
TCLK low to TDO high-Z
—
22.1
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
J2
J3
J3
TCLK (input)
J4
J4
Figure 7. Test clock input timing
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Peripheral operating requirements and behaviors
TCLK
J5
Data inputs
J6
Input data valid
J7
Data outputs
Output data valid
J8
Data outputs
J7
Data outputs
Output data valid
Figure 8. Boundary scan (JTAG) timing
TCLK
J9
TDI/TMS
J10
Input data valid
J11
TDO
Output data valid
J12
TDO
J11
TDO
Output data valid
Figure 9. Test Access Port timing
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NXP Semiconductors
Peripheral operating requirements and behaviors
TCLK
J14
J13
TRST
Figure 10. TRST timing
6.2 System modules
There are no specifications necessary for the device's system modules.
6.3 Clock modules
6.3.1 MCG specifications
Table 15. MCG specifications
Symbol
Description
Min.
Typ.
Max.
Unit
—
32.768
—
kHz
31.25
—
39.0625
kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
—
± 0.3
± 0.6
%fdco
1
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM only
—
± 0.2
± 0.5
%fdco
1
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
—
± 4.5
—
%fdco
1
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
4
—
MHz
fintf_t
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
3
—
5
MHz
fints_ft
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
fints_t
Internal reference frequency (slow clock) — user
trimmed
Δfdco_t
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
31.25
—
39.0625
kHz
Notes
FLL
ffll_ref
FLL reference frequency range
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 15. MCG specifications (continued)
Symbol
fdco
Description
DCO output
frequency range
Low range (DRS=00)
Min.
Typ.
Max.
Unit
Notes
20
20.97
25
MHz
2, 3
40
41.94
50
MHz
60
62.91
75
MHz
80
83.89
100
MHz
—
23.99
—
MHz
—
47.97
—
MHz
—
71.99
—
MHz
—
95.98
—
MHz
—
180
—
—
150
—
—
—
1
ms
8
—
16
MHz
640 × ffll_ref
Mid range (DRS=01)
1280 × ffll_ref
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX32 DCO output
frequency
Low range (DRS=00)
4, 5
732 × ffll_ref
Mid range (DRS=01)
1464 × ffll_ref
Mid-high range (DRS=10)
2197 × ffll_ref
High range (DRS=11)
2929 × ffll_ref
Jcyc_fll
FLL period jitter
• fVCO = 48 MHz
• fVCO = 98 MHz
tfll_acquire
FLL target frequency acquisition time
ps
6
PLL0,1
fpll_ref
PLL reference frequency range
fvcoclk_2x
VCO output frequency
fvcoclk
PLL output frequency
fvcoclk_90
Ipll
PLL0 operating current
• VCO @ 184 MHz (fosc_hi_1 = 32 MHz, fpll_ref
= 8 MHz, VDIV multiplier = 23)
Ipll
PLL0 operating current
• VCO @ 360 MHz (fosc_hi_1 = 32 MHz, fpll_ref
= 8 MHz, VDIV multiplier = 45)
Ipll
PLL1 operating current
• VCO @ 184 MHz (fosc_hi_1 = 32 MHz, fpll_ref
= 8 MHz, VDIV multiplier = 23)
Ipll
PLL1 operating current
• VCO @ 360 MHz (fosc_hi_1 = 32 MHz, fpll_ref
= 8 MHz, VDIV multiplier = 45)
Lock detector detection time
Jcyc_pll
PLL period jitter (RMS)
—
90
PLL quadrature output frequency
tpll_lock
—
180
—
90
360
180
180
MHz
MHz
MHz
—
2.8
—
mA
—
4.7
—
mA
—
2.3
—
mA
—
3.6
—
mA
—
—
100 × 10-6
+ 1075(1/
fpll_ref)
s
7
7
7
8
9
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Table 15. MCG specifications (continued)
Symbol
Jacc_pll
Description
Min.
Typ.
Max.
Unit
• fvco = 180 MHz
—
100
—
ps
• fvco = 360 MHz
—
75
—
ps
PLL accumulated jitter over 1µs (RMS)
Notes
10
• fvco = 180 MHz
—
600
—
ps
• fvco = 360 MHz
—
300
—
ps
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
(Δfdco_t) over voltage and temperature should be considered.
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
7. Excludes any oscillator currents that are also consuming power while PLL is in operation.
8. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
9. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
10. Accumulated jitter depends on VCO frequency and VDIV.
6.3.2 Oscillator electrical specifications
6.3.2.1
Oscillator DC electrical specifications
Table 16. Oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
IDDOSC
Supply current — low-power mode (HGO=0)
1
• 32 kHz
—
500
—
nA
• 4 MHz
—
200
—
μA
• 8 MHz (RANGE=01)
—
300
—
μA
• 16 MHz
—
950
—
μA
• 24 MHz
—
1.2
—
mA
• 32 MHz
—
1.5
—
mA
Supply current — high-gain mode (HGO=1)
• 32 kHz
Notes
1
—
25
—
μA
—
400
—
μA
Table continues on the next page...
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27
Peripheral operating requirements and behaviors
Table 16. Oscillator DC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
• 4 MHz
—
500
—
μA
• 8 MHz (RANGE=01)
—
2.5
—
mA
• 16 MHz
—
3
—
mA
• 24 MHz
—
4
—
mA
Notes
• 32 MHz
Cx
EXTAL load capacitance
—
—
—
2, 3
Cy
XTAL load capacitance
—
—
—
2, 3
RF
Feedback resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
10
—
MΩ
Feedback resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
—
1
—
MΩ
Series resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
Series resistor — low-frequency, high-gain mode
(HGO=1)
—
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
—
0
—
kΩ
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
RS
2, 4
Series resistor — high-frequency, high-gain
mode (HGO=1)
5
Vpp
1.
2.
3.
4.
5.
VDD=3.3 V, Temperature =25 °C
See crystal or resonator manufacturer's recommendation
Cx and Cy can be provided by using either integrated capacitors or external components.
When low-power mode is selected, RF is integrated and must not be attached externally.
The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other device.
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Peripheral operating requirements and behaviors
6.3.2.2
Symbol
Oscillator frequency specifications
Table 17. Oscillator frequency specifications
Description
Min.
Typ.
Max.
Unit
fosc_lo
Oscillator crystal or resonator frequency — lowfrequency mode (MCG_C2[RANGE]=00)
32
—
40
kHz
fosc_hi_1
Oscillator crystal or resonator frequency — highfrequency mode (low range)
(MCG_C2[RANGE]=01)
3
—
8
MHz
fosc_hi_2
Oscillator crystal or resonator frequency — high
frequency mode (high range)
(MCG_C2[RANGE]=1x)
8
—
32
MHz
fec_extal
Input clock frequency (external clock mode)
—
—
60
MHz
tdc_extal
Input clock duty cycle (external clock mode)
40
50
60
%
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
—
1000
—
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
500
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
—
0.6
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
tcst
Notes
1
2, 3
4, 5
1. Frequencies less than 8 MHz are not in the PLL range.
2. Other frequency limits may apply when external clock is being used as a reference for the FLL
3. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
4. Proper PC board layout procedures must be followed to achieve specifications.
5. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register
being set.
NOTE
The 32 kHz oscillator works in low power mode by default and
cannot be moved into high power/gain mode.
6.3.3 32 kHz oscillator electrical characteristics
6.3.3.1
32 kHz oscillator DC electrical specifications
Table 18. 32kHz oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VBAT
Supply voltage
1.71
—
3.6
V
Internal feedback resistor
—
100
—
MΩ
Cpara
Parasitical capacitance of EXTAL32 and XTAL32
—
5
7
pF
Vpp1
Peak-to-peak amplitude of oscillation
—
0.6
—
V
RF
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Peripheral operating requirements and behaviors
1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
6.3.3.2
Symbol
fosc_lo
tstart
32 kHz oscillator frequency specifications
Table 19. 32 kHz oscillator frequency specifications
Description
Min.
Typ.
Max.
Unit
Oscillator crystal
—
32.768
—
kHz
Crystal start-up time
—
1000
—
ms
1
700
—
VBAT
mV
2, 3
vec_extal32 Externally provided input clock amplitude
Notes
1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The
oscillator remains enabled and XTAL32 must be left unconnected.
3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied
clock must be within the range of VSS to VBAT.
6.4 Memories and memory interfaces
6.4.1 Flash (FTFE) electrical specifications
This section describes the electrical characteristics of the FTFE module.
6.4.1.1
Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 20. NVM program/erase timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
thvpgm8
thversscr
Notes
Program Phrase high-voltage time
—
7.5
18
μs
Erase Flash Sector high-voltage time
—
13
113
ms
1
thversblk128k Erase Flash Block high-voltage time for 128 KB
—
104
1808
ms
1
thversblk256k Erase Flash Block high-voltage time for 256 KB
—
208
3616
ms
1
Unit
Notes
1. Maximum time based on expectations at cycling end-of-life.
6.4.1.2
Symbol
Flash timing specifications — commands
Table 21. Flash command timing specifications
Description
Min.
Typ.
Max.
Read 1s Block execution time
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 21. Flash command timing specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
trd1blk128k
• 128 KB data flash
—
—
0.5
ms
trd1blk256k
• 256 KB program flash
—
—
1.0
ms
Notes
256 KB data flash
trd1sec4k
Read 1s Section execution time (4 KB flash)
—
—
100
μs
1
tpgmchk
Program Check execution time
—
—
80
μs
1
trdrsrc
Read Resource execution time
—
—
40
μs
1
tpgm8
Program Phrase execution time
—
70
150
μs
Erase Flash Block execution time
2
tersblk128k
• 128 KB data flash
—
110
925
ms
tersblk256k
• 256 KB program flash
—
220
1850
ms
Erase Flash Sector execution time
—
15
115
ms
Program Section execution time (4KB flash)
—
20
—
ms
256 KB data flash
tersscr
tpgmsec4k
2
Read 1s All Blocks execution time
trd1allx
• FlexNVM devices
—
—
3.4
ms
trd1alln
• Program flash only devices
—
—
3.4
ms
Read Once execution time
—
—
30
μs
Program Once execution time
—
70
—
μs
tersall
Erase All Blocks execution time
—
650
5600
ms
2
tvfykey
Verify Backdoor Access Key execution time
—
—
30
μs
1
trdonce
tpgmonce
1
Swap Control execution time
tswapx01
• control code 0x01
—
200
—
μs
tswapx02
• control code 0x02
—
70
150
μs
tswapx04
• control code 0x04
—
70
150
μs
tswapx08
• control code 0x08
—
—
30
μs
Program Partition for EEPROM execution time
tpgmpart64k
• 64 KB EEPROM backup
—
235
—
ms
tpgmpart256k
• 256 KB EEPROM backup
—
240
—
ms
• Control Code 0xFF
—
205
—
μs
tsetram64k
• 64 KB EEPROM backup
—
1.6
2.5
ms
tsetram128k
• 128 KB EEPROM backup
—
2.7
3.8
ms
tsetram256k
• 256 KB EEPROM backup
—
4.8
6.2
ms
—
140
225
μs
—
400
1700
μs
Set FlexRAM Function execution time:
tsetramff
t eewr8bers
Byte-write to erased FlexRAM location execution
time
3
Byte-write to FlexRAM execution time:
teewr8b64k
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 21. Flash command timing specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
teewr8b128k
• 64 KB EEPROM backup
—
450
1800
μs
teewr8b256k
• 128 KB EEPROM backup
—
525
2000
μs
—
140
225
μs
Notes
• 256 KB EEPROM backup
t eewr16bers 16-bit write to erased FlexRAM location
execution time
16-bit write to FlexRAM execution time:
teewr16b64k
• 64 KB EEPROM backup
—
400
1700
μs
teewr16b128k
• 128 KB EEPROM backup
—
450
1800
μs
teewr16b256k
• 256 KB EEPROM backup
—
525
2000
μs
—
180
275
μs
teewr32bers 32-bit write to erased FlexRAM location
execution time
32-bit write to FlexRAM execution time:
teewr32b64k
• 64 KB EEPROM backup
—
475
1850
μs
teewr32b128k
• 128 KB EEPROM backup
—
525
2000
μs
teewr32b256k
• 256 KB EEPROM backup
—
600
2200
μs
1. Assumes 25MHz or greater flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.
6.4.1.3
Flash high voltage current behaviors
Table 22. Flash high voltage current behaviors
Symbol
Description
IDD_PGM
IDD_ERS
6.4.1.4
Symbol
Min.
Typ.
Max.
Unit
Average current adder during high voltage flash
programming operation
—
3.5
7.5
mA
Average current adder during high voltage flash
erase operation
—
1.5
4.0
mA
Reliability specifications
Table 23. NVM reliability specifications
Description
Min.
Typ.1
Max.
Unit
Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles
5
50
—
years
tnvmretp1k
Data retention after up to 1 K cycles
20
100
—
years
nnvmcycp
Cycling endurance
10 K
50 K
—
cycles
5
50
—
years
2
Data Flash
tnvmretd10k Data retention after up to 10 K cycles
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 23. NVM reliability specifications (continued)
Symbol
Description
tnvmretd1k
Data retention after up to 1 K cycles
nnvmcycd
Cycling endurance
Min.
Typ.1
Max.
Unit
20
100
—
years
10 K
50 K
—
cycles
Notes
2
FlexRAM as EEPROM
tnvmretee100 Data retention up to 100% of write endurance
5
50
—
years
tnvmretee10 Data retention up to 10% of write endurance
20
100
—
years
20 K
50 K
—
cycles
nnvmcycee
Cycling endurance for EEPROM backup
Write endurance
2
3
nnvmwree16
• EEPROM backup to FlexRAM ratio = 16
70 K
175 K
—
writes
nnvmwree128
• EEPROM backup to FlexRAM ratio = 128
630 K
1.6 M
—
writes
nnvmwree512
• EEPROM backup to FlexRAM ratio = 512
2.5 M
6.4 M
—
writes
nnvmwree2k
• EEPROM backup to FlexRAM ratio = 2,048
10 M
25 M
—
writes
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering
Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.
3. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the cycling
endurance of the FlexNVM and the allocated EEPROM backup per subsystem. Minimum and typical values assume all 16bit or 32-bit writes to FlexRAM; all 8-bit writes result in 50% less endurance.
6.4.1.5
Write endurance to FlexRAM for EEPROM
When the FlexNVM partition code is not set to full data flash, the EEPROM data set size
can be set to any of several non-zero values.
The bytes not assigned to data flash via the FlexNVM partition code are used by the
FTFE to obtain an effective endurance increase for the EEPROM data. The built-in
EEPROM record management system raises the number of program/erase cycles that can
be attained prior to device wear-out by cycling the EEPROM data through a larger
EEPROM NVM storage space.
While different partitions of the FlexNVM are available, the intention is that a single
choice for the FlexNVM partition code and EEPROM data set size is used throughout the
entire lifetime of a given application. The EEPROM endurance equation and graph
shown below assume that only one configuration is ever used.
Writes_subsystem =
EEPROM – 2 × EEESPLIT × EEESIZE
EEESPLIT × EEESIZE
× Write_efficiency × n nvmcycee
where
• Writes_subsystem — minimum number of writes to each FlexRAM location for
subsystem (each subsystem can have different endurance)
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Peripheral operating requirements and behaviors
• EEPROM — allocated FlexNVM for each EEPROM subsystem based on DEPART;
entered with the Program Partition command
• EEESPLIT — FlexRAM split factor for subsystem; entered with the Program
Partition command
• EEESIZE — allocated FlexRAM based on DEPART; entered with the Program
Partition command
• Write_efficiency —
• 0.25 for 8-bit writes to FlexRAM
• 0.50 for 16-bit or 32-bit writes to FlexRAM
• nnvmcycee — EEPROM-backup cycling endurance
Figure 11. EEPROM backup writes to FlexRAM
6.4.2 EzPort switching specifications
Table 24. EzPort switching specifications
Num
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 24. EzPort switching specifications (continued)
Num
Description
Min.
Max.
Unit
EP1
EZP_CK frequency of operation (all commands except
READ)
—
fSYS/2
MHz
EP1a
EZP_CK frequency of operation (READ command)
—
fSYS/8
MHz
EP2
EZP_CS negation to next EZP_CS assertion
2 x tEZP_CK
—
ns
EP3
EZP_CS input valid to EZP_CK high (setup)
5
—
ns
EP4
EZP_CK high to EZP_CS input invalid (hold)
5
—
ns
EP5
EZP_D input valid to EZP_CK high (setup)
2
—
ns
EP6
EZP_CK high to EZP_D input invalid (hold)
5
—
ns
EP7
EZP_CK low to EZP_Q output valid
—
16
ns
EP8
EZP_CK low to EZP_Q output invalid (hold)
0
—
ns
EP9
EZP_CS negation to EZP_Q tri-state
—
12
ns
EZP_CK
EP3
EP2
EP4
EZP_CS
EP9
EP7
EP8
EZP_Q (output)
EP5
EP6
EZP_D (input)
Figure 12. EzPort Timing Diagram
6.4.3 NAND flash controller specifications
The NAND flash controller (NFC) implements the interface to standard NAND flash
memory devices. This section describes the timing parameters of the NFC.
In the following table:
• TH is the flash clock high time and
• TL is flash clock low time,
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35
Peripheral operating requirements and behaviors
which are defined as:
T NFC = T L + T H =
T input clock
SCALER
The SCALER value is derived from the fractional divider specified in the SIM's
CLKDIV4 register:
SCALER =
SIM_CLKDIV4[NFCFRAC] + 1
SIM_CLKDIV4[NFCDIV] + 1
In case the reciprocal of SCALER is an integer, the duty cycle of NFC clock is 50%,
means TH = TL. In case the reciprocal of SCALER is not an integer:
T L = (1 + SCALER / 2) x
T H = (1 – SCALER / 2) x
T NFC
2
T NFC
2
For example, if SCALER is 0.2, then TH = TL = TNFC/2.
TNFC
TH
TL
However, if SCALER is 0.667, then TL = 2/3 x TNFC and TH = 1/3 x TNFC.
TNFC
TH
TL
NOTE
The reciprocal of SCALER must be a multiple of 0.5. For
example, 1, 1.5, 2, 2.5, etc.
Table 25. NFC specifications
Num
Description
Min.
Max.
Unit
tCLS
NFC_CLE setup time
2TH + TL – 1
—
ns
tCLH
NFC_CLE hold time
TH + TL – 1
—
ns
tCS
NFC_CEn setup time
2TH + TL – 1
—
ns
tCH
NFC_CEn hold time
TH + TL
—
ns
tWP
NFC_WP pulse width
TL – 1
—
ns
tALS
NFC_ALE setup time
2TH + TL
—
ns
Table continues on the next page...
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NXP Semiconductors
Peripheral operating requirements and behaviors
Table 25. NFC specifications (continued)
Num
Description
Min.
Max.
Unit
tALH
NFC_ALE hold time
TH + TL
—
ns
tDS
Data setup time
TL – 1
—
ns
tDH
Data hold time
TH – 1
—
ns
tWC
Write cycle time
TH + TL – 1
—
ns
tWH
NFC_WE hold time
TH – 1
—
ns
tRR
Ready to NFC_RE low
4TH + 3TL + 90
—
ns
tRP
NFC_RE pulse width
TL + 1
—
ns
tRC
Read cycle time
TL + TH – 1
—
ns
tREH
NFC_RE high hold time
TH – 1
—
ns
tIS
Data input setup time
11
—
ns
NFC_CLE
tCLS
tCLH
NFC_CEn
tCS
tWP
tCH
NFC_WE
tDS
tDH
NFC_IOn
Figure 13. Command latch cycle timing
NFC_ALE
tALS
tALH
NFC_CEn
tCS
tWP
tCH
NFC_WE
tDS
NFC_IOn
tDH
address
Figure 14. Address latch cycle timing
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Peripheral operating requirements and behaviors
tCS
tCH
tWC
NFC_CEn
tWP
tWH
tDS
tDH
NFC_WE
NFC_IOn
data
data
data
Figure 15. Write data latch cycle timing
tCH
tRC
NFC_CEn
tREH
tRP
NFC_RE
tIS
NFC_IOn
data
data
data
tRR
NFC_RB
Figure 16. Read data latch cycle timing in Slow mode
tCH
tRC
NFC_CEn
tRP
tREH
NFC_RE
tIS
NFC_IOn
data
data
data
tRR
NFC_RB
Figure 17. Read data latch cycle timing in Fast mode and EDO mode
6.4.4 Flexbus switching specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
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NXP Semiconductors
Peripheral operating requirements and behaviors
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be
derived from these values.
Table 26. Flexbus limited voltage range switching specifications
Num
Description
Min.
Max.
Unit
Notes
Operating voltage
2.7
3.6
V
Frequency of operation
—
FB_CLK
MHz
FB1
Clock period
20
—
ns
FB2
Address, data, and control output valid
—
11.5
ns
1
FB3
Address, data, and control output hold
0.5
—
ns
1
FB4
Data and FB_TA input setup
8.5
—
ns
2
FB5
Data and FB_TA input hold
0.5
—
ns
2
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
Table 27. Flexbus full voltage range switching specifications
Num
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
Frequency of operation
Notes
—
FB_CLK
MHz
1/FB_CLK
—
ns
Address, data, and control output valid
—
13.5
ns
1
FB3
Address, data, and control output hold
0
—
ns
1
FB4
Data and FB_TA input setup
13.7
—
ns
2
FB5
Data and FB_TA input hold
0.5
—
ns
2
FB1
Clock period
FB2
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
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Peripheral operating requirements and behaviors
Read Timing Parameters
S0
S1
S2
S3
S0
FB1
FB_CLK
FB5
FB_A[Y]
Address
FB4
FB2
FB_D[X]
FB3
Address
Data
FB_RW
FB_TS
FB_ALE
AA=1
FB_CSn
AA=0
FB_OEn
electricals_read.svg
FB4
FB_BEn
FB5
AA=1
FB_TA
AA=0
FB_TSIZ[1:0]
TSIZ
S0
S1
S2
S3
S0
Figure 18. FlexBus read timing diagram
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NXP Semiconductors
Peripheral operating requirements and behaviors
Write Timing Parameters
FB1
FB_CLK
FB2
FB3
FB_A[Y]
FB_D[X]
Address
Address
Data
FB_RW
FB_TS
FB_ALE
AA=1
FB_CSn
AA=0
FB_OEn
FB_BEn
FB5
AA=1
FB_TA
FB_TSIZ[1:0]
AA=0
electricals_write.svg
FB4
TSIZ
Figure 19. FlexBus write timing diagram
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
6.6 Analog
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Peripheral operating requirements and behaviors
6.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 28 and Table 29 are achievable on the
differential pins ADCx_DP0, ADCx_DM0.
The ADCx_DP2 and ADCx_DM2 ADC inputs are connected to the PGA outputs and are
not direct device pins. Accuracy specifications for these pins are defined in Table 30 and
Table 31.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
6.6.1.1
16-bit ADC operating conditions
Table 28. 16-bit ADC operating conditions
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
VDDA
Supply voltage
Absolute
1.71
—
3.6
V
ΔVDDA
Supply voltage
Delta to VDD (VDD – VDDA)
-100
0
+100
mV
2
ΔVSSA
Ground voltage
Delta to VSS (VSS – VSSA)
-100
0
+100
mV
2
VREFH
ADC reference
voltage high
1.13
VDDA
VDDA
V
VREFL
ADC reference
voltage low
VSSA
VSSA
VSSA
V
VADIN
Input voltage
• 16-bit differential mode
VREFL
—
31/32 ×
VREFH
V
• All other modes
VREFL
—
• 16-bit mode
—
8
10
• 8-bit / 10-bit / 12-bit
modes
—
4
5
—
2
5
CADIN
RADIN
RAS
Input capacitance
Input series
resistance
Notes
VREFH
pF
kΩ
Analog source
resistance
(external)
13-bit / 12-bit modes
fADCK < 4 MHz
—
—
5
kΩ
fADCK
ADC conversion
clock frequency
≤ 13-bit mode
1.0
—
18.0
MHz
4
fADCK
ADC conversion
clock frequency
16-bit mode
2.0
—
12.0
MHz
4
Crate
ADC conversion
rate
≤ 13-bit modes
No ADC hardware averaging
3
5
20.000
—
818.330
kS/s
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion
rate
16-bit mode
5
No ADC hardware averaging
37.037
—
461.467
kS/s
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Peripheral operating requirements and behaviors
Table 28. 16-bit ADC operating conditions
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS
time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
ZAS
RAS
ADC SAR
ENGINE
RADIN
VADIN
CAS
VAS
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN
CADIN
Figure 20. ADC input impedance equivalency diagram
6.6.1.2
16-bit ADC electrical characteristics
Table 29. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
0.215
—
1.7
mA
3
• ADLPC = 1, ADHSC = 0
1.2
2.4
3.9
MHz
• ADLPC = 1, ADHSC = 1
2.4
4.0
6.1
MHz
tADACK = 1/
fADACK
IDDA_ADC Supply current
fADACK
ADC asynchronous
clock source
Table continues on the next page...
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Table 29. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Sample Time
TUE
DNL
INL
EFS
EQ
ENOB
Conditions1
Min.
Typ.2
Max.
Unit
• ADLPC = 0, ADHSC = 0
3.0
5.2
7.3
MHz
• ADLPC = 0, ADHSC = 1
4.4
6.2
9.5
MHz
LSB4
5
LSB4
5
LSB4
5
LSB4
VADIN = VDDA5
See Reference Manual chapter for sample times
Total unadjusted
error
• 12-bit modes
—
±4
±6.8
• <12-bit modes
—
±1.4
±2.1
Differential nonlinearity
• 12-bit modes
—
±0.7
–1.1 to
+1.9
• <12-bit modes
—
±0.2
• 12-bit modes
—
±1.0
• <12-bit modes
—
±0.5
• 12-bit modes
—
–4
–5.4
• <12-bit modes
—
–1.4
–1.8
• 16-bit modes
—
–1 to 0
—
• ≤13-bit modes
—
—
±0.5
Integral non-linearity
Full-scale error
Quantization error
Effective number of
bits
Notes
–0.3 to
0.5
–2.7 to
+1.9
–0.7 to
+0.5
LSB4
16-bit differential mode
6
• Avg = 32
12.8
14.5
• Avg = 4
11.9
13.8
—
—
bits
bits
16-bit single-ended mode
• Avg = 32
• Avg = 4
SINAD
THD
Signal-to-noise plus
distortion
See ENOB
Total harmonic
distortion
16-bit differential mode
12.2
13.9
11.4
13.1
—
—
6.02 × ENOB + 1.76
• Avg = 32
bits
bits
dB
dB
—
-94
7
—
dB
16-bit single-ended mode
• Avg = 32
SFDR
Spurious free
dynamic range
—
-85
82
95
16-bit differential mode
• Avg = 32
16-bit single-ended mode
78
—
—
dB
—
dB
7
90
• Avg = 32
EIL
Input leakage error
IIn × RAS
mV
IIn = leakage
current
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 29. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Conditions1
Symbol Description
Typ.2
Min.
Max.
Unit
Notes
(refer to the
MCU's voltage
and current
operating
ratings)
Temp sensor slope
Across the full temperature
range of the device
VTEMP25 Temp sensor voltage 25 °C
1.55
1.62
1.69
mV/°C
8
706
716
726
mV
8
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1
MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
8. ADC conversion clock < 3 MHz
Typical ADC 16-bit Differential ENOB vs ADC Clock
100Hz, 90% FS Sine Input
15.00
14.70
14.40
14.10
ENOB
13.80
13.50
13.20
12.90
12.60
Hardware Averaging Disabled
Averaging of 4 samples
Averaging of 8 samples
Averaging of 32 samples
12.30
12.00
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 21. Typical ENOB vs. ADC_CLK for 16-bit differential mode
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Peripheral operating requirements and behaviors
Typical ADC 16-bit Single-Ended ENOB vs ADC Clock
100Hz, 90% FS Sine Input
14.00
13.75
13.50
13.25
13.00
ENOB
12.75
12.50
12.25
12.00
11.75
11.50
11.25
11.00
Averaging of 4 samples
Averaging of 32 samples
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 22. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
6.6.1.3
16-bit ADC with PGA operating conditions
Table 30. 16-bit ADC with PGA operating conditions
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
VDDA
Supply voltage
Absolute
1.71
—
3.6
V
VREFPGA
PGA ref voltage
VADIN
VCM
RPGAD
VREF_OU VREF_OU VREF_OU
T
T
T
V
Notes
2, 3
Input voltage
VSSA
—
VDDA
V
Input Common
Mode range
VSSA
—
VDDA
V
Gain = 1, 2, 4, 8
—
128
—
kΩ
IN+ to IN-4
Gain = 16, 32
—
64
—
Gain = 64
—
32
—
Differential input
impedance
RAS
Analog source
resistance
—
100
—
Ω
5
TS
ADC sampling
time
1.25
—
—
µs
6
18.484
—
450
Ksps
7
37.037
—
250
Ksps
8
Crate
ADC conversion
rate
≤ 13 bit modes
No ADC hardware
averaging
Continuous conversions
enabled
Peripheral clock = 50
MHz
16 bit modes
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Peripheral operating requirements and behaviors
Table 30. 16-bit ADC with PGA operating conditions
Symbol
Description
Conditions
Typ.1
Min.
Max.
Unit
Notes
No ADC hardware
averaging
Continuous conversions
enabled
Peripheral clock = 50
MHz
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 6 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. ADC must be configured to use the internal voltage reference (VREF_OUT)
3. PGA reference is internally connected to the VREF_OUT pin. If the user wishes to drive VREF_OUT with a voltage other
than the output of the VREF module, the VREF module must be disabled.
4. For single ended configurations the input impedance of the driven input is RPGAD/2
5. The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
time should be allowed for Fin=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at
8 MHz ADC clock.
7. ADC clock = 18 MHz, ADLSMP = 1, ADLST = 00, ADHSC = 1
8. ADC clock = 12 MHz, ADLSMP = 1, ADLST = 01, ADHSC = 1
6.6.1.4
16-bit ADC with PGA characteristics
Table 31. 16-bit ADC with PGA characteristics
Symbol
Description
Conditions
IDDA_PGA
Supply current
Low power
(ADC_PGA[PGALPb]=0)
IDC_PGA
Input DC current
G
BW
PSRR
Gain4
Input signal
bandwidth
Power supply
rejection ratio
Min.
Typ.1
Max.
Unit
Notes
—
420
644
μA
2
A
3
Gain =1, VREFPGA=1.2V,
VCM=0.5V
—
1.54
—
μA
Gain =64, VREFPGA=1.2V,
VCM=0.1V
—
0.57
—
μA
• PGAG=0
0.95
1
1.05
• PGAG=1
1.9
2
2.1
• PGAG=2
3.8
4
4.2
• PGAG=3
7.6
8
8.4
• PGAG=4
15.2
16
16.6
• PGAG=5
30.0
31.6
33.2
• PGAG=6
58.8
63.3
67.8
—
—
4
kHz
—
—
40
kHz
—
-84
—
dB
• 16-bit modes
• < 16-bit modes
Gain=1
RAS < 100Ω
VDDA= 3V
±100mV,
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 31. 16-bit ADC with PGA characteristics (continued)
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
fVDDA= 50Hz,
60Hz
CMRR
VOFS
Common mode
rejection ratio
• Gain=1
—
-84
—
dB
• Gain=64
—
-85
—
dB
Input offset
voltage
• Chopping disabled
(ADC_PGA[PGACHPb]
=1)
• Chopping enabled
(ADC_PGA[PGACHPb]
=0)
—
2.4
—
mV
—
0.2
—
mV
—
—
10
µs
• Gain=1
• Gain=64
—
6
10
ppm/°C
—
31
42
ppm/°C
• Gain=1
• Gain=64
—
0.07
0.21
%/V
—
0.14
0.31
%/V
TGSW
Gain switching
settling time
dG/dT
Gain drift over full
temperature range
dG/dVDDA Gain drift over
supply voltage
EIL
Input leakage
error
All modes
IIn × RAS
mV
VCM=
500mVpp,
fVCM= 50Hz,
100Hz
Output offset =
VOFS*(Gain+1)
5
VDDA from 1.71
to 3.6V
IIn = leakage
current
(refer to the
MCU's voltage
and current
operating
ratings)
VPP,DIFF
Maximum
differential input
signal swing
SNR
Signal-to-noise
ratio
• Gain=1
80
90
• Gain=64
52
Total harmonic
distortion
• Gain=1
THD
SFDR
ENOB
V
6
—
dB
66
—
dB
16-bit
differential
mode,
Average=32
85
100
—
dB
• Gain=64
49
95
—
dB
Spurious free
dynamic range
• Gain=1
85
105
—
dB
• Gain=64
53
88
—
dB
Effective number
of bits
• Gain=1, Average=4
11.6
13.4
—
bits
• Gain=1, Average=8
8.0
13.6
—
bits
• Gain=64, Average=4
7.2
9.6
—
bits
• Gain=64, Average=8
6.3
9.6
—
bits
12.8
14.5
—
bits
where VX = VREFPGA × 0.583
16-bit
differential
mode,
Average=32,
fin=100Hz
16-bit
differential
mode,
Average=32,
fin=100Hz
16-bit
differential
mode,fin=100Hz
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 31. 16-bit ADC with PGA characteristics (continued)
Symbol
Description
Min.
Typ.1
Max.
Unit
• Gain=1, Average=32
11.0
14.3
—
bits
• Gain=2, Average=32
7.9
13.8
—
bits
• Gain=4, Average=32
7.3
13.1
—
bits
• Gain=8, Average=32
6.8
12.5
—
bits
• Gain=16, Average=32
6.8
11.5
—
bits
• Gain=32, Average=32
7.5
10.6
—
bits
Conditions
Notes
• Gain=64, Average=32
SINAD
Signal-to-noise
plus distortion
ratio
See ENOB
6.02 × ENOB + 1.76
dB
1. Typical values assume VDDA =3.0V, Temp=25°C, fADCK=6MHz unless otherwise stated.
2. This current is a PGA module adder, in addition to ADC conversion currents.
3. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong
function of input common mode voltage (VCM) and the PGA gain.
4. Gain = 2PGAG
5. After changing the PGA gain setting, a minimum of 2 ADC+PGA conversions should be ignored.
6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the
PGA reference voltage and gain setting.
6.6.2 CMP and 6-bit DAC electrical specifications
Table 32. Comparator and 6-bit DAC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDHS
Supply current, High-speed mode (EN=1, PMODE=1)
—
—
200
μA
IDDLS
Supply current, low-speed mode (EN=1, PMODE=0)
—
—
20
μA
VAIN
Analog input voltage
VSS – 0.3
—
VDD
V
VAIO
Analog input offset voltage
—
—
20
mV
• CR0[HYSTCTR] = 00
—
5
—
mV
• CR0[HYSTCTR] = 01
—
10
—
mV
• CR0[HYSTCTR] = 10
—
20
—
mV
• CR0[HYSTCTR] = 11
—
30
—
mV
VH
Analog comparator
hysteresis1
VCMPOh
Output high
VDD – 0.5
—
—
V
VCMPOl
Output low
—
—
0.5
V
tDHS
Propagation delay, high-speed mode (EN=1, PMODE=1)
20
50
200
ns
tDLS
Propagation delay, low-speed mode (EN=1, PMODE=0)
80
250
600
ns
—
—
40
μs
—
7
—
μA
Analog comparator initialization
IDAC6b
delay2
6-bit DAC current adder (enabled)
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 32. Comparator and 6-bit DAC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
INL
6-bit DAC integral non-linearity
–0.5
—
0.5
LSB3
DNL
6-bit DAC differential non-linearity
–0.3
—
0.3
LSB
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
0.08
0.07
CMP Hystereris (V)
0.06
HYSTCTR
Setting
0.05
00
0.04
01
10
11
0.03
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 23. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
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Peripheral operating requirements and behaviors
0.18
0.16
0.14
CMP Hysteresis (V)
0.12
HYSTCTR
Setting
0.1
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
Vin level (V)
2.2
2.5
2.8
3.1
Figure 24. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
6.6.3 12-bit DAC electrical characteristics
6.6.3.1
Symbol
12-bit DAC operating requirements
Table 33. 12-bit DAC operating requirements
Desciption
Min.
Max.
Unit
VDDA
Supply voltage
1.71
3.6
V
VDACR
Reference voltage
1.13
3.6
V
1
2
CL
Output load capacitance
—
100
pF
IL
Output load current
—
1
mA
Notes
1. The DAC reference can be selected to be VDDA or VREF_OUT.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
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Peripheral operating requirements and behaviors
6.6.3.2
Symbol
12-bit DAC operating behaviors
Table 34. 12-bit DAC operating behaviors
Description
IDDA_DACL Supply current — low-power mode
Min.
Typ.
Max.
Unit
—
—
150
μA
—
—
700
μA
Notes
P
IDDA_DACH Supply current — high-speed mode
P
tDACLP
Full-scale settling time (0x080 to 0xF7F) —
low-power mode
—
100
200
μs
1
tDACHP
Full-scale settling time (0x080 to 0xF7F) —
high-power mode
—
15
30
μs
1
—
0.7
1
μs
1
—
—
100
mV
tCCDACLP Code-to-code settling time (0xBF8 to 0xC08)
— low-power mode and high-speed mode
Vdacoutl
DAC output voltage range low — high-speed
mode, no load, DAC set to 0x000
Vdacouth
DAC output voltage range high — highspeed mode, no load, DAC set to 0xFFF
VDACR
−100
—
VDACR
mV
INL
Integral non-linearity error — high speed
mode
—
—
±8
LSB
2
DNL
Differential non-linearity error — VDACR > 2
V
—
—
±1
LSB
3
DNL
Differential non-linearity error — VDACR =
VREF_OUT
—
—
±1
LSB
4
—
±0.4
±0.8
%FSR
5
Gain error
—
±0.1
±0.6
%FSR
5
Power supply rejection ratio, VDDA ≥ 2.4 V
60
—
90
dB
TCO
Temperature coefficient offset voltage
—
3.7
—
μV/C
TGE
Temperature coefficient gain error
—
0.000421
—
%FSR/C
Rop
Output resistance (load = 3 kΩ)
—
—
250
Ω
SR
Slew rate -80h→ F7Fh→ 80h
VOFFSET Offset error
EG
PSRR
1.
2.
3.
4.
5.
6.
V/μs
• High power (SPHP)
1.2
1.7
—
• Low power (SPLP)
0.05
0.12
—
—
—
-80
CT
Channel to channel cross talk
BW
3dB bandwidth
6
dB
kHz
• High power (SPHP)
550
—
—
• Low power (SPLP)
40
—
—
Settling within ±1 LSB
The INL is measured for 0 + 100 mV to VDACR −100 mV
The DNL is measured for 0 + 100 mV to VDACR −100 mV
The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to
0x800, temperature range is across the full range of the device
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Peripheral operating requirements and behaviors
8
6
4
DAC12 INL (LSB)
2
0
-2
-4
-6
-8
0
500
1000
1500
2000
2500
3000
3500
4000
Digital Code
Figure 25. Typical INL error vs. digital code
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Peripheral operating requirements and behaviors
1.499
DAC12 Mid Level Code Voltage
1.4985
1.498
1.4975
1.497
1.4965
1.496
25
-40
55
85
105
125
Temperature °C
Figure 26. Offset at half scale vs. temperature
6.6.4 Voltage reference electrical specifications
Table 35. VREF full-range operating requirements
Symbol
Description
Min.
Max.
Unit
VDDA
Supply voltage
1.71
3.6
V
TA
Temperature
CL
Output load capacitance
Operating temperature
range of the device
°C
100
nF
Notes
1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range of
the device.
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Table 36. VREF full-range operating behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
nominal VDDA and temperature=25C
1.1915
1.195
1.1977
V
1
Vout
Voltage reference output — factory trim
1.1584
—
1.2376
V
1
Vout
Voltage reference output — user trim
1.193
—
1.197
V
1
Vstep
Voltage reference trim step
—
0.5
—
mV
1
Vtdrift
Temperature drift (Vmax -Vmin across the full
temperature range)
—
—
80
mV
1
Ibg
Bandgap only current
—
—
80
µA
1
Ihp
High-power buffer current
—
—
1
mA
1
mV
1, 2
ΔVLOAD
Load regulation
• current = + 1.0 mA
—
2
—
• current = - 1.0 mA
—
5
—
Tstup
Buffer startup time
—
—
100
µs
Vvdrift
Voltage drift (Vmax -Vmin across the full voltage
range)
—
2
—
mV
1
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 37. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
TA
Temperature
0
50
°C
Notes
Table 38. VREF limited-range operating behaviors
Symbol
Vout
Description
Voltage reference output with factory trim
Min.
Max.
Unit
1.173
1.225
V
Notes
6.7 Timers
See General switching specifications.
6.8 Communication interfaces
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Peripheral operating requirements and behaviors
6.8.1 CAN switching specifications
See General switching specifications.
6.8.2 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface DSPI provides a synchronous serial bus with master
and slave operations. Many of the transfer attributes are programmable. The tables below
provide DSPI timing characteristics for classic DSPI timing modes. Refer to the DSPI
chapter of the Reference Manual for information on the modified transfer formats used
for communicating with slower peripheral devices.
Table 39. Master mode DSPI timing (limited voltage range)
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Frequency of operation
—
30
MHz
2 x tBUS
—
ns
Notes
DS1
DSPI_SCK output cycle time
DS2
DSPI_SCK output high/low time
(tSCK/2) − 2
(tSCK/2) + 2
ns
DS3
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2) −
2
—
ns
1
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
2
—
ns
2
DS5
DSPI_SCK to DSPI_SOUT valid
—
8.5
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
−2
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
15
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
1. The delay is programmable in DSPIx_CTARn[PSSCK] and DSPIx_CTARn[CSSCK].
2. The delay is programmable in DSPIx_CTARn[PASC] and DSPIx_CTARn[ASC].
SPI_PCSn
DS3
SPI_SCK
(CPOL=0)
SPI_SIN
SPI_SOUT
DS7
DS1
DS2
DS4
DS8
First data
First data
Data
Last data
DS5
DS6
Data
Last data
Figure 27. DSPI classic DSPI timing — master mode
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Table 40. Slave mode DSPI timing (limited voltage range)
Num
Description
Min.
Max.
Unit
2.7
3.6
V
15
MHz
4 x tBUS
—
ns
(tSCK/2) − 2
(tSCK/2) + 2
ns
Operating voltage
Frequency of operation
DS9
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
DS11
DSPI_SCK to DSPI_SOUT valid
—
10
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2
—
ns
DS14
DSPI_SCK to DSPI_SIN input hold
7
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
14
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
14
ns
SPI_SS
DS10
DS9
SPI_SCK
DS15
(POL=0)
SPI_SOUT
DS12
First data
DS13
SPI_SIN
DS16
DS11
Last data
Data
DS14
First data
Data
Last data
Figure 28. DSPI classic DSPI timing — slave mode
6.8.3 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface DSPI provides a synchronous serial bus with master
and slave operations. Many of the transfer attributes are programmable. The tables below
provides DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI
chapter of the Reference Manual for information on the modified transfer formats used
for communicating with slower peripheral devices.
Table 41. Master mode DSPItiming (full voltage range)
Num
Description
Operating voltage
Frequency of operation
DS1
DSPI_SCK output cycle time
Min.
Max.
Unit
Notes
1.71
—
3.6
V
1
15
MHz
4 x tBUS
—
ns
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 41. Master mode DSPItiming (full voltage range) (continued)
Num
Description
Min.
Max.
Unit
Notes
DS2
DSPI_SCK output high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS3
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2) −
4
—
ns
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
3
DS5
DSPI_SCK to DSPI_SOUT valid
—
10
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
-4.5
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
20.5
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
SPI_PCSn
DS3
SPI_SCK
SPI_SIN
DS4
DS8
DS7
(CPOL=0)
DS1
DS2
First data
SPI_SOUT
Data
Last data
DS5
First data
DS6
Data
Last data
Figure 29. DSPI classic SPI timing — master mode
Table 42. Slave mode DSPI timing (full voltage range)
Num
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
1.71
3.6
V
—
7.5
MHz
8 x tBUS
—
ns
DS9
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS11
DSPI_SCK to DSPI_SOUT valid
—
20
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2
—
ns
DS14
DSPI_SCK to DSPI_SIN input hold
7
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
19
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
19
ns
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SPI_SS
DS10
DS9
SPI_SCK
DS15
(POL=0)
SPI_SOUT
DS12
First data
DS13
SPI_SIN
DS16
DS11
Last data
Data
DS14
First data
Data
Last data
Figure 30. DSPI classic SPI timing — slave mode
6.8.4 Inter-Integrated Circuit Interface (I2C) timing
Table 43. I 2C timing
Characteristic
Symbol
Standard Mode
Fast Mode
Unit
Minimum
Maximum
Minimum
Maximum
SCL Clock Frequency
fSCL
0
100
0
400 1
kHz
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD; STA
4
—
0.6
—
µs
LOW period of the SCL clock
tLOW
4.7
—
1.25
—
µs
HIGH period of the SCL clock
tHIGH
4
—
0.6
—
µs
Set-up time for a repeated START
condition
tSU; STA
4.7
—
0.6
—
µs
Data hold time for I2C bus devices
tHD; DAT
02
3.453
04
0.92
µs
tSU; DAT
2505
—
1003,6
Data set-up time
—
ns
7
Rise time of SDA and SCL signals
tr
—
1000
20 +0.1Cb
300
ns
Fall time of SDA and SCL signals
tf
—
300
20 +0.1Cb6
300
ns
Set-up time for STOP condition
tSU; STO
4
—
0.6
—
µs
Bus free time between STOP and
START condition
tBUF
4.7
—
1.3
—
µs
Pulse width of spikes that must be
suppressed by the input filter
tSP
N/A
N/A
0
50
ns
1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only be achieved when using a pin
configured for high drive across the full voltage range and when using the a pin configured for low drive with VDD ≥ 2.7 V.
2. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
4. Input signal Slew = 10 ns and Output Load = 50 pF
5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
6. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a
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Peripheral operating requirements and behaviors
device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU; DAT
= 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.
7. Cb = total capacitance of the one bus line in pF.
SDA
tf
tLOW
tSU; DAT
tr
tf
tHD; STA
tSP
tr
tBUF
SCL
S
HD; STA
tHD; DAT
tHIGH
tSU; STA
tSU; STO
SR
P
S
Figure 31. Timing definition for fast and standard mode devices on the I2C bus
6.8.5 UART switching specifications
See General switching specifications.
6.8.6 SDHC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
Table 44. SDHC switching specifications over a limited operating voltage range
Num
Symbol
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Card input clock
SD1
fpp
Clock frequency (low speed)
0
400
kHz
fpp
Clock frequency (SD\SDIO full speed\high speed)
0
25\40
MHz
fpp
Clock frequency (MMC full speed\high speed)
0
25\50
MHz
fOD
Clock frequency (identification mode)
0
400
kHz
SD2
tWL
Clock low time
7
—
ns
SD3
tWH
Clock high time
7
—
ns
SD4
tTLH
Clock rise time
—
3
ns
SD5
tTHL
Clock fall time
—
3
ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6
tOD
SDHC output delay (output valid)
-5
6.5
ns
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD7
tISU
SDHC input setup time
5
—
ns
SD8
tIH
SDHC input hold time
0
—
ns
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Table 45. SDHC switching specifications over the full operating voltage range
Num
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
Card input clock
SD1
fpp
Clock frequency (low speed)
0
400
kHz
fpp
Clock frequency (SD\SDIO full speed\high speed)
0
25\40
MHz
fpp
Clock frequency (MMC full speed\high speed)
0
25\50
MHz
fOD
Clock frequency (identification mode)
0
400
kHz
tWL
Clock low time
7
—
ns
SD3
tWH
Clock high time
7
—
ns
SD4
tTLH
Clock rise time
—
3
ns
SD5
tTHL
Clock fall time
—
3
ns
SD2
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6
tOD
SDHC output delay (output valid)
-5
6.5
ns
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD7
tISU
SDHC input setup time
5
—
ns
SD8
tIH
SDHC input hold time
1.3
—
ns
SD3
SD2
SD1
SDHC_CLK
SD6
Output SDHC_CMD
Output SDHC_DAT[3:0]
SD7
SD8
Input SDHC_CMD
Input SDHC_DAT[3:0]
Figure 32. SDHC timing
6.8.7 I2S/SAI switching specifications
This section provides the AC timing for the I2S/SAI module in master mode (clocks are
driven) and slave mode (clocks are input). All timing is given for noninverted serial clock
polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP]
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is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the
frame sync (FS) signal shown in the following figures.
6.8.7.1
Normal Run, Wait and Stop mode performance over a limited
operating voltage range
This section provides the operating performance over a limited operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 46. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (limited voltage
range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
S1
I2S_MCLK cycle time
40
—
ns
S2
I2S_MCLK pulse width high/low
45%
55%
MCLK period
S3
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
80
—
ns
S4
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
15
ns
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
I2S_TX_BCLK to I2S_TXD valid
—
15
ns
S8
I2S_TX_BCLK to I2S_TXD invalid
0
—
ns
S9
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
15
—
ns
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
0
—
ns
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S1
S2
S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S4
S6
S5
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 33. I2S/SAI timing — master modes
Table 47. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (limited voltage
range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
S11
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
80
—
ns
S12
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
4.5
—
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2
—
ns
S15
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
21
—
15
• Multiple SAI Synchronous mode
• All other modes
ns
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
0
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
4.5
—
ns
S18
I2S_RXD hold after I2S_RX_BCLK
2
—
ns
—
25
ns
S19
I2S_TX_FS input assertion to I2S_TXD output
valid1
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
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S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
I2S_TX_FS/
I2S_RX_FS (input)
S19
S14
S15
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 34. I2S/SAI timing — slave modes
6.8.7.2
Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 48. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (full voltage
range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S1
I2S_MCLK cycle time
40
—
ns
S2
I2S_MCLK pulse width high/low
45%
55%
MCLK period
S3
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
80
—
ns
S4
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
15
ns
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
-1.0
—
ns
S7
I2S_TX_BCLK to I2S_TXD valid
—
15
ns
S8
I2S_TX_BCLK to I2S_TXD invalid
0
—
ns
S9
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
20.5
—
ns
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
0
—
ns
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S1
S2
S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S4
S6
S5
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 35. I2S/SAI timing — master modes
Table 49. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (full voltage
range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S11
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
80
—
ns
S12
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
5.8
—
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2
—
ns
S15
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
24
—
20.6
• Multiple SAI Synchronous mode
• All other modes
ns
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
0
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
5.8
—
ns
S18
I2S_RXD hold after I2S_RX_BCLK
2
—
ns
—
25
ns
S19
I2S_TX_FS input assertion to I2S_TXD output
valid1
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
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S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
I2S_TX_FS/
I2S_RX_FS (input)
S19
S14
S15
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 36. I2S/SAI timing — slave modes
6.8.7.3
VLPR, VLPW, and VLPS mode performance over the full operating
voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
Table 50. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S1
I2S_MCLK cycle time
62.5
—
ns
S2
I2S_MCLK pulse width high/low
45%
55%
MCLK period
S3
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
250
—
ns
S4
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
45
ns
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
I2S_TX_BCLK to I2S_TXD valid
—
45
ns
S8
I2S_TX_BCLK to I2S_TXD invalid
-1.6
—
ns
S9
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
45
—
ns
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
0
—
ns
K10 Sub-Family, Rev. 7, 02/2018
66
NXP Semiconductors
Peripheral operating requirements and behaviors
S1
S2
S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S4
S6
S5
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 37. I2S/SAI timing — master modes
Table 51. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S11
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
250
—
ns
S12
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
30
—
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
3
—
ns
S15
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
63
ns
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
0
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
30
—
ns
S18
I2S_RXD hold after I2S_RX_BCLK
2
—
ns
—
72
ns
S19
I2S_TX_FS input assertion to I2S_TXD output
valid1
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
K10 Sub-Family, Rev. 7, 02/2018
NXP Semiconductors
67
Peripheral operating requirements and behaviors
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
I2S_TX_FS/
I2S_RX_FS (input)
S19
S14
S15
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 38. I2S/SAI timing — slave modes
6.9 Human-machine interfaces (HMI)
6.9.1 TSI electrical specifications
Table 52. TSI electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDDTSI
Operating voltage
1.71
—
3.6
V
Target electrode capacitance range
1
20
500
pF
1
fREFmax
Reference oscillator frequency
—
8
15
MHz
2, 3
fELEmax
Electrode oscillator frequency
—
1
1.8
MHz
2, 4
Internal reference capacitor
—
1
—
pF
Oscillator delta voltage
—
600
—
mV
2, 5
μA
2, 6
μA
2, 7
CELE
CREF
VDELTA
IREF
IELE
Reference oscillator current source base current
• 2 μA setting (REFCHRG = 0)
• 32 μA setting (REFCHRG = 15)
Electrode oscillator current source base current
• 2 μA setting (EXTCHRG = 0)
• 32 μA setting (EXTCHRG = 15)
—
2
3
—
36
50
—
2
3
—
36
50
Notes
Pres5
Electrode capacitance measurement precision
—
8.3333
38400
fF/count
8
Pres20
Electrode capacitance measurement precision
—
8.3333
38400
fF/count
9
Pres100
Electrode capacitance measurement precision
—
8.3333
38400
fF/count
10
0.008
1.46
—
fF/count
11
—
—
16
bits
Response time @ 20 pF
8
15
25
μs
Current added in run mode
—
55
—
μA
Low power mode current adder
—
1.3
2.5
μA
MaxSens Maximum sensitivity
Res
TCon20
ITSI_RUN
ITSI_LP
Resolution
12
13
K10 Sub-Family, Rev. 7, 02/2018
68
NXP Semiconductors
Dimensions
1. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed.
2. Fixed external capacitance of 20 pF.
3. REFCHRG = 2, EXTCHRG=0.
4. REFCHRG = 0, EXTCHRG = 10.
5. VDD = 3.0 V.
6. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current.
7. The programmable current source value is generated by multiplying the SCANC[EXTCHRG] value and the base current.
8. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16.
9. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16.
10. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16.
11. Sensitivity defines the minimum capacitance change when a single count from the TSI module changes. Sensitivity
depends on the configuration used. The documented values are provided as examples calculated for a specific
configuration of operating conditions using the following equation: (Cref * Iext)/( Iref * PS * NSCN)
The typical value is calculated with the following configuration:
Iext = 6 μA (EXTCHRG = 2), PS = 128, NSCN = 2, Iref = 16 μA (REFCHRG = 7), Cref = 1.0 pF
The minimum value is calculated with the following configuration:
Iext = 2 μA (EXTCHRG = 0), PS = 128, NSCN = 32, Iref = 32 μA (REFCHRG = 15), Cref = 0.5 pF
The highest possible sensitivity is the minimum value because it represents the smallest possible capacitance that can be
measured by a single count.
12. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1
electrode, EXTCHRG = 7.
13. REFCHRG=0, EXTCHRG=4, PS=7, NSCN=0F, LPSCNITV=F, LPO is selected (1 kHz), and fixed external capacitance of
20 pF. Data is captured with an average of 7 periods window.
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to nxp.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package
Then use this document number
144-pin LQFP
98ASS23177W
144-pin MAPBGA
98ASA00222D
8 Pinout
8.1 Pins with active pull control after reset
The following pins are actively pulled up or down after reset:
K10 Sub-Family, Rev. 7, 02/2018
NXP Semiconductors
69
Pinout
Table 53. Pins with active pull control after reset
Pin
Active pull direction after reset
PTA0
pulldown
PTA1
pullup
PTA3
pullup
PTA4
pullup
RESET_b
pullup
8.2 K10 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
144 144
LQFP MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
—
L5
RTC_
WAKEUP_B
RTC_
WAKEUP_B
RTC_
WAKEUP_B
—
M5
NC
NC
NC
—
A10
NC
NC
NC
—
B10
NC
NC
NC
—
C10 NC
NC
NC
1
D3
PTE0
ADC1_SE4a
ADC1_SE4a
PTE0
SPI1_PCS1
UART1_TX
SDHC0_D1
I2C1_SDA
RTC_
CLKOUT
2
D2
PTE1/
LLWU_P0
ADC1_SE5a
ADC1_SE5a
PTE1/
LLWU_P0
SPI1_SOUT
UART1_RX
SDHC0_D0
I2C1_SCL
SPI1_SIN
3
D1
PTE2/
LLWU_P1
ADC1_SE6a
ADC1_SE6a
PTE2/
LLWU_P1
SPI1_SCK
UART1_
CTS_b
SDHC0_
DCLK
4
E4
PTE3
ADC1_SE7a
ADC1_SE7a
PTE3
SPI1_SIN
UART1_
RTS_b
SDHC0_CMD
5
E5
VDD
VDD
VDD
6
F6
VSS
VSS
VSS
7
E3
PTE4/
LLWU_P2
DISABLED
PTE4/
LLWU_P2
SPI1_PCS0
UART3_TX
SDHC0_D3
8
E2
PTE5
DISABLED
PTE5
SPI1_PCS2
UART3_RX
SDHC0_D2
FTM3_CH0
9
E1
PTE6
DISABLED
PTE6
SPI1_PCS3
UART3_
CTS_b
I2S0_MCLK
FTM3_CH1
10
F4
PTE7
DISABLED
PTE7
UART3_
RTS_b
I2S0_RXD0
FTM3_CH2
11
F3
PTE8
ADC2_SE16
ADC2_SE16
PTE8
I2S0_RXD1
UART5_TX
I2S0_RX_FS
FTM3_CH3
12
F2
PTE9
ADC2_SE17
ADC2_SE17
PTE9
I2S0_TXD1
UART5_RX
I2S0_RX_
BCLK
FTM3_CH4
EzPort
SPI1_SOUT
K10 Sub-Family, Rev. 7, 02/2018
70
NXP Semiconductors
Pinout
144 144
LQFP MAP
BGA
Pin Name
Default
13
F1
PTE10
DISABLED
14
G4
PTE11
ADC3_SE16
15
G3
PTE12
16
E6
17
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
PTE10
UART5_
CTS_b
I2S0_TXD0
FTM3_CH5
ADC3_SE16
PTE11
UART5_
RTS_b
I2S0_TX_FS
FTM3_CH6
ADC3_SE17
ADC3_SE17
PTE12
I2S0_TX_
BCLK
FTM3_CH7
VDD
VDD
VDD
F7
VSS
VSS
VSS
18
H1
PTE16
ADC0_SE4a
ADC0_SE4a
PTE16
SPI0_PCS0
UART2_TX
FTM_CLKIN0
FTM0_FLT3
19
H2
PTE17
ADC0_SE5a
ADC0_SE5a
PTE17
SPI0_SCK
UART2_RX
FTM_CLKIN1
LPTMR0_
ALT3
20
G1
PTE18
ADC0_SE6a
ADC0_SE6a
PTE18
SPI0_SOUT
UART2_
CTS_b
I2C0_SDA
21
G2
PTE19
ADC0_SE7a
ADC0_SE7a
PTE19
SPI0_SIN
UART2_
RTS_b
I2C0_SCL
22
H3
VSS
VSS
VSS
23
J1
PGA2_DP/
ADC2_DP0/
ADC3_DP3/
ADC0_DP1
PGA2_DP/
ADC2_DP0/
ADC3_DP3/
ADC0_DP1
PGA2_DP/
ADC2_DP0/
ADC3_DP3/
ADC0_DP1
24
J2
PGA2_DM/
ADC2_DM0/
ADC3_DM3/
ADC0_DM1
PGA2_DM/
ADC2_DM0/
ADC3_DM3/
ADC0_DM1
PGA2_DM/
ADC2_DM0/
ADC3_DM3/
ADC0_DM1
25
K1
PGA3_DP/
ADC3_DP0/
ADC2_DP3/
ADC1_DP1
PGA3_DP/
ADC3_DP0/
ADC2_DP3/
ADC1_DP1
PGA3_DP/
ADC3_DP0/
ADC2_DP3/
ADC1_DP1
26
K2
PGA3_DM/
ADC3_DM0/
ADC2_DM3/
ADC1_DM1
PGA3_DM/
ADC3_DM0/
ADC2_DM3/
ADC1_DM1
PGA3_DM/
ADC3_DM0/
ADC2_DM3/
ADC1_DM1
27
L1
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
28
L2
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
29
M1
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
30
M2
PGA1_DM/
ADC1_DM0/
ADC0_DM3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
31
H5
VDDA
VDDA
VDDA
32
G5
VREFH
VREFH
VREFH
33
G6
VREFL
VREFL
VREFL
34
H6
VSSA
VSSA
VSSA
ALT7
EzPort
CMP3_OUT
K10 Sub-Family, Rev. 7, 02/2018
NXP Semiconductors
71
Pinout
144 144
LQFP MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
35
K3
ADC1_SE16/ ADC1_SE16/ ADC1_SE16/
CMP2_IN2/ CMP2_IN2/ CMP2_IN2/
ADC0_SE22 ADC0_SE22 ADC0_SE22
36
J3
ADC0_SE16/ ADC0_SE16/ ADC0_SE16/
CMP1_IN2/ CMP1_IN2/ CMP1_IN2/
ADC0_SE21 ADC0_SE21 ADC0_SE21
37
M3
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
38
L3
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
39
L4
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
40
M7
XTAL32
XTAL32
XTAL32
41
M6
EXTAL32
EXTAL32
EXTAL32
42
L6
VBAT
VBAT
VBAT
43
—
VDD
VDD
VDD
44
—
VSS
VSS
VSS
45
M4
PTE24
ADC0_SE17/ ADC0_SE17/ PTE24
EXTAL1
EXTAL1
CAN1_TX
UART4_TX
I2S1_TX_FS
EWM_OUT_b I2S1_RXD1
46
K5
PTE25
ADC0_SE18/ ADC0_SE18/ PTE25
XTAL1
XTAL1
CAN1_RX
UART4_RX
I2S1_TX_
BCLK
EWM_IN
47
K4
PTE26
ADC3_SE5b
ADC3_SE5b
PTE26
UART4_
CTS_b
I2S1_TXD0
RTC_
CLKOUT
48
J4
PTE27
ADC3_SE4b
ADC3_SE4b
PTE27
UART4_
RTS_b
I2S1_MCLK
49
H4
PTE28
ADC3_SE7a
ADC3_SE7a
PTE28
50
J5
PTA0
JTAG_TCLK/ TSI0_CH1
SWD_CLK/
EZP_CLK
PTA0
UART0_
CTS_b/
UART0_
COL_b
FTM0_CH5
JTAG_TCLK/ EZP_CLK
SWD_CLK
51
J6
PTA1
JTAG_TDI/
EZP_DI
TSI0_CH2
PTA1
UART0_RX
FTM0_CH6
JTAG_TDI
EZP_DI
52
K6
PTA2
JTAG_TDO/
TRACE_
SWO/
EZP_DO
TSI0_CH3
PTA2
UART0_TX
FTM0_CH7
JTAG_TDO/
TRACE_
SWO
EZP_DO
53
K7
PTA3
JTAG_TMS/
SWD_DIO
TSI0_CH4
PTA3
UART0_
RTS_b
FTM0_CH0
JTAG_TMS/
SWD_DIO
54
L7
PTA4/
LLWU_P3
NMI_b/
EZP_CS_b
TSI0_CH5
PTA4/
LLWU_P3
FTM0_CH1
NMI_b
55
M8
PTA5
DISABLED
PTA5
FTM0_CH2
56
E7
VDD
VDD
CMP2_OUT
I2S0_TX_
BCLK
I2S1_TXD1
EZP_CS_b
JTAG_TRST_
b
VDD
K10 Sub-Family, Rev. 7, 02/2018
72
NXP Semiconductors
Pinout
144 144
LQFP MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
57
G7
VSS
VSS
VSS
58
J7
PTA6
ADC3_SE6a
ADC3_SE6a
PTA6
FTM0_CH3
I2S1_RXD0
59
J8
PTA7
ADC0_SE10
ADC0_SE10
PTA7
FTM0_CH4
I2S1_RX_
BCLK
60
K8
PTA8
ADC0_SE11
ADC0_SE11
PTA8
FTM1_CH0
I2S1_RX_FS
61
L8
PTA9
ADC3_SE5a
ADC3_SE5a
PTA9
62
M9
PTA10
ADC3_SE4a
ADC3_SE4a
63
L9
PTA11
ADC3_SE15
64
K9
PTA12
65
J9
66
ALT5
ALT6
CLKOUT
ALT7
TRACE_
CLKOUT
TRACE_D3
FTM1_QD_
PHA
TRACE_D2
FTM1_CH1
FTM1_QD_
PHB
TRACE_D1
PTA10
FTM2_CH0
FTM2_QD_
PHA
TRACE_D0
ADC3_SE15
PTA11
FTM2_CH1
FTM2_QD_
PHB
CMP2_IN0
CMP2_IN0
PTA12
CAN0_TX
FTM1_CH0
I2S0_TXD0
FTM1_QD_
PHA
PTA13/
LLWU_P4
CMP2_IN1
CMP2_IN1
PTA13/
LLWU_P4
CAN0_RX
FTM1_CH1
I2S0_TX_FS
FTM1_QD_
PHB
L10
PTA14
CMP3_IN0
CMP3_IN0
PTA14
SPI0_PCS0
UART0_TX
I2S0_RX_
BCLK
I2S0_TXD1
67
L11
PTA15
CMP3_IN1
CMP3_IN1
PTA15
SPI0_SCK
UART0_RX
I2S0_RXD0
68
K10
PTA16
CMP3_IN2
CMP3_IN2
PTA16
SPI0_SOUT
UART0_
CTS_b/
UART0_
COL_b
I2S0_RX_FS
69
K11
PTA17
ADC1_SE17
ADC1_SE17
PTA17
SPI0_SIN
UART0_
RTS_b
I2S0_MCLK
70
E8
VDD
VDD
VDD
71
G8
VSS
VSS
VSS
72
M12 PTA18
EXTAL0
EXTAL0
PTA18
FTM0_FLT2
FTM_CLKIN0
73
M11 PTA19
XTAL0
XTAL0
PTA19
FTM1_FLT0
FTM_CLKIN1
74
L12
RESET_b
RESET_b
RESET_b
75
K12
PTA24
CMP3_IN4
CMP3_IN4
PTA24
FB_A29
76
J12
PTA25
CMP3_IN5
CMP3_IN5
PTA25
FB_A28
77
J11
PTA26
ADC2_SE15
ADC2_SE15
PTA26
FB_A27
78
J10
PTA27
ADC2_SE14
ADC2_SE14
PTA27
FB_A26
79
H12 PTA28
ADC2_SE13
ADC2_SE13
PTA28
FB_A25
80
H11 PTA29
ADC2_SE12
ADC2_SE12
PTA29
81
H10 PTB0/
LLWU_P5
ADC0_SE8/
ADC1_SE8/
ADC2_SE8/
ADC3_SE8/
TSI0_CH0
ADC0_SE8/
ADC1_SE8/
ADC2_SE8/
ADC3_SE8/
TSI0_CH0
PTB0/
LLWU_P5
I2C0_SCL
FTM1_CH0
FTM1_QD_
PHA
82
H9
ADC0_SE9/
ADC1_SE9/
ADC2_SE9/
ADC0_SE9/
ADC1_SE9/
ADC2_SE9/
PTB1
I2C0_SDA
FTM1_CH1
FTM1_QD_
PHB
PTB1
EzPort
I2S0_RXD1
LPTMR0_
ALT1
FB_A24
K10 Sub-Family, Rev. 7, 02/2018
NXP Semiconductors
73
Pinout
144 144
LQFP MAP
BGA
Pin Name
Default
ALT0
ADC3_SE9/
TSI0_CH6
ADC3_SE9/
TSI0_CH6
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
83
G12 PTB2
ADC0_SE12/ ADC0_SE12/ PTB2
TSI0_CH7
TSI0_CH7
I2C0_SCL
UART0_
RTS_b
FTM0_FLT3
84
G11 PTB3
ADC0_SE13/ ADC0_SE13/ PTB3
TSI0_CH8
TSI0_CH8
I2C0_SDA
UART0_
CTS_b/
UART0_
COL_b
FTM0_FLT0
85
G10 PTB4
ADC1_SE10
ADC1_SE10
PTB4
FTM1_FLT0
86
G9
PTB5
ADC1_SE11
ADC1_SE11
PTB5
FTM2_FLT0
87
F12
PTB6
ADC1_SE12
ADC1_SE12
PTB6
FB_AD23
88
F11
PTB7
ADC1_SE13
ADC1_SE13
PTB7
FB_AD22
89
F10
PTB8
DISABLED
PTB8
90
F9
PTB9
DISABLED
PTB9
91
E12
PTB10
ADC1_SE14
ADC1_SE14
92
E11
PTB11
ADC1_SE15
ADC1_SE15
93
H7
VSS
VSS
VSS
94
F5
VDD
VDD
VDD
95
E10
PTB16
TSI0_CH9
96
E9
PTB17
97
UART3_
RTS_b
FB_AD21
SPI1_PCS1
UART3_
CTS_b
FB_AD20
PTB10
SPI1_PCS0
UART3_RX
I2S1_TX_
BCLK
FB_AD19
FTM0_FLT1
PTB11
SPI1_SCK
UART3_TX
I2S1_TX_FS
FB_AD18
FTM0_FLT2
TSI0_CH9
PTB16
SPI1_SOUT
UART0_RX
I2S1_TXD0
FB_AD17
EWM_IN
TSI0_CH10
TSI0_CH10
PTB17
SPI1_SIN
UART0_TX
I2S1_TXD1
FB_AD16
EWM_OUT_b
D12 PTB18
TSI0_CH11
TSI0_CH11
PTB18
CAN0_TX
FTM2_CH0
I2S0_TX_
BCLK
FB_AD15
FTM2_QD_
PHA
98
D11 PTB19
TSI0_CH12
TSI0_CH12
PTB19
CAN0_RX
FTM2_CH1
I2S0_TX_FS
FB_OE_b
FTM2_QD_
PHB
99
D10 PTB20
ADC2_SE4a
ADC2_SE4a
PTB20
SPI2_PCS0
FB_AD31/
NFC_
DATA15
CMP0_OUT
100
D9
ADC2_SE5a
ADC2_SE5a
PTB21
SPI2_SCK
FB_AD30/
NFC_
DATA14
CMP1_OUT
101
C12 PTB22
DISABLED
PTB22
SPI2_SOUT
FB_AD29/
NFC_
DATA13
CMP2_OUT
102
C11 PTB23
DISABLED
PTB23
SPI2_SIN
SPI0_PCS5
FB_AD28/
NFC_
DATA12
CMP3_OUT
103
B12
PTC0
ADC0_SE14/ ADC0_SE14/ PTC0
TSI0_CH13 TSI0_CH13
SPI0_PCS4
PDB0_
EXTRG
FB_AD14/
NFC_
DATA11
I2S0_TXD1
104
B11
PTC1/
LLWU_P6
ADC0_SE15/ ADC0_SE15/ PTC1/
TSI0_CH14 TSI0_CH14 LLWU_P6
SPI0_PCS3
UART1_
RTS_b
FB_AD13/
NFC_
DATA10
I2S0_TXD0
PTB21
FTM0_CH0
ALT7
EzPort
K10 Sub-Family, Rev. 7, 02/2018
74
NXP Semiconductors
Pinout
144 144
LQFP MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
105
A12
PTC2
ADC0_SE4b/ ADC0_SE4b/ PTC2
CMP1_IN0/ CMP1_IN0/
TSI0_CH15 TSI0_CH15
SPI0_PCS2
UART1_
CTS_b
FTM0_CH1
FB_AD12/
NFC_DATA9
I2S0_TX_FS
106
A11
PTC3/
LLWU_P7
CMP1_IN1
CMP1_IN1
PTC3/
LLWU_P7
SPI0_PCS1
UART1_RX
FTM0_CH2
CLKOUT
I2S0_TX_
BCLK
107
H8
VSS
VSS
VSS
108
—
VDD
VDD
VDD
109
A9
PTC4/
LLWU_P8
DISABLED
PTC4/
LLWU_P8
SPI0_PCS0
UART1_TX
FTM0_CH3
FB_AD11/
NFC_DATA8
CMP1_OUT
I2S1_TX_
BCLK
110
D8
PTC5/
LLWU_P9
DISABLED
PTC5/
LLWU_P9
SPI0_SCK
LPTMR0_
ALT2
I2S0_RXD0
FB_AD10/
NFC_DATA7
CMP0_OUT
I2S1_TX_FS
111
C8
PTC6/
LLWU_P10
CMP0_IN0
CMP0_IN0
PTC6/
LLWU_P10
SPI0_SOUT
PDB0_
EXTRG
I2S0_RX_
BCLK
FB_AD9/
NFC_DATA6
I2S0_MCLK
112
B8
PTC7
CMP0_IN1
CMP0_IN1
PTC7
SPI0_SIN
I2S0_RX_FS
FB_AD8/
NFC_DATA5
113
A8
PTC8
ADC1_SE4b/ ADC1_SE4b/ PTC8
CMP0_IN2
CMP0_IN2
FTM3_CH4
I2S0_MCLK
FB_AD7/
NFC_DATA4
114
D7
PTC9
ADC1_SE5b/ ADC1_SE5b/ PTC9
CMP0_IN3
CMP0_IN3
FTM3_CH5
I2S0_RX_
BCLK
FB_AD6/
NFC_DATA3
FTM2_FLT0
115
C7
PTC10
ADC1_SE6b
ADC1_SE6b
PTC10
I2C1_SCL
FTM3_CH6
I2S0_RX_FS
FB_AD5/
NFC_DATA2
I2S1_MCLK
116
B7
PTC11/
LLWU_P11
ADC1_SE7b
ADC1_SE7b
PTC11/
LLWU_P11
I2C1_SDA
FTM3_CH7
I2S0_RXD1
FB_RW_b/
NFC_WE
117
A7
PTC12
DISABLED
PTC12
UART4_
RTS_b
FB_AD27
118
D6
PTC13
DISABLED
PTC13
UART4_
CTS_b
FB_AD26
119
C6
PTC14
DISABLED
PTC14
UART4_RX
FB_AD25
120
B6
PTC15
DISABLED
PTC15
UART4_TX
FB_AD24
121
—
VSS
VSS
VSS
122
—
VDD
VDD
VDD
123
A6
PTC16
DISABLED
PTC16
CAN1_RX
UART3_RX
FB_CS5_b/
FB_TSIZ1/
FB_BE23_
16_b
NFC_RB
124
D5
PTC17
DISABLED
PTC17
CAN1_TX
UART3_TX
FB_CS4_b/
FB_TSIZ0/
FB_BE31_
24_b
NFC_CE0_b
125
C5
PTC18
DISABLED
PTC18
UART3_
RTS_b
FB_TBST_b/ NFC_CE1_b
FB_CS2_b/
FB_BE15_8_
b
126
B5
PTC19
DISABLED
PTC19
UART3_
CTS_b
FB_CS3_b/ FB_TA_b
FB_BE7_0_b
127
A5
PTD0/
LLWU_P12
DISABLED
PTD0/
LLWU_P12
SPI0_PCS0
UART2_
RTS_b
FTM3_CH0
FB_ALE/
FB_CS1_b/
FB_TS_b
EzPort
FTM3_FLT0
I2S1_RXD1
K10 Sub-Family, Rev. 7, 02/2018
NXP Semiconductors
75
Pinout
144 144
LQFP MAP
BGA
Pin Name
Default
ALT0
ADC0_SE5b
128
D4
PTD1
ADC0_SE5b
129
C4
PTD2/
LLWU_P13
130
B4
131
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
PTD1
SPI0_SCK
UART2_
CTS_b
FTM3_CH1
FB_CS0_b
I2S1_RXD0
DISABLED
PTD2/
LLWU_P13
SPI0_SOUT
UART2_RX
FTM3_CH2
FB_AD4
I2S1_RX_FS
PTD3
DISABLED
PTD3
SPI0_SIN
UART2_TX
FTM3_CH3
FB_AD3
I2S1_RX_
BCLK
A4
PTD4/
LLWU_P14
DISABLED
PTD4/
LLWU_P14
SPI0_PCS1
UART0_
RTS_b
FTM0_CH4
FB_AD2/
NFC_DATA1
EWM_IN
132
A3
PTD5
ADC0_SE6b
ADC0_SE6b
PTD5
SPI0_PCS2
UART0_
CTS_b/
UART0_
COL_b
FTM0_CH5
FB_AD1/
NFC_DATA0
EWM_OUT_b
133
A2
PTD6/
LLWU_P15
ADC0_SE7b
ADC0_SE7b
PTD6/
LLWU_P15
SPI0_PCS3
UART0_RX
FTM0_CH6
FB_AD0
FTM0_FLT0
134
M10 VSS
VSS
VSS
135
F8
VDD
VDD
VDD
136
A1
PTD7
DISABLED
PTD7
CMT_IRO
UART0_TX
FTM0_CH7
137
C9
PTD8
DISABLED
PTD8
I2C0_SCL
UART5_RX
FB_A16/
NFC_CLE
138
B9
PTD9
DISABLED
PTD9
I2C0_SDA
UART5_TX
FB_A17/
NFC_ALE
139
B3
PTD10
DISABLED
PTD10
UART5_
RTS_b
FB_A18/
NFC_RE
140
B2
PTD11
DISABLED
PTD11
SPI2_PCS0
UART5_
CTS_b
SDHC0_
CLKIN
FB_A19
141
B1
PTD12
DISABLED
PTD12
SPI2_SCK
FTM3_FLT0
SDHC0_D4
FB_A20
142
C3
PTD13
DISABLED
PTD13
SPI2_SOUT
SDHC0_D5
FB_A21
143
C2
PTD14
DISABLED
PTD14
SPI2_SIN
SDHC0_D6
FB_A22
144
C1
PTD15
DISABLED
PTD15
SPI2_PCS1
SDHC0_D7
FB_A23
ALT7
EzPort
FTM0_FLT1
8.3 K10 pinouts
The figure below shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
K10 Sub-Family, Rev. 7, 02/2018
76
NXP Semiconductors
PTC7
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
111
110
109
PTC13
PTC8
PTC14
118
112
PTC15
119
PTC9
VSS
120
113
VDD
121
PTC10
PTC16
122
115
PTC17
123
114
PTC18
124
PTC12
PTC19
125
PTC11/LLWU_P11
PTD0/LLWU_P12
126
116
PTD1
127
117
PTD2/LLWU_P13
VSS
134
128
VDD
135
PTD3
PTD7
136
129
PTD8
137
PTD4/LLWU_P14
PTD9
138
131
PTD10
139
130
PTD11
140
PTD6/LLWU_P15
PTD12
141
PTD5
PTD13
142
132
PTD14
143
133
PTD15
144
Pinout
PTE0
1
108
VDD
PTE1/LLWU_P0
2
107
VSS
PTE2/LLWU_P1
3
106
PTC3/LLWU_P7
PTE3
4
105
PTC2
VDD
5
104
PTC1/LLWU_P6
VSS
6
103
PTC0
PTE4/LLWU_P2
7
102
PTB23
PTE5
8
101
PTB22
PTE6
9
100
PTB21
PTE7
10
99
PTB20
PTE8
11
98
PTB19
PTE9
12
97
PTB18
PTE10
13
96
PTB17
PTE11
14
95
PTB16
PTE12
15
94
VDD
VDD
16
93
VSS
VSS
17
92
PTB11
PTE16
18
91
PTB10
PTE17
19
90
PTB9
PTE18
20
89
PTB8
PTE19
21
88
PTB7
VSS
22
87
PTB6
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VDD
VSS
PTA6
PTA7
PTA8
PTA9
PTA10
PTA11
PTA12
PTA13/LLWU_P4
PTA14
PTA15
PTA16
PTA17
VDD
VSS
PTA18
PTA19
55
RESET_b
73
PTA5
74
36
54
35
PTA4/LLWU_P3
ADC1_SE16/CMP2_IN2/ADC0_SE22
ADC0_SE16/CMP1_IN2/ADC0_SE21
53
PTA24
PTA3
75
52
34
PTA2
PTA25
VSSA
51
PTA26
76
50
77
33
PTA1
32
VREFL
PTA0
VREFH
49
PTA27
PTE28
78
48
31
PTE27
PTA28
VDDA
47
79
PTE26
30
46
PTA29
PGA1_DM/ADC1_DM0/ADC0_DM3
PTE25
80
45
29
PTE24
PTB0/LLWU_P5
PGA1_DP/ADC1_DP0/ADC0_DP3
44
81
VSS
28
43
PTB1
PGA0_DM/ADC0_DM0/ADC1_DM3
VDD
82
42
27
VBAT
PTB2
PGA0_DP/ADC0_DP0/ADC1_DP3
41
83
EXTAL32
26
40
PTB3
PGA3_DM/ADC3_DM0/ADC2_DM3/ADC1_DM1
XTAL32
84
39
25
DAC1_OUT/CMP0_IN4/CMP2_IN3/ADC1_SE23
PTB4
PGA3_DP/ADC3_DP0/ADC2_DP3/ADC1_DP1
38
PTB5
85
37
86
24
DAC0_OUT/CMP1_IN3/ADC0_SE23
23
VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18
PGA2_DP/ADC2_DP0/ADC3_DP3/ADC0_DP1
PGA2_DM/ADC2_DM0/ADC3_DM3/ADC0_DM1
Figure 39. K10 144 LQFP Pinout Diagram
K10 Sub-Family, Rev. 7, 02/2018
NXP Semiconductors
77
Revision History
1
2
3
4
5
6
7
8
9
10
11
12
A
PTD7
PTD6/
LLWU_P15
PTD5
PTD4/
LLWU_P14
PTD0/
LLWU_P12
PTC16
PTC12
PTC8
PTC4/
LLWU_P8
NC
PTC3/
LLWU_P7
PTC2
A
B
PTD12
PTD11
PTD10
PTD3
PTC19
PTC15
PTC11/
LLWU_P11
PTC7
PTD9
NC
PTC1/
LLWU_P6
PTC0
B
C
PTD15
PTD14
PTD13
PTD2/
LLWU_P13
PTC18
PTC14
PTC10
PTC6/
LLWU_P10
PTD8
NC
PTB23
PTB22
C
D
PTE2/
LLWU_P1
PTE1/
LLWU_P0
PTE0
PTD1
PTC17
PTC13
PTC9
PTC5/
LLWU_P9
PTB21
PTB20
PTB19
PTB18
D
E
PTE6
PTE5
PTE4/
LLWU_P2
PTE3
VDD
VDD
VDD
VDD
PTB17
PTB16
PTB11
PTB10
E
F
PTE10
PTE9
PTE8
PTE7
VDD
VSS
VSS
VDD
PTB9
PTB8
PTB7
PTB6
F
G
PTE18
PTE19
PTE12
PTE11
VREFH
VREFL
VSS
VSS
PTB5
PTB4
PTB3
PTB2
G
H
PTE16
PTE17
VSS
PTE28
VDDA
VSSA
VSS
VSS
PTB1
PTB0/
LLWU_P5
PTA29
PTA28
H
J
PGA2_DP/
ADC2_DP0/
ADC3_DP3/
ADC0_DP1
PGA2_DM/
ADC0_SE16/
ADC2_DM0/
CMP1_IN2/
ADC3_DM3/
ADC0_SE21
ADC0_DM1
PTE27
PTA0
PTA1
PTA6
PTA7
PTA13/
LLWU_P4
PTA27
PTA26
PTA25
J
K
PGA3_DP/
ADC3_DP0/
ADC2_DP3/
ADC1_DP1
PGA3_DM/
ADC1_SE16/
ADC3_DM0/
CMP2_IN2/
ADC2_DM3/
ADC0_SE22
ADC1_DM1
PTE26
PTE25
PTA2
PTA3
PTA8
PTA12
PTA16
PTA17
PTA24
K
L
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
RTC_
WAKEUP_B
VBAT
PTA4/
LLWU_P3
PTA9
PTA11
PTA14
PTA15
RESET_b
L
PGA1_DP/
M ADC1_DP0/
ADC0_DP3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
PTE24
NC
EXTAL32
XTAL32
PTA5
PTA10
VSS
PTA19
PTA18
M
2
3
4
5
6
7
8
9
10
11
12
1
Figure 40. K10 144 MAPBGA Pinout Diagram
9 Revision History
The following table provides a revision history for this document.
Table 54. Revision History
Rev. No.
Date
3
3/2012
Substantial Changes
Initial public release
Table continues on the next page...
K10 Sub-Family, Rev. 7, 02/2018
78
NXP Semiconductors
Revision History
Table 54. Revision History (continued)
Rev. No.
Date
Substantial Changes
4
10/2012
Replaced TBDs throughout.
5
10/2013
Changes for 4N96B mask set:
• Min VDD operating requirement specification updated to support operation down to
1.71V.
New specifications:
• Updated Vdd_ddr min specification.
• Added Vodpu specification.
• Removed Ioz, Ioz_ddr, and Ioz_tamper Hi-Z leakage specfications. They have been
replaced by new Iina, Iind, and Zind specifications.
• Fpll_ref_acc specification has been added.
• I2C module was previously covered by the general switching specifications. To provide
more detail on I2C operation a dedicated Inter-Integrated Circuit Interface (I2C) timing
section has been added.
Modified specifications:
•
•
•
•
Vref_ddr max spec has been updated.
Tpor spec has been split into two specifications based on VDD slew rate.
Trd1allx and Trd1alln max have been updated.
16-bit ADC Temp sensor slope and Temp sensor voltage (Vtemp25) have been
modified. The typical values that were listed previously have been updated, and min
and max specifications have been added.
Corrections:
• Some versions of the datasheets listed incorrect clock mode information in the
"Diagram: Typical IDD_RUN operating behavior section." These errors have been
corrected.
• Fintf_ft specification was previously shown as a max value. It has been corrected to be
shown as a typical value as originally intended.
• Corrected DDR write and read timing diagrams to show the correct location of the Tcmv
specification.
• SDHC peripheral 50MHz high speed mode options were left out of the last datasheet.
These have been added to the SDHC specifications section.
6
09/2015
• Updated the footnotes of Thermal Attributes table
• Removed Power Sequencing section
• Added footnote to ambient temperature specification of Thermal Operating
requirements
• Updated Terminology and guidelines section
• Updated the footnotes and the values of Power consumption operating behaviors table
• Updated I2C timing table
7
02/2018
• Updated maximum SDHC frequency in SDHC specifications
K10 Sub-Family, Rev. 7, 02/2018
NXP Semiconductors
79
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Document Number K10P144M120SF3
Revision 7, 02/2018