M29F040 4 Mbit (512Kb x8, Uniform Block) Single Supply Flash Memory NOT FOR NEW DESIGN M29F040 is replaced by the M29F040B 5V ± 10% SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS FAST ACCESS TIME: 70ns BYTE PROGRAMMING TIME: 10µs typical ERASE TIME – Block: 1.0 sec typical – Chip: 2.5 sec typical PROGRAM/ERASE CONTROLLER (P/E.C.) – Program Byte-by-Byte – Data Polling and Toggle bits Protocol for P/E.C. Status MEMORY ERASE in BLOCKS – 8 Uniform Blocks of 64 KBytes each – Block Protection – Multiblock Erase ERASE SUSPEND and RESUME MODES LOW POWER CONSUMPTION – Read mode: 8mA typical (at 12MHz) – Stand-by mode: 25µA typical – Automatic Stand-by mode 100,000 PROGRAM/ERASE CYCLES per BLOCK 20 YEARS DATA RETENTION – Defectivity below 1ppm/year ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code: E2h PLCC32 (K) TSOP32 (N) 8 x 20 mm Figure 1. Logic Diagram VCC 19 8 A0-A18 W DQ0-DQ7 M29F040 E Table 1. Signal Names A0-A18 Address Inputs DQ0-DQ7 Data Input / Outputs E Chip Enable G Output Enable W Write Enable VCC Supply Voltage VSS Ground November 1999 This is information on a product still in production but not recommended for new designs. G VSS AI01372 1/31 M29F040 Figure 2B. TSOP Pin Connections A12 A15 A16 A18 VCC W A17 Figure 2A. LCC Pin Connections 1 32 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 M29F040 9 25 A14 A13 A8 A9 A11 G A10 E DQ7 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 17 AI01378 A11 A9 A8 A13 A14 A17 W VCC A18 A16 A15 A12 A7 A6 A5 A4 1 8 9 16 32 M29F040 (Normal) 25 24 17 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 AI01379 Figure 2C. TSOP Reverse Pin Connections G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 1 8 9 16 32 M29F040 (Reverse) 25 24 17 AI01174B 2/31 A11 A9 A8 A13 A14 A17 W VCC A18 A16 A15 A12 A7 A6 A5 A4 DESCRIPTION The M29F040 is a non-volatile memory that may be erased electrically at the block level, and programmed Byte-by-Byte. The interface is directly compatible with most microprocessors. PLCC32 and TSOP32 (8 x 20mm) packages are available. Both normal and reverse pin outs are available for the TSOP32 package. Organisation The Flash Memory organisation is 512K x8 bits with Address lines A0-A18 and Data Inputs/Outputs DQ0-DQ7. Memory control is provided by Chip Enable, Output Enable and Write Enable Inputs. Erase and Program are performed through the internal Program/Erase Controller (P/E.C.). Data Outputs bits DQ7 and DQ6 provide polling or toggle signals during Automatic Program or Erase to indicate the Ready/Busy state of the internal Program/Erase Controller. Memory Blocks Erasure of the memory is in blocks. There are 8 uniform blocks of 64 Kbytes each in the memory address space. Each block can be programmed and erased over 100,000 cycles. Each uniform block may separately be protected and unpro- M29F040 Table 2. Absolute Maximum Ratings (1) Symbol TA Parameter Ambient Operating Temperature (3) Value Unit –40 to 125 °C TBIAS Temperature Under Bias –50 to 125 °C TSTG Storage Temperature –65 to 150 °C Input or Output Voltages –0.6 to 7 V Supply Voltage –0.6 to 7 V A9 Voltage –0.6 to 13.5 V VIO (2) VCC VA9 (2) Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns. 3. Depends on range. tected against program and erase. Block erasure may be suspended, while data is read from other blocks of the memory, and then resumed. Bus Operations Seven operations can be performed by the appropriate bus cycles, Read Array, Read Electronic Signature, Output Disable, Standby, Protect Block, Unprotect Block, and Write the Command of an Instruction. Command Interface Command Bytes can be written to a Command Interface (C.I.) latch to perform Reading (from the Array or Electronic Signature), Erasure or Programming. For added data protection, command execution starts after 4 or 6 command cycles. The first, second, fourth and fifth cycles are used to input a code sequence to the Command Interface (C.I.). This sequence is equal for all P/E.C. instructions. Command itself and its confirmation - if it applies - are given on the third and fourth or sixth cycles. Instructions Seven instructions are defined to perform Reset, Read Electronic Signature, Auto Program, Block Auto Erase, Chip Auto Erase, Block Erase Suspend and Block Erase Resume. The internal Program/Erase Controller (P/E.C.) handles all timing and verification of the Program and Erase instruc- tions and provides Data Polling, Toggle, and Status data to indicate completion of Program and Erase Operations. Instructions are composed of up to six cycles. The first two cycles input a code sequence to the Command Interface which is common to all P/E.C. instructions (see Table 7 for Command Descriptions). The third cycle inputs the instruction set up command instruction to the Command Interface. Subsequent cycles output Signature, Block Protection or the addressed data for Read operations. For added data protection, the instructions for program, and block or chip erase require further command inputs. For a Program instruction, the fourth command cycle inputs the address and data to be programmed. For an Erase instruction (block or chip), the fourth and fifth cycles input a further code sequence before the Erase confirm command on the sixth cycle. Byte programming takes typically 10µs while erase is performed in typically 1.0 second. Erasure of a memory block may be suspended, in order to read data from another block, and then resumed. Data Polling, Toggle and Error data may be read at any time, including during the programming or erase cycles, to monitor the progress of the operation. When power is first applied or if VCC falls below VLKO, the command interface is reset to Read Array. 3/31 M29F040 Table 3. Operations Operation E G W DQ0 - DQ7 Read VIL VIL VIH Data Output Write VIL VIH VIL Data Input Output Disable VIL VIH VIH Hi-Z Standby VIH X X Hi-Z Note: X = VIL or VIH Table 4. Electronic Signature Code E G W A0 A1 A6 A9 Other Addresses DQ0 - DQ7 Manufact. Code VIL VIL VIH VIL VIL VIL VID Don’t Care 20h Device Code VIL VIL VIH VIH VIL VIL VID Don’t Care E2h Table 5. Block Protection Status E G W A0 A1 A6 A16 A17 A18 Other Addresses DQ0 - DQ7 Protected Block VIL VIL VIH VIL VIH VIL SA SA SA Don’t Care 01h Unprotected Block VIL VIL VIH VIL VIH VIL SA SA SA Don’t Care 00h Code Note: SA = Address of block being checked DEVICE OPERATION Signal Descriptions Address Inputs (A0-A18). The address inputs for the memory array are latched during a write operation. The A9 address input is used also for the Electronic Signature read and Block Protect verification. When A9 is raised to VID, either a Read Manufacturer Code, Read Device Code or Verify Block Protection is enabled depending on the combination of levels on A0, A1 and A6. When A0, A1 and A6 are Low, the Electronic Signature Manufacturer code is read, when A0 is High and A1 and A6 are Low, the Device code is read, and when A1 is High and A0 and A6 are low, the Block Protection Status is read for the block addressed by A16, A17, A18. Data Input/Outputs (DQ0-DQ7). The data input is a byte to be programmed or a command written to the C.I. Both are latched when Chip Enable E and Write Enable W are active. The data output is from the memory Array, the Electronic Signature, the Data Polling bit (DQ7), the Toggle Bit (DQ6), the Error bit (DQ5) or the Erase Timer bit (DQ3). Ouputs are valid when Chip Enable E and Output Enable G are active. The output is high impedance 4/31 when the chip is deselected or the outputs are disabled. Chip Enable (E). The Chip Enable activates the memory control logic, input buffers, decoders and sense amplifiers. E High deselects the memory and reduces the power consumption to the standby level. E can also be used to control writing to the command register and to the memory array, while W remains at a low level. Addresses are then latched on the falling edge of E while data is latched on the rising edge of E. The Chip Enable must be forced to VID during Block Unprotect operations. Output Enable (G). The Output Enable gates the outputs through the data buffers during a read operation. G must be forced to VID level during Block Protect and Block Unprotect operations. Write Enable (W). This input controls writing to the Command Register and Address and Data latches. Addresses are latched on the falling edge of W, and Data Inputs are latched on the rising edge of W. VCC Supply Voltage. The power supply for all operations (Read, Program and Erase). VSS Ground. VSS is the reference for all voltage measurements. M29F040 Table 6. Instructions (1,2) Mne. Instr. Cyc. 1+ RST (4,10) Read Array/ Reset 1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. Addr. (3,7) Data 3+ Addr. (3,7) Data Read RSIG (4) Electronic Signature RBP (4) Read Block Protection Addr. (3,7) Data 3+ Addr. (3,7) Addr. (3,7) Program Block Erase 6 Addr. (3,7) Data CE Chip Erase 6 Addr. (3,7) Data ES Erase Suspend 1 Addr. (3,7) Data ER Erase Resume 1 Addr. (3,7) Data Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 5555h 2AAAh 5555h AAh 55h F0h 5555h 2AAAh 5555h AAh 55h 90h 5555h 2AAAh 5555h AAh 55h 90h 5555h 2AAAh 5555h AAh 55h A0h 5555h 2AAAh 5555h 5555h 2AAAh AAh 55h 80h AAh 55h 30h 5555h 2AAAh 5555h 5555h 2AAAh 5555h AAh 55h 80h AAh 55h 10h 4 Data BE Read Memory Array until a new write cycle is initiated. F0h 3+ Data PG X 7th Cyc. X Read Memory Array until a new write cycle is initiated. Read Electronic Signature until a new write cycle is initiated. See Note 5. Read Block Protection until a new write cycle is initiated. See Note 6. Program Address Read Data Polling or Toggle Bit until Program completes. Program Data Block Additional Address Block (8) 30h Note 9 Read until Toggle stops, then read all the data needed from any uniform block(s) not being erased then Resume Erase. B0h X Read Data Polling or Toggle Bit until Erase completes or Erase is suspended another time 30h Command not interpreted in this table will default to read array mode. While writing any command or during RSG and RSP execution, the P/E.C. can be reset by writing the command 00h to the C.I. X = Don’t Care. The first cycle of the RST, RBP or RSIG instruction is followed by read operations to read memory array, Status Register or Electronic Signature codes. Any number of read cycles can occur after one command cycle. Signature Address bits A0, A1, A6 at VIL will output Manufacturer code (20h). Address bits A0 at VIH and A1, A6 at VIL will output Device code. Protection Address: A0, A6 at VIL, A1 at VIH and A16, A17, A18 within the uniform block to be checked, will output the Block Protection status. Address bits A15-A18 are don’t care for coded address inputs. Optional, additional blocks addresses must be entered within a 80µs delay after last write entry, timeout status can be verified through DQ3 value. When full command is entered, read Data Polling or Toggle bit until Erase is completed or suspended. Read Data Polling or Toggle bit until Erase completes. A wait time of 5µs is necessary after a Reset command, if the memory is in a Block Erase status, before starting any operation. 5/31 M29F040 Memory Blocks The memory blocks of the M29F040 are shown in Figure 3. The memory array is divided in 8 uniform blocks of 64 Kbytes. Each block can be erased separately or any combination of blocks can be erased simultaneously. The Block Erase operation is managed automatically by the P/E.C. The operation can be suspended in order to read from any other block, and then resumed. Block Protection provides additional data security. Each uniform block can be separately protected or unprotected against Program or Erase. Bringing A9 and G to VID initiates protection, while bringing A9, G and E to VID cancels the protection. The block affected during protection is addressed by the inputs on A16, A17, and A18. Unprotect operation affects all blocks. Operations Operations are defined as specific bus cycles and signals which allow Memory Read, Command Write, Output Disable, Standby, Read Status Bits, Block Protect/Unprotect, Block Protection Check and Electronic Signature Read. They are shown in Tables 3, 4, 5. Read. Read operations are used to output the contents of the Memory Array, the Status Register or the Electronic Signature. Both Chip Enable E and Output Enable G must be low in order to read the output of the memory. The Chip Enable input also provides power control and should be used for device selection. Output Enable should be used to gate data onto the output independent of the device selection. The data read depends on the previous command written to the memory (see instructions RST and RSIG, and Status Bits). Write. Write operations are used to give Instruction Commands to the memory or to latch input data to be programmed. A write operation is initiated when Chip Enable E is Low and Write Enable W is Low with Output Enable G High. Addresses are latched on the falling edge of W or E whichever occurs last. Commands and Input Data are latched on the rising edge of W or E whichever occurs first. Output Disable. The data outputs are high impedance when the Output Enable G is High with Write Enable W High. Standby. The memory is in standby when Chip Enable E is High and Program/Erase Controller P/E.C. is Idle. The power consumption is reduced to the standby level and the outputs are high impedance, independent of the Output Enable G or Write Enable W inputs. Automatic Standby. After 150ns of inactivity and when CMOS levels are driving the addresses, the chip automatically enters a pseudo standby mode 6/31 where consumption is reduced to the CMOS standby value, while outputs are still driving the bus. Electronic Signature. Two codes identifying the manufacturer and the device can be read from the memory, the manufacturer’s code for STMicroelectronics is 20h, and the device code is E2h for the M29F040. These codes allow programming equipment or applications to automatically match their interface to the characteristics of the particular manufacturer’s product. The Electronic Signature is output by a Read operation when the voltage applied to A9 is at VID and address inputs A1 and A6 are at Low. The manufacturer code is output when the Address input A0 is Low and the device code when this input is High. Other Address inputs are ignored. The codes are output on DQ0-DQ7. This is shown in Table 4. The Electronic Signature can also be read, without raising A9 to VID by giving the memory the instruction RSIG (see below). Block Protection. Each uniform block can be separately protected against Program or Erase. Block Protection provides additional data security, as it disables all program or erase operations. This mode is activated when both A9 and G are set to VID and the block address is applied on A16-A18. Block Protection is programmed using a Presto F program like algorithm. Protection is initiated on the edge of W falling to VIL. Then after a delay of 100µs, the edge of W rising to VIH ends the protection operation. Protection verify is achieved by bringing G, E and A6 to VIL while W is at VIH and A9 at VID. Under these conditions, reading the data output will yield 01h if the block defined by the inputs on A16-A18 is protected. Any attempt to program or erase a protected block will be ignored by the device. Any protected block can be unprotected to allow updating of bit contents. All blocks must be protected before an unprotect operation. Block Unprotect is activated when A9, G and E are at VID. The addresses inputs A6, A12, A16 must be maintained at VIH. Block Unprotect is performed through a Presto F Erase like algorithm. Unprotect is initiated by the edge of W falling to VIL. After a delay of 10ms, the edge of W rising to VIH will end the unprotection operation. Unprotect verify is achieved by bringing G and E to VIL while A6 and W are at VIH and A9 at VID. In these conditions, reading the output data will yield 00h if the block defined by the inputs on A16-A18 has been successfully unprotected. All combinations of A16A18 must be addressed in order to ensure that all of the 8 uniform blocks have been unprotected. Block Protection Status is shown in Table 5. M29F040 Figure 3. Memory Map and Block Address Table TOP ADDRESS BOTTOM ADDRESS 64K Bytes Block 7FFFFh 70000h 0 64K Bytes Block 6FFFFh 60000h 0 1 64K Bytes Block 5FFFFh 50000h 1 0 0 4FFFFh 40000h 0 1 1 3FFFFh 30000h 0 1 0 2FFFFh 20000h 0 0 1 64K Bytes Block 1FFFFh 10000h 0 0 0 64K Bytes Block 0FFFFh 00000h A18 A17 A16 1 1 1 1 1 1 AI01362B Instructions and Commands The Command Interface (C.I.) latches commands written to the memory. Instructions are made up from one or more commands to perform Read Array/Reset, Read Electronic Signature, Block Erase, Chip Erase, Program, Block Erase Suspend and Erase Resume. Commands are made of address and data sequences. Addresses are latched on the falling edge of W or E and data is latched on the rising of W or E. The instructions require from 1 to 6 cycles, the first or first three of which are always write operations used to initiate the command. They are followed by either further write cycles to confirm the first command or execute the command immediately. Command sequencing must be followed exactly. Any invalid combination of commands will reset the device to Read Array. The increased number of cycles has been chosen to assure maximum data security. Commands are initialised by two preceding coded cycles which unlock the Command Interface. In addition, for Erase, command confirmation is again preceeded by the two coded cycles. P/E.C. status is indicated during command execution by Data Polling on DQ7, detection of Toggle on Table 7. Commands Hex Code Command 00h Read 10h Chip Erase Confirm 30h Block Erase Resume/Confirm 80h Set-up Erase 90h Read Electronic Signature/ Block Protection Status A0h Program B0h Erase Suspend F0h Read Array/Reset DQ6, or Error on DQ5 and Erase Timer DQ3 bits. Any read attempt during Program or Erase command execution will automatically output those four bits. The P/E.C. automatically sets bits DQ3, DQ5, DQ6 and DQ7. Other bits (DQ0, DQ1, DQ2 and DQ4) are reserved for future use and should be masked. 7/31 M29F040 Table 8. Status Register DQ 7 6 5 Name Data Polling Toggle Bit Error Bit Logic Level Definition ’1’ Erase Complete ’0’ Erase on Going DQ Program Complete DQ Program on Going Note Indicates the P/E.C. status, check during Program or Erase, and on completion before checking bits DQ5 for Program or Erase Success. ’-1-0-1-0-1-0-1-’ Erase or Program on Going ’-0-0-0-0-0-0-0-’ Program (’0’ on DQ6) Complete ’-1-1-1-1-1-1-1-’ Erase or Program (’1’ on DQ6) Complete ’1’ Program or Erase Error ’0’ Program or Erase on Going Successive read output complementary data on DQ6 while Programming or Erase operations are going on. DQ6 remain at constant level when P/E.C. operations are completed or Erase Suspend is acknowledged. This bit is set to ’1’ if P/E.C. has exceded the specified time limits. ’1’ 4 ’0’ 3 Erase Time Bit 2 Reserved 1 Reserved 0 Note: ’1’ Erase Timeout Period Expired ’0’ Erase Timeout Period on Going Reserved Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations. Data Polling bit (DQ7). When Programming operations are in progress, this bit outputs the complement of the bit being programmed on DQ7. During Erase operation, it outputs a ’0’. After completion of the operation, DQ7 will output the bit last programmed or a ’1’ after erasing. Data Polling is valid only effective during P/E.C. operation, that is after the fourth W pulse for programming or after the sixth W pulse for Erase. It must be performed at the address being programmed or at an address within the block being erased. If the byte to be programmed belongs to a protected block the command is ignored. If all the blocks selected for erasure are protected, DQ7 will set to ’0’ for about 100µs, and then return to previous addressed memory data. See Figure 9 for the Data Polling flowchart and Figure 10 for the Data Polling waveforms. Toggle bit (DQ6). When Programming operations are in progress, successive attempts to read DQ6 will output complementary data. DQ6 will toggle following toggling of either G or E when G is low. 8/31 P/E.C. Erase operation has started. Only possible command entry is Erase Suspend (ES). An additional block to be erased in parallel can be entered to the P/E.C. The operation is completed when two successive reads yield the same output data. The next read will output the bit last programmed or a ’1’ after erasing. The toggle bit is valid only effective during P/E.C. operations, that is after the fourth W pulse for programming or after the sixth W pulse for Erase. If the byte to be programmed belongs to a protected block the command will be ignored. If the blocks selected for erasure are protected, DQ6 will toggle for about 100µs and then return back to Read. See Figure 11 for Toggle Bit flowchart and Figure 12 for Toggle Bit waveforms. Error bit (DQ5). This bit is set to ’1’ by the P/E.C when there is a failure of byte programming, block erase, or chip erase that results in invalid data being programmed in the memory block. In case of error in block erase or byte program, the block in which the error occured or to which the programmed byte belongs, must be discarded. Other blocks may still be used. Error bit resets after Reset (RST) instruction. In case of success, the error bit will set to ’0’ during Program or Erase and to valid data after write operation is completed. M29F040 Table 9. AC Measurement Conditions High Speed Standard Input Rise and Fall Times ≤ 10ns ≤ 10ns Input Pulse Voltages 0 to 3V 0.45V to 2.4V 1.5V 0.8V and 2V Input and Output Timing Ref. Voltages Figure 4. AC Testing Input Output Waveform Figure 5. AC Testing Load Circuit 1.3V High Speed 1N914 3V 1.5V 3.3kΩ 0V DEVICE UNDER TEST Standard 2.4V OUT CL 2.0V 0.8V 0.45V CL = 30pF for High Speed CL = 100pF for Standard AI01275B CL includes JIG capacitance AI01276B Table 10. Capacitance (1) (TA = 25 °C, f = 1 MHz ) Symbol CIN COUT Parameter Test Condition Max Unit VIN = 0V 6 pF VOUT = 0V 12 pF Input Capacitance Output Capacitance Min Note: 1. Sampled only, not 100% tested. Erase Timer bit (DQ3). This bit is set to ’0’ by the P/E.C. when the last Block Erase command has been entered to the Command Interface and it is awaiting the Erase start. When the wait period is finished, after 80 to 120µs, DQ3 returns back to ’1’. Coded Cycles. The two coded cycles unlock the Command Interface. They are followed by a command input or a comand confirmation. The coded cycles consist of writing the data AAh at address 5555h during the first cycle and data 55h at address 2AAAh during the second cycle. Addresses are latched on the falling edge of W or E while data is latched on the rising edge of W or E. The coded cycles happen on first and second cycles of the command write or on the fourth and fifth cycles. Read Array/Reset (RST) instruction. The Reset instruction consists of one write operation giving the command F0h. It can be optionally preceded by the two coded cycles. A wait state of 5µs before read operations is necessary if the Reset command is applied during an Erase operation. Read Electronic Signature (RSIG) instruction. This instruction uses the two coded cycles followed by one write cycle giving the command 90h to address 5555h for command setup. A subsequent read will output the manufacturer code, the device code or the Block Protection status depending on the levels of A0, A1, A6, A16, A17 and A18. The manufacturer code, 20h, is output when the addresses lines A0, A1 and A6 are Low, the device code, E2h is output when A0 is High with A1 and A6 Low. 9/31 M29F040 Table 11. DC Characteristics (TA = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C; VCC = 5V ± 10%) Symbol Parameter Test Condition Min Max Unit 0V ≤ VIN ≤ VCC ±1 µA 0V ≤ VOUT ≤ VCC ±1 µA E = VIL, G = VIH, f = 6MHz 15 mA E = VIH 1 mA ILI Input Leakage Current ILO Output Leakage Current ICC1 Supply Current (Read) ICC2 Supply Current (Standby) TTL ICC3 Supply Current (Standby) CMOS E = VCC ± 0.2V 50 µA ICC4 Supply Current (Program or Erase) Byte Program, Block Erase 20 mA ICC5 Supply Current Chip Erase in progress 40 mA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 2 VCC + 0.5 V VOL Output Low Voltage 0.45 V Output High Voltage TTL VOH Output High Voltage CMOS VID A9 Voltage (Electronic Signature) IID A9 Current (Electronic Signature) VLKO Supply Voltage (Erase and Program lock-out) Read Block Protection (RBP) instruction. The use of Read Electronic Signature (RSIG) command also allows access to the Block Protection status verify. After giving the RSIG command, A0 and A6 are set to VIL with A1 at VIH, while A16, A17 and A18 define the block of the block to be verified. A read in these conditions will output a 01h if block is protected and a 00h if block is not protected. This Read Block Protection is the only valid way to check the protection status of a block. Nevertheless, it must not be used during the Block Protection phase as a method to verify the block protection. Please refer to Block Protection paragraph. Chip Erase (CE) instruction. This instruction uses six write cycles. The Erase Set-up command 80h is written to address 5555h on third cycle after the two coded cycles. The Chip Erase Confirm com- 10/31 IOL = 10mA IOH = –2.5mA 2.4 V IOH = –100µA VCC –0.4 V IOH = –2.5mA 0.85 VCC V 11.5 A9 = VID 3.2 12.5 V 50 µA 4.2 V mand 10h is written at address 5555h on sixth cycle after another two coded cycles. If the second command given is not an erase confirm or if the coded cycles are wrong, the instruction aborts and the device is reset to Read Array. It is not necessary to program the array with 00h first as the P/E.C. will automatically do this before erasing to FFh. Read operations after the sixth rising edge of W or E output the status register bits. During the execution of the erase by the P/E.C. the memory accepts only the Reset (RST) command. Read of Data Polling bit DQ7 returns ’0’, then ’1’ on completion. The Toggle Bit DQ6 toggles during erase operation and stops when erase is completed. After completion the Status Register bit DQ5 returns ’1’ if there has been an Erase Failure because the erasure has not been verified even after the maximum number of erase cycles have been executed. M29F040 Table 12A. Read AC Characteristics (TA = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C)(3) M29F040 Symbol Alt Parameter Test Condition -70 -90 VCC = 5V ± 5% VCC = 5V ± 10% Standard Interface Standard Interface Min tAVAV tRC Address Valid to Next Address Valid E = VIL, G = VIL tAVQV tACC Address Valid to Output Valid E = VIL, G = VIL (1) tLZ Chip Enable Low to Output Transition G = VIL tELQV (2) tCE Chip Enable Low to Output Valid G = VIL tGLQX (1) tOLZ Output Enable Low to Output Transition E = VIL tGLQV (2) tOE Output Enable Low to Output Valid E = VIL tEHQX tOH Chip Enable High to Output Transition G = VIL tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL tGHQX tOH Output Enable High to Output Transition E = VIL tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL tAXQX tOH Address Transition to Output Transition tELQX E = VIL, G = VIL Max 70 Min 0 ns 90 0 70 0 0 0 0 0 ns ns 20 0 20 ns ns 35 20 ns ns 90 30 20 Max 90 70 Unit ns ns 20 20 ns ns Notes: 1. Sampled only, not 100% tested. 2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV. 3. The temperature range –40 to 125°C is guaranteed at 70ns with High Speed Interface test condition and VCC = 5V ± 5%. Block Erase (BE) instruction. This instruction uses a minimum of six write cycles. The Erase Set-up command 80h is written to address 5555h on third cycle after the two coded cycles. The Block Erase Confirm command 30h is written on sixth cycle after another two coded cycles. During the input of the second command an address within the block to be erased is given and latched into the memory. Additional Block Erase confirm commands and block addresses can be written subsequently to erase other blocks in parallel, without further coded cycles. The erase will start after an Erase timeout period of about 100µs. Thus, additional Block Erase commands must be given within this delay. The input of a new Block Erase command will restart the timeout period. The status of the internal timer can be monitored through the level of DQ3, if DQ3 is ’0’ the Block Erase Command has been given and the timeout is running, if DQ3 is ’1’, the timeout has expired and the P/E.C is erasing the block(s). Before and during Erase timeout, any command different from 30h will abort the instruction and reset the device to read array mode. It is not necessary to program the block with 00h as the P/E.C. will do this automatically before erasing to FFh. Read operations after the sixth rising edge of W or E output the status register bits. During the execution of the erase by the P/E.C., the memory accepts only the ES (Erase Suspend) and RST (Reset) instructions. Data Polling bit DQ7 returns ’0’ while the erasure is in progress and ’1’ when it has completed. The Toggle Bit DQ6 toggles during the erase operation. It stops when erase is completed. After completion the Status Register bit DQ5 returns ’1’ if there has been an Erase Failure because erasure has not completed even after the maximum number of erase cycles have been executed. In this case, it will be necessary to input a Reset (RST) to the command interface in order to reset the P/E.C. 11/31 M29F040 Table 12B. Read AC Characteristics (TA = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C) M29F040 -120 Symbol Alt Parameter Test Condition -150 VCC = 5V ± 10% VCC = 5V ± 10% Standard Interface Min tAVAV tRC Address Valid to Next Address Valid E = VIL, G = VIL tAVQV tACC Address Valid to Output Valid E = VIL, G = VIL (1) tLZ Chip Enable Low to Output Transition G = VIL tELQV (2) tCE Chip Enable Low to Output Valid G = VIL tGLQX (1) tOLZ Output Enable Low to Output Transition E = VIL tGLQV (2) tOE Output Enable Low to Output Valid E = VIL tEHQX tOH Chip Enable High to Output Transition G = VIL tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL tGHQX tOH Output Enable High to Output Transition E = VIL tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL tAXQX tOH Address Transition to Output Transition tELQX E = VIL, G = VIL Max 120 Standard Interface Min 120 ns 150 0 120 0 0 0 0 0 0 ns ns 35 20 ns ns 35 30 ns ns 55 30 ns ns 150 50 20 Max 150 0 Unit ns ns Notes: 1. Sampled only, not 100% tested. 2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV. Program (PG) instruction. The memory can be programmed Byte-by-Byte. This instruction uses four write cycles. The Program command A0h is written on the third cycle after two coded cycles. A fourth write operation latches the Address on the falling edge of W or E and the Data to be written on its rising edge and starts the P/E.C. During the execution of the program by the P/E.C., the memory will not accept any instruction. Read operations output the status bits after the programming has started. The status bits DQ5, DQ6 and DQ7 allow a check of the status of the programming operation. Memory programming is made only by writing ’0’ in place of ’1’ in a Byte. Erase Suspend (ES) instruction. The Block Erase operation may be suspended by this instruction which consists of writing the command 0B0h without any specific address code. No coded cycles are required. It allows reading of data from another 12/31 block while erase is in progress. Erase suspend is accepted only during the Block Erase instruction execution and defaults to read array mode. Writing this command during Erase timeout will, in addition to suspending the erase, terminate the timeout. The Toggle Bit DQ6 stops toggling when the P/E.C. is suspended. Toggle Bit status must be monitored at an address out of the block being erased. Toggle Bit will stop toggling between 0.1µs and 15µs after the Erase Suspend (ES) command has been written. The M29F040 will then automatically set to Read Memory Array mode. When erase is suspended, Read from blocks being erased will output invalid data, Read from block not being erased is valid. During the suspension the memory will respond only to Erase Resume (ER) and Reset (RST) instructions. RST command will definitively abort erasure and result in the invalid data in the blocks being erased. Note: Write Enable (W) = High DQ0-DQ7 G E A0-A18 ADDRESS VALID AND CHIP ENABLE tAVQV tGLQV OUTPUT ENABLE tGLQX tELQX tELQV VALID tAVAV DATA VALID VALID tGHQZ tGHQX tEHQX tEHQZ tAXQX AI01363B M29F040 Figure 6. Read Mode AC Waveforms 13/31 M29F040 Table 13A. Write AC Characteristics, Write Enable Controlled (TA = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C)(2) M29F040 Symbol Alt Parameter -70 -90 VCC = 5V ± 10% VCC = 5V ± 10% Standard Interface Standard Interface Min Max Min Unit Max tAVAV tWC Address Valid to Next Address Valid 70 90 ns tELWL tCS Chip Enable Low to Write Enable Low 0 0 ns tWLWH tWP Write Enable Low to Write Enable High 35 45 ns tDVWH tDS Input Valid to Write Enable High 30 45 ns tWHDX tDH Write Enable High to Input Transition 0 0 ns tWHEH tCH Write Enable High to Chip Enable High 0 0 ns tWPH Write Enable High to Write Enable Low 20 20 ns tWHWL tAVWL tAS Address Valid to Write Enable Low 0 0 ns tWLAX tAH Write Enable Low to Address Transition 45 45 ns Output Enable High to Write Enable Low 0 0 ns VCC High to Chip Enable Low 50 50 µs Write Enable High to Output Valid (Program) 10 10 µs Write Enable High to Output Valid (Block Erase) 1.0 tGHWL tVCHEL tWHQV1 tVCS (1) tWHQV2 (1) tWHGL tOEH Write Enable High to Output Enable Low 0 30 1.0 30 0 sec ns Note: 1. Time is measured to Data Polling or Toggle Bit, tWHQV = tWHQ7V + tQ7VQV 2. The temperature range –40 to 125°C is guaranteed at 70ns with High Speed Interface test condition and VCC = 5V ± 5%. Erase Resume (ER) instruction. If an Erase Suspend instruction was previously executed, the erase operation may be resumed by giving the command 30h, at any address, and without any coded cycles. Power Up The memory Command Interface is reset on power up to Read Array. Either E or W must be tied to VIH during Power-up to allow maximum security and the possibility to write a command on the first rising 14/31 adge of E or W. Any write cycle initiation is blocked when VCC is below VLKO. Supply Rails Normal precautions must be taken for supply voltage decoupling, each device in a system should have the VCC rail decoupled with a 1.0µF capacitor close to the VCC and VSS pins. The PCB trace widths should be sufficient to carry the VCC program and erase currents required. M29F040 Table 13B. Write AC Characteristics, Write Enable Controlled (TA = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C) M29F040 Symbol Alt Parameter -120 -150 VCC = 5V ± 10% VCC = 5V ± 10% Standard Interface Standard Interface Min tAVAV tWC Address Valid to Next Address Valid tELWL tCS tWLWH Max Min Unit Max 120 150 ns Chip Enable Low to Write Enable Low 0 0 ns tWP Write Enable Low to Write Enable High 50 50 ns tDVWH tDS Input Valid to Write Enable High 50 50 ns tWHDX tDH Write Enable High to Input Transition 0 0 ns tWHEH tCH Write Enable High to Chip Enable High 0 0 ns tWPH Write Enable High to Write Enable Low 20 20 ns tWHWL tAVWL tAS Address Valid to Write Enable Low 0 0 ns tWLAX tAH Write Enable Low to Address Transition 50 50 ns Output Enable High to Write Enable Low 0 0 ns VCC High to Chip Enable Low 50 50 µs Write Enable High to Output Valid (Program) 10 10 µs Write Enable High to Output Valid (Block Erase) 1.0 tGHWL tVCHEL tWHQV1 tVCS (1) tWHQV2 (1) tWHGL tOEH Write Enable High to Output Enable Low 0 30 1.0 0 30 sec ns Note: 1. Time is measured to Data Polling or Toggle Bit, tWHQV = tWHQ7V + tQ7VQV 15/31 M29F040 Figure 7. Write AC Waveforms, W Controlled WRITE CYCLE A0-A18 VALID tWLAX tAVWL tWHEH E tELWL tWHGL G tGHWL tWLWH W tWHWL tDVWH DQ0-DQ7 tWHDX VALID VCC tVCHEL Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W. 16/31 AI01365B M29F040 Table 14A. Write AC Characteristics, Chip Enable Controlled (TA = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C)(2) M29F040 Symbol Alt Parameter -70 -90 VCC = 5V ± 10% VCC = 5V ± 10% Standard Interface Standard Interface Min Max Min Unit Max tAVAV tWC Address Valid to Next Address Valid 70 90 ns tWLEL tWS Write Enable Low to Chip Enable Low 0 0 ns tELEH tCP Chip Enable Low to Chip Enable High 35 45 ns tDVEH tDS Input Valid to Chip Enable High 30 45 ns tEHDX tDH Chip Enable High to Input Transition 0 0 ns tEHWH tWH Chip Enable High to Write Enable High 0 0 ns tEHEL tCPH Chip Enable High to Chip Enable Low 20 20 ns tAVEL tAS Address Valid to Chip Enable Low 0 0 ns tELAX tAH Chip Enable Low to Address Transition 45 45 ns Output Enable High Chip Enable Low 0 0 ns VCC High to Write Enable Low 50 50 µs Chip Enable High to Output Valid (Program) 10 10 µs Chip Enable High to Output Valid (Block Erase) 1.0 tGHEL tVCHWL tEHQV1 tVCS (1) tEHQV2 (1) tEHGL tOEH Chip Enable High to Output Enable Low 0 30 1.0 30 0 sec ns Note: 1. Time is measured to Data Polling or Toggle Bit, tWHQV = tWHQ7V + tQ7VQV. 2. The temperature range –40 to 125°C is guaranteed at 70ns with High Speed Interface test condition and VCC = 5V ± 5%. 17/31 M29F040 Table 14B. Write AC Characteristics, Chip Enable Controlled (TA = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C) M29F040 Symbol Alt Parameter -120 -150 VCC = 5V ± 10% VCC = 5V ± 10% Standard Interface Standard Interface Min tAVAV tWC Address Valid to Next Address Valid tWLEL tWS tELEH Max Min Unit Max 120 150 ns Write Enable Low to Chip Enable Low 0 0 ns tCP Chip Enable Low to Chip Enable High 50 50 ns tDVEH tDS Input Valid to Chip Enable High 50 50 ns tEHDX tDH Chip Enable High to Input Transition 0 0 ns tEHWH tWH Chip Enable High to Write Enable High 0 0 ns tEHEL tCPH Chip Enable High to Chip Enable Low 20 20 ns tAVEL tAS Address Valid to Chip Enable Low 0 0 ns tELAX tAH Chip Enable Low to Address Transition 50 50 ns Output Enable High Chip Enable Low 0 0 ns VCC High to Write Enable Low 50 50 µs Chip Enable High to Output Valid (Program) 10 10 µs Chip Enable High to Output Valid (Block Erase) 1.0 tGHEL tVCHWL tEHQV1 tVCS (1) tEHQV2 (1) tEHGL tOEH Chip Enable High to Output Enable Low Note: 1. Time is measured to Data Polling or Toggle Bit, tWHQV = tWHQ7V + tQ7VQV. 18/31 0 30 1.0 0 30 sec ns M29F040 Figure 8. Write AC Waveforms, E Controlled WRITE CYCLE A0-A18 VALID tELAX tAVEL tEHWH W tWLEL tEHGL G tGHEL tELEH E tEHEL tDVEH DQ0-DQ7 tEHDX VALID VCC tVCHWL AI01366B Note: Address are latched on the falling edge of E, Data is latched on the rising edge of E. 19/31 M29F040 Table 15A. Data Polling and Toggle Bit AC Characteristics (1) (TA = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C)(3) M29F040 Symbol Parameter -70 -90 VCC = 5V ± 10% VCC = 5V ± 10% Standard Interface Standard Interface Min tWHQ7V1 (2) Write Enable High to DQ7 Valid (Program, W Controlled) 10 tWHQ7V2 (2) Write Enable High to DQ7 Valid (Block Erase, W Controlled) 1.0 tEHQ7V1 (2) Chip Enable High to DQ7 Valid (Program, E Controlled) 10 tEHQ7V2 (2) Chip Enable High to DQ7 Valid (Block Erase, E Controlled) 1.0 tQ7VQV Q7 Valid to Output Valid (Data Polling) tWHQV1 Write Enable High to Output Valid (Program) 10 tWHQV2 Write Enable High to Output Valid (Block Erase) 1.0 tEHQV1 Chip Enable High to Output Valid (Program) 10 tEHQV2 Chip Enable High to Output Valid (Block Erase) 1.0 Max Min Max µs 10 30 1.0 30 1.0 30 30 sec 35 ns µs 10 30 1.0 30 1.0 30 Notes: 1. All other timings are defined in Read AC Characteristics table. 2. tWHQ7V is the Program or Erase time. 3. The temperature range –40 to 125°C is guaranteed at 70ns with High Speed Interface test condition and VCC = 5V ± 5%. 20/31 sec µs 10 30 sec µs 10 30 Unit sec M29F040 Table 15B. Data Polling and Toggle Bit AC Characteristics (1) (TA = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C) M29F040 Symbol Parameter -120 150 VCC = 5V ± 10% VCC = 5V ± 10% Standard Interface Standard Interface Min tWHQ7V1 (2) Write Enable High to DQ7 Valid (Program, W Controlled) 10 tWHQ7V2 (2) Write Enable High to DQ7 Valid (Block Erase, W Controlled) 1.0 tEHQ7V1 (2) Chip Enable High to DQ7 Valid (Program, E Controlled) 10 tEHQ7V2 (2) Chip Enable High to DQ7 Valid (Block Erase, E Controlled) 1.0 tQ7VQV Q7 Valid to Output Valid (Data Polling) tWHQV1 Write Enable High to Output Valid (Program) 10 tWHQV2 Write Enable High to Output Valid (Block Erase) 1.0 tEHQV1 Chip Enable High to Output Valid (Program) 10 tEHQV2 Chip Enable High to Output Valid (Block Erase) 1.0 Max Min Unit Max µs 10 30 1.0 30 µs 10 30 1.0 50 30 sec 55 ns µs 10 30 1.0 30 1.0 sec µs 10 30 sec 30 sec Notes: 1. All other timings are defined in Read AC Characteristics table. 2. tWHQ7V is the Program or Erase time. 21/31 22/31 Notes: 1. 2. 3. 4. LAST CYCLE OF PROGRAM OR ERASE DATA POLLING READ CYCLES tWHQ7V tEHQ7V tELQV tAVQV tQ7VQV IGNORE DQ7 DATA POLLING (LAST) CYCLE tGLQV BYTE ADDRESS (WITHIN BLOCKS) All other timings are as a normal Read cycle. DQ7 and DQ0-DQ6 can transmit to valid at any point during the data output valid period. tWHQ7V is the Program or Erase time. During erasing operation Byte address must be within Block being erased. DQ0-DQ6 DQ7 W G E A0-A18 VALID VALID DATA OUTPUT VALID AI01364B DATA VERIFY READ CYCLE M29F040 Figure 9. Data Polling DQ7 AC Waveforms M29F040 Figure 10. Data Polling Flowchart Figure 11. Data Toggle Flowchart START START READ DQ5 & DQ7 at VALID ADDRESS READ DQ5 & DQ6 DQ7 = DATA DQ6 = TOGGLE YES YES NO NO NO DQ5 =1 DQ5 =1 YES YES READ DQ7 READ DQ6 DQ7 = DATA NO DQ6 = TOGGLE YES YES NO FAIL NO FAIL PASS PASS AI01370 AI01369 Table 16. Program, Erase Times and Program, Erase Endurance Cycles (TA = 0 to 70°C; VCC = 5V ± 10% or 5V ± 5%) M29F040 Parameter Min Chip Program (Byte) Typ 6 Chip Erase (Preprogrammed) 2.5 Chip Erase 8.5 Block Erase (Preprogrammed) 1 Block Erase Byte Program Program/Erase Cycles (per Block) Unit Max sec 30 sec 30 1.5 10 100,000 sec sec sec 1500 µs cycles 23/31 24/31 LAST CYCLE OF PROGRAM OF ERASE DATA TOGGLE READ CYCLE Note: All other timings are as a normal Read cycle. DQ0-DQ5, DQ7 DQ6 W G E A0-A18 DATA TOGGLE READ CYCLE IGNORE STOP TOGGLE tWHQV tEHQV tAVQV READ CYCLE VALID VALID tGLQV tELQV VALID AI01367 M29F040 Figure 12. Data Toggle DQ6 AC Waveforms M29F040 Figure 13. Block Protection Flowchart START BLOCK ADDRESS on A16, A17, A18 n=0 G, A9 = VID, E = VIL Wait 4µs W = VIL Wait 100µs W = VIH G = VIH Wait 4µs READ DQ0 at PROTECTION ADDRESS: A0, A6 = VIL, A1 = VIH and A16, A17, A18 DEFINING BLOCK DQ0 =1 NO YES A9 = VIH NO ++n = 25 PASS YES A9 = VIH FAIL AI01368D 25/31 M29F040 Figure 14. Block Unprotecting Flowchart START PROTECT ALL BLOCKS n=0 A6, A12, A16 = VIH E, G, A9 = VIH Wait 4µs E, G, A9 = VID Wait 4µs W = VIL Wait 10ms W = VIH E, G = VIH Wait 4µs READ at UNPROTECTION ADDRESS: A1, A6 = VIH, A0 = VIL and A16, A17, A18 DEFINING BLOCK (see Note 1) NO NO ++n = 1000 YES FAIL DATA = 00h INCREMENT BLOCK YES LAST SECT. NO YES PASS AI01371E Note: 1. A6 is kept at VIH during unprotection algorithm in order to secure best unprotection verification. During all other protection status reads, A6 must be kept at VIL. 26/31 M29F040 ORDERING INFORMATION SCHEME Example: M29F040 -70 X N 1 TR Operating Voltage F Option 5V R Reverse Pinout TR Tape & Reel Packing Speed Power Supplies Temp. Range Package -70 70ns blank VCC ± 10% K PLCC32 1 0 to 70 °C -90 90ns X VCC ± 5% N 3 –40 to 125 °C -120 120ns TSOP32 8 x 20mm 5 –20 to 85 °C -150 150ns 6 –40 to 85 °C M29F040 is replaced by the new version M29F040B Device are shipped from the factory with the memory content erased (to FFh). For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 27/31 M29F040 PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular mm Symb Typ inches Min Max A 2.54 A1 1.52 Typ Min Max 3.56 0.100 0.140 2.41 0.060 0.095 A2 – 0.38 – 0.015 B 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 0.032 D 12.32 12.57 0.485 0.495 D1 11.35 11.56 0.447 0.455 D2 9.91 10.92 0.390 0.430 E 14.86 15.11 0.585 0.595 E1 13.89 14.10 0.547 0.555 E2 12.45 13.46 0.490 0.530 – – – – 0.00 0.25 0.000 0.010 – – – – e 1.27 F R 0.89 0.050 0.035 N 32 32 Nd 7 7 Ne 9 9 CP 0.10 0.004 D D1 A1 A2 1 N B1 E1 E Ne e D2/E2 F B 0.51 (.020) 1.14 (.045) A Nd R PLCC Drawing is not to scale. 28/31 CP M29F040 TSOP32 Normal Pinout - 32 lead Plastic Thin Small Outline, 8 x 20mm mm Symb Typ inches Min Max A Typ Min 1.20 Max 0.047 A1 0.05 0.15 0.002 0.007 A2 0.95 1.05 0.037 0.041 B 0.15 0.27 0.006 0.011 C 0.10 0.21 0.004 0.008 D 19.80 20.20 0.780 0.795 D1 18.30 18.50 0.720 0.728 E 7.90 8.10 0.311 0.319 - - - - L 0.50 0.70 0.020 0.028 α 0° 5° 0° 5° N 32 e 0.50 0.020 32 CP 0.10 0.004 A2 N 1 e E B N/2 D1 A CP D DIE C TSOP-a A1 α L Drawing is not to scale. 29/31 M29F040 TSOP32 Reverse Pinout - 32 lead Plastic Thin Small Outline, 8 x 20mm mm Symb Typ inches Min Max A Typ Min 1.20 0.047 A1 0.05 0.17 0.002 0.006 A2 0.95 1.05 0.037 0.041 B 0.15 0.27 0.006 0.011 C 0.10 0.21 0.004 0.008 D 19.80 20.20 0.780 0.795 D1 18.30 18.50 0.720 0.728 E 7.90 8.10 0.311 0.319 – – – – L 0.50 0.70 0.020 0.028 α 0° 5° 0° 5° N 32 e 0.50 0.020 32 CP 0.10 0.004 A2 1 N e E B N/2 D1 A CP D DIE C TSOP-b Drawing is not to scale. 30/31 Max A1 α L M29F040 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 1999 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. 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