Intersil ISL28227FUZ Precision single and dual low noise operational amplifier Datasheet

ISL28127, ISL28227
Features
The ISL28127 and ISL28227 are very high precision
amplifiers featuring very low noise, low offset voltage,
low input bias current and low temperature drift making
them the ideal choice for applications requiring both high
DC accuracy and AC performance. The combination of
precision, low noise, and small footprint provides the
user with outstanding value and flexibility relative to
similar competitive parts.
• Very Low Voltage Noise . . . . . . . . . . . . . 2.5nV/Hz
Applications for these amplifiers include precision active
filters, medical and analytical instrumentation, precision
power supply controls, and industrial controls.
The ISL28127 single and ISL28227 dual are available in
an 8 Ld SOIC, TDFN and MSOP packages. All devices are
offered in standard pin configurations and operate over
the extended temperature range to -40°C to +125°C.
• Low Input Offset . . . . . . . . . . . . . . . 70µV, Max.
• Superb Offset Drift . . . . . . . . . . . 0.5µV/°C, Max.
• Input Bias Current . . . . . . . . . . . . . . 10nA, Max.
• Wide Supply Range. . . . . . . . . . . . . . 4.5V to 40V
• Gain-bandwidth Product . 10MHz Unity Gain Stable
• No Phase Reversal
Applications*(see page 20)
• Precision Instruments
• Medical Instrumentation
• Industrial Controls
• Active Filter Blocks
• Data Acquisition
• Power Supply Control
Related Literature*(see page 20)
• AN1508: ISL281X7SOICEVAL1Z Evaluation Board
User’s Guide
Typical Application
Input Noise Voltage Spectral
Density
C1
1.5nF
V+
VIN
R1
R2
95.3
232
68.3nF
OUTPUT
+
C2
V-
Sallen-Key Low Pass Filter (1MHz)
INPUT NOISE VOLTAGE (nV/√Hz)
100
VS = ±19V
AV = 1
10
1
0.1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
March 18, 2010
FN6633.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL28127, ISL28227
Precision Single and Dual Low Noise Operational
Amplifiers
ISL28127, ISL28227
Ordering Information
.
PART NUMBER
(Notes 3, 4)
PART
MARKING
ISL28127FBZ (Note 1)
28127 FBZ
Coming Soon
ISL28127FRTBZ (Note 2)
127Z
Coming Soon
ISL28127FRTZ (Note 2)
-C 127Z
Coming Soon
ISL28127FUBZ (Note 2)
8127Z
ISL28127FUZ (Note 2)
8127Z -C
ISL28227FBZ (Note 2)
28227 FBZ
Coming Soon
ISL28227FRTBZ (Note 2)
227Z
Coming Soon
ISL28227FRTZ (Note 2)
-C 227Z
Coming Soon
ISL28227FUBZ (Note 2)
8227Z
Coming Soon
ISL28227FUZ (Note 2)
8227Z -C
ISL28127SOICEVAL1Z
Evaluation Board
VOS (MAX)
(µV)
70
PACKAGE
(Pb-Free)
PKG.
DWG. #
8 Ld SOIC
M8.15E
8 Ld TDFN
L8.3x3A
8 Ld TDFN
L8.3x3A
8 Ld MSOP
M8.118
150 (C Grade)
8 Ld MSOP
M8.118
75
8 Ld SOIC
M8.15E
8 Ld TDFN
L8.3x3A
8 Ld TDFN
L8.3x3A
8 Ld MSOP
M8.118
8 Ld MSOP
M8.118
TBD (B Grade)
150 (C Grade)
TBD (B Grade)
TBD (B Grade)
150 (C Grade)
TBD (B Grade)
150 (C Grade)
1. Add “-T7” or “-T13” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. Add “-T13” suffix for tape and reel.Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see device information page for ISL28127, ISL28227. For more information on
MSL please see techbrief TB363.
2
FN6633.3
March 18, 2010
ISL28127, ISL28227
Pin Configurations
ISL28227
(8 LD SOIC, MSOP)
TOP VIEW
ISL28127
(8 LD SOIC, MSOP)
TOP VIEW
8 NC
VOUTA
1
7 V+
-IN_A
2
+IN_A
3
V-
4
NC
1
-IN_A
2
+IN_A
3
6 VOUTA
V-
4
5 NC
-+
-IN_A 2
7 V+
- +
+IN 3
+IN_A 3
6 VOUT
PD
V- 4
+ -
6 -IN_B
5 +IN_B
VOUT_A 1
8 NC
-IN 2
7 VOUTB
- +
ISL28227
(8 LD TDFN)
TOP VIEW
ISL28127
(8 LD TDFN)
TOP VIEW
NC 1
8 V+
V- 4
5 NC
8 V+
7 VOUT_B
- +
PD
+ -
6 -IN_B
5 +IN_B
Pin Descriptions
ISL28227
ISL28127
(8 LD SOIC,
ISL28127 (8 LD SOIC, ISL28227
8 LD MSOP) (8 LD TDFN) 8 LD MSOP) (8 LD TDFN)
3
3
4
4
PIN
NAME
EQUIVALENT
CIRCUIT
+IN
Circuit 1
Amplifier non-inverting input
DESCRIPTION
3
3
+IN_A
Circuit 1
Amplifier A non-inverting input
4
4
V-
Circuit 3
Negative power supply
5
5
+IN_B
Circuit 1
Amplifier B non-inverting input
-IN
Circuit 1
Amplifier inverting input
-IN_B
Circuit 1
Amplifier B inverting input
VOUT
Circuit 2
Amplifier output
2
6
6
6
7
7
VOUTB
Circuit 2
Amplifier B output
8
8
V+
Circuit 3
Positive power supply
6
1
1
VOUTA
Circuit 2
Amplifier A output
2
2
2
-IN_A
Circuit 1
Amplifier A inverting input
1, 5, 8
NC
-
Not Connected – This pin is not
electrically connected internally.
PD
PD
-
Thermal Pad. Pad should be
connecte to lowest potential source
in the circuit.
7
1, 5, 8
7
V+
IN-
V+
V-
VCIRCUIT 2
3
CAPACITIVELY
TRIGGERED
ESD CLAMP
OUT
IN+
CIRCUIT 1
V+
VCIRCUIT 3
FN6633.3
March 18, 2010
ISL28127, ISL28227
Absolute Maximum Ratings
Thermal Information
Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 42V
Maximum Differential Input Current . . . . . . . . . . . . . 20mA
Maximum Differential Input Voltage . . . . . . . . . . . . . . .0.5V
Min/Max Input Voltage . . . . . . . . . . . V- - 0.5V to V+ + 0.5V
Max/Min Input Current for
Input Voltage >V+ or <V- . . . . . . . . . . . . . . . . . . ±20mA
Output Short-Circuit Duration
(1 Output at a Time) . . . . . . . . . . . . . . . . . . . . Indefinite
ESD Tolerance
Human Body Model (Tested per JESD22-A114F)
ISL28127. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0kV
ISL28227. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.0kV
Machine Model (Tested per EIA/JESD22-A115-A) . . . . 500V
Charged Device Model (Tested per JESD22-C101D) . . 1.5kV
Di-electrically Isolated PR40 process. . . . . . . . Latch-up free
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
8 Ld SOIC (Note 5, 7)
ISL28127 . . . . . . . . . . . . . . . . .
120
60
ISL28227 . . . . . . . . . . . . . . . . .
110
55
8 Ld TDFN (Notes 5, 6)
ISL28127 . . . . . . . . . . . . . . . . .
48
7
ISL28227 . . . . . . . . . . . . . . . . .
47
6
8 Ld MSOP (Note 5, 7)
ISL28127 . . . . . . . . . . . . . . . . .
155
50
ISL28227 . . . . . . . . . . . . . . . . .
150
45
Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Ambient Operating Temperature Range . . . -40°C to +125°C
Maximum Operating Junction Temperature . . . . . . . +150°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
6. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
7. For θJC, the “case temp” location is taken at the package top center.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless
otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications VS ±15V, VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits
apply over the operating temperature range, -40°C to +125°C. Temperature data
established by characterization.
PARAMETER
VOS
DESCRIPTION
Offset Voltage; SOIC Package
CONDITIONS
ISL28127
ISL28227
TCVOS
IOS
IB
VCM
CMRR
MIN
(Note 8)
TYP
MAX
(Note 8)
UNIT
-70
10
70
µV
-120
-
120
µV
-75
10
75
µV
-150
-
150
µV
-150
10
150
µV
-250
-
250
µV
Offset Voltage;
MSOP, TDFN Grade C Package
ISL28127
ISL28227
Offset Voltage Drift;
SOIC Pacakge
ISL28127
-0.5
0.1
0.5
µV/°C
ISL28227
-0.75
0.1
0.75
µV/°C
Offset Voltage Drift;
MSOP, TDFN, Grade C
ISL28127
ISL28227
-1
0.1
1
µV/°C
-10
1
10
nA
-12
-
12
nA
-10
1
10
nA
-12
-
12
nA
-13
-
13
V
-12
-
12
V
VCM = -13V to +13V
115
120
-
dB
VCM = -12V to +12V
115
-
-
dB
Input Offset Current
Input Bias Current
Input Voltage Range
Common-Mode Rejection Ratio
4
Guaranteed by CMRR
FN6633.3
March 18, 2010
ISL28127, ISL28227
Electrical Specifications VS ±15V, VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits
apply over the operating temperature range, -40°C to +125°C. Temperature data
established by characterization. (Continued)
PARAMETER
PSRR
DESCRIPTION
CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNIT
Power Supply Rejection Ratio
ISL28127
VS = ±2.25V to ±20V
115
125
-
dB
VS = ±3V to ± 20V
115
-
-
dB
Power Supply Rejection Ratio
ISL28227
VS = ±2.25V to ±20V
110
117
-
dB
VS = ±3V to ± 20V
110
-
-
dB
AVOL
Open-Loop Gain
VO = -13V to +13V
RL = 10kΩ to ground
1000
1500
-
V/mV
VOH
Output Voltage High
RL = 10kΩ to ground
13.5
13.65
-
V
13.2
-
-
V
13.4
13.5
-
V
13.1
-
-
V
RL = 2kΩ to ground
VOL
Output Voltage Low
RL = 10kΩ to ground
RL = 2kΩ to ground
IS
ISC
VSUPPLY
Supply Current/Amplifier
Short-Circuit
RL = 0Ω to ground
Supply Voltage Range
Guaranteed by PSRR
-
-13.65
-13.5
V
-
-
-13.2
V
-
-13.5
-13.4
V
-
-
-13.1
V
-
2.2
2.8
mA
-
-
3.7
mA
-
±45
-
mA
±2.25
-
±20
V
AC SPECIFICATIONS
GBW
Gain Bandwidth Product
enp-p
Voltage Noise
0.1Hz to 10Hz
10
MHz
85
nVP-P
en
Voltage Noise Density
f = 10Hz
3
nV/√Hz
en
Voltage Noise Density
f = 100Hz
2.8
nV/√Hz
en
Voltage Noise Density
f = 1kHz
2.5
nV/√Hz
en
Voltage Noise Density
f = 10kHz
2.5
nV/√Hz
in
Current Noise Density
f = 10kHz
0.4
pA/√Hz
Total Harmonic Distortion +
Noise
1kHz, G = 1, VO = 3.5VRMS,
RL = 2kΩ
0.00022
%
THD + N
TRANSIENT RESPONSE
SR
tr, tf, Small
Signal
ts
tOL
Slew Rate
AV = 10, RL = 2kΩ, VO = 4VP-P
±3.6
V/µs
Rise Time
10% to 90% of VOUT
AV = -1, VOUT = 100mVP-P,
Rf = Rg = 2kΩ, RL = 2kΩ to VCM
36
ns
Fall Time
90% to 10% of VOUT
AV = -1, VOUT = 100mVP-P,
Rf = Rg = 2kΩ, RL = 2kΩ to VCM
38
ns
Settling Time to 0.1%
10V Step; 10% to VOUT
AV = -1 VOUT = 10VP-P,
Rg = Rf =10k, RL = 2kΩ to VCM
3.4
µs
Settling Time to 0.01%
10V Step; 10% to VOUT
AV = -1, VOUT = 10VP-P,
RL = 2kΩ to VCM
3.8
µs
1.7
µs
Output Overload Recovery Time AV = 100, VIN = 0.2V
RL = 2kΩ to VCM
5
FN6633.3
March 18, 2010
ISL28127, ISL28227
Electrical Specifications VS ±5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply over
the operating temperature range, -40°C to +125°C. Temperature data established
by characterization.
PARAMETER
VOS
DESCRIPTION
CONDITIONS
Offset Voltage
MIN
(Note 8)
TYP
MAX
(Note 8)
UNIT
-70
10
70
µV
-120
-
120
µV
VOS/T
Offset Voltage Drift
-0.5
0.1
0.5
µV/°C
IOS
Input Offset Current
-10
1
10
nA
-12
-
12
nA
10
1
10
nA
-12
-
12
nA
-3
-
3
V
-2
-
2
V
IB
VCM
CMRR
Input Bias Current
Common Mode Input Voltage
Range
Common-Mode Rejection Ratio
Guaranteed by CMRR
VCM = -3V to +3V
115
120
-
dB
VCM = -2V to +2V
115
-
-
dB
VS = ±2.25V to ±5V
115
125
-
dB
PSRR
Power Supply Rejection Ratio
VS = ±3V to ±5V
115
-
-
dB
AVOL
Open-Loop Gain
VO = -3V to +3V
RL = 10kΩ to ground
1000
1500
-
V/mV
VOH
Output Voltage High
RL = 10kΩ to ground
3.5
3.65
-
V
3.2
-
-
V
3.4
3.5
-
3.1
-
-
V
-
-3.65
-3.5
V
-
-
-3.2
V
-
-3.5
-3.4
-
-
-3.1
V
-
2.2
2.8
mA
-
-
3.7
mA
-
± 45
-
mA
RL = 2kΩ to ground
VOL
Output Voltage Low
RL = 10kΩ to ground
RL = 2kΩ to ground
IS
ISC
Supply Current/Amplifier
Short-Circuit
AC SPECIFICATIONS
GBW
THD + N
Gain Bandwidth Product
Total Harmonic Distortion +
Noise
1kHz, G = 1, Vo = 2.5VRMS,
RL = 2kΩ
10
MHz
0.0034
%
±3.6
V/µs
TRANSIENT RESPONSE
SR
tr, tf, Small
Signal
ts
Slew Rate
AV = 10, RL = 2kΩOH
Rise Time
10% to 90% of VOUT
AV = -1, VOUT = 100mVP-P,
Rf = Rg = 2kΩ, RL = 2kΩ to VCM
36
ns
Fall Time
90% to 10% of VOUT
AV = -1, VOUT = 100mVP-P,
Rf = Rg = 2kΩ, RL = 2kΩ to VCM
38
ns
Settling Time to 0.1%
AV = -1, VOUT = 4VP-P,
Rf = Rg = 2kΩ, RL = 2kΩ to VCM
1.6
µs
Settling Time to 0.01%
AV = -1, VOUT = 4VP-P,
Rf = Rg = 2kΩ, RL = 2kΩ to VCM
4.2
µs
NOTE:
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
6
FN6633.3
March 18, 2010
ISL28127, ISL28227
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, unless otherwise
specified.
100
80
60
40
20
0
-20
V+ = 38V
RL = 10k
CL = 3.5pF
Rg = 10, Rf = 100k
AV = 10,000
-40
-60
-80
-100
0
1
2
3
4
5
6
7
8
9
10
INPUT NOISE VOLTAGE (nV/√Hz)
INPUT NOISE VOLTAGE (nV)
100
TIME (s)
10
PSRR (dB)
INPUT NOISE CURRENT (pA/√Hz)
VS = ±19V
AV = 1
1
10
100
1
0.1
1
10
1k
10k
130
120
110
100
90
80
70
60
50
40
30
20
10
0
-10
100k
10k
100k
PSRR+ and PSRR- VS = ±5V
RL = INF
CL = 5.25pF
AV = +1
VS = 1VP-P
PSRR+ and PSRR- VS = ±15V
10
100
1k
FREQUENCY (Hz)
130
VS = ±5V
120
110
VS = ±2.25V
100
90
80
70
VS = ±15V
60
50
40
RL = INF
30
CL = 5.25pF
20
AV = +1
10
0 VCM = 1VP-P
-10
10
100
1k
10k
100k
10k
100k
1M
10M
FIGURE 4. PSRR vs FREQUENCY, VS = ±5V, ±15V
25
MEDIAN
20
15
VOS (µV)
CMRR (dB)
1k
FREQUENCY (Hz)
FIGURE 3. INPUT NOISE CURRENT SPECTRAL
DENSITY
VS = ±21V
10
5
VS = ±15V
0
-5
-10
VS = ±3V
VS = ±5V
-15
1M
10M
FREQUENCY (Hz)
FIGURE 5. CMRR vs FREQUENCY, VS = ±2.25, ±5V,
±15V
7
100
FIGURE 2. INPUT NOISE VOLTAGE SPECTRAL
DENSITY
100
1
10
FREQUENCY (Hz)
FIGURE 1. INPUT NOISE VOLTAGE 0.1Hz to 10Hz
0.1
0.1
VS = ±19V
AV = 1
36 UNITS
-20
-40 -20 0
20
40
60
80
100 120 140 160
TEMPERATURE (°C)
FIGURE 6. VOS vs TEMPERATURE vs VSUPPLY
FN6633.3
March 18, 2010
ISL28127, ISL28227
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, unless otherwise
specified. (Continued)
3.0
4.5
50 UNITS
4.0
MEDIAN
IBIASIBIAS (nA)
IBIAS (nA)
3.5
2.5
3.0
2.5
2.0
IBIAS+
50 UNITS
MEDIAN
2.0
IBIAS+
1.5
1.0
IBIAS-
1.5
0.5
1.0
0.5
-40
-20
0
20
40
60
80
100
0
-40
120
-20
0
20
60
80
100
120
FIGURE 7. IIB vs TEMPERATURE, VS = ±15V
FIGURE 8. IIB vs TEMPERATURE, VS = ±5V
0.5
60
29 UNITS
vs = ±5
0.0
vs = ±15
MEDIAN
20
VOS (µV)
-1.0
-1.5
AVERAGE
40
50 UNITS
-0.5
IOS (nA)
40
TEMPERATURE (°C)
TEMPERATURE (°C)
-2.0
+25°C
0
+125°C
-20
-2.5
-3.5
-40°C
-40
-3.0
-40
-20
0
20
40
60
80
100
-60
120
-15
-10
FIGURE 9. IOS vs TEMPERATURE vs SUPPLY
50 UNITS
-13.2
MEDIAN
10
15
50 UNITS
-13.4
VOUT (V)
13.8
RL = 100k
13.7
13.6
RL = 2k
13.5
MEDIAN
-13.3
13.9
VOUT (V)
5
-13.1
14.0
RL = 2k
-13.5
-13.6
-13.7
RL = 100k
-13.8
-13.9
13.4
-14.0
13.3
-14.1
13.2
0
FIGURE 10. INPUT OFFSET VOLTAGE vs INPUT
COMMON MODE VOLTAGE, VS = ±15V
14.2
14.1
-5
INPUT COMMON MODE VOLTAGE
TEMPERATURE (°C)
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 11. VOH vs TEMPERATURE, VS = ±15V
8
-14.2
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 12. VOL vs TEMPERATURE, VS = ±15V
FN6633.3
March 18, 2010
ISL28127, ISL28227
200
180
160
140
120
100
80
60
40
20
0
-20 R = 10k
L
-40
CL = 10pF
-60
SIMULATION
-80
-100
0.1m1m 10m100m 1
VS = ±15V, VCM = 0V, RL = Open, unless otherwise
specified. (Continued)
OPEN LOOP GAIN (dB)/PHASE(°)
OPEN LOOP GAIN (dB)/PHASE (°)
Typical Performance Curves
PHASE
GAIN
10 100 1k 10k100k 1M 10M 100M
200
180
160
140
120
100
80
60
40
20
0
-20 R = 10k
L
-40
CL = 100pF
-60
SIMULATION
-80
-100
0.1m1m 10m100m 1
70
15
Rg = 100, Rf = 100k
AV = 100
VS = ±15V
CL = 3.5pF
RL = INF
VOUT = 100mVP-P
30
20
AV = 10
Rg = 10k, Rf = 100k
10
0
AV = 1
-10
100
NORMALIZED GAIN (dB)
GAIN (dB)
40
Rg = OPEN, Rf = 0
1k
10k
100k
1M
10M
Rf = Rg = 100k
13
Rg = 1k, Rf = 100k
50
Rf = Rg = 1k
9
7
5
3
1
VS = ±15V
RL = 10k
CL = 3.5pF
AV = +2
-3
VOUT = 100mVP-P
1k
10k
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
RL = 1k
0
RL = 499
-4
RL = 100
VS = ±15V
RL = 49.9
CL = 3.5pF
AV = +1
VOUT = 100mVP-P
-5
1k
10k
6
1M
10M
FREQUENCY (Hz)
FIGURE 17. GAIN vs FREQUENCY vs RL
9
100M
5
4
3
VS = ±15V
RL = 10k
AV = +1
CL = 1000pF
VOUT = 100mVP-P
CL = 220pF
CL = 100pF
2
CL = 25.5pF
1
0
-1
CL = 3.5pF
-2
100k
10M
7
RL = 10k
-3
1M
FIGURE 16. FREQUENCY RESPONSE vs FEEDBACK
RESISTANCE Rf/Rg
2
-2
100k
FREQUENCY (Hz)
FIGURE 15. FREQUENCY RESPONSE vs CLOSED LOOP
GAIN
-1
Rf = Rg = 100
-1
-5
100M
Rf = Rg = 10k
11
FREQUENCY (Hz)
1
10 100 1k 10k100k 1M 10M 100M
FIGURE 14. OPEN-LOOP GAIN, PHASE vs
FREQUENCY, RL = 10kΩ, CL = 100pF
FIGURE 13. OPEN-LOOP GAIN, PHASE vs
FREQUENCY, RL = 10kΩ, CL = 10pF
AV = 1000
GAIN
FREQUENCY (Hz)
FREQUENCY (Hz)
60
PHASE
100M
-3
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 18. GAIN vs FREQUENCY vs CL
FN6633.3
March 18, 2010
ISL28127, ISL28227
Typical Performance Curves
6
VS = ±2.25V
5
4
0
VS = ±5V
-1
VS = ±15V
CL = 3.5pF
RL = 10k
AV = +1
VOUT = 100mVP-P
10k
1k
VS = ±15V
CL = 3.5pF
AV = 1
Rf = 0 Rg = inf
VOUT = 10VP-P
3
2
1
0
1
-2
RL = 2k
-3
RL = 10k
-4
-5
100k
1M
10M
-6
100M
0
5
10
2.4
SMALL SIGNAL (mV)
LARGE SIGNAL (V)
1.2
VS = ±15V, RL = 2k, 10k
0.8
0.4
0
-0.4
VS = ±5V, RL = 2k, 10k
-0.8
-1.2
CL = 3.5pF
AV = 1
VOUT = 4VP-P
-1.6
-2.0
0
5
10
15
20
40
20
VS = ±5V, ±15V
0
20
RL = 2k
CL = 3.5pF
AV = 1
VOUT = 100mVP-P
40
60
25
30
35
80
40
0
0.2
0.4
TIME (µs)
0.06
VS = ±15V
RL = 10k
CL = 3.5pF
AV = 100
Rf = 100k, Rg = 1k
VIN = 200mVP-P
-0.14
-0.18
-0.20
OUTPUT
5
10
15
20
25
TIME (µs)
30
FIGURE 23. POSITIVE OUTPUT OVERLOAD
RESPONSE TIME, VS = ±15V
10
35
13
0.22
11
0.08
9
7
5
INPUT (V)
-0.02
-0.10
1.0
1.2
1.4
1.6
0.26
OUTPUT (V)
INPUT
-0.06
0.8
1.8
2.0
FIGURE 22. SMALL SIGNAL TRANSIENT RESPONSE,
VS = ±5V, ±15V
15
0.02
0.6
TIME (ms)
FIGURE 21. LARGE SIGNAL TRANSIENT RESPONSE vs
RL VS = ±5V, ±15V
INPUT (V)
30
60
1.6
0
25
80
2.0
-0.26
20
FIGURE 20. LARGE SIGNAL 10V STEP RESPONSE,
VS = ±15V
FIGURE 19. GAIN vs FREQUENCY vs SUPPLY
VOLTAGE
-2.4
15
TIME (µs)
FREQUENCY (Hz)
0.10
0.06
0.02
1
-0.02
-0.06
0
0
-2
VS = ±15V
RL = 10k
CL = 3.5pF
AV = 100
Rf = 100k, Rg = 1k
VIN = 200mVP-P
0.04
3
-1
40
2
OUTPUT
-4
-6
-8
OUTPUT (V)
-2
-3
LARGE SIGNAL (V)
NORMALIZED GAIN (dB)
1
VS = ±15V, VCM = 0V, RL = Open, unless otherwise
specified. (Continued)
-10
INPUT
-12
5
10
15
20
25
TIME (µs)
30
35
-14
40
FIGURE 24. NEGATIVE OUTPUT OVERLOAD
RESPONSE TIME, VS = ±15V
FN6633.3
March 18, 2010
ISL28127, ISL28227
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, unless otherwise
specified. (Continued)
90
80
VS = ±15V
RL = 10k
AV = 1
VOUT = 100mVP-P
OVERSHOOT (%)
70
60
50
40
+
OT
HO
S
ER
OV
T
OO
SH
ER
V
O
30
20
-
10
0
10
100
1000
CAPACITANCE (pF)
10000
FIGURE 25. % OVERSHOOT vs LOAD CAPACITANCE, VS = ±15V
Applications Information
Functional Description
The ISL28127 and ISL28227 are single and dual, low
noise 10MHz BW precision op amps. Both devices are
fabricated in a new precision 40V complementary bipolar
DI process. A super-beta NPN input stage with input bias
current cancellation provides low input bias current (1nA
typical), low input offset voltage (10µV typ), low input
noise voltage (3nV/√Hz), and low 1/f noise corner
frequency (5Hz). These amplifiers also feature high open
loop gain (1500V/mV) for excellent CMRR (120dB) and
THD+N performance (0.0002% @ 3.5VRMS, 1kHz into
2kΩ). A complimentary bipolar output stage enables high
capacitive load drive without external compensation.
Operating Voltage Range
The devices are designed to operate over the 4.5V
(±2.25V) to 40V (±20V) range and are fully
characterized at 10V (±5V) and 30V (±15V). Parameter
variation with operating voltage is shown in the “Typical
Performance Curves” beginning on page 7.
Input ESD Diode Protection
The input terminals (IN+ and IN-) have internal ESD
protection diodes to the positive and negative supply
rails, and an additional anti-parallel diode pair across
the inputs (see Figures 26 and 27).
For unity gain applications (see Figure 26) where the
output is connected directly to the non-inverting input a
current limiting resistor (RIN) will be needed under the
following conditions to protect the anti-parallel
differential input protection diodes.
• The amplifier input is supplied from a low impedance
source.
• The input voltage rate-of-rise (dV/dt) exceeds the
maximum slew rate of the amplifier (±3.6V/µs).
If the output lags far enough behind the input, the
anti-parallel input diodes can conduct. For example, if
an input pulse ramps from 0V to +10V in 1µs, then the
output of the ISL28x27 will reach only +3.6V (slew
rate = 3.6V/µs) while the input is at 10V, The input
differential voltage of 6.4V will force input ESD diodes to
conduct, dumping the input current directly into the
output stage and the load. The resulting current flow
can cause permanent damage to the ESD diodes. The
ESD diodes are rated to 20mA, and in the previous
example, setting RIN to 1k resistor (see Figure 26)
would limit the current to < 6.4mA, and provide
additional protection up to ±20V at the input.
In applications where one or both amplifier input
terminals are at risk of exposure to high voltage, current
limiting resistors may be needed at each input terminal
(see Figure 27 RIN+, RIN-) to limit current through the
power supply ESD diodes to 20mA.
V+
V+
VIN
RIN
VOUT
+
RL
V-
FIGURE 26. INPUT ESD DIODE CURRENT LIMITINGUNITY GAIN
11
VINVIN+
RIN-
-
RIN
+
VOUT
RL
V-
FIGURE 27. INPUT ESD DIODE CURRENT LIMITING DIFFERENTIAL INPUT
FN6633.3
March 18, 2010
ISL28127, ISL28227
Output Current Limiting
ISL28127 and ISL28227 SPICE Model
The output current is internally limited to approximately
±45mA at +25°C and can withstand an short circuit to
either rail as long as the power dissipation limits are not
exceeded. This applies to only 1 amplifier at a time for
the dual op amp. Continuous operation under these
conditions may degrade long term reliability.
Figure 28 shows the SPICE model schematic and
Figure 29 shows the net list for the ISL28127 and
ISL28227 SPICE model. The model is a simplified
version of the actual device and simulates important AC
and DC parameters. AC parameters incorporated into
the model are: 1/f and flatband noise, Slew Rate,
CMRR, Gain and Phase. The DC parameters are VOS,
IOS, total supply current and output voltage swing. The
model does not model input bias current. The model
uses typical parameters given in the “Electrical
Specifications” Table beginning on page 4. The AVOL is
adjusted for 128dB with the dominate pole at 5Hz. The
CMRR is set higher than the “Electrical Specifications”
Table to better match design simulations (150dB,
f = 50Hz). The input stage models the actual device to
present an accurate AC representation. The model is
configured for ambient temperature of +25°C.
Output Phase Reversal
Output phase reversal is a change of polarity in the
amplifier transfer function when the input voltage
exceeds the supply voltage. The ISL28127 and ISL28227
are immune to output phase reversal, even when the
input voltage is 1V beyond the supplies.
Power Dissipation
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power supply
conditions. It is therefore important to calculate the
maximum junction temperature (TJMAX) for all
applications to determine if power supply voltages, load
conditions, or package type need to be modified to
remain in the safe operating area. These parameters are
related using Equation 1:
(EQ. 1)
T JMAX = T MAX + θ JA xPD MAXTOTAL
where:
• PDMAXTOTAL is the sum of the maximum power
dissipation of each amplifier in the package (PDMAX)
• PDMAX for each amplifier can be calculated using
Equation 2:
V OUTMAX
PD MAX = V S × I qMAX + ( V S - V OUTMAX ) × ---------------------------R
L
(EQ.2)
where:
• TMAX = Maximum ambient temperature
• θJA = Thermal resistance of the package
• PDMAX = Maximum power dissipation of 1 amplifier
• VS = Total supply voltage
• IqMAX = Maximum quiescent supply current of 1
amplifier
• VOUTMAX = Maximum output voltage swing of the
application
RL = Load resistance
12
Figures 30 through 45 show the characterization vs
simulation results for the Noise Voltage, Closed Loop
Gain vs Frequency, Closed Loop Gain vs Rf/Rg, Closed
Loop Gain vs RL, Closed Loop Gain vs CL, Large Signal
10V Step Response, Open Loop Gain Phase and
Simulated CMRR vs Frequency.
LICENSE STATEMENT
The information in this SPICE model is protected under
the United States copyright laws. Intersil Corporation
hereby grants users of this macro-model hereto referred
to as “Licensee”, a nonexclusive, nontransferable licence
to use this model as long as the Licensee abides by the
terms of this agreement. Before using this macro-model,
the Licensee should read this license. If the Licensee
does not accept these terms, permission to use the
model is not granted.
The Licensee may not sell, loan, rent, or license the
macro-model, in whole, in part, or in modified form, to
anyone outside the Licensee’s company. The Licensee
may modify the macro-model to suit his/her specific
applications, and the Licensee may make copies of this
macro-model for use within their company only.
This macro-model is provided “AS IS, WHERE IS, AND
WITH NO WARRANTY OF ANY KIND EITHER EXPRESSED
OR IMPLIED, INCLUDING BUY NOT LIMITED TO ANY
IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE.”
In no event will Intersil be liable for special, collateral,
incidental, or consequential damages in connection with
or arising out of the use of this macro-model. Intersil
reserves the right to make changes to the product and
the macro-model without prior notice.
FN6633.3
March 18, 2010
ISL28127, ISL28227
.
V++
V++
R3
R4
4.45k
4.45k
4
5
CASCODE
Q4
D1
SUPERB
DX
R1
8
D12
C6
2pF
0.1V
EOS
1
IOS
Mirror
VCM
1E-9
+
-
5E11
+
-
En
+ VOS
-
In+
VIN+
Vmid
9
IEE
200E-6
R2
377.4
Vc
+
-
+
-
Q3
R17
25
C5
2.5pF
7
5E11
24
5
3
-
+
2
4
6
Q1 Q2
V5
DN
CASCODE
Q5
C4
2.5pF SUPERB
Vin-
VIN-
IEE1
96E-6
10E-6
V-VCM
Voltage Noise
Input Stage
V++
V++
10
+
-
4
5
D2
DX
+
V1
- 1.86V
G3
13
+
-
R5
1
D4
DX
+
V3
- 1.86V
11
G5
R7
572.9E6
Vg
12
-
R8
G4
V2
1.86V
+
+
-
+
D3
DX
+
V-VCM
R6
1
G2
1ST Gain Stage
14
-
3.18E-3
17
R11
1
Vc
Vmid
Vc
Vmid
+
-
R9
1
C2
55.55pF
R10
1
C3
572.9E6
V4
1.86V
L1
55.55pF
R12
1
G6
18
VCM
D5
DX
Vg
+
-
G1
L2
3.18E-3
V--
2nd Gain Stage
Mid Supply Ref
Common Mode Gain Stage
V++
+
-
D9
DX
G7
+
E2
22
ISY
2.2mA
Vg
D6
DX
23
V5
20
1.12V
V-
1.12V
G8
+
E3
V-
V--
D10
DY
+
G9
+
-
D11
DY
R16
90
+
-
+
VOUT
VOUT
V6
21
+
DX
-
D7
R15
90
-
+
-
D8
DX
V+
+
V+
G10
Output Stage
Supply Isolation Stage
FIGURE 28. SPICE SCHEMATIC
13
FN6633.3
March 18, 2010
ISL28127, ISL28227
* source ISL28127_SPICEmodel
* Revision C, August 8th 2009 LaFontaine
* Model for Noise, supply currents, 150dB f=50Hz
CMRR, *128dB f=5Hz AOL
*Copyright 2009 by Intersil Corporation
*Refer to data sheet “LICENSE STATEMENT” Use of
*this model indicates your acceptance with the
*terms and provisions in the License Statement.
* Connections: +input
*
|
-input
*
|
|
+Vsupply
*
|
|
|
-Vsupply
*
|
|
|
|
output
*
|
|
|
|
|
.subckt ISL28127subckt Vin+ Vin-V+ V- VOUT
* source ISL28127_SPICEMODEL_0_0
*
*Voltage Noise
E_En
IN+ VIN+ 25 0 1
R_R17
25 0 377.4 TC=0,0
D_D12
24 25 DN
V_V7
24 0 0.1
*
*Input Stage
I_IOS
IN+ VIN- DC 1e-9
C_C6
IN+ VIN- 2E-12
R_R1
VCM VIN- 5e11 TC=0,0
R_R2
IN+ VCM 5e11 TC=0,0
Q_Q1
2 VIN- 1 SuperB
Q_Q2
3 8 1 SuperB
Q_Q3
V-- 1 7 Mirror
Q_Q4
4 6 2 Cascode
Q_Q5
5 6 3 Cascode
R_R3
4 V++ 4.45e3 TC=0,0
R_R4
5 V++ 4.45e3 TC=0,0
C_C4 VIN- 0 2.5e-12
C_C5 8 0 2.5e-12
D_D1
6 7 DX
I_IEE
1 V-- DC 200e-6
I_IEE1
V++ 6 DC 96e-6
V_VOS
9 IN+ 10e-6
E_EOS
8 9 VC VMID 1
*
*1st Gain Stage
G_G1
V++ 11 4 5 0.0487707
G_G2
V-- 11 4 5 0.0487707
R_R5
11 V++ 1 TC=0,0
R_R6
V-- 11 1 TC=0,0
D_D2
10 V++ DX
D_D3
V-- 12 DX
V_V1
10 11 1.86
V_V2
11 12 1.86
*
*2nd Gain Stage
G_G3
V++ VG 11 VMID 4.60767E-3
G_G4
V-- VG 11 VMID 4.60767E-3
R_R7
VG V++ 572.958E6 TC=0,0
R_R8
V-- VG 572.958E6 TC=0,0
C_C2
VG V++ 55.55e-12 TC=0,0
C_C3
V-- VG 55.55e-12 TC=0,0
D_D4
13 V++ DX
D_D5
V-- 14 DX
V_V3
13 VG 1.86
V_V4
VG 14 1.86
*
*Mid supply Ref
R_R9
VMID V++ 1 TC=0,0
R_R10
V-- VMID 1 TC=0,0
I_ISY
V+ V- DC 2.2E-3
E_E2
V++ 0 V+ 0 1
E_E3
V-- 0 V- 0 1
*
*Common Mode Gain Stage with Zero
G_G5
V++ VC VCM VMID 31.6228e-9
G_G6
V-- VC VCM VMID 31.6228e-9
R_R11
VC 17 1 TC=0,0
R_R12
18 VC 1 TC=0,0
L_L1
17 V++ 3.183e-3
L_L2
18 V-- 3.183e-3
*
*Output Stage with Correction Current Sources
G_G7
VOUT V++ V++ VG 1.11e-2
G_G8
V-- VOUT VG V-- 1.11e-2
G_G9
22 V-- VOUT VG 1.11e-2
G_G10
23 V-- VG VOUT 1.11e-2
D_D6
VG 20 DX
D_D7
21 VG DX
D_D8
V++ 22 DX
D_D9
V++ 23 DX
D_D10
V-- 22 DY
D_D11
V-- 23 DY
V_V5
20 VOUT 1.12
V_V6
VOUT 21 1.12
R_R15
VOUT V++ 9E1 TC=0,0
R_R16
V-- VOUT 9E1 TC=0,0
*
.model SuperB npn
+ is=184E-15 bf=30e3 va=15 ik=70E-3 rb=50
+ re=0.065 rc=35 cje=1.5E-12 cjc=2E-12
+ kf=0 af=0
.model Cascode npn
+ is=502E-18 bf=150 va=300 ik=17E-3 rb=140
+ re=0.011 rc=900 cje=0.2E-12 cjc=0.16E-12f
+ kf=0 af=0
.model Mirror pnp
+ is=4E-15 bf=150 va=50 ik=138E-3 rb=185
+ re=0.101 rc=180 cje=1.34E-12 cjc=0.44E-12
+ kf=0 af=0
.model DN D(KF=6.69e-9 AF=1)
.MODEL DX D(IS=1E-12 Rs=0.1)
.MODEL DY D(IS=1E-15 BV=50 Rs=1)
.ends ISL28127subckt
FIGURE 29. SPICE NET LIST
14
FN6633.3
March 18, 2010
ISL28127, ISL28227
Characterization vs Simulation Results
100
INPUT NOISE VOLTAGE (nV/√Hz)
INPUT NOISE VOLTAGE (nV/√Hz)
100
VS = ±19V
AV = 1
10
1
0.1
1
10
100
1k
10k
10
V(INOISE)
1
0.1
100k
1
10
FIGURE 30. CHARACTERIZED INPUT NOISE VOLTAGE
Rg = 100, Rf = 100k
VS = ±15V
CL = 3.5pF
RL = INF
VOUT = 100mVP-P
AV = 10
20
Rg = 10k, Rf = 100k
10
40
Rg = OPEN, Rf = 0
1k
10k
100k
1M
FREQUENCY (Hz)
15
10M
100M
20
11
9
Rf = Rg = 1k
7
5
10k
Rg = 10k, Rf = 100k
Rf = Rg = 100
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 34. CHARACTERIZED CLOSED LOOP GAIN vs
Rf/Rg
15
AV = 1
Rg = OPEN, Rf = 0
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
FIGURE 33. SIMULATED CLOSED LOOP GAIN vs
FREQUENCY
Rf = Rg = 100k
13
11
Rf = Rg = 10k
9
7
Rf = Rg = 1k
5
3 VS = ±15V
RL = 10k
1
CL = 3.5pF
-1 A = +2
V
-3 VOUT = 100mVP-P
-5
1k
AV = 10
15
Rf = Rg = 10k
3 VS = ±15V
RL = 10k
1
CL = 3.5pF
-1 A = +2
V
-3 VOUT = 100mVP-P
AV = 100
-10
100
Rf = Rg = 100k
13
Rg = 100, Rf = 100k
30
0
FIGURE 32. CHARACTERIZED CLOSED LOOP GAIN vs
FREQUENCY
NORMALIZED GAIN (dB)
100k
Rg = 1k, Rf = 100k
10
AV = 1
-10
100
-5
GAIN (dB)
AV = 100
AV = 1000
50
NORMALIZED GAIN (dB)
GAIN (dB)
60
Rg = 1k, Rf = 100k
30
0
10k
70
AV = 1000
50
40
1k
FIGURE 31. SIMULATED INPUT NOISE VOLTAGE
70
60
100
FREQUENCY (Hz)
FREQUENCY (Hz)
1k
10k
Rf = Rg = 100
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 35. SIMULATED CLOSED LOOP GAIN vs Rf/Rg
FN6633.3
March 18, 2010
ISL28127, ISL28227
Characterization vs Simulation Results (Continued)
2
2
1
RL = 1k
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
RL = 10k
0
-1
RL = 499
-2
RL = 100
VS = ±15V
-3
RL = 49.9
CL = 3.5pF
AV = +1
VOUT = 100mVP-P
-4
-5
1k
10k
100k
1M
FREQUENCY (Hz)
10M
RL = 499
-2
RL = 100
VS = ±15V
-3
CL = 3.5pF
AV = +1
VOUT = 100mVP-P
10k
RL = 49.9
100k
1M
FREQUENCY (Hz)
10M
100M
FIGURE 37. SIMULATED CLOSED LOOP GAIN vs RL
7
5
4
3
CL = 1000pF
CL = 220pF
CL = 100pF
2
CL = 25.5pF
1
0
-1
CL = 3.5pF
-2
1k
10k
100k
1M
FREQUENCY (Hz)
5
4
CL = 1000pF
3
2
CL = 220pF
1
CL = 100pF
0
CL = 25.5pF
-1
-2
10M
-3
100M
FIGURE 38. CHARACTERIZED CLOSED LOOP GAIN vs
CL
CL = 3.5pF
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
FIGURE 39. SIMULATED CLOSED LOOP GAIN vs CL
6
5
6
5
4
4
2
1
0
LARGE SIGNAL (V)
VS = ±15V
CL = 3.5pF
AV = 1
Rf = 0, Rg = INF
VOUT = 10VP-P
3
1
-2
-3
RL = 2k
RL = 10k
-4
VS = ±15V
CL = 3.5pF
AV = 1
Rf = 0, Rg = INF
VOUT = 10VP-P
3
2
1
0
1
-2
-3
RL = 10k
-4
-5
-5
-6
VS = ±15V
RL = 10k
AV = +1
VOUT = 100mVP-P
6
NORMALIZED GAIN (dB)
VS = ±15V
RL = 10k
AV = +1
VOUT = 100mVP-P
6
NORMALIZED GAIN (dB)
RL = 1k
-1
-5
1k
100M
7
LARGE SIGNAL (V)
RL = 10k
0
-4
FIGURE 36. CHARACTERIZED CLOSED LOOP GAIN vs
RL
-3
1
-6
0
5
10
15
TIME (µs)
20
25
FIGURE 40. CHARACTERIZED LARGE SIGNAL 10V
STEP RESPONSE
16
30
0
5
10
15
TIME (µs)
20
25
30
FIGURE 41. SIMULATED LARGE SIGNAL 10V STEP
RESPONSE
FN6633.3
March 18, 2010
ISL28127, ISL28227
200
180
160
140
120
100
80
60
40
20
0
-20 R = 10k
L
-40
CL = 10pF
-60
-80 SIMULATION
-100
0.1m 1m 10m100m 1
200
OPEN LOOP GAIN (dB)/PHASE (°)
OPEN LOOP GAIN (dB)/PHASE (°)
Characterization vs Simulation Results (Continued)
PHASE
GAIN
10 100 1k 10k 100k 1M 10M100M
FREQUENCY (Hz)
130
120
110
100
90
80
70
60
50
40
30
20
10
0
-10
10
PHASE
100
50
GAIN
0
RL = 10k
-50 CL = 10pF
Model VOS set to zero
for this test
-100
0.1Hz
10Hz
1.0k
100k
10M
FREQUENCY (Hz)
FIGURE 43. SIMULATED OPEN-LOOP GAIN, PHASE vs
FREQUENCY
150
VS = ±5V
VS = ±2.25V
100
CMRR (dB)
CMRR (dB)
FIGURE 42. SIMULATED OPEN-LOOP GAIN, PHASE vs
FREQUENCY
150
VS = ±15V
RL = INF
CL = 5.25pF
AV = +1
VCM = 1VP-P
100
50
0
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 44. CHARACTERIZED CMRR vs FREQUENCY
17
Generated using full
model. CMRR delta input
base voltage/VCM
input Voltage
-50
10m
1.0Hz
100Hz 10k
1.0M
100M
10G 1.0T
FREQUENCY (Hz)
FIGURE 45. SIMULATED CMRR vs FREQUENCY
FN6633.3
March 18, 2010
ISL28127, ISL28227
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
REVISION
DATE
CHANGE
FN6633.3
3/11/10
PODs M8.118 and L8.3x3A - Updated to new intersil format by adding land pattern
and moving dimensions from table onto drawing.
3/3/10
Page 2:
Under "Ordering Information"
ISL28227FBZ: Changed Vos max from 80µV to 75µV
Page 4:
Changed:
1. ISL28227 SOIC Room Temp limit for Vos from 80µV (MAX) and -80µV (MIN) to
75µV (MAX) and -75µV (MIN).
2. ISL28227 SOIC Full Temp limit for Vos from 160µV (MAX) and -160µV (MIN) to
150µV (MAX) and -150µV (MIN)
3. ISL28227 SOIC limit for TCVos from 0.8µV (MAX) and -0.8µV (MIN) to 0.75µV
(MAX) and -0.75µV (MIN)
3/2/10
2/25/10
HBM for ISL28227 changed from “4kV” to “6kV”
Tjc values for ISL28227 changed:
For MSOP from “50” to “45”
For SOIC from “60” to “55”
On the ordering info (page 2):
Part Number
Part Marking
ISL28127FRTBZ
ISL28127FRTZ
-C 127Z instead of 127Z C
ISL28127FUBZ
ISL28127FUZ
8127Z -C instead of 8127Z
Removed "Coming Soon) for ISL28127FUZ package
ISL28227FBZ
Removed "Coming Soon) for ISL28227FBZ package
ISL28227FRTBZ
ISL28227FRTZ
-C 227Z instead of 227Z C
ISL28227FUZ
8227Z -C instead of 8227Z
Added the following row of data
ISL28227FUBZ
8227Z
Vos (Max) (uV)
TBD instead of 70
TBD instead of 70
150 instead of 70
80 instead of 70
TBD instead of 70
150 instead of 70
TBD
On the Electrical specifications on page 4 and page 6 the following changes were
made. The change applies to the same spec found on page 4 and page 6.
VOS Offset Voltage; SOIC Package, ISL28127: Added -70 to MIN across room
temp and -120 MIN across full temp
VOS Offset Voltage; SOIC Package, ISL28227: Added -80 to MIN across room
temp and -160 MIN across full temp
VOS Offset Voltage; MSOP and TDFN Package Grade C, ISL28127/ISL28227:
Added -150 to MIN across room temp and -250 MIN across full temp
TCVOS Offset Voltage Drift; SOIC Package, ISL28127: Added -0.5 to MIN across
full temp
TCVOS Offset Voltage Drift; SOIC Package, ISL28227: Added -0.8 to MIN across
full temp
TCVOS Offset Voltage Drift; MSOP and TDFN Package Grade C,
ISL28127/ISL28227: Added -1 to MIN across full temp
IOS Input Offset Current: Added -10 to MIN across room temp and -12 to MIN
across full temp
IB Input Bias Current :Added -10 to MIN across room temp and -12 to MIN across
full temp
2/19/10
18
Added differentiated part numbers for B-grade and C-grade for TDFN and MSOP.
Added ESD and latch-up information. Broke out Theta JA to list the single and dual
and added Theta JC.
FN6633.3
March 18, 2010
ISL28127, ISL28227
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev. (Continued)
REVISION
DATE
CHANGE
FN6633.2
1/29/10
Added license statement for P-Spice Model.
Updated Spice Schematic by adding capacitors
C4, C5 and C6
Updated Spice Net List as follows:
From:
Revision B, July 23 2009
To:
Revision C, August 8th 2009 LaFontaine
From:
source ISL28127_SPICEMODEL_7_9
To:
source ISL28127_SPICEMODEL_0_0
Added after I_IOS:
C_C6
IN+ VIN- 2E-12
Added after R_R4:
C_C4 VIN- 0 2.5e-12
C_C5 8 0 2.5e-12
From:
.ends ISL28127
To:
.ends ISL28127subckt
Replaced POD MDP0027 with M8.15E to match ASYD in Intrepid (no dimension
changes; the PODs are the same. The change was to update to the Intersil format,
moving dimensions from table onto drawing and adding land pattern)
FN6633.1
9/14/09
“Functional Description” on page 11. Corrected low 1/f noise corner frequency
from 3Hz to 5Hz to match “Input Noise Voltage Spectral Density” on page 1.
Corrected high open loop gain from 1400V/mV to 1500V/mV to match “Open-Loop
Gain” on page 5 spec table.
“Operating Voltage Range” on page 11. Removed following 2 sentences since
there are no graphs illustrating common mode voltage sensitivity vs temperature
or VOS as a function of supply voltage and temperature:
"The input common mode voltage sensitivity to temperature is shown in Figure 3
(±15V). Figure 20 shows VOS as a function of supply voltage and temperature
with the common mode voltage at 0V for split supply operation."
9/2/09
FN6633.0
19
Added Theta JC in Thermal Information for TDFN package
7/21/09
Updated Features to show only key features and updated applications section.
Added Typical Application Circuit and performance graph, Updated Ordering
Information to match Intrepid and added POD's L8.3x3A and M8.118, also added
MSL level as part of new format. Added TDFN pinouts, updated pin descriptions to
include TDFN pinouts, Added Theta Ja in Thermal information for TDFN and MSOP
packages. Added Revision History and Products Text with device info links. Added
SPICE Model with referencing text and Net List.
5/28/09
Techdocs Issued File Number FN6633. Initial release of Datasheet with file number
FN6633 making this a Rev 0.
FN6633.3
March 18, 2010
ISL28127, ISL28227
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL28127, ISL28227
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
20
FN6633.3
March 18, 2010
ISL28127, ISL28227
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.10 C
0.175 ± 0.075
SIDE VIEW “A
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
(5.40)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5.
The pin #1 identifier may be either a mold or mark feature.
6.
Reference to JEDEC MS-012.
TYPICAL RECOMMENDED LAND PATTERN
21
FN6633.3
March 18, 2010
ISL28127, ISL28227
Package Outline Drawing
L8.3x3A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 4, 2/10
( 2.30)
3.00
( 1.95)
A
B
3.00
( 8X 0.50)
6
PIN 1
INDEX AREA
(4X)
(1.50)
( 2.90 )
0.15
PIN 1
TOP VIEW
(6x 0.65)
( 8 X 0.30)
TYPICAL RECOMMENDED LAND PATTERN
SEE DETAIL "X"
2X 1.950
PIN #1
INDEX AREA
0.10 C
0.75 ±0.05
6X 0.65
C
0.08 C
1
SIDE VIEW
6
1.50 ±0.10
8
C
8X 0.30 ±0.05
8X 0.30 ± 0.10
0 . 2 REF
5
4
0.10 M C A B
0 . 02 NOM.
0 . 05 MAX.
2.30 ±0.10
DETAIL "X"
BOTTOM VIEW
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.20mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
7.
Compliant to JEDEC MO-229 WEEC-2 except for the foot length.
either a mold or mark feature.
22
FN6633.3
March 18, 2010
ISL28127, ISL28227
Package Outline Drawing
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 3, 3/10
5
3.0±0.05
A
DETAIL "X"
D
8
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
B
0.65 BSC
GAUGE
PLANE
TOP VIEW
0.55 ± 0.15
0.25
3°±3°
0.85±010
H
DETAIL "X"
C
SEATING PLANE
0.25 - 0.036
0.08 M C A-B D
0.10 ± 0.05
0.10 C
SIDE VIEW 1
(5.80)
NOTES:
(4.40)
(3.00)
1. Dimensions are in millimeters.
(0.65)
(0.40)
(1.40)
TYPICAL RECOMMENDED LAND PATTERN
23
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
FN6633.3
March 18, 2010
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