AVAGO ACPL-312U-000E 2.0 a minimum peak output current Datasheet

ACPL-312U-000E
Wide Operating Temperature IGBT Gate Drive
with R2Coupler™ Isolation and 2.5 Amp Output Current
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
The ACPL-312U device contains an AlGaAs LED. The LED
is optically coupled to an integrated circuit with a power
output stage. This wide operating temperature optocoupler is ideally suited for driving power IGBTs and MOSFETs
used in wide operating temperature motor control
inverter and DC-DC converters applications. The high
operating voltage range of the output stage provides the
drive voltages required by gate controlled devices. The
voltage and current supplied by these optocouplers make
them ideally suited for directly driving IGBTs with ratings
up to 1200 V/100 A. For IGBTs with higher ratings, the
ACPL-312U series can be used to drive a discrete power
stage which drives the IGBT gate.
• 2.5 A maximum peak output current
Avago R2Coupler isolation products provide the reinforced insulation and reliability needed for critical in automotive and high temperature industrial applications.
• Wide temperature range:
Functional Diagram
8 V CC
ANODE 2
7 VO
CATHODE 3
6 VO
SHIELD
• 0.5 V maximum low level output voltage (VOL) – Eliminates need for negative gate drive
• ICC = 5 mA maximum supply current
• Under Voltage Lock-Out protection (UVLO) with
hysteresis
• Wide operating VCC range: 15 to 30 Volts
• 500 ns maximum switching speeds
- -40°C to 125°C
• Safety Approval:
- CSA
N/ C 1
4
• 25 kV/μs minimum Common Mode Rejection (CMR) at
VCM = 1500 V
- UL Recognized 3750 Vrms for 1 min.
ACPL-312U-000E
N/C
• 2.0 A minimum peak output current
- IEC/EN/DIN EN 60747-5-5 Viorm = 630 Vpeak
Applications
• IGBT/MOSFET Gate Drive
• AC and Brushless DC Motor Drives
• Industrial Inverters Systems
5 V EE
• Switching power supplies
TRUTH TABLE
LED
OFF
ON
ON
ON
VCC - VEE
“POSITIVE GOING”
(i.e., TURN-ON)
VCC - VEE
“NEGATIVE GOING”
(i.e., TURN-OFF)
0 - 30 V
0 - 30 V
0 - 11 V
0 - 9.5 V
11 - 13.5 V
9.5 - 12 V
13.5 - 30 V
12 - 30 V
VO
LOW
LOW
TRANSITION
HIGH
A 0.1 μF bypass capacitor must be connected between pins 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information
Options
Part Number
ACPL-312U
RoHS Compliant
Package
-000E
DIP 8
-300E
Surface
Mount
Gullwing
-500E
Gullwing
X
X
X
X
Tape
& Reel
IEC/EN/DIN EN
60747-5-5
Quantity
X
X
50 per tube
X
50 per tube
X
1000 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
ACPL-312U-500E to order product of gullwing DIP-8 package in Tape and Reel packaging with RoHS compliant.
Example 2:
ACPL-312U-000E to order product of DIP-8 package in tube packaging with RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Package Outline Drawings
ACPL-312U-000E Standard DIP Package
7.62 ± 0.25
(0.300 ± 0.010)
9.65 ± 0.25
(0.380 ± 0.010)
TYPE NUMBER
8
7
6
5
DATE CODE
A 312U
YYWW
1
2
3
6.35 ± 0.25
(0.250 ± 0.010)
4
1.78 (0.070) MAX.
1.19 (0.047) MAX.
5° TYP.
3.56 ± 0.13
(0.140 ± 0.005)
4.70 (0.185) MAX.
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
0.51 (0.020) MIN.
2.92 (0.115) MIN.
1.080 ± 0.320
(0.043 ± 0.013)
0.65 (0.025) MAX.
2.54 ± 0.25
(0.100 ± 0.010)
DIMENSIONS IN MILLIMETERS AND (INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
LAND PATTERN RECOMMENDATION
9.65 ± 0.25
(0.380 ± 0.010)
8
2
7
6
A 312U
YYWW
1.016 (0.040)
5
6.350 ± 0.25
(0.250 ± 0.010)
10.9 (0.430)
Gull Wing Surface Mount Option 300
LAND PATTERN RECOMMENDATION
9.65 ± 0.25
(0.380 ± 0.010)
8
6
7
1.016 (0.040)
5
A 312U
YYWW
1
2
3
6.350 ± 0.25
(0.250 ± 0.010)
10.9 (0.430)
4
1.27 (0.050)
1.19
(0.047)
MAX.
1.780
(0.070)
MAX.
9.65 ± 0.25
(0.380 ± 0.010)
7.62 ± 0.25
(0.300 ± 0.010)
3.56 ± 0.13
(0.140 ± 0.005)
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.130
2.54
(0.025 ± 0.005)
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
0.635 ± 0.25
(0.025 ± 0.010)
2.0 (0.080)
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
12° NOM.
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
Recommended Pb-Free IR Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.
Regulatory Information
The ACPL-312U-000E is approved by the following organizations:
UL
Recognized under UL 1577, component recognition program up to VISO = 3750 VRMS expected prior to product release.
CSA
Approved under CSA Component Acceptance Notice #5, File CA88324.
IEC/EN/DIN EN 60747-5-5
Approved with Maximum Working Insulation Voltage VIORM = 630 Vpeak.
3
Insulation and Safety Related Specifications
Parameter
Symbol
Value
Units
Conditions
Minimum External Air Gap
(Clearance)
L(101)
7.1
mm
Measured from input terminals to output terminals, shortest
distance through air.
Minimum External Tracking
(Creepage)
L(102)
7.4
mm
Measured from input terminals to output terminals, shortest
distance path along body.
Minimum Internal Plastic Gap
(Internal Clearance)
0.08
mm
Through insulation distance conductor to conductor, usually the
straight line distance thickness between the emitter and detector.
Tracking Resistance
CTI
(Comparative Tracking Index)
>175
Volts
DIN IEC 112/VDE 0303 Part 1
Isolation Group
(DIN VDE0109)
IIIa
Material Group (DIN VDE 0110)
All Avago data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements.
However, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as
specified for individual equipment standards. For creepage, the shortest distance path along the surface of a printed
circuit board between the solder fillets of the input and output leads must be considered. There are recommended
techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and
clearances. Creepage and clearance distances will also change depending on factors such as pollution degree and insulation level.
IEC/EN/DIN EN 60747-5-5 Insulation Related Characteristics[1]
Description
Symbol
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤150 V rms
for rated mains voltage ≤300 V rms
for rated mains voltage ≤450 V rms
for rated mains voltage ≤600 V rms
for rated mains voltage ≤1000 V rms
ACPL-312U
Units
I-IV
I-IV
I-III
Climatic Classification
55/125/21
Pollution Degree (DIN VDE 0110/1.89)
2
Maximum Working Insulation Voltage
VIORM
630
VPEAK
Input to Output Test Voltage, Method b
VIORM x 1.875 = VPR, 100% Production
Test tm = 1 sec, Partial Discharge < 5 pC
VPR
1181
VPEAK
Input to Output Test Voltage, Method a
VIORM x 1.6 = VPR, 100% Type and Sample Test
tm = 10 sec, Partial Discharge < 5 pC
VPR
1008
VPEAK
Highest Allowable Overvoltage
(Transient Overvoltage, tini = 60 sec)
VIOTM
6000
VPEAK
Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Thermal Derating curve, Figure 11.)
Case Temperature
Input Current
Output Power
Ts
Is, INPUT
Ps,OUTPUT
175
230
600
°C
mA
mW
Insulation Resistance at TS, V10 = 500 V
RIO
≥109
Ω
Notes:
1. Insulation characteristics are guaranteed only within the safety maximum ratings, which must be ensured by protective circuits within the
application.
4
Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
Storage Temperature
TS
-55
125
°C
Operating Temperature
TA
-40
125
°C
Average Input Current
IF(AVG)
20
mA
Peak Transient Input Current
(<1 μs pulse width, 300 pps)
IF(TRAN)
1.0
A
Reverse Input Voltage
VR
5
V
“High” Peak Output Current
IOH(PEAK)
2.5
A
2
“Low” Peak Output Current
IOL(PEAK)
2.5
A
2
Supply Voltage
(VCC - VEE)
35
Volts
Input Current (Rise/Fall Time)
tr(IN) /tf(IN)
500
ns
Output Voltage
VO(PEAK)
Vcc
Volts
Output Power Dissipation
PO
370
mW
3
Total Power Dissipation
PT
400
mW
4
Lead Solder Temperature
0
0
Notes
1
260°C for 10 sec., 1.6 mm below seating plane
Solder Reflow Temperature Profile
See Package Outline Drawings Section
Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Ambient Operating Temperature
TA
-40
125
°C
Power Supply Voltage
(VCC - VEE)
15
30
Volts
Input Current
IF(ON)
7
16
mA
Input Voltage (OFF)
VF(OFF)
-3.6
0.8
V
5
DC Electrical Specifications
Over recommended operating conditions
(TA = -40 to 125°C, IF(ON) = 7 to 16 mA, VF(OFF) = -3.6 to 0.8 V, VCC = 15 to 30 V, VEE = Ground) unless otherwise specified.
Parameter
Symbol
Min.
Typ.*
High Level Output Current
IOH
0.5
1.5
Max.
Units
Test Conditions
Fig.
Note
A
VO = (VCC - 4 V)
2,3,17
5
A
VO = (VCC - 15 V)
A
VO = (VEE + 2.5 V)
5,6 ,18 5
2.0
A
VO = (VEE + 15 V)
2
(VCC - 4) (VCC - 3)
V
IO = -100 mA
1,3, 19 6,7
2.0
Low Level Output Current
IOL
0.5
2.0
2
High Level Output Voltage
VOH
Low Level Output Voltage
VOL
0.1
0.5
V
IO = 100 mA
4,6,20
High Level Supply Current
ICCH
2.5
5.0
mA
Output Open,
IF = 7 to 16mA
7,8
Low Level Supply Current
ICCL
2.5
5.0
mA
Output Open,
VF = -3.0 to +0.8 V
Threshold Input Current
Low to High
IFLH
0.8
5.0
mA
IO = 0 mA, VO > 5 V
Threshold Input Voltage
High to Low
VFHL
0.8
Input Forward Voltage
VF
1.2
Temperature Coefficient of
Forward Voltage
ΔVF/ΔTA
Input Reverse Breakdown Voltage
BVR
Input Capacitance
CIN
UVLO Threshold
VUVLO+
11.0
12.3
VUVLO–
9.5
10.7
UVLO Hysteresis
V
1.5
1.95
IF = 10 mA
mV/°C
IF = 10 mA
V
IR = 10 μA
pF
f = 1 MHz, VF = 0 V
13.5
V
12.0
V
VO > 5 V,
IF = 10 mA
5.0
70
UVLOHYS
9
V
-1.6
1.6
9, 15,
21
16
22, 34
V
*All typical values at TA = 25°C and VCC - VEE = 30 V, unless otherwise noted.
AC Electrical Specifications
Over recommended operating conditions
(TA = -40 to 125°C, IF(ON) = 7 to 16 mA, VF(OFF) = -3.6 to 0.8 V, VCC = 15 to 30 V, VEE = Ground) unless otherwise specified.
Parameter
Symbol
Min.
Typ.*
Max.
Units
Test Conditions
Propagation Delay Time to
High Output Level
tPLH
0.10
0.30
0.50
μs
Propagation Delay Time to
Low Output Level
tPHL
0.10
0.30
0.50
μs
Rg = 10 Ω, Cg = 10 nF,
10, 11,
f = 10 kHz, Duty Cycle = 50% 12,13,
14, 23
Pulse Width Distortion
PWD
0.3
μs
Propagation Delay Difference
Between Any Two Parts
PDD
-0.35
(tPHL - tPLH)
0.35
μs
35, 36
Rise Time
tR
0.1
μs
23
Fall Time
tF
0.1
μs
UVLO Turn On Delay
tUVLO ON
0.8
μs
VO > 5 V, IF = 10 mA
UVLO Turn Off Delay
tUVLO OFF
0.6
μs
VO < 5 V, IF = 10 mA
Output High Level Common
Mode Transient Immunity
|CMH|
25
35
kV/μs
TA = 25°C, IF = 10 to 16 mA,
VCM = 1500 V, VCC = 30 V
Output Low Level Common
Mode Transient Immunity
|CML|
25
35
kV/μs
TA = 25°C, VCM = 1500 V,
VF = 0 V, VCC = 30 V
*All typical values at TA = 25°C and VCC - VEE = 30 V, unless otherwise noted.
6
Fig.
Note
14
15
10
22
24
11, 12
11, 13
Package Characteristics
Parameter
Symbol
Min.
Input-Output Momentary
Withstand Voltage**
VISO
3750
Resistance (Input-Output)
RI-O
Capacitance (Input-Output)
Typ.*
Max.
Units
Test Conditions
Fig.
Note
VRMS
RH < 50%, t = 1 min.
TA = 25°C
8, 9
1012
Ω
VI-O = 500 VDC
9
CI-O
0.8
pF
ƒ = 1 MHz
LED-to-Case Thermal
Resistance
qLC
467
°C/W
Thermocouple located at
28
center underside of package
LED-to-Detector Thermal
Resistance
qLD
442
°C/W
Detector-to-Case Thermal
Resistance
qDC
126
°C/W
* All typicals at TA = 25°C.
** The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage
rating. For the continuous voltage rating refers to your equipment level safety specification or Avago Application Note 1074 entitled “Optocoupler
Input-Output Endurance Voltage.”
Notes:
1. Derate linearly above 70°C free-air temperature at a rate of 0.0727 mA/°C.
2. Maximum pulse width = 10 μs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO peak
minimum = 2.0 A. See Applications section for additional details on limiting IOH peak.
3. Derate linearly above 70°C free-air temperature at a rate of 5.0 mW/°C.
4. Derate linearly above 70°C free-air temperature at a rate of 5.0 mW/°C. The maximum LED junction temperature should not exceed 150°C.
5. Maximum pulse width = 50 μs, maximum duty cycle = 0.5%.
6. In this test VOH is measured with a dc load current. When driving capacitive loads VOH will approach VCC as IOH approaches zero amps.
7. Maximum pulse width = 1 ms, maximum duty cycle = 20%.
8. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥4500 Vrms for 1 second (leakage detection
current limit, II-O ≤ 5 μA).
9. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.
10. The difference between tPHL and tPLH between any two ACPL-312U parts under the same test condition.
11. Pins 1 and 4 need to be connected to LED common.
12. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output
will remain in the high state (i.e., VO > 15.0 V).
13. Common mode transient immunity in a low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output
will remain in a low state (i.e., VO < 1.0 V).
14. This load condition approximates the gate load of a 1200 V/75A IGBT.
15. Pulse Width Distortion (PWD) is defined as |tPHL-tPLH| for any given device.
7
2.00
I OH – OUTPUT HIGH CURRENT – A
(VOH – V CC ) – HIGH OUTPUT VOLTAGE DROP – V
0
IF = 7 to 16 mA
IOUT = -100 mA
V CC = 15 to 30 V
V EE = 0 V
-1
-2
-3
-40
-20
0
20
40
60
80
T A – TEMPERATURE – °C
100
120
0
-1
-2
-3
-4
IF = 7 to 16 mA
V CC = 15 to 30 V
V EE = 0 V
-5
-6
0.0
0.5
1.0
1.5
2.0
IOH – OUTPUT HIGH CURRENT – A
2.5
1.75
-40
-20
0
20 40 60 80
T A – TEMPERATURE – °C
100 120
140
0.15
V F (OFF) = -3.0 TO 0.8 V
IOUT = 100 mA
V CC = 15 TO 30 V
V EE = 0 V
0.10
0.05
-40
-20
0
20 40 60 80
T A – TEMPERATURE – °C
100
120
140
Figure 4. VOL vs. temperature.
V OL – OUTPUT LOW VOLTAGE – V
4.50
2.50
2.00
1.50
V F (OFF) = -3.0 TO 0.8 V
V OUT = 2.5 V
V CC = 15 TO 30 V
V EE = 0 V
1.00
0.50
0.00
0.20
0.00
3.0
3.00
IOL – OUTPUT LOW CURRENT – A
1.80
0.25
125°C
-40°C
25°C
Figure 3. VOH vs. IOH.
-40
-20
0
Figure 5. IOL vs. temperature.
8
1.85
Figure 2. IOH vs. temperature.
V OL – OUTPUT LOW VOLTAGE – V
(VOH – V CC ) – OUTPUT HIGH VOLTAGE DROP – V
Figure 1. VOH vs. temperature.
1.90
1.70
140
IF = 7 to 16 mA
IOUT = -100 mA
V CC = 15 to 30 V
V EE = 0 V
1.95
20 40 60 80
T A – TEMPERATURE – °C
100
120
140
25°C
-40°C
125°C
4.00
3.50
3.00
2.50
2.00
V F(OFF) = -3.0 to 0.8 V
V CC = 15 to 30 V
V EE = 0 V
1.50
1.00
0.50
0.00
0.0
Figure 6. VOL vs. IOL.
1.0
2.0
3.0
IOL – OUTPUT LOW CURRENT – A
4.0
2.8
Iccl
Icch
3.00
ICC – SUPPLY CURRENT – mA
ICC – SUPPLY CURRENT – mA
3.50
2.50
V CC = 30 V
V EE = 0 V
IF = 10 mA for I CCH
IF = 0 mA for I CCL
2.00
1.50
-40
-20
0
20 40
60 80
T A – TEMPERATURE – °C
100
Iccl
Icch
2.6
IF = 10 mA for I CCH
IF = 0 mA for I CCL
T A = 25°C VEE = 0 V
2.5
2.4
120 140
Figure 7. ICC vs. temperature.
15
20
25
V CC – SUPPLY VOLTAGE – V
1.20
500
1.00
0.80
0.60
0.40
V CC = 15 TO 30 V
V EE = 0 V
OUTPUT = OPEN
0.20
0.00
-40
-20
0
20 40 60 80 100
T A – TEMPERATURE – °C
Tplh
Tphl
400
300
IF = 10 mA TA = 25°C
Rg = 10 Ω
Cg = 10 nF
DUTY CYCLE = 50%
f = 10 kHz
200
100
120 140
Figure 9. IFLH vs. temperature.
15
20
25
V CC – SUPPLY VOLTAGE – V
500
Tphl
Tplh
400
500
300
VCC = 30 V, V EE = 0 V
Rg = 10 Ω, Cg = 10 nF
TA = 25°C
DUTY CYCLE = 50%
f = 10 kHz
6
8
10
12
14
IF – FORWARD LED CURRENT – mA
Figure 11. Propagation delay vs. IF.
9
500
16
Tp – PROPAGATION DELAY – ns
T p – PROPAGATION DELAY – ns
Tphl
200
30
Figure 10. Propagation delay vs. VCC.
500
100
30
Figure 8. ICC vs. VCC.
Tp – PROPAGATION DELAY – ns
IFLH – LOW TO HIGH CURRENT THRESHOLD – mA
2.7
Tplh
400
300
IF = 10 mA
VCC = 30 V, VEE = 0 V
Rg = 10 Ω , Cg = 10 nF
DUTY CYCLE = 50%
f = 10 kHz
200
100
-40
-20
0
20 40
60 80 100
T A – TEMPERATURE – °C
Figure 12. Propagation delay vs. temperature.
120
140
500
Tphl
400
T p – PROPAGATION DELAY – ns
Tp – PROPAGATION DELAY – ns
500
Tplh
300
V CC = 30 V, V EE = 0 V
T A = 25 °C I F = 10 mA
Cg = 10 nF
DUTY CYCLE = 50%
f = 10 kHz
200
100
0
10
20
30
40
Rg – SERIES LOAD RESISTANCE – Ω
0
20
40
60
Cg – LOAD CAPACITANCE – nF
80
100
TA = 25 °C
25
IF - FORWARD CURRENT - mA
V O – OUTPUT VOLTAGE – V
200
100
20
15
10
5
0
1
2
3
4
IF – FORWARD LED CURRENT – mA
Figure 15. Transfer characteristics.
10
VCC = 30 V, VEE = 0 V
T A = 25°C I F = 10 mA
Cg = 10 nF
DUTY CYCLE = 50%
f = 10 kHz
Figure 14. Propagation delay vs. Cg.
30
0
Tplh
300
100
50
Figure 13. Propagation delay vs. Rg.
Tphl
400
5
10
1
0.1
0.01
1.2
1.3
1.4
1.5
V F - Forward Voltage - VOLTS
Figure 16. Input current vs. forward voltage.
1.6
I F = 7 to
16 mA
1
8
0.1 µF
2
7
3
6
4
5
+
– 4V
V CC = 15
+
– to
30 V
8
0.1 µF
2
7
3
6
4
5
I OH
Figure 17. IOH test circuit.
I F = 7 to
16 mA
1
I OL
+ V CC = 15
– to 30 V
2.5 V +
–
Figure 18. IOL Test circuit.
1
8
0.1 µF
2
7
3
VOH
+ V CC =15
– to 30 V
6
1
8
0.1 µF
2
7
3
6
4
5
100 mA
+ V CC = 15
– to 30 V
VOL
100 mA
4
5
Figure 19. VOH Test circuit.
1
8
0.1 µF
2
7
IF
3
6
4
5
Figure 21. IFLH Test circuit.
11
Figure 20. VOL Test circuit.
I F = 10 mA
VO > 5 V
V CC = 15
+
– to
30 V
1
8
0.1 µF
2
7
3
6
4
5
Figure 22. UVLO test circuit.
V O > 5V
+
– V CC
1
I F = 7 to 16 mA
10 KHz
50% DUTY
CYCLE
+ 500 Ω
–
8
0.1 µF
2
7
V CC = 15
+ to
30 V
–
IF
tr
VO
3
6
90%
10 Ω
50%
10%
V OUT
10 nF
4
tf
5
t PLH
t PHL
Figure 23. tPLH, tPHL, tR, and tF test circuit and waveforms.
V CM
IF
5V +
–
1
0.1 µF
A
B
2
0V
7
3
6
4
5
–
+
V CM = 1500V
Figure 24. CMR test circuit and waveforms.
12
δ V V CM
=
δ t ∆t
8
VO +
–
V CC = 30 V
∆t
VO
V OH
SWITCH AT A: I F = 10 mA
VO
SWITCH AT B: I F = 0 mA
V OL
Applications Information
Eliminating Negative IGBT Gate Drive ACPL-312U
To keep the IGBT firmly off, the ACPL-312U has a very
low maximum VOL specification of 0.5 V. The ACPL-312U
realizes this very low VOL by using a DMOS transistor
with 1 Ω (typical) on resistance in its pull down circuit.
When the ACPL-312U is in the low state, the IGBT gate is
shorted to the emitter by Rg + 1 Ω. Minimizing Rg and
the lead inductance from the ACPL-312U to the IGBT gate
and emitter (possibly by mounting the ACPL-312U on a
small PC board directly above the IGBT) can eliminate the
need for negative IGBT gate drive in many applications
as shown in Figure 25. Care should be taken with such
a PC board design to avoid routing the IGBT collector or
emitter traces close to the ACPL-312U input as this can
result in unwanted coupling of transient signals into the
ACPL-312U and degrade performance. (If the IGBT drain
must be routed near the ACPL-312U input, then the LED
should be reverse-biased when in the off state, to prevent
the transient signals coupled from the IGBT drain from
turning on the ACPL-312U).
Selecting the Gate Resistor (Rg) to Minimize IGBT Switching
Losses.
Step 1: Calculate Rg Minimum from the IOL Peak Specification. The IGBT and Rg in Figure 26 can be analyzed as
a simple RC circuit with a voltage supplied by the ACPL312U.
Rg ≥
=
(VCC − VEE − VOL ) (VCC − VEE − 2.5V )
=
IOLPEAK
IOLPEAK
(15 + 5 − 2.5V)
2.5 A
Rg = 7ohm
The VOL value of 2.5V in the previous equation is a conservative value of VOL at the peak current of 2.5A (see Figure
6). At lower Rg values the voltage supplied by the ACPL312U is not an ideal voltage step. This results in lower peak
currents (more margin) than predicted by this analysis.
When negative gate drive is not used VEE in the previous
equation is equal to zero volts.
ACPL-312U
+5 V
8
0.1 µF
1
270 Ω
2
7
CONTROL
INPUT
3
6
CMOS
DRIVER
4
5
+
–
V CC = 18 V
+ HVDC
Rg
Q1
3-PHASE
AC
Q2
- HVDC
Figure 25. Recommended LED drive and application circuit.
+5V
1
270Ω
8
0.1 µF
2
7
CONTROL
INPUT
3
6
CMOS
DRIVER
4
V CC = 15 V
+ HVDC
Rg
+
–
Q1
V EE = -5 V
3-PHASE
AC
Q2
- HVDC
5
Figure 26. ACPL-312U typical application circuit with negative IGBT gate drive.
13
+
–
Step 2: Check the ACPL-312U Power Dissipation and Increase
Rg if Necessary.
The ACPL-312U total power dissipation (PT ) is equal to the
sum of the emitter power (PE) and the output power (PO):
PT
= PE + PO
PE
= IF .VF .Duty Cycle
PO
= PO(BIAS) + PO (SWITCHING)
= ICC.(VCC - VEE) + ESW(RG, QG).f
For the circuit in Figure 26 with IF (worst case) = 16 mA,
Rg = 8 Ω, Max Duty Cycle = 80%, Qg = 500 nC, f = 20 kHz:
PE
= 16mA . 1.95V . 0.8 = 24.96mW
PO
= 5mA .20V + 5.2μJ .20kHz
Thermal Model
The steady state thermal model for the ACPL-312U is
shown in Figure 28. The thermal resistance values given
in this model can be used to calculate the temperatures
at each node for a given operating condition. As shown
by the model, all heat generated flows through qCA which
raises the case temperature TC accordingly. The value of
qCA depends on the conditions of the board design and is,
therefore, determined by the designer. The value of qCA =
83°C/W was obtained from thermal measurements using
a 2.5 x 2.5 inch PC board, with small traces (no ground
plane), a single ACPL-312U soldered into the center of
the board and still air. The absolute maximum power dissipation de-rating specifications assume a qCA value of
83°C/W. From the thermal mode in Figure 28 the LED and
detector IC junction temperatures can be expressed as:
= 100mW + 104mW
TJE = PE =(θLC || θLC + θDC) + θCA)
= 204mW
PO
= 204mW < 370mW (abs. max.)OK
θLC * θDC
+ PD . (----------- + θCA) + TA
θLC + θDC + θLD
θLC . θDC
TJD = PE (----------- + θCA)
θLC + θDC + θLD
PT
= 24.96mW + 204mW
+PD . (θDC || θLD + θLC) + θCA) + TA
Step 3: Comparing the calculated power dissipation with the
absolute maximum values for the ACPL-312U:
= 228.96mW < 400mW (abs. max.) OK
Esw – ENERGY PER SWITCHING CYCLE – µJ
Therefore, the power dissipation absolute maximum
rating has not been exceeded for the example.
Qg = 100 nC
Qg = 500 nC
Qg = 1000 nC
14
12
10
= PE.(256°C/W + qCA) + PD.(57°C/W + qCA) + TA
TJD
= PE.(57°C/W + qCA) + PD.(111°C/W + qCA) + TA
TJE
= PE.339°C/W + PD.140°C/W + TA
= 30 mW.339°C/W + 230 mW .140°C/W + 100°C
6
= 142°C
4
TJD
2
= PE.140°C/W + PD.194°C/W + TA
= 30 mW.140°C/W + 230 mW.194°C/W + 100°C
0
10
0
20
30
40
Rg – GATE RESISTANCE – Ω
50
Figure 27. Energy dissipated in the ACPL-312U for each IGBT switching cycle.
θLD = 442°C/W
T JE
θLC = 467°C/W
T JD
θDC = 126°C/W
TC
θ CA = 83°C/W *
TA
Figure 28. Thermal model.
14
TJE
For example, given PE = 30 mW, PO = 230 mW, TA = 100°C
and qCA = 83°C/W:
V CC = 19 V
V EE = -9 V
8
Inserting the values for qLC and qDC shown in Figure 28
gives:
T JE
T JD
TC
θLC
θLD
θDC
θCA
* θCA
= 149°C
TJE and TJD should be limited to 150°C based on the board
layout and part placement (qCA) specific to the application.
= LED junction temperature
= detector IC junction temeperature
= case temperature measured at the ce nter of the package bottom
= LED-to-case thermal resistance
= LED-to-detector thermal resistance
= detector-to-case thermal resistance
= case-to-ambient thermal resistance
will depend on the board design and the placement of the part.
LED Drive Circuit Considerations for Ultra High CMR Performance.
CMR with the LED On (CMRH).
A high CMR LED drive circuit must keep the LED on during
common mode transients. This is achieved by overdriving the LED current beyond the input threshold so that
it is not pulled below the threshold during a transient.
A minimum LED current of 10 mA provides adequate
margin over the maximum IFLH of 5 mA to achieve 25 kV/
μs CMR. CMR with the LED Off (CMRL). A high CMR LED
drive circuit must keep the LED off (VF ≤ VF(OFF)) during
common mode transients. For example, during a -dVcm/dt
transient in Figure 31, the current flowing through CLEDP
also flows through the RSAT and VSAT of the logic gate. As
long as the low state voltage developed across the logic
gate is less than VF(OFF), the LED will remain off and no
common mode failure will occur. The open collector drive
circuit, shown in Figure 32, cannot keep the LED off during
a +dVcm/dt transient, since all the current flowing through
CLEDN must be supplied by the LED, and it is not recommended for applications requiring ultra high CMRL performance. Figure 33 is an alternative drive circuit which,
like the recommended application circuit (Figure 25), does
achieve ultra high CMR performance by shunting the LED
in the off state.
Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the
input side of the optocoupler, through the package, to
the detector IC as shown in Figure 29. The ACPL-312U
improves CMR performance by using a detector IC with
an optically transparent Faraday shield, which diverts the
capacitively coupled current away from the sensitive IC
circuitry. However, this shield does not eliminate the capacitive coupling between the LED and optocoupler pins
5-8 as shown in Figure 30. This capacitive coupling causes
perturbations in the LED current during common mode
transients and becomes the major source of CMR failures
for a shielded optocoupler. The main design objective of
a high CMR LED drive circuit becomes keeping the LED in
the proper state (on or off ) during common mode transients. For example, the recommended application circuit
(Figure 25), can achieve 25 kV/μs CMR while minimizing
component complexity. Techniques to keep the LED in the
proper state are discussed in the next two sections.
+5V
1 8
2 7
3 6
1
C LEDP
2
+
V SAT
–
3
C LEDN
4 5
4
C LEDO1
8
1
8
C LEDP
7
I LEDP
2
6C
LEDN
3
5
4
SHIELD
C LEDP
C LEDO1
1 8
+5V
0.1
µF + V CC C=
18 V
– 2 7 LEDP
7
C LEDO2
C LEDN
6
3 6 •••
Rg C LEDN
4 5
5
SHIELD
1
+5V
+
V SAT
–
1
2
+
V SAT
C LEDO2
–
Q1
8
C LEDP
7
C LEDP
2 I LEDP
3
3
4
4
+5V
C LEDN
6
C LEDN
SHIELD
5
SHIELD
* THE ARROWS INDICATE THE DIRECTION
OF CURRENT FLOW DURING –d VCM /dt.
Rg
•••
5
77
66
C LEDN
I LEDN
55
SHIELD
SHIELD
+5V
1
2
8
1 C LEDP
2
•••
LEDP
CCLEDP
Q1
3
C LEDP
C LEDN
3 I LEDN
C LEDN
4
SHIELD
4
SHIELD
7
8
7
6
6
5
5
+–
V CM
Figure 31. Equivalent circuit for figure 25 during common mode transient.
15
+5V
1
2
8
C LEDP
7
0.1
µF + V CC
–
I LEDP
633
544
7
6
88
* THE ARROWS INDICATE THE DIRECTION
OF CURRENT FLOW
DURING –d
VCM /dt.
Figure 32. Not recommended
open collector
drive
+–
circuit.
V CM
8
0.1
µF + V CC = 18 V
–
722
•••
SHIELD
* THE ARROWS INDICATE THE DIRECTION
OF CURRENT FLOW DURING –d VCM /dt.
Figure 29. Optocoupler input to output
Figure 30. Optocoupler input to output
+ –capacitance model for shielded optocapacitance model for unshielded optoV CMcouplers.
couplers.
+5V
811
+5V
Figure 33. Recommended LED drive circuit for ultra-high CMR.
Rg
Under Voltage Lockout Feature.
Dead Time and Propagation Delay Specifications
The ACPL-312U contains an under voltage lockout (UVLO)
feature that is designed to protect the IGBT under fault
conditions which cause the ACPL-312U supply voltage
(equivalent to the fully-charged IGBT gate voltage) to
drop below a level necessary to keep the IGBT in a low resistance state. When the ACPL-312U output is in the high
state and the supply voltage drops below the ACPL-312U
VUVLO– threshold (9.5 < VUVLO– < 12.0) the optocoupler
output will go into the low state with a typical delay, UVLO
Turn Off Delay, of 0.6 μs. When the ACPL-312U output is
in the low state and the supply voltage rises above the
ACPL-312U VUVLO+ threshold (11.0 < VUVLO+ < 13.5) the
optocoupler output will go into the high state (assumes
LED is “ON”) with a typical delay, UVLO Turn On Delay of
0.8 μs.
The ACPL-312U includes a Propagation Delay Difference
(PDD) specification intended to help designers minimize
“dead time” in their power inverter designs. Dead time
is the time period during which both the high and low
side power transistors (Q1 and Q2 in Figure 25) are off.
Any overlap in Q1 and Q2 conduction will result in large
currents flowing through the power devices between the
high and low voltage motor rails.
14
V O – OUTPUT VOLTAGE – V
12
10
(10.7, 9.2)
(12.3, 10.8)
8
6
4
2
0
0
(12.3, 0.1)
(10.7, 0.1)
5
10
15
(VCC - V EE ) – SUPPLY VOLTAGE – V
20
Figure 34. Under voltage lock out.
VOUT 2
I LED2
Note that the propagation delays used to calculate PDD
and dead time are taken at equal temperatures and test
conditions since the optocouplers under consideration
are typically mounted in close proximity to each other and
are switching identical IGBTs.
I LED1
I LED1
VOUT 1
To minimize dead time in a given design, the turn on of
LED2 should be delayed (relative to the turn off of LED1)
so that under worst-case conditions, transistor Q1 has just
turned off when transistor Q2 turns on, as shown in Figure
35. The amount of delay necessary to achieve this condition
is equal to the maximum value of the propagation delay
difference specification, PDDMAX, which is specified to be
350 ns over the operating temperature range of -40°C to
125°C. Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time
is zero, but it does not tell a designer what the maximum
dead time will be. The maximum dead time is equivalent
to the difference between the maximum and minimum
propagation delay difference specifications as shown in
Figure 36. The maximum dead time for the ACPL-312U is
700 ns (= 350 ns - (-350 ns)) over an operating temperature range of -40°C to 125°C.
Q1 ON
Q2 OFF
VOUT 1
Q1 OFF
Q2 ON
VOUT 2
I LED2
tPHL MAX
tPLH MIN
PDD* MAX = (tPHL- tPLH )MAX =tPHL MAX - tPLH MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
Figure 35. Minimum LED skew for zero dead time.
Q1 ON
Q1 OFF
Q2 ON
Q2 OFF
tPHL MIN
tPHL MAX
tPLH
MIN
tPLH MAX
(tPHL- tPLH) MAX
PDD* MAX
MAXIMUM DEAD TIME
(DUE TO OPTOCOUPLER)
= (tPHL MAX - tPHL MIN) + (tPLH MAX- tPLH MIN)
= (tPHL MAX - tPLH MIN ) – (tPHL MIN- tPLH MAX )
= PDD* MAX – PDD* MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION
DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
Figure 36. Waveforms for dead time.
16
Output Power Derating Curve
450
400
350
Po
300
250
200
150
100
50
0
0
20
40
60
80
100
120
140
Ta
Figure 37. Thermal derating curve, dependence of safety limiting value with
case temperature per IEC/EN/DIN EN 60747-5-5.
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, the A logo and R2Coupler™ are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2013 Avago Technologies. All rights reserved.
AV02-1843EN - September 30, 2013