STMicroelectronics M41T93RQA6F Serial spi bus rtc with battery switchover Datasheet

M41T93
Serial SPI bus RTC with battery switchover
Features
■
Ultra-low battery supply current of 365 nA
■
Factory calibrated accuracy ±5 ppm
guaranteed after 2 reflows (SOX18)
– Much better accuracies achievable using
built-in programmable analog and digital
calibration circuits
■
2.0 V to 5.5 V clock operating voltage
■
Counters for tenths/hundredths of seconds,
seconds, minutes, hours, day, date, month,
year, and century
■
Automatic switchover and reset output circuitry
(fixed reference)
– M41T93S: VCC = 3.0 V to 5.5 V
(2.85 V ≤ VRST ≤ 3.00 V)
– M41T93R: VCC = 2.7 V to 5.5 V
(2.55 V ≤ VRST ≤ 2.70 V)
– M41T93Z: VCC = 2.38 V to 5.50 V
(2.25 V ≤ VRST ≤ 2.38 V)
■
Compatible with SPI bus serial interface
(supports SPI mode 0 [CPOL = 0, CPHA = 0])
■
Programmable alarm with interrupt function
(valid even during battery back-up mode)
■
Optional 2nd programmable alarm available
■
Square wave output (defaults to 32 kHz on
power-up)
■
RESET (RST) output
■
Watchdog timer
■
Programmable 8-bit counter/timer
■
7 bytes of battery-backed user SRAM
■
Battery low flag
■
Power-down time stamp (HT bit)
■
Low operating current of 80 µA
■
Oscillator stop detection
■
Battery or SuperCap™ backup
■
Operating temperature of –40°C to +85°C
August 2008
QFN16, 4 mm x 4 mm (QA)
18
1
SOX18 (MY, 18-pin, 300 mil SOIC
with embedded crystal)
■
Package options include:
– a 16-lead QFN or an 18-lead embedded
crystal SOIC
■
RoHS compliance: lead-free components are
compliant with the RoHS directive
Rev 4
1/51
www.st.com
1
Contents
M41T93
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
2
3
2/51
SPI signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1.1
Serial data output (SDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1.2
Serial data input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1.3
Serial clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1.4
Chip enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1
SPI bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2
Read and write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3
Data retention and battery switchover (VSO = VRST) . . . . . . . . . . . . . . . . 15
2.4
Power-on reset (trec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1
Power-down time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2
Clock/control register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3
Real-time clock accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4
Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.1
Digital calibration (periodic counter correction) . . . . . . . . . . . . . . . . . . . 20
3.4.2
Analog calibration (programmable load capacitance) . . . . . . . . . . . . . . 22
3.5
Setting the alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.6
Optional second programmable alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.7
Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.8
8-bit (countdown) timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.8.1
TI/TP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.8.2
TF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.8.3
TIE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.8.4
TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.8.5
TD1/0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.9
Square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.10
Battery low warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.11
Century bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
M41T93
Contents
3.12
Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.13
Oscillator fail detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.14
Oscillator fail interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.15
Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.16
OTP bit operation (SOX18 package only) . . . . . . . . . . . . . . . . . . . . . . . . 35
4
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3/51
List of tables
M41T93
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
4/51
Signal name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Clock/control register map (32 bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Digital calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Analog calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Timer control register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Interrupt operation (bit TI/TP = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Timer source clock frequency selection (244.1 µs to 4.25 hrs). . . . . . . . . . . . . . . . . . . . . . 31
Timer countdown value register bits (addr 11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Century bits examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Initial power-on default values (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Initial power-up default values (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
QFN16 – 16-lead, quad, flat package, no lead, 4 x 4 mm body, mech. data . . . . . . . . . . . 45
SOX18 – 18-lead plastic SO, 300 mils, embedded crystal, pkg. mech. data . . . . . . . . . . . 47
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
M41T93
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
QFN16 (QA) connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SOX18 (MY) connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data and clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Internal load capacitance adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Clock accuracy vs. on-chip load capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Clock divider chain and calibration circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Crystal isolation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Alarm interrupt reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Backup mode alarm waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Measurement AC I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
ICC2 vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Input timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Output timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
QFN16 – 16-lead, quad, flat package, no lead, 4 x 4 mm body size, outline . . . . . . . . . . . 44
QFN16 – 16-lead, quad, flat, no lead, 4 x 4 mm, recommended footprint . . . . . . . . . . . . . 46
32 kHz crystal + QFN16 vs. VSOJ20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
SOX18 – 18-lead plastic small outline, 300 mils, embedded crystal . . . . . . . . . . . . . . . . . 47
5/51
Description
1
M41T93
Description
The M41T93 is a low-power serial SPI bus real-time clock with a built-in 32.768 kHz
oscillator (external crystal-controlled for the QFN16 package, and embedded crystal for the
SOX18 package). Eight bytes of the register map (see Table 3 on page 18) are used for the
clock/calendar function and are configured in binary coded decimal (BCD) format. An
additional 17 bytes of the register map provide status/control of the two alarms, watchdog,
8-bit counter, and square wave functions. An additional seven bytes are made available as
user SRAM.
Addresses and data are transferred serially via a serial SPI bus-compatible interface. The
built-in address register is incremented automatically after each WRITE or READ data byte.
The M41T93 has a built-in power sense circuit which detects power failures and
automatically switches to the battery supply when a power failure occurs. The energy
needed to sustain the clock operations can be supplied by a small lithium button battery
when a power failure occurs.
Functions available to the user include a non-volatile, time-of-day clock/calendar, alarm
interrupt, watchdog timer, programmable 8-bit counter, and square wave outputs. The eight
clock address locations contain the century, year, month, date, day, hour, minute, second,
and tenths/hundredths of a second in 24-hour BCD format. Corrections for 28, 29 (leap
year), 30, and 31 day months are made automatically. The M41T93 is supplied in either a
QFN16 or an SOX18 (MY), 300mil SOIC which includes an embedded 32 kHz crystal. The
SOX18 package requires only a user-supplied battery to provide non-volatile operation.
6/51
M41T93
Description
Figure 1.
Logic diagram
VBAT VCC
XI(1)
SQW(2)
XO(1)
IRQ/OUT/FT(3)
SDI
RST(3)
SCL
SDO
E
VSS
AI11818
1. For QFN16 package only
2. Defaults to 32 kHz on power-up
3. Open drain
Table 1.
Signal name
Symbol
XI(1)
XO
(1)
IRQ/FT/OUT
(2)
SQW
RST
E
Description
32 kHz oscillator input
32 kHz oscillator output
Interrupt /frequency test/output driver (open drain)
32 kHz programmable square wave output
Power-on reset output (open drain)
Chip enable
SDI
Serial data address input
SDO
Serial data address output
SCL
Serial clock input
VBAT
Battery supply voltage (Tie VBAT to VSS if no battery is connected.)
DU(3)
Do not use
VCC
Supply voltage
VSS
Ground
1. For QFN16 package only
2. Defaults to 32 kHz on power-up
3. Do not use (must be tied to VCC)
7/51
Description
M41T93
(1)
XI
VCC
E
QFN16 (QA) connections
XO
Figure 2.
16
15
14
13
1
12
SDO
NC
2
11
IRQ/FT/OUT
NC
3
10
SCL
(2)
4
9
SDI
RST
(1)
5
6
7
8
VSS
NC
NC
SQW
VBAT
M41T93
AI11819
1. Open drain output
2. Defaults to 32 kHz on power-up
Figure 3.
SOX18 (MY) connections
NC
NF(1)
(1)
NF
NC
(2)
RST
(3)
DU
(4)
SQW
VBAT
VSS
1
2
3
4
5
6
7
8
9
M41T93
18
17
16
15
14
13
12
11
10
NC
NF(1)
(1)
NF
VCC
E
SDO
IRQ/FT/OUT(2)
SCL
SDI
AI11820
1. NF pins must be tied to VSS. Pins 2 and 3, and 16 and 17 are internally shorted together.
2. Open drain output
3. Do not use (must be tied to VCC)
4. Defaults to 32kHz on power-up
8/51
M41T93
Figure 4.
Description
Block diagram
REAL TIME CLOCK
CALENDAR
OSCILLATOR FAIL
CIRCUIT
XI
32kHz
OSCILLATOR
XO
CRYSTAL
E
OFIE
A1IE
ALARM1
ALARM2
(1)
IRQ/FT/OUT
WATCHDOG
SDI
SPI
INTERFACE
SCL
SDO
WRITE
PROTECT
VCC < VRST
FT
FREQUENCY TEST
OUT
OUTPUT DRIVER
TIE
8-BIT COUNTER
SQWE
SQUARE WAVE
SQW
8 BITS OF OTP
USER SRAM (7 Bytes)
INTERNAL
POWER
VCC
VBAT
VRST/VSO(2)
COMPARE
trec
TIMER
RST(1)
AI11821
1. Open drain output
2. VRST = VSO = 2.93 V (S), 2.63 V (R), and 2.32 V (Z)
9/51
Description
Figure 5.
M41T93
Hardware hookup
VCC
MCU
(ST6, ST7, ST9, ST10, Others)
M41T93
VCC
XI
VCC
(1)
IRQ/FT/OUT
(1)
RST
INT
Reset Input
XO
SCL
SCL
VBAT
SDO
SDI
SDI
SDO
VSS
(2)
SPI Interface with
(CPOL = 0, CPHA = 0)
CS
E
32kHz CLKIN
SQW
AI11822
1. Open drain output
2. CPOL (clock polarity) and CPHA (clock phase) are bits that may be set in the SPI control register of the MCU.
Table 2.
Function table
Mode
E
SCL
SDI
SDO
Disable reset
H
Input disabled
Input disabled
High Z
WRITE
L
Data bit latch
High Z
X
Next data bit shift(1)
AI04630
READ
L
AI04631
1. SDO remains at High Z until eight bits of data are ready to be shifted out during a READ.
Figure 6.
Data and clock timing
CPOL
CPHA
0
0
C
SDI
MSB
LSB
SDO
MSB
LSB
AI04632
Note:
10/51
Supports SPI mode 0 (CPOL = 0, CPHA = 0) only.
M41T93
Description
1.1
SPI signal description
1.1.1
Serial data output (SDO)
The output pin is used to transfer data serially out of the memory. Data is shifted out on the
falling edge of the serial clock.
1.1.2
Serial data input (SDI)
The input pin is used to transfer data serially into the device. Instructions, addresses, and
the data to be written, are each received this way. Input is latched on the rising edge of the
serial clock.
1.1.3
Serial clock (SCL)
The serial clock provides the timing for the serial interface (as shown in Figure 19 on
page 41 and Figure 20 on page 41). The W/R bit, addresses, or data are latched, from the
input pin, on the rising edge of the clock input. The output data on the SDO pin changes
state after the falling edge of the clock input.
The M41T93 can be driven by a microcontroller with its SPI peripheral running in only mode
0: (CPOL, CPHA) = (0,0).
For this mode, input data (SDI) is latched in by the low-to-high transition of clock SCL, and
output data (SDO) is shifted out on the high-to-low transition of SCL (see Table 2 on
page 10 and Figure 6 on page 10).
1.1.4
Chip enable (E)
When E is high, the memory device is deselected, and the SDO output pin is held in its high
impedance state.
After power-on, a high-to-low transition on E is required prior to the start of any operation.
11/51
Operation
2
M41T93
Operation
The M41T93 clock operates as a slave device on the SPI serial bus. Each memory device is
accessed by a simple serial interface that is SPI bus-compatible. The bus signals are SCL,
SDI, and SDO (see Table 1 on page 7 and Figure 5 on page 10). The device is selected
when the chip enable input (E) is held low. All instructions, addresses and data are shifted
serially in and out of the chip. The most significant bit is presented first, with the data input
(SDI) sampled on the first rising edge of the clock (SCL) after the chip enable (E) goes low.
The 32 bytes contained in the device can then be accessed sequentially in the following
order:
1
Tenths/hundredths of a second register
2
Seconds register
3
Minutes register
4
Century/hours register
5
Day register
6
Date register
7
Month register
8
Year register
9
Digital calibration register
10
Watchdog register
11-15 Alarm1 registers
16
Flags register
17
Timer value register
18
Timer control register
19
Analog calibration register
20
Square wave register
21-25 Alarm2 registers
26-32 User RAM
The M41T93 clock continually monitors VCC for an out-of tolerance condition. Should VCC
fall below VRST, the device terminates an access in progress and resets the device address
counter. Inputs to the device will not be recognized at this time to prevent erroneous data
from being written to the device from a an out-of-tolerance system.
The power input will also be switched from the VCC pin to the external battery when VCC falls
below the battery back-up switchover voltage (VSO = VRST). At this time the clock registers
will be maintained by the battery supply. As system power returns and VCC rises above VSO,
the battery is disconnected, and the power supply is switched to external VCC.
Write protection continues until VCC reaches VPFD (min) plus tREC (min). For more
information on battery storage life refer to application note AN1012.
12/51
M41T93
2.1
Operation
SPI bus characteristics
The serial peripheral interface (SPI) bus is intended for synchronous communication
between different ICs. It consists of four signal lines: serial data input (SDI), serial data
output (SDO), serial clock (SCL) and a chip enable (E).
By definition a device that gives out a message is called “transmitter,” the receiving device
that gets the message is called “receiver.” The device that controls the message is called
“master.” The devices that are controlled by the master are called “slaves.”
The E input is used to initiate and terminate a data transfer. The SCL input is used to
synchronize data transfer between the master (micro) and the slave (M41T93) device.
The SCL input, which is generated by the microcontroller, is active only during address and
data transfer to any device on the SPI bus (see Figure 5 on page 10).
The M41T93 can be driven by a microcontroller with its SPI peripheral running in only mode
0: (CPOL, CPHA) = (0,0).
For this mode, input data (SDI) is latched in by the low-to-high transition of clock SCL, and
output data (SDO) is shifted out on the high-to-low transition of SCL (see Table 2 and
Figure 6 on page 10).
There is one clock for each bit transferred. Address and data bits are transferred in groups
of eight bits. Due to memory size the second most significant address bit is a “don’t care”
(address bit 6).
2.2
Read and write cycles
Address and data are shifted MSB first into the serial data input (SDI) and out of the serial
data output (SDO). Any data transfer considers the first bit to define whether a READ or
WRITE will occur. This is followed by seven bits defining the address to be read or written.
Data is transferred out of the SDO for a READ operation and into the SDI for a WRITE
operation. The address is always the second through the eighth bit written after the enable
(E) pin goes low. If the first bit is a '1,' one or more WRITE cycles will occur. If the first bit is a
'0,' one or more READ cycles will occur (see Figure 7 and Figure 8 on page 14).
Data transfers can occur one byte at a time or in multiple byte burst mode, during which the
address pointer will be automatically incremented. For a single byte transfer, one byte is
read or written and then E is driven high. For a multiple byte transfer all that is required is
that E continue to remain low. Under this condition, the address pointer will continue to
increment as stated previously. Incrementing will continue until the device is deselected by
taking E high. The address will wrap to 00h after incrementing to 3Fh.
The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (00h to 07h). Although the clock continues to maintain the correct time, this
will prevent updates of time and date during either a READ or WRITE of these address
locations by the user. The update will resume either due to a deselect condition or when the
pointer increments to an non-clock or RAM address (08h to 1Fh).
Note:
This is true both in READ and WRITE mode.
13/51
Operation
Figure 7.
M41T93
Read mode sequence
E
0
3
2
1
5
4
7
6
9
8
12 13 14 15 16 17
22
SCL
7 BIT ADDRESS
W/R BIT
7
SDI
6
5
4
3
2
1
0
MSB
SDO
DATA OUT
(BYTE 1)
7
HIGH IMPEDANCE
6
5
4
3
2
DATA OUT
(BYTE 2)
1
0
7
6
5
4
3
2
1
0
MSB
MSB
AI04635
Figure 8.
Write mode sequence
E
0
1
3
2
4
5
6
7
8
9
15
10
SCL
SDI
DATA BYTE
7 BIT ADDR
W/R BIT
7
MSB
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
SDO
HIGH IMPEDANCE
AI04636
14/51
M41T93
2.3
Operation
Data retention and battery switchover (VSO = VRST)
Once VCC falls below the switchover voltage (VSO = VRST), the device automatically
switches over to the battery and powers down into an ultra low current mode of operation to
preserve battery life. If VBAT is less than, or greater than VRST, the device power is switched
from VCC to VBAT when VCC drops below VRST (see Figure 18 on page 40). At this time the
clock registers and user RAM will be maintained by the attached battery supply.
When it is powered back up, the device switches back from battery to VCC at VSO +
hysteresis. When VCC rises above VRST, it will recognize the inputs. For more information
on battery storage life refer to application note AN1012.
2.4
Power-on reset (trec)
The M41T93 continuously monitors VCC. When VCC falls to the power fail detect trip point,
the RST output pulls low (open drain) and remains low after power-up for trec (210ms
typical) after VCC rises above VRST (max).
Note:
The trec period does not affect the RTC operation. Write protect only occurs when VCC is
below VRST. When VCC rises above VRST, the RTC will be selectable immediately. Only the
RST output is affected by the trec period.
The RST pin is an open drain output and an appropriate pull-up resistor to VCC should be
chosen to control the rise time.
15/51
Clock operation
3
M41T93
Clock operation
The M41T93 is driven by a quartz-controlled oscillator with a nominal frequency of
32.768 kHz. The accuracy of the real-time clock depends on the frequency of the quartz
crystal that is used as the time-base for the RTC.
The 8-byte clock register (see Table 3 on page 18) is used to both set the clock and to read
the date and time from the clock, in binary coded decimal format. Tenths/hundredths of
seconds, seconds, minutes, and hours are contained within the first four registers.
Bit D7 of register 01h contains the STOP bit (ST). Setting this bit to a '1' will cause the
oscillator to stop. When reset to a '0' the oscillator restarts within one second (typical).
Note:
Upon initial power-up, the user should set the ST bit to a '1,' then immediately reset the ST
bit to '0.' This provides an additional “kick-start” to the oscillator circuit.
Bits D6 and D7 of clock register 03h (century/ hours register) contain the CENTURY bit 0
(CB0) and CENTURY bit 1 (CB1). Bits D0 through D2 of register 04h contain the day (day of
week). Registers 05h, 06h, and 07h contain the date (day of month), month, and years. The
ninth clock register is the digital calibration register, while the analog calibration register is
found at address 12h (these are both described in the clock calibration section). Bit D7 of
register 09h (watchdog register) contains the oscillator fail interrupt enable bit (OFIE). When
the user sets this bit to '1,' any condition which sets the oscillator fail bit (OF) (see Oscillator
fail detection on page 34) will also generate an interrupt output.
Note:
A WRITE to ANY location within the first eight bytes of the clock register (00h-07h),
including the ST bit and CB0-CB1 bits will result in an update of the system clock and a
reset of the divider chain. This could result in an inadvertent change of the current time.
These non-clock related bits should be written prior to setting the clock, and remain
unchanged until such time as a new clock time is also written.
The eight clock registers may be read one byte at a time, or in a sequential block. Provision
has been made to assure that a clock update does not occur while any of the eight clock
addresses are being read. If a clock address is being read, an update of the clock registers
will be halted. This will prevent a transition of data during the READ.
3.1
Power-down time-stamp
When a power failure occurs, the halt update bit (HT) will automatically be set to a “1”. This
will prevent the clock from updating the clock/control registers, and will allow the user to
read the exact time of the power-down event. Resetting the HT bit to a “0” will allow the clock
to update the clock/registers with the current time. For more information, see application
note AN1572.
3.2
Clock/control register map
The M41T93 offers 32 internal registers which contain clock, calibration (digital and analog),
alarm 1 and 2, watchdog, flags, timer, and square wave. The clock registers are memory
locations which contain external (user accessible) and internal copies of the data (usually
referred to as BiPORT™ TIMEKEEPER® cells). The external copies are independent of
internal functions except that they are updated periodically by the simultaneous transfer of
the incremented internal copy. The internal divider (or clock) chain will be reset upon the
16/51
M41T93
Clock operation
completion of a WRITE to any clock address (00h to 07h). The system-to-user transfer of
clock data will be halted whenever the address being read is a clock address (00h to 07h).
The update will resume either due to a stop condition or when the pointer increments to a
non-clock address. Clock and alarm registers store data in BCD format. Calibration, timer,
watchdog, and square wave bits are written in a binary format.
17/51
Clock operation
Table 3.
M41T93
Clock/control register map (32 bytes)
Addr
Function/range BCD format
D7
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
ST
0
CB1
0
0
0
OUT
OFIE
A1IE
RPT14
RPT13
RPT12
RPT11
WDF
TE
12h
ACS
13h
14h
15h
16h
17h
18h
19h1Fh
RS3
0
RPT24
RPT23
RPT22
RPT21
D6
D5
D4
D3
D2
D1
D0
0.1 seconds
0.01 seconds
10 seconds
Seconds
10 minutes
Minutes
CB0
10 hours
Hours (24-hour format)
0
0
0
0
Day of week
0
10 date
Date: day of month
0
0
10M
Month
10 Years
Year
FT
DCS
DC4
DC3
DC2
DC1
DC0
BMB4
BMB3
BMB2
BMB1
BMB0
RB1
RB0
SQWE
ABE Al1 10M
Alarm1month
RPT15
AI1 10 date
Alarm1 date
HT
AI1 10 hour
Alarm1 hour
Alarm1 10 minutes
Alarm1 minutes
Alarm1 10 seconds
Alarm1 seconds
BL
TF
OF
0
0
AF1
AF2(1)
Timer countdown value
TIE
0
0
0
TD1
TD0
TI/TP
AC6
AC5
AC4
RS2
RS1
RS0
0
0
Al2 10M
RPT25
AI2 10 date
0
AI2 10 hour
Alarm2 10 minutes
Alarm2 10 seconds
AC3
0
User SRAM (7 bytes)
AC2
AC1
0
AL2E
Alarm2 month
Alarm2 month
Alarm2 date
Alarm2 minutes
Alarm2 seconds
AC0
OTP
Seconds
00-99
Seconds
00-59
Minutes
00-59
Century/hours
0-3/00-23
Day
01-7
Date
01-31
Month
01-12
Year
00-99
Digital calibration
Watchdog
Al1 month
01-12
Al1 date
01-31
Al1 hour
00-23
Al1 min
00-59
Al1 sec
00-59
Flags
Timer value
Timer control
Analog
calibration
SQW
SRAM/Al2 month
01-12
SRAM/Al2 date
01-31
SRAM/Al2 hour
00-23
SRAM/Al2 min
00-59
SRAM/Al2 sec
00-59
SRAM
1. AF2 will always read ‘0’ if the AL2E bit is set to ‘0’.
0 = Must be set to zero
ABE = Alarm in battery backup enable bit
A1IE = Alarm1 interrupt enable bit
AC0-AC6 = analog calibration bits
ACS = analog calibration sign bit
AF1, AF2 = Alarm flag
AL2E = Alarm 2 enable bit
BL = Battery low bit
BMB0-BMB4 = Watchdog multiplier bits
CB0, CB1 = Century bits
DC0-DC4 = Digital calibration bits
DCS = Digital calibration sign bit
FT = Frequency test bit
HT = Halt update bit
OF = Oscillator fail bit
OUT= Output level
18/51
OFIE = Oscillator fail interrupt enable
OTP = OTP control bit
RB0-RB2 = Watchdog resolution bits
RPT11-RPT15 = Alarm 1 repeat mode bits
RPT21-RPT25 = Alarm 2 repeat mode bits
RS0-RS3 = SQW frequency
SQWE = Square wave enable
SRAM/ALM2 = SRAM/Alarm 2 bit
ST = Stop bit
TD0, TD1 = Timer frequency bits
TE = Timer enable bit
TF = Timer flag
TI/TP = Timer interrupt or pulse
TIE = Timer interrupt enable
WDF = Watchdog flag
M41T93
3.3
Clock operation
Real-time clock accuracy
The M41T93 is driven by a quartz controlled oscillator with a nominal frequency of
32,768 Hz. The accuracy of the real-time clock is dependent upon the accuracy of the
crystal, and the match between the capacitive load of the oscillator circuit and the capacitive
load for which the crystal was trimmed. Temperature also affects the crystal frequency,
causing additional error (see Figure 10 on page 23).
The M41T93 provides the option of clock correction through either manufacturing calibration
or in-application calibration. The total possible compensation is typically –93 ppm to +156
ppm. The two compensation circuits that are available are:
1.
An analog calibration register (12h) can be used to adjust internal (on-chip) load
capacitors for oscillator capacitance trimming. The individual load capacitors CXI and
CXO (see Figure 9), are selectable from a range of –18 pF to +9.75 pF in steps of
0.25pF. This translates to a calculated compensation of approximately ±30 ppm (see
Analog calibration (programmable load capacitance) on page 22).
2.
A digital calibration register (08h) can also be used to adjust the clock counter by
adding or subtracting a pulse at the 512 Hz divider stage. This approach provides
periodic compensation of approximately –63 ppm to +126 ppm (see Digital calibration
(periodic counter correction) on page 20).
Figure 9.
Internal load capacitance adjustment
XI
CXI
Crystal Oscillator
XO
CXO
AI11804
19/51
Clock operation
3.4
M41T93
Clock calibration
The M41T93 oscillator is designed for use with a 12.5 pF crystal load capacitance. When
the calibration circuit is properly employed, accuracy improves to better than ±1 ppm at
25°C.
The M41T93 design provides the following two methods for clock error correction.
3.4.1
Digital calibration (periodic counter correction)
This method employs the use of periodic counter correction by adjusting the ratio of the
100 Hz divider stage to the 512 Hz divider stage. Under normal operation, the 100Hz divider
stage outputs precisely 100 pulses for every 512 pulses of the 512 Hz input stage to provide
the input frequency to the fraction of seconds clock register. By adjusting the number of
512 Hz input pulses used to generate 100 output pulses, the clock can be sped up or slowed
down, as shown in Figure 12 on page 26.
When a non-zero value is loaded into the five calibration bits (DC4 – DC0) found in the
digital calibration register (08h) and the sign bit is ‘1,’ (indicating positive calibration), the
100 Hz stage outputs 100 pulses for every 511 input pulses instead of the normal 512.
Since the 100 pulses are now being output in a shorter window, this has the effect of
speeding up the clock by 1/512 seconds for each second the circuit is active. Similarly, when
the sign bit is ‘0,’ indicating negative calibration, the block outputs 100 pulses for every 513
input pulses. Since the 100 pulses are then being output in a longer window, this has the
effect of slowing down the clock by 1/512 seconds for each second the circuit is active.
The amount of calibration is controlled by using the value in the calibration register (N) to
generate the adjustment in one second increments. This is done for the first N seconds once
every eight minutes for positive calibration, and for N seconds once every sixteen minutes
for negative calibration (see Table 4 on page 21).
For example, if the calibration register is set to '100010,' then the adjustment will occur for
two seconds in every minute. Similarly, if the calibration register is set to '000011,' then the
adjustment will occur for 3 seconds in every alternating minute.
The digital calibration bits (DC4 – DC0) occupy the five lower order bits in the digital
calibration register (08h). These bits can be set to represent any value between 0 and 31 in
binary form. The sixth bit (DCS) is a sign bit; '1' indicates positive calibration, '0' indicates
negative calibration. Calibration occurs within an 8-minute (positive) or 16-minute (negative)
cycle. Therefore, each calibration step has an effect on clock accuracy of +4.068 or –2.034
ppm. Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments
in the calibration byte would represent +10.7 or –5.35 seconds per month, which
corresponds to a total range of +5.5 or –2.75 minutes per month.
Note:
20/51
1
The modified pulses are not observable on the frequency test (FT) output, nor will the effect
of the calibration be measurable real-time, due to the periodic nature of the error
compensation.
2
Positive digital calibration is performed on an eight minute cycle, therefore the value in the
calibration register should not be modified more frequently than once every eight minutes for
positive values of calibration. Negative digital calibration is performed on a sixteen minute
cycle, therefore negative values in the calibration register should not be modified more
frequently than once every sixteen minutes.
M41T93
Clock operation
Table 4.
Digital calibration values
Calibration value (binary)
Calibration value rounded to the nearest ppm
DC4 – DC0
Negative calibration (DCS = 0) Positive calibration (DCS = 1)
0 (00000)
0
0
1 (00001)
–2
4
2 (00010)
–4
8
3 (00011)
–6
12
4 (00100)
–8
16
5 (00101)
–10
20
6 (00110)
–12
24
7 (00111)
–14
28
8 (01000)
–16
33
9 (01001)
–18
37
10 (01010)
–20
41
11 (01011)
–22
45
12 (01100)
–24
49
13 (01101)
–26
53
14 (01110)
–28
57
15 (01111)
–31
61
16 (10000)
–33
65
17 (10001)
–35
69
18 (10010)
–37
73
19 (10011)
–39
77
20 (10100)
–41
81
21 (10101)
–43
85
22 (10110)
–45
90
23 (10111)
–47
94
24 (11000)
–49
98
25 (11001)
–51
102
26 (11010)
–53
106
27 (11011)
–55
110
28 (11100)
–57
114
29 (11101)
–59
118
30 (11110)
–61
122
31 (11111)
–63
126
N
N/491520 (per minute)
N/245760 (per minute)
21/51
Clock operation
3.4.2
M41T93
Analog calibration (programmable load capacitance)
A second method of calibration employs the use of programmable internal load capacitors to
adjust (or trim) the oscillator frequency.
By design, the oscillator is intended to be 0 ppm ± crystal accuracy at room temperature
(25°C, see Figure 10 on page 23). For a 12.5 pF crystal, the default loading on each side of
the crystal will be 25 pF. For incrementing or decrementing the calibration value,
capacitance will be added or removed in increments of 0.25 pF to each side of the crystal.
Internally, CLOAD of the oscillator is changed via two digitally controlled capacitors, CXI and
CXO, connected from the XI and XO pins to ground (see Figure 9 on page 19). The effective
on-chip series load capacitance, CLOAD, ranges from 3.5 pF to 17.4 pF, with a nominal value
of 12.5 pF (AC0-AC6 = ‘0’).
The effective series load capacitance (CLOAD) is the combination of CXI and CXO:
C LOAD = 1 ⁄ ( 1 ⁄ C XI + 1 ⁄ C XO )
Seven analog calibration bits, AC0 to AC6, are provided in order to adjust the on-chip load
capacitance value for frequency compensation of the RTC. Each bit has a different weight
for capacitance adjustment. An analog calibration sign (ACS) bit determines if capacitance
is added (ACS bit = ‘0,’ negative calibration) or removed (ACS bit = ‘1,’ positive calibration).
The majority of the calibration adjustment is positive (i.e. to increase the oscillator frequency
by removing capacitance) due to the typical characteristic of quartz crystals to slow down
due to changes in temperature, but negative calibration is also available.
Since the analog calibration register adjustment is essentially “pulling” the frequency of the
oscillator, the resulting frequency changes will not be linear with incremental capacitance
changes. The equations which govern this mechanism indicate that smaller capacitor values
of analog calibration adjustment will provide larger increments. Thus, the larger values of
analog calibration adjustment will produce smaller incremental frequency changes. These
values typically vary from 6-10 ppm/bit at the low end to <1 ppm/bit at the highest
capacitance settings. The range provided by the analog calibration register adjustment with
a typical surface mount crystal is approximately ±30 ppm around the AC6-AC0 = 0 default
setting because of this property (see Table 5 on page 23).
22/51
M41T93
Clock operation
Figure 10. Crystal accuracy across temperature
Frequency (ppm)
20
0
–20
–40
–60
ΔF = K x (T – T )2
O
F
–80
2
K = –0.036 ppm/°C ± 0.006 ppm/°C
–100
2
TO = 25°C ± 5°C
–120
–140
–160
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
AI07888
Table 5.
Addr
Analog calibration values
Analog
calibration
value
D7
ACS
(±)
12h
D6
D5
AC5
AC6
(16 pF) (8 pF)
D4
D3
D2
D1
D0
AC4
AC3
AC2
AC1
AC0
(4 pF)
(2 pF)
( 1pF)
CXI, CXO CLOAD(1)
(0.5 pF) (0.25 pF)
0 pF
x
0
0
0
0
0
0
0
25 pF
12.5 pF
3 pF
0
0
0
0
1
1
0
0
28 pF
14 pF
5 pF
0
0
0
1
0
1
0
0
30 pF
15 pF
–7 pF
1
0
0
1
1
1
0
0
18 pF
9 pF
pF(2)
0
0
1
0
0
1
1
1
34.75 pF
17.4 pF
(3)
1
1
0
0
1
0
0
0
7 pF
3.5 pF
9.75
–18 pF
1. CLOAD = 1/(1/CXI + 1/CXO)
2. Maximum negative calibration value
3. Maximum positive calibration value
23/51
Clock operation
M41T93
The on-chip capacitance can be calculated as follows:
C LOAD = [ ( AC6 – AC0 value, decimal) × 0.25pF ] + 7pF
For example:
CLOAD (12h = x0000000) = 12.5 pF
CLOAD (12h =11001000) = 3.5 pF and
CLOAD (12h = 00100111) = 17.4 pF
The oscillator sees a minimum of 3.5 pF with no programmable load capacitance selected.
Note:
These are typical values, and the total load capacitance seen by the crystal will include
approximately 1-2 pF of package and board capacitance in addition to the analog calibration
register value.
Any invalid value of analog calibration will result in the default capacitance of 25 pF.
The combination of analog and digital trimming can give up to –93 to +156 ppm of the total
adjustment.
Figure 11 on page 25 represents a typical curve of clock ppm adjustment versus the Analog
Calibration value. This curve may vary with different crystals, so it is good practice to
evaluate the crystal to be used with an M41T93 device before establishing the adjustment
values for the application in question.
24/51
M41T93
Clock operation
Figure 11. Clock accuracy vs. on-chip load capacitors
100.0
XI
XO
PPM ADJUSTMENT
80.0
Crystal
Oscillator
60.0
CXI
CXO
40.0
CLOAD =
20.0
CXI * CXO
CXI + CXO
On-Chip
FASTER
DECREASING LOAD CAP.
0.0
INCREASING LOAD CAP.
SLOWER
-20.0
OFFSET TO
CXI, CXO (pF)
NET EQUIV. LOAD
CAP., C LOAD, (pF)
Analog Calibration
Value, AC,
register 0x12
-18.0 -15.0
3.5
5.0
0xC8 0xBC
-10.0
-5.0
0.0
5.0
7.5
10
12.5
15
0xA8
0x94
0x00
0x14
9.75
17.4
0x27
ai13906
25/51
Clock operation
M41T93
Two methods are available for ascertaining how much calibration a given M41T93 may
require:
Note:
●
The first involves setting the clock, letting it run for a month and comparing it to a known
accurate reference and recording deviation over a fixed period of time. This allows the
designer to give the end user the ability to calibrate the clock as the environment
requires, even if the final product is packaged in a non-user serviceable enclosure. The
designer could provide a simple utility that accesses either or both of the calibration
bytes.
●
The second approach is better suited to a manufacturing environment, and involves the
use of the IRQ/FT/OUT pin. The IRQ/FT/ OUT pin will toggle at 512 Hz when FT and
OUT bits = '1' and ST = '0.' Any deviation from 512 Hz indicates the degree and
direction of oscillator frequency shift at the test temperature. For example, a reading of
512.010124 Hz would indicate a +20 ppm oscillator frequency error, requiring either a
–10 (xx001010) to be loaded into the digital calibration byte, or +6 pF (00011000) into
the analog calibration byte for correction.
Setting or changing the digital calibration byte does not affect the frequency test, square
wave, or watchdog timer frequency, but changing the analog calibration byte DOES affect all
functions derived from the low current oscillator (see Figure 12).
Figure 12. Clock divider chain and calibration circuits
512Hz Output
Frequency Test
÷2
÷2
÷2
÷2
÷2
Remainder of
Divider Circuit
Square Wave
Watchdog Timer
8-Bit Timer
CXI
Low Current
Oscillator
32kHz
÷8
CXO
Clock
Registers
1Hz Signal
Analog Calibration
Circuitry
26/51
Digital Calibration Circuitry
(divide by 511/512/513)
AI11806a
M41T93
Clock operation
Figure 13. Crystal isolation example
Crystal
Local Grounding
Plane (Layer 2)
XI XO
VSS
AI11814
Note:
The substrate pad should be tied to VSS.
3.5
Setting the alarm clock registers
Address locations 0Ah-0Eh (alarm 1) and 14h-18h (alarm 2) contain the alarm settings.
Either alarm can be configured independently to go off at a prescribed time on a specific
month, date, hour, minute, or second, or repeat every year, month, day, hour, minute, or
second. Bits RPT15–RPT11 and RPT25-RPT21 put the alarms in the repeat mode of
operation. Table 6 on page 28 shows the possible bit configurations.
Codes not listed in the table default to the once-per-second mode to quickly alert the user of
an incorrect alarm setting. When the clock information matches the alarm clock settings
based on the match criteria defined by RPT15–RPT11 and/or RPT25-RPT21, AF1 (alarm 1
flag) or AF2 (alarm 2 flag) is set. If A1IE (alarm 1 interrupt enable) is set, the alarm condition
activates the IRQ/FT/OUT output pin. To disable either of the alarms, write a '0' to the alarm
date registers and to the RPTx5–RPTx1 bits.
Note:
If the address pointer is allowed to increment to the flag register address, or the last address
written is “Alarm Seconds,” the address pointer will increment to the flag address, and an
alarm condition will not cause the interrupt/flag to occur until the address pointer is moved to
a different address.
The IRQ output is cleared by a READ to the flags register (0Fh) as shown in Figure 14. A
subsequent READ of the flags register is necessary to see that the value of the alarm flag
has been reset to '0.'.
The IRQ/FT/OUT pin can also be activated in the battery backup mode (see Figure 15 on
page 28).
27/51
Clock operation
3.6
M41T93
Optional second programmable alarm
When the alarm 2 enable (AL2E) bit (D1 of address 13h) is set to a logic ‘1,’ registers 14h
through 18h provide control for a second programmable alarm which operates in the same
manner as the alarm function described above.
The AL2E bit defaults on initial power-up to a logic ‘0’ (alarm 2 disabled). In this mode, the
five address bytes (14h-18h) function as additional user SRAM, for a total of 12 bytes of
user SRAM.
Figure 14. Alarm interrupt reset waveform
0Eh
0Fh
00h
ALARM FLAG BITS (AFx)
HIGH-Z
IRQ/FT/OUT
AI11823
Figure 15. Backup mode alarm waveform
VCC
VPFD
VSO
trec
AFx Bits in Flags
Register
IRQ/FT/OUT
HIGH-Z
Note:
ABE and A1IE bits = 1.
Table 6.
28/51
AI11824
Alarm repeat modes
RPT5
RPT4
RPT3
RPT2
RPT1
Alarm setting
1
1
1
1
1
Once per second
1
1
1
1
0
Once per minute
1
1
1
0
0
Once per hour
1
1
0
0
0
Once per day
1
0
0
0
0
Once per month
0
0
0
0
0
Once per year
M41T93
3.7
Clock operation
Watchdog timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user
programs the watchdog timer by setting the desired amount of time-out into the watchdog
register, address 09h. Bits BMB4-BMB0 store a binary multiplier and the two lower order bits
RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second,
and 11 = 4 seconds. The amount of time-out is then determined to be the multiplication of
the five-bit multiplier value with the resolution. (For example: writing 00001110 in the
watchdog register = 3*1, or 3 seconds). If the processor does not reset the timer within the
specified period, the M41T93 sets the WDF (watchdog flag) and generates a watchdog
interrupt.
The watchdog timer can be reset by having the microprocessor perform a WRITE of the
watchdog register. The time-out period then starts over.
Should the watchdog timer time-out, a value of 00h needs to be written to the watchdog
register in order to clear the IRQ/FT/OUT pin. This will also disable the watchdog function
until it is again programmed correctly. A READ of the flags register will reset the watchdog
flag (bit D7; register 0Fh).
The watchdog function is automatically disabled upon power-up and the watchdog register
is cleared. If the watchdog function is set, the frequency test function is activated, and the
SQWE bit is '0,' the watchdog function prevails and the frequency test function is denied.
3.8
8-bit (countdown) timer
The timer value register is an 8-bit binary countdown timer. It is enabled and disabled via the
timer control register (11h) TE bit. Other timer properties such as the source clock, or
interrupt generation are also selected in the timer control register (see Table 7). For
accurate read back of the countdown value, the serial clock (SCL) must be operating at a
frequency of at least twice the selected timer clock.
The timer control register selects one of four source clock frequencies for the timer (4096,
64, 1, or 1/60 Hz), and enables/disables the timer. The timer counts down from a softwareloaded 8-bit binary value. At the end of every countdown, the timer sets the timer flag (TF)
bit. The TF bit can only be cleared by software. When asserted, the timer flag (TF) can also
be used to generate an interrupt (IRQ/FT/OUT) on the M41T93. The interrupt may be
generated as a pulsed signal every countdown period or as a permanently active signal
which follows the condition of TF. The timer interrupt/timer pulse (TI/TP) bit is used to control
this mode selection. When reading the timer, the current countdown value is returned.
Table 7.
Timer control register map
Addr
D7
D6
D5
D4
D3
D2
D1
D0
Function
0Fh
WDF
AF1
AF2
BL
TF
OF
0
0
Flags
10h
11h
Note:
Timer countdown value
TE
TI/TP
TIE
0
0
Timer value
0
TD1
TD0
Timer control
Bit positions labeled with ‘0’ should always be written with logic '0.'
29/51
Clock operation
3.8.1
M41T93
TI/TP
●
TI/TP = 0
IRQ/FT/OUT is active when TF is logic '1' (subject to the status of the timer interrupt
enable bit (TIE).
●
TI/TP = 1
IRQ/FT/OUT pulses active according to Table 8 (subject to the status of the TIE bit).
Note:
If an alarm condition, watchdog time-out, oscillator failure, or OUT = 0 cause IRQ/FT/OUT to
be asserted low, then IRQ/FT/OUT will remain asserted even if TI/TP is set to '1.' When in
pulse mode (TI/TP = 1), clearing the TF bit will not stop the pulses on IRQ/FT/OUT. The
output pulses will only stop if TE, TIE, or TI/TP are reset to '0.'
Table 8.
Interrupt operation (bit TI/TP = 1)
IRQ(1) period(s)
Source clock (Hz)
n(2) = 1
n>1
4096
1/8192
1/4096
64
1/128
1/64
1
1/64
1/64
1/60
1/64
1/64
1. TF and IRQ/FT/OUT become active simultaneously.
2. n = loaded countdown timer value. The timer is stopped when n = 0.
3.8.2
TF
At the end of a timer countdown, TF is set to logic '1.' If both timer and alarm interrupts are
required in the application, the source of the interrupt can be determined by reading the flag
bits. The timer will auto-reload and continue to count down regardless of the state of TF bit
(or TI/TP bit). The TF bit is cleared by reading the flags register.
3.8.3
TIE
In level mode (TI/TP = 0), when TF is asserted, the interrupt is asserted (if TIE = 1). To clear
the interrupt, the TF bit or the TIE bit must be reset.
3.8.4
TE
●
TE = 0
When the timer register (10h) is set to ‘0,’ the timer is disabled.
●
TE = 1
The timer is enabled. TE is reset (disabled) on power-down. When re-enabled, the
counter will begin from the same value as when it was disabled.
30/51
M41T93
3.8.5
Clock operation
TD1/0
These are the timer source clock frequency selection bits (see Table 9). These bits
determine the source clock for the countdown timer (see Table 10). When not in use, the
TD1 and TD0 bits should be set to ‘11’ (1/60 Hz) for power saving.
Table 9.
Table 10.
Timer source clock frequency selection (244.1 µs to 4.25 hrs)
TD1
TD0
Timer source clock frequency (Hz)
0
0
4096 (244.1 µs)
0
1
64 (15.6 ms)
1
0
1 (1 s)
1
1
1/60 (60 s)
Timer countdown value register bits (addr 11h)
Bit
Symbol
7-0
<timer countdown value>
Description
This register holds the loaded countdown value ‘n.’
Countdown period = n / source clock frequency
Note:
Writing to the timer register will not reset the TF bit or clear the interrupt.
31/51
Clock operation
3.9
M41T93
Square wave output
The M41T93 offers the user a programmable square wave function which is output on the
SQW pin. RS3-RS0 bits located in 13h establish the square wave output frequency. These
frequencies are listed in Table 11. Once the selection of the SQW frequency has been
completed, the SQW pin can be turned on and off under software control with the square
wave enable bit (SQWE) located in register 0Ah.
Note:
If the SQWE bit is set to '1', and VCC falls below the switchover (VSO) voltage, the
squarewave output will be disabled.
Table 11.
Square wave output frequency
Square wave bits
32/51
Square wave
RS3
RS2
RS1
RS0
Frequency
Units
0
0
0
0
None
–
0
0
0
1
32.768
kHz
0
0
1
0
8.192
kHz
0
0
1
1
4.096
kHz
0
1
0
0
2.048
kHz
0
1
0
1
1.024
kHz
0
1
1
0
512
Hz
0
1
1
1
256
Hz
1
0
0
0
128
Hz
1
0
0
1
64
Hz
1
0
1
0
32
Hz
1
0
1
1
16
Hz
1
1
0
0
8
Hz
1
1
0
1
4
Hz
1
1
1
0
2
Hz
1
1
1
1
1
Hz
M41T93
3.10
Clock operation
Battery low warning
The M41T93 automatically performs battery voltage monitoring upon power-up and at
factory-programmed time intervals of approximately 24 hours. The battery low (BL) bit, bit
D4 of flags register 0Fh, will be asserted if the battery voltage is found to be less than
approximately 2.5 V. The BL bit will remain asserted until completion of battery replacement
and subsequent battery low monitoring tests, either during the next power-up sequence or
the next scheduled 24-hour interval.
If a battery low is generated during a power-up sequence, this indicates that the battery is
below approximately 2.5 volts and may not be able to maintain data integrity. Clock data
should be considered suspect and verified as correct. A fresh battery should be installed.
If a battery low indication is generated during the 24-hour interval check, this indicates that
the battery is near end of life. However, data is not compromised due to the fact that a
nominal VCC is supplied. In order to insure data integrity during subsequent periods of
battery backup mode, the battery should be replaced.
The M41T93 only monitors the battery when a nominal VCC is applied to the device. Thus
applications which require extensive durations in the battery backup mode should be
powered-up periodically (at least once every few months) in order for this technique to be
beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon
power-up via a checksum or other technique.
3.11
Century bits
These two bits will increment in a binary fashion at the turn of the century, and handle all
leap years correctly. See Table 12 for additional explanation.
Table 12.
Century bits examples
CB0
CB1
Leap Year?
Example(1)
0
0
Yes
2000
0
1
No
2100
1
0
No
2200
1
1
No
2300
1. Leap year occurs every four years (for years evenly divisible by four), except for years evenly divisible by
100. The only exceptions are those years evenly divisible by 400 (the year 2000 was a leap year, year
2100 is not).
3.12
Output driver pin
When the OFIE bit, A1IE bit, and watchdog register are not set to generate an interrupt, the
IRQ/FT/OUT pin becomes an output driver that reflects the contents of D7 of register 08h. In
other words, when D7 (OUT bit) is a '0,' then the IRQ/FT/OUT pin will be driven low.
Note:
The IRQ/FT/OUT pin is an open drain which requires an external pull-up resistor.
33/51
Clock operation
3.13
M41T93
Oscillator fail detection
If the oscillator fail (OF) bit is internally set to a '1,' this indicates that the oscillator has either
stopped, or was stopped for some period of time and can be used to judge the validity of the
clock and date data. This bit will be set to '1' any time the oscillator stops.
In the event the OF bit is found to be set to '1' at any time other than the initial power-up, the
STOP bit (ST) should be written to a '1,' then immediately reset to '0.' This will restart the
oscillator. The following conditions can cause the OF bit to be set:
●
Note:
The first time power is applied (defaults to a '1' on power-up).
If the OF bit cannot be written to '1' four seconds after the initial power-up, the STOP bit (ST)
should be written to a '1,' then immediately reset to '0.'
●
The voltage present on VCC or battery is insufficient to support oscillation
●
The ST Bit is set to '1.'
●
External interference of the crystal
For the M41T93, if the oscillator fail interrupt enable bit (OFIE) is set to a '1,' the
IRQ/FT/OUT pin will also be activated. The IRQ/FT/OUT output is cleared by resetting the
OFIE or OF bit to '0' (NOT by reading the flag register).
The OF bit will remain set to '1' until written to logic '0.' The oscillator must start and have
run for at least 4 seconds before attempting to reset the OF bit to '0.' If the trigger event
occurs during a power down condition, this bit will be set correctly.
3.14
Oscillator fail interrupt enable
If the oscillator fail interrupt bit (OFIE) is set to a '1,' the IRQ/FT/OUT pin will also be
activated. The IRQ/FT/OUT output is cleared by resetting the OFIE or OF bit to '0' (not be
reading the flags register).
34/51
M41T93
3.15
Clock operation
Initial power-on defaults
Upon initial application of power to the device, the register bits will initially power-on in the
state indicated in Table 13 and Table 14.
Table 13.
Initial power-on default values (part 1)
Condition(1)
ST
Initial
power-up
Subsequent
power-up(3)(4)
CB1 CB0 OUT FT
DCS Digital Analog
OFIE Watchdog(2)
ACS calib. calib.
A1IE SQWE ABE
0
0
0
1
0
0
0
0
0
0
0
1
0
UC
UC
UC
UC
0
UC
UC
UC
UC
0
UC
UC
UC
1. All other control bits power-up in an undetermined state
2. BMB0-BMB4, RB0, RB1
3. With battery backup
4. UC = Unchanged
Table 14.
Initial power-up default values (part 2)
Condition(1)
RPT11-15
HT
OF
TE
TI/TP
TIE
0
1
1
0
0
0
1
1
1
0
0
0
0
UC
1
UC
0
UC
UC
UC
UC
UC
UC
UC
UC
UC
Initial
power-up
Subsequent
power-up (2)(3)
TD1 TD0 RS0 RS1-3 OTP RPT21-25
AL2E
1. All other control bits power-up in an undetermined state
2. With battery backup
3. UC = Unchanged
3.16
OTP bit operation (SOX18 package only)
When the OTP (one time programmable) bit is set to a '1,' the value in the internal OTP
registers will be transferred to the analog calibration register (12h) and are “read only.” The
OTP value is programmed by the manufacturer, and will contain the calibration value
necessary to achieve ±5 ppm at room temperature after two SMT reflows. This clock
accuracy can be guaranteed to drift no more than ±3 ppm the first year, and ±1 ppm for
each following year due to crystal aging.
If the OTP bit is set to '0,' the analog calibration register will become a WRITE/READ
register and function like standard SRAM memory cells, allowing the user to implement any
desired value of analog calibration.
When the user sets the OTP bit, they need to wait for approximately 8 ms before the analog
registers transfer the value from the OTP to the analog registers due to the OTP read
operation.
35/51
Maximum ratings
4
M41T93
Maximum ratings
Stressing the device above the rating listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 15.
Absolute maximum ratings
Symbol
Parameter
Value(1)
Unit
TSTG
Storage temperature (VCC off, oscillator off)
–55 to 125
°C
VCC
Supply voltage
–0.3 to 7.0
V
QFN16
260
°C
SOX18
245
°C
–0.2 to Vcc+0.3
V
TSLD(2)
VIO
Lead solder temperature for 10 seconds
Input or output voltages
IO
Output current
20
mA
PD
Power dissipation
1
W
1. Data based on characterization results, not tested in production.
2. Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C for greater than 30
seconds).
36/51
M41T93
5
DC and AC parameters
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic
tables are derived from tests performed under the measurement conditions listed in the
relevant tables. Designers should check that the operating conditions in their projects match
the measurement conditions when using the quoted parameters.
Table 16.
Operating and AC measurement conditions
Parameter
M41T93
Supply voltage (VCC)
2.38 V to 5.5 V
Ambient operating temperature (TA)
–40 to +85°C
Load capacitance (CL, typical)
30 pF
≤ 50 ns
Input rise and fall times
Note:
Input pulse voltages
0.2VCC to 0.8VCC
Input and output timing ref. voltages
0.3VCC to 0.7VCC
Output Hi-Z is defined as the point where data is no longer driven.
Figure 16. Measurement AC I/O waveform
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI02568
Table 17.
Capacitance
Symbol
CIN
COUT
(3)
Parameter(1)(2)
Min
Max
Unit
Input capacitance
7
pF
Output capacitance
10
pF
1. Effective capacitance measured with power supply at 3.6 V; sampled only, not 100% tested
2. At 25°C, f = 1 MHz
3. Outputs deselected
37/51
DC and AC parameters
Table 18.
Sym
VCC
M41T93
DC characteristics
Test condition(1)
Min
Operating voltage (S)
–40 to 85°C
Operating voltage (R)
Parameter
Typ
Max
Unit
3.00
5.50
V
–40 to 85°C
2.70
5.50
V
2.38
Operating voltage (Z)
–40 to 85°C
5.50
V
ILI
Input leakage current
±1
µA
ILO
Output leakage current
0V ≤ VIN ≤ VCC
0V ≤ VOUT ≤ VCC
±1
µA
fSCL = 2 MHz
0.5
mA
ICC1
Supply current
SCL = 0.1VCC/0.9VCC
SDO = open
fSCL = 5 MHz
1.0
mA
fSCL = 10 MHz
2.0
mA
10
µA
ICC2
E = VCC;
Supply current (standby) All inputs ≥ VCC – 0.2 V;
≤ VSS + 0.2 V
VIL
Input low voltage
–0.3
0.3VCC
V
VIH
Input high voltage
0.7VCC
VCC+0.3
V
VOL
VOH
Output low voltage
Output high voltage
Pull-up supply voltage
(open drain)
VBAT
Backup supply voltage
IBAT
Battery supply current
5.5 V
8
3.0 V
6.5
RST, FT/RST
VCC/VBAT = 3.0 V,
IOL = 1.0 mA
0.4
V
SQW, IRQ/FT/OUT
VCC = 3.0 V,
IOL = 1.0 mA
0.4
V
SDO
VCC = 3.0 V,
IOL = 3.0 mA
0.4
V
VCC = 3.0 V, IOH = –1.0 mA (push-pull)
2.4
V
IRQ/FT/OUT
1.8
25°C; VCC = 0 V; OSC on; VBAT = 3 V;
32 kHz off
365
1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 2.38 V to 5.5 V (except where noted)
38/51
µA
5.5
V
5.5
V
450
nA
M41T93
DC and AC parameters
Figure 17. ICC2 vs. temperature
10.000
9.000
8.000
Icc2 (μA)
7.000
(3.0V)
(5.0V)
6.000
5.000
4.000
3.000
2.000
-40
-20
0
20
40
60
80
Temperature (˚C)
ai 13909
Table 19.
Crystal electrical characteristics
Symbol
Parameter(1)(2)
fO
Min
Resonant frequency
RS
Series resistance
CL
Load capacitance
Typ
Max
Units
32.768
kHz
65(3)
kΩ
12.5
pF
1. Externally supplied if using the QFN16 package. STMicroelectronics recommends the Citizen CFS-145
(1.5 x 5 mm) and the KDS DT-38 (3 x 8 mm) for thru-hole, or the KDS DMX-26S (3.2 x 8 mm) or Micro
Crystal MS3V-T1R (1.5 x 5 mm) for surface-mount, tuning fork-type quartz crystals. For contact
information, see Section 8: References on page 49.
2. Load capacitors are integrated within the M41T93. Circuit board layout considerations for the 32.768 kHz
crystal of minimum trace lengths and isolation from RF generating signals should be taken into account.
3. Guaranteed by design.
Table 20.
Oscillator characteristics
Parameter(1)(2)
Symbol
VSTA
Oscillator start voltage
tSTA
Oscillator start time
CXI, CXO(1)
Conditions
Min
≤4 s
2.0
IC-to-IC frequency
Max
1
25
–10
Units
V
VCC = VSO
Capacitor input, capacitor output
variation(2)(3)
Typ
s
pF
+10
ppm
1. With default analog calibration value ( = 0)
2. Reference value
3. TA = 25°C, VCC = 5.0 V
39/51
DC and AC parameters
M41T93
Figure 18. Power down/up mode AC waveforms
VCC
VSO
tPD
trec
SCL
SDI
DON'T CARE
AI11839
Table 21.
Power down/up trip points DC characteristics
Parameter(1)(2)
Sym
VRST
Reset threshold voltage
Min
Typ
Max
Unit
S
2.85
2.93
3.0
V
R
2.55
2.63
2.7
V
Z
2.25
2.32
2.38
V
Battery backup switchover
VSO
trec
VRST
V
Hysteresis
25
mV
Reset pulse width (VCC rising)
140
VCC to reset delay, VCC = (VRST + 100 mV), falling to
(VRST – 100 mV; for VCC slew rate of 10 mV/µs
280
2.5
1. All voltages referenced to VSS
2. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 2.38 to 5.5 V (except where noted)
40/51
ms
µs
M41T93
DC and AC parameters
Figure 19. Input timing requirements
tEHEL
E
tCHEL
tELCH
tCHEH
tEHCH
SCL
tDVCH
tCHCL
tCHDX
tCLCH
MSB IN
SDI
HIGH IMPEDANCE
SDO
LSB IN
tDLDH
tDHDL
AI12295
Figure 20. Output timing requirements
E
tCH
SCL
tCLQV
tCL
tEHQZ
tCLQX
SDO
LSB OUT
MSB OUT
tQLQH
tQHQL
SDI
ADDR. LSB IN
AI04634
41/51
DC and AC parameters
Table 22.
Sym
M41T93
AC characteristics
Parameter(1)
VCC < 2.7 V
VCC ≥ 2.7 V
Min
Max
Min
Max
D.C.
5
D.C.
10
Units
fSCL
SCL clock frequency
tELCH
E active setup time
90
30
ns
tEHCH
E not active setup time
90
30
ns
tEHEL
E deselect time
100
40
ns
tCHEH
E active hold time
90
30
ns
tCHEL
E not active hold time
90
30
ns
tCH(2)
Clock high time
90
40
ns
Clock low time
90
40
ns
tCL
(2)
tCLCH(3)
Clock rise time
1
2
µs
tCHCL(3)
Clock fall time
1
2
µs
tDVCH
Data in setup time
20
10
ns
tCHDX
Data in hold time
30
10
ns
(3)
Output disable time
100
40
ns
tCLQV
Clock low to output valid
60
40
ns
tCLQX
Output hold time
tQLQH(3)
Output rise time
50
40
ns
Output fall time
50
40
ns
tEHQZ
tQHQL
(3)
0
0
ns
1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 2.38 to 5.5 V (except where noted)
2. tCH and tCL must never be lower than the shortest possible clock period, 1/fC(max)
3. Value guaranteed by characterization, not 100% tested in production
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MHz
M41T93
6
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at www.st.com.
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Package mechanical data
M41T93
Figure 21. QFN16 – 16-lead, quad, flat package, no lead, 4 x 4 mm body size, outline
D
E
A3
A
A1
ddd C
e
b
L
K
1
(2)
2
E2
Ch
3
K
D2
QFN16-A2
1. Drawing is not to scale
2. Substrate pad should be tied to VSS
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M41T93
Package mechanical data
Table 23.
QFN16 – 16-lead, quad, flat package, no lead, 4 x 4 mm body, mech. data
mm
inches
Sym
Typ
Min
Max
Typ
Min
Max
A
0.90
0.80
1.00
0.035
0.032
0.039
A1
0.02
0.00
0.05
0.001
0.000
0.002
A3
0.20
–
–
0.008
–
–
b
0.30
0.25
0.35
0.010
0.007
0.012
D
4.00
3.90
4.10
0.118
0.114
0.122
D2
–
2.50
2.80
0.067
0.061
0.071
E
4.00
3.90
4.10
0.118
0.114
0.122
E2
–
2.50
2.80
0.067
0.061
0.071
e
0.65
–
–
0.020
–
–
K
0.20
–
–
0.008
–
–
L
0.40
0.30
0.50
0.016
0.012
0.020
ddd
–
0.08
–
–
0.003
–
Ch
–
0.33
–
–
0.013
–
N
16
16
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Package mechanical data
M41T93
Figure 22. QFN16 – 16-lead, quad, flat, no lead, 4 x 4 mm, recommended footprint
2.70
0.70
0.20
(2)
4.50
2.70
0.35
0.325
0.65
AI11815
1. Dimensions shown are in millimeters (mm)
2. Substrate pad should be tied to VSS
Figure 23. 32 kHz crystal + QFN16 vs. VSOJ20 mechanical data
6.0 ± 0.2
3.2
VSOJ20
SMT
CRYSTAL
1.5
7.0 ± 0.3
13
14
16 XO
15 XI
1
3.9
2
3
ST QFN16
4
3.9
Note:
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Dimensions shown are in millimeters (mm).
AI11816
M41T93
Package mechanical data
Figure 24. SOX18 – 18-lead plastic small outline, 300 mils, embedded crystal
D
9
h x 45°
1
C
E
10
H
18
A2
A
B
ddd
A1
e
A1
α
L
SO-J
Note:
Drawing is not to scale.
Table 24.
SOX18 – 18-lead plastic SO, 300 mils, embedded crystal, pkg. mech. data
mm
inches
Sym
Typ
Min
Max
Typ
Min
Max
A
–
2.44
2.69
–
0.096
0.106
A1
–
0.15
0.31
–
0.006
0.012
A2
–
2.29
2.39
–
0.090
0.094
B
–
0.41
0.51
–
0.016
0.020
C
–
0.20
0.31
–
0.008
0.012
D
11.61
11.56
11.66
0.457
0.455
0.459
ddd
–
–
0.10
–
–
0.004
E
–
7.57
7.67
–
0.298
0.302
e
1.27
–
–
0.050
–
–
H
–
10.16
10.52
–
0.400
0.414
L
–
0.51
0.81
–
0.020
0.032
α
–
0°
8°
–
0°
8°
N
18
18
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Part numbering
7
Part numbering
Table 25.
Ordering information
Example:
M41T93
M41T
93
S
QA
6
E
Device family
M41T
Device type
93
Operating voltage
S = VCC = 3.00 to 5.5 V
R = VCC = 2.70 to 5.5 V
Z = VCC = 2.38 to 5.5 V
Package
QA = QFN16 (4 mm x 4 mm)
MY(1) = SOX18
Temperature range
6 = –40°C to +85°C
Shipping method
E = ECOPACK® package, tubes
F = ECOPACK® package, tape & reel
1. The SOX18 package includes an embedded 32,768 Hz crystal. Contact local ST sales office for availability.
For other options, or for more information on any aspect of this device, please contact the ST sales office
nearest you.
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M41T93
8
References
References
Below is a listing of the crystal component suppliers mentioned in this document.
●
KDS can be contacted at [email protected] or http://www.kdsj.co.jp.
●
Citizen can be contacted at [email protected] or
http://www.citizencrystal.com.
●
Micro Crystal can be contacted at [email protected] or
http://www.microcrystal.com.
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Revision history
9
M41T93
Revision history
Table 26.
50/51
Document revision history
Date
Revision
Changes
07-Aug-2006
1
Initial release.
08-May-2007
2
Document status upgraded to full datasheet; updated Figure 11:
Clock accuracy vs. on-chip load capacitors; Section 3.16;
Section 3.4.1; Table 1, 15, and 18, Figure 3 and 23; added Figure 17:
ICC2 vs. temperature. Micro Crystal information added (Table 19).
22-Oct-2007
3
Updated Features on cover page; minor formatting changes;
modified footnote 1 in Table 19; added Section 8: References.
15-Aug-2008
4
Removed references to SPI bus mode 3 operation (updated cover
page, Figure 5, 6, Section 1.1.3, Section 2.1); minor formatting
changes.
M41T93
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