ICST ICS1886 Fddi / fast ethernet phyceivertm Datasheet

ICS1886
Integrated
Circuit
Systems, Inc.
FDDI / Fast Ethernet PHYceiverTM
General Description
Features
The ICS1886 is designed to provide high performance clock
recovery and generation for either 32.064 Mb/s, 34.368
Mb/s, 125 Mb/s or 139.264 Mb/s NRZ or NRZI serial data
streams. The ICS1886 is ideally suited for LAN transceiver
applications in either European or Japanese communication
environments.
•
Data and clock recovery for: 32.064 Mb/s (Japan)
34.368 Mb/s (Europe - E3) 125 MHz (Ethernet)
139.264 Mb/s (Europe - E4)
•
Clock multiplication from either a crystal, differential
or single-ended timing source
•
Continuous clock in the absence of data
The ICS1886 also operates at the 100Mbit Ethernet
frequency of 125 MHz. This is ideal for serial Ethernet data
applications where no serial to parallel conversion is
required.
•
No external PLL components
•
Lock/Loss status indicator output
•
Loopback mode for system diagnostics
•
Selectable loop timing mode
Clock and data recovery is performed on an input serial data
stream or the buffered transmit data depending upon the state
of the loopback input. A continuous clock source will
continue to be present even in the absence of input data. All
internal timing is derived from either a low cost crystal or an
external clock module.
•
PECL drivers with settable sink current
The ICS1886 utilizes advanced CMOS phase-locked loop
technology which combines high performance and low
power at a greatly reduced cost.
Pin Configuration
Block Diagram
28-Pin SOIC
PHYceiver is a trademark of Integrated Circuit Systems, Inc.
ICS1886RevC120996
ICS1886
Table 1 - Device Clock Selection
CS1
CS0
LOOP
INPUT
VSS
VSS
VDD
VDD
VSS
VSS
VDD
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
Tx
Tx
Tx
Tx
Rx
Rx
Rx
Rx
Data
Data
Data
Data
Data
Data
Data
Data
CLOCK FREQ
32.064 MHz
34.368 MHz
125.000 MHz
139.264 MHz
32.064 MHz
34.368 MHz
125.000MHz
139.264 MHz
MODE
Japan
Europe Ethernet
Europe Japan
Europe Ehternet
Europe -
E3
E4
E3
E4
REF FREQ or
CRYSTAL
4.008 MHz
4.296 MHz
25.000 MHz
17.408 MHz
4.008 MHz
4.296 MHz
25.000 MHz
17.408 MHz
Pin Descriptions
PIN
NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PIN NAME
TYPE
DESCRIPTION
VSS
LT~
CD~
TX+
TXVSS
IPRG1
RXRX+
LB~
LOCK
CS1
CS0
VSS
IPRG2
VSS
RD+
RDRC+
RCVDD
REF+
REFVDD
TCTC+
TDTD+
Negative supply voltage.
Loop Timing mode select.*
Carrier Detect input.*
Positive Transmit serial data output.
Negative Transmit serial data output.
Negative supply voltage.
PECL Output stage current set (TX).
Negative Receive serial data input.
Positive Receive serial data input.
Loop Back mode select.*
Lock detect output.
Clock select 1 input.
Clock select 0 input.
Negative supply voltage.
PECL Output stage current set (TC, RC and RD).
Negative supply voltage.
Positive recovered data output
Negative recovered data output.
Positive recovered clock output.
Negative recovered clock output.
Positive supply voltage.
Positive reference clock/crystal input.
Negative reference clock/crystal input.
Positive supply voltage.
Negative Transmit clock output.
Positive Transmit clock output.
Negative Transmit data input.
Positive Transmit data input.
* Active Low Input.
2
ICS1886
Absolute Maximum Ratings
VDD (measured to VSS) . . . . . . . . . . . . . . . . . .
Ambient Operating Temperature . . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . . .
Junction Temperature . . . . . . . . . . . . . . . . . . .
Soldering Temperature . . . . . . . . . . . . . . . . . .
7.0 V
– 55°C to +125°C
– 65°C to +150°C
175°C
260°C
Stresses above those listed under Absolute Maximum Ratings above may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those listed in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.
Recommended Operating Conditions
PARAMETER
Ambient Operating Temp.
Using a Negitive Supply
Using a Positive Supply
SYMBOL TEST CONDITIONS
TA
VSS
VDD
VSS
VDD
ICS1886 FDDI / Fast Ethernet Application
3
MIN
0
-4.50
0.0
0.0
+4.50
MAX
+70
-5.50
0.0
0.0
+5.50
UNITS
ºC
V
V
V
V
ICS1886
DC Characteristics
VDD = VMIN to VMAX , VSS = 0V, TA = TMIN to TMAX
PARAMETER
Supply Current
ECL Input/Output
PARAMETER
ECL Input High Voltage
ECL Input Low Voltage
ECL Differential
Threshold Voltage Range
ECL Input Common
Mode Voltage
ECL Output High Voltage
ECL Output Low Voltage
TTL Input/Output
PARAMETER
TTL Input High Voltage
TTL Input Low Voltage
TTL Output High Voltage
TTL Output Low Voltage
TTL Driving CMOS
Output High Voltage
TTL Driving CMOS
Output Low Voltage
TTL / CMOS Output
Sink Current
TTL / CMOS Output
Source Current
REF_IN Input
PARAMETER
Input High Voltage
Input Low Voltage
SYMBOL
ISS
CONDITIONS
VDD = +5.0V, VSS = 0.0V
MIN
—
MAX
50
UNITS
mA
SYMBOL
VI H
VI L
CONDITIONS
MIN
VDD -1.16
VDD -1.81
MAX
VDD -0.88
VDD -1.47
UNITS
V
V
VT H
—
150
mV
VC M
1.3
VDD - .4
V
VOH
VOL
VDD -1.02
—
—
VDD -1.62
V
V
0.0V
0.0V
0.0V
0.0V
MIN
2.0
—
2.7
—
MAX
—
0.8
—
0.5
UNITS
V
V
V
V
VOH
VDD = 5.0V, VSS = 0.0V
3.68
—
V
VOL
VDD = 5.0V, VSS = 0.0V
—
0.4
V
IOL
VDD = 5.0V, VSS = 0.0V
—
8
mA
IOH
VDD = 5.0V, VSS = 0.0V
—
-0.4
mA
CONDITIONS
VDD = 5.0V, VSS = 0.0V
VDD = 5.0V, VSS = 0.0V
MIN
3.5
MAX
UNITS
V
V
SYMBOL
VIH
VI L
VOH
VOL
SYMBOL
VIH
VI L
VDD
VDD
VDD
VDD
CONDITIONS
= 5.0V, VSS =
= 5.0V, VSS =
= 5.0V, VSS =
= 5.0V, VSS =
Note: REF_IN Input switch point is 50% of VDD.
4
1.5
ICS1886
AC Characteristics
VDD = VMIN to VMAX , VSS = 0V, TA = TMIN to TMAX
PARAMETER
Rise/Fall Time
Recovered clock
Duty Cycle
Output Data Setup
Output Data Hold
Transmit Latency
Recieve Latency
Lock Acquisition
SYMBOL CONDITIONS
ECL Outputs
tr , t f
15pF Load
MIN
MAX
UNITS
1.4
1.7
ns
15pF Load
45
55
%
3.3
4.5
9
1clock+20
ns
ns
ns
ns
5
tDC
tsv
thd
TL
RL
tacq
Capture Range
Receive Jitter Tolerance
Transmit Clock Stability
tjt
W.R.T. RC at 139.264MHz
2.2
W.R.T. RC at 139.264MHz
3.9
139.264MHz
6
139.264MHz
1clock+15
Phase-Locked Loop Characteristics
139.264MHz
—
139.264MHz
—
±5
139.264MHz
139.264MHz
17.408MHz crystal
—
.15%
µs
% of
center freq.
UIp-p
—
6
ppm
5
ICS1886
Input Pin Descriptions
Transmit Data Input (TD+ and TD-) For normal operation
this differential input is transferred to the TX± output
through a PECL buffer. In loopback testing mode, this input
is multiplexed to the input of the device clock recovery
section.
Receive Clock Differential ECL (RC+ and RC-) The
differential clock recovered with the internal clock recovery PLL. In loopback mode this clock is recovered from the
transmit data (TD±) input. This clock is phase-aligned with
the RD data output.
Lock/Loss Detect (LOCK) Set high when the clock
recovery PLL has locked onto the incoming data. Set low
when there is no incoming data, which in turn causes the
PLL to free-run. This signal can be used to indicate or
‘alarm’ the next receive stage that the incoming serial data
has stopped.
Receive Data Input (RX+ and RX-) The clock recovery
and data regenerator from the receive buffer are driven from
this PECL input. During loopback testing mode this input is
ignored.
Clock Select (CS0 and CS1) Selects the operating
frequency according to Table 1. Internal pull-up resistors
set both inputs high when left unconnected.
Output Description
The differential output drivers are current mode and are designed to drive resistive terminations in a complementary
fash-ion. The outputs are current-sinking only, with the
amount of sink current programmable via the IPRGx pins.
The sink current is equal to four times the IPRGx current.
For most applications, a resistor from VDD to IPRGx will
set the current to the necessary precision. IPRG1 supplies
the current mirror for the TX± output. IPRG2 supplies the
current mirrors for the RD±, RC± and TC± outputs.
Carrier Detect (CD~) Active low input which forces the
VCO to free run. Upon receipt of a loss of input signal
(such as from an optical-to-elec-trical transducer), the
internal phase-lock loop will free-run at the selected
operating frequency. Also, when asserted, CD will set the
lock output low.
Loop Timing Mode (LT~) Active low input which routes
the recovered receive clock to the TC± outputs as well as
the RC± outputs. Forces the transmit clock to be ‘looptimed’ to the system clock derived from the incoming data.
The differential PECL output pins are incapble of sourcing
current, so VOH must be set by the ratios of the termination
resistors for each of these lines. R1 is a pull-up resistor
con-nected from the PECL output to VSS. R1 and R2 are
electrically in parallel from an AC stand point. If we pick a
target imped-ance of 50Ω for our transmission line
impedance, a value of 62Ω for R1 and a value of 300Ω for
R2 would yield a Thevenin equivalent characteristic
impedance of 50Ω and a VOH value of VDD-.88 volts,
compatible with PECL circuits.
Loopback Mode (LB~) Active low input which causes the
clock recovery PLL to operate using the transmit TD± input
data and ignore the receive RX± data. Utilized for system
loopback testing.
External Crystal or Reference Clock (REF+ and REF-)
This oscillator input can be driven from either a
fundamental mode crystal or a stable reference. For either
method, the reference frequency is 1 ⁄8 the operating
frequency. See Table 1 for more information.
To set a value for VOL, we must determine a value for Iprg
that will cause the output FET’s to sink an appropriate
current. We desire VOL to be VDD-1.81 or greater. Setting
up a sink current of 19 milliamperes would guarantee this
through out output terminating resistors. As this is
controlled by a 4/1 current mirror, 4.75mA into Iprg should
set this current properly. An 910Ω resistor from VDD to
Iprg should work fine.
Output Pin Descriptions Transmit Data Differential
ECL (TX+ and TX-) This differential output is buffered TD±
data. This output remains active during loopback mode.
Transmit Clock Differential ECL (TC+ and TC-)
Differential output clock used by the PDH/ATM processor
for clocking out transmit data. This clock can be derived
from either an independent clock source or from the
recovered data clock (system loop time mode).
Receive Data Differential ECL (RD+ and RD-) The
regenerated differential data derived from the serial data
input. In loopback mode this data is regenerated from the
transmit data input (TD±). This data is phase-aligned with
the negative edge of the RC clock output.
6
ICS1886
ICS1886 PECL Termination for 50W Transmission Lines
7
ICS1886
The current ICS1886 device provides a single
TTL-compatible input, carrier detect (CD~).
When carrier detect is asserted, the ICS1886
locks to the incoming receive data. When
carrier detect is deasserted, or if carrier detect
is asserted and no data is present on the receive
inputs, the PLL will free run and continue to
provide RXCLK at the nominal 25 MHz
frequency. This provides a continuous Receive
clock source, even if CD~ is always tied to
ground.
CD PECL Input: Board Layout Options
Option 1
Differential PECL to CMOS Conversion Circuit
If a true signal detect is required by a chip that
connects to the ICS1886, a simple, low cost
PECL to CMOS converter can be used. The
following circuits implement this function:
These circuits provide PECL to CMOS
conversion for less than $0.80 in single unit
quantities. Note that the LM393 has two
amplifiers, so the unused one is tied inactive.
A running production change will be made to
the ICS1886 to change the CD~ input to PECL.
Therefore, boards should be layed out with a
direct normal PECL termination connection
stuffing option. This allows either version of
the part to be used by stuffing one of two sets
of external components. A version of this
circuit is shown in the diagram above.
Option 2
Single-Ended PECL to CMOS Conversion Circuit
8
ICS1886
9
ICS1886
SOIC PACKAGE
LEAD COUNT
DIMENSION L
28L
0.704
Ordering Information
ICS1886M
Example:
ICS XXXX M
Package Type
M = SOIC
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
10