HI-303/883 ® Data Sheet November 2003 FN6058 Dual SPDT CMOS Analog Switch Features The HI-303/883 switch is a monolithic device fabricated using CMOS technology and the Intersil Dielectric Isolation process. This switch features break-before-make switching, low and nearly constant ON resistance over the full analog signal range, and low power dissipation. • This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. • Analog Signal Range (±15V Supplies). . . . . . . . . . . .±15V • Low Leakage (+25°C) . . . . . . . . . . . . . . . . . . . .1nA (Max) The HI-303/883 is TTL compatible and has a logic “0” condition with an input less than 0.8V and a logic “1” condition with an input greater than 4.0V. • Low Leakage (+125°C) . . . . . . . . . . . . . . . . .100nA (Max) • Low ON Resistance . . . . . . . . . . . . . . . . . . . . . 50Ω (Max) The HI-303/883 is pin-for-pin compatible with the industry standard Siliconix DG303. The device is available in a 14 pin Ceramic DIP. The HI-303/883 operates over the -55°C to +125°C temperature range. • Charge Injection . . . . . . . . . . . . . . . . . . . . . . . . 30pC (Typ) • TTL Compatible • System Switch Elements • Low Operating Power Pinout • Compatible with DG303 HI1-303/883 (CERAMIC DIP) TOP VIEW NC 1 14 V+ S3 2 13 S4 D3 3 12 D4 D1 4 11 D2 S1 5 10 S2 A1 6 9 A2 GND 7 8 V- Applications • Sample and Hold, i.e. Low Leakage Switching • Op Amp Gain Switching, i.e. Low ON Resistance • Portable, Battery Operated Circuits • Low Level Switching Circuits • Dual or Single Supply Systems LOGIC SW1 SW2 SW3 SW4 0 Off On 1 On Off 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HI-303/883 Absolute Maximum Ratings Thermal Information Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . . . . . . . .44V ±VSUPPLY to Ground (V+, V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±22V Analog Input Voltage, (+VS ). . . . . . . . . . . . . . . . . . +VSUPPLY +1.5V Analog Input Voltage, (-VS ) . . . . . . . . . . . . . . . . . . . -VSUPPLY -1.5V Digital Input Voltage, (+VA) . . . . . . . . . . . . . . . . . . . .+VSUPPLY +4V Digital Input Voltage, (-VA) . . . . . . . . . . . . . . . . . . . . . .-VSUPPLY -4V Peak Current (S or D) (Pulse at 1ms, 10% Duty Cycle Max). . . . . . . . . . . . . . . . . . 40mA Continuous Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . . . . . . . ≤275°C Thermal Resistance θJA (oC/W) θJC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 88 24 Package Power Dissipation at 75oC Ceramic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . 0.85W/oC Package Power Dissipation Derating Factor above +75oC Ceramic DIP Package . . . . . . . . . . . . . . . . . . . . . . . 11.36mW/oC Recommended Operating Conditions Operating Temperature Range . . . . . . . . . . . . . . . -55oC to +125oC Operating Supply Voltage Range (±VSUPPLY) . . . . . . . . . . . . . . ±15V Analog Input Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . ±VSUPPLY Logic Low Level (VAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 0.8V Logic High Level (VAH) . . . . . . . . . . . . . . . . . . . . 4.0V to +VSUPPLY CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TABLE 1. D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS Device Tested at: +VSUPPLY = +15V, −VSUPPLY = −15V, GND = 0V, Unless Otherwise Specified. D.C. PARAMETERS Switch “ON” Resistance Source “OFF” Leakage Current Drain “OFF” Leakage Current Channel “ON” Leakage Current SYMBOL rDS IS(OFF) ID(OFF) ID(ON) Low Level Input Current IAL High Level Input Current IAH Supply Current +ICC CONDITIONS -ICC MIN MAX UNITS 1 25 - 50 Ω 2, 3 -55 to 125 - 75 Ω VA1 = 0.8V, VD = -10V, IS = 10mA, VA2 = 4.0V, S1 /S2/S3/S4 1 25 - 50 Ω 2, 3 -55 to 125 - 75 Ω VS = +14V, VD = -14V, VA1 = 0.8V, VA2 = 4.0V, S1 /S2/S3/S4 1 25 -1 1 nA 2, 3 -55 to 125 -100 100 nA VS = -14V, VD = +14V, VA1 = 4.0V, VA2 = 0.8V, S1 /S2/S3/S4 1 25 -1 1 nA 2, 3 -55 to 125 -100 100 nA VS = +14V, VD = -14V, VA1 = 0.8V, VA2 = 4.0V, S1 /S2/S3/S4 1 25 -1 1 nA 2, 3 -55 to 125 -100 100 nA VS = -14V, VD = +14V, VA1 = 4.0V, VA2 = 0.8V, S1 /S2/S3/S4 1 25 -1 1 nA 2, 3 -55 to 125 -100 100 nA VD = VS = +14V, VA1 = 4.0V, VA2 = 0.8V, S1 /S2/S3/S4 1 25 -1 1 nA 2, 3 -55 to 125 -100 100 nA VD = VS = -14V, VA1 = 0.8V, VA2 = 4.0V, S1 /S2/S3/S4 1 25 -1 1 nA 2, 3 -55 to 125 -100 100 nA 1 25 -1.0 1.0 µA 2, 3 -55 to 125 -1.0 1.0 µA All Channels VAL = 0.8V All Channels VAH = 4.0V All Channels VA = 0.8V All Channels VA = 0.8V VA1 = 0V, VA2 = 4.0V and VA1 = 4.0V, VA2 = 0V 2 TEMPERATURE (oC) VA1 = 4.0V, VD = 10V, IS = -10mA, VA2 = 0.8V, S1 /S2/S3/S4 VA1 = 0V, VA2 = 4.0V and VA1 = 4.0V, VA2 = 0V Supply Current GROUP A SUBGROUPS 1 25 -1.0 1.0 µA 2, 3 -55 to 125 -1.0 1.0 µA 1 25 - 10 µA 2, 3 -55 to 125 - 100 µA 1 25 - 0.5 mA 2, 3 -55 to 125 - 1.0 mA 1 25 -10 - µA 2, 3 -55 to 125 -100 - µA 1 25 -10 - µA 2, 3 -55 to 125 -100 - µA HI-303/883 TABLE 2. A.C. ELECTRICAL PERFORMANCE SPECIFICATIONS Device Tested at: +VSUPPLY = +15V, −VSUPPLY = −15V, GND = 0V, Unless Otherwise Specified. PARAMETERS tON Turn “OFF” Time tOFF TEMPERATURE (oC) MIN MAX UNITS CL = 33pF, RL = 300Ω 9 25 - 300 ns 10, 11 55 to 125 - 500 ns CL = 33pF, RL = 300Ω 9 25 - 250 ns 10, 11 55 to 125 - 450 ns SYMBOL Turn “ON” Time GROUP A SUBGROUPS CONDITIONS TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS (NOTE 1) Device Tested at: +VSUPPLY = +15V, −VSUPPLY = −15V, GND = 0V, Unused Pins are Grounded. PARAMETERS NOTE TEMPERATURE (oC) MIN MAX UNITS Measured Source to GND 1 25 - 28 pF SYMBOL Switches Input Capacitance CIS (OFF) CONDITIONS Driver Input Capacitance CC1 VA = 0V 1 25 - 10 pF CC2 VA = 15V 1 25 - 10 pF Switch Output Capacitance COS Measured Drain to GND 1 25 - 28 pF Off Isolation VISO f = 1MHz, VGEN = 1VP-P 1 25 40 - dB Cross Talk VCT f = 1MHz, VGEN = 1VP-P 1 25 40 - dB VCTE VS = GND, CL + 0.01µF 1 25 - 15 mV Charge Transfer NOTE: 1. Parameters listed in Table 2 are controlled via design or process parameters and are not directly tested at final production. These parameters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon data from multiple production runs which reflect lot to lot and within lot variation. TABLE 4. ELECTRICAL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS Interim Electrical Parameters (Pre Burn-in) Final Electrical Test Parameters SUBGROUPS (Tables 1 and 2) 1 1 (Note 2), 2, 3, 9, 10, 11 Group A Test Requirements 1, 2, 3, 9, 10, 11 Groups C & D Endpoints 1 NOTE: 2. PDA applies to Subgroup 1 only. 3 HI-303/883 Test Circuits +VCC +VCC S VS D D S VD ID VIN IIN VIN -VCC GND GND -VCC FIGURE 2. ID (OFF) FIGURE 1. INPUT LEAKAGE CURRENT +VCC +VCC S VS S VD IS D ID(ON) VIN VIN V GND -VCC GND -VCC FIGURE 4. ID (ON) FIGURE 3. IS (OFF) D S +VCC 0.01MF DRIVER f = 1kHz SQUARE WAVE TR ≤ 20ms I1 TO MEASUREMENT CIRCUITRY WITH INPUT RESISTANCE OF 1mΩ OR GREATER IF PULSE TEST IS USED: TR, TF ≤ 20ms D S VIN (DRIVER) VIN GND I2 VCTE -VCC DROOP CAUSED BY DEVICE LEAKAGE AND MEASUREMENT CIRCUITRY SWITCHING TRANSIENT NOTE: VCTE may be a positive or negative value. FIGURE 5. SUPPLY CURRENTS 4 FIGURE 6. CHARGE TRANSFER ERROR HI-303/883 Test Circuits (Continued) +VCC S VIN D S D VGEN = 1VP-P 1kΩ f = 1MHz VD -VCC GND FIGURE 8. OFF CHANNEL ISOLATION FIGURE 7. RDS VGEN S D S D VGEN = 1VP-P 1kΩ 1kΩ 1kΩ f = 1MHz FIGURE 9. CROSSTALK BETWEEN CHANNELS Test Waveforms 15V +15V V+ S1 V+ S D VS = +3V RL VO VS1 = +3V SWITCH OUTPUT VS2 = +3V D1 OUT 2 CL RL2 LOGIC INPUT LOGIC INPUT GND GND V-15V FIGURE 10. 5 OUT 1 D2 S2 V-15V FIGURE 11. CL2 RL1 CL1 HI-303/883 Test Waveforms (Continued) LOGIC “1” = SWITCH ON LOGIC INPUT 0V LOGIC “1” = SWITCH ON LOGIC INPUT VINH 50% 50% 0V 50% 50% VS 90% 0V SWITCH OUTPUT VINH OUT 1 0V SWITCH OUTPUTS 10% OUT 2 50% 50% 0V tOFF tON tOPEN FIGURE 12. MEASUREMENT POINTS tOPEN FIGURE 13. TTL LOGIC INPUT NOTES: 3. RL = RL1 = RL2 = 300Ω; CL = CL1 = CL2 = 33pF 4. VINH = 4V RISETIME (0.4V to 3.6V) ≤ 20ns FALLTIME (3.6V to 0.4V) ≤ 20ns Burn-In Circuit +V 1 NC +V 14 2 S3 S4 13 3 D3 D4 12 4 D1 D2 11 5 S1 S2 10 6 A1 A2 9 7 GND -V 8 R1 R4 R2 R3 -V C2 HI-303/883 CERAMIC DIP NOTES: 5. R1 = R2 = R3 = R4 = 10kΩ, 5%, 1/4 or 1/2W 6. C1 = C2 = 0.01µF (per socket) or 0.1µF (per row) 7. D1 = D2 = IN4002 (per board) 8. |(V+) - (V-)| = 30V 6 D1 C1 D2 HI-303/883 Schematic Diagram V+ D2A MP1A MP2A MP3A MP4A MP5A MP6A MP7A MP8A 200Ω A LOGIC IN D1A A MN1A MN2A MN3A MN4A MN5A MN6A MN7A MN8A GND VSWITCH CELL DRIVER (ONE PER SWITCH CELL) FIGURE 14. DIGITAL INPUT BUFFER AND LEVEL SHIFTER A V+ MN1B MN2B MN3B MP5B IN MP4B OUT MN4B MN6B MP3B MP2B MP1B V- A FIGURE 15. SWITCH CELL 7 HI-303/883 Typical Performance Curves TA = 25oC, V+ = +15V, V- = -15V, Unless Otherwise Specified. 80 DRAIN TO SOURCE ON RESISTANCE (Ω) DRAIN TO SOURCE ON RESISTANCE (Ω) 80 V+ = +15V, V- = -15V 60 125oC 25oC -55oC 40 20 0 -15 -10 -5 0 5 10 TA = 25oC 60 C B 40 A 20 A B C D 0 -15 15 D V+ = +15V, V- = -15V V+ = +10V, V- = -10V V+ = +7.5V, V- = -7.5V V+ = +5V, V- = -5V -10 -5 0 10 15 FIGURE 17. rDS(ON) vs VD AND POWER SUPPLY VOLTAGE FIGURE 16. rDS(ON) vs VD AND TEMPERATURE 100 100 V+ = +15V, V- = -15V CLOAD = 3pF, VS = 1VRMS V+ = +15V, V- = -15V TA = 25oC, VS = 15V, RL = 2K 80 OFF ISOLATION (dB) POWER DISSIPATION (mW) 5 DRAIN VOLTAGE (V) DRAIN VOLTAGE (V) 10 HI-300 THRU HI-303 1.0 RL = 100Ω 60 RL = 1kΩ 40 20 HI-304 THRU HI-307 0 105 0.1 1 10 100 1K 10K 100K 1M 107 108 FREQUENCY (Hz) LOGIC SWITCHING FREQUENCY (50% DUTY CYCLE) (Hz) FIGURE 19. OFF ISOLATION vs FREQUENCY FIGURE 18. DEVICE POWER DISSIPATION vs SWITCHING FREQUENCY (SINGLE LOGIC INPUT) 10.0 10.0 V+ = +15V, V- = -15V | VD | = | VS | = 14V ID(ON) - CHANNEL LEAKAGE (nA) V+ = +15V, V- = -15V SOURCE OR DRAIN OFF LEAKAGE CURRENT (nA) 106 1.0 0.1 0.01 25 75 125 TEMPERATURE (oC) FIGURE 20. IS(OFF) OR ID(OFF) vs TEMPERATURE (Note) 1.0 0.1 0.01 25 75 125 TEMPERATURE (oC) FIGURE 21. ID(ON) vs TEMPERATURE (Note) NOTE: The net leakage into the source or drain is the N-Channel leakage minus the P-Channel leakage. This difference can be positive, negative or zero depending on the analog voltage and temperature, and will vary greatly from unit to unit. 8 HI-303/883 Typical Performance Curves TA = 25oC, V+ = +15V, V- = -15V, Unless Otherwise Specified. (Continued) 16 INPUT CAPACITANCE (pF) OUTPUT ON CAPACITANCE (pF) 60 50 40 30 12 8 TRANSITION (INDETERMINATE DUE TO ACTIVE INPUT) HI-300 THRU HI-303 4 HI-304 THRU HI-307 TRANSITION 20 0 2 4 6 8 10 12 14 0 16 2 4 6 8 10 12 14 16 INPUT VOLTAGE (V) DRAIN VOLTAGE (V) FIGURE 22. OUTPUT ON CAPACITANCE vs DRAIN VOLTAGE FIGURE 23. DIGITAL INPUT CAPACITANCE vs INPUT VOLTAGE 300 SWITCHING TIME (µs) SWITCHING TIME (ns) V+ = +15V, V- = -15V VINH = 4.0V, VINL = 0V tON 200 tOFF 100 300 tON 200 tOFF 100 -55 -35 -15 5 25 45 65 85 105 125 0 TEMPERATURE (oC) 5 10 15 NEGATIVE SUPPLY (V) FIGURE 24. SWITCHING TIME vs TEMPERATURE FIGURE 25. SWITCHING TIME vs NEGATIVE SUPPLY VOLTAGE 7 1.8 V- = -15V, TA = 25oC VINH = 4.0V, VINL = 0V 1.6 V- = -15V, TA = 25oC INPUT SWITCHING THRESHOLD (V) SWITCHING TIME/BREAK-BEFORE-MAKE TIME (µs) V+ = +15V, TA = 25oC VINH = 4V, VINL = 0V 1.4 1.2 1.0 0.8 0.6 tON 0.4 tOFF tBBM HI-301/303 ONLY 0.2 0 0 6 HI-304 THRU HI-307 5 4 3 2 HI-300 THRU 303 1 0 5 10 15 POSITIVE SUPPLY VOLTAGE (V) FIGURE 26. SWITCHING TIME AND BREAK-BEFORE-MAKE TIME vs POSITIVE SUPPLY VOLTAGE 9 0 5 10 15 POSITIVE SUPPLY VOLTAGE (V) FIGURE 27. INPUT SWITCHING THRESHOLD vs POSITIVE SUPPLY VOLTAGE HI-303/883 Die Characteristics DIE DIMENSIONS: DIE ATTACH: 76 mils x 83.9 mils x 19 mils Material: Gold/Silicon Eutectic Alloy Temperature: Ceramic DIP - 460°C (Max) METALLIZATION: WORST CASE CURRENT DENSITY: Type: Aluminum Thickness: 16kÅ ±2kÅ 3.9 x 105A/cm2 at 30mA This device meets Glassivation Integrity Test requirement per MIL-STD-883 Method 2021 and MIL-M-38510 paragraph 3.5.5.4 GLASSIVATION: Type: Nitride Thickness: 7kÅ ±0.7kÅ Metallization Mask Layout HI-303/883 D4 12 S4 13 V+ 14 S3 2 D2 11 S2 10 IN2 9 8 V- 7 GND 10 3 4 5 6 D3 D1 S1 IN1 HI-303/883 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A) 14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE LEAD FINISH c1 -D- -A- BASE METAL E M -Bbbb S C A-B S -C- S1 0.200 - 5.08 - 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.785 - 19.94 5 E 0.220 0.310 5.59 7.87 5 eA e ccc M C A-B S eA/2 c aaa M C A - B S D S D S NOTES - b2 b MAX 0.014 α A A MIN b A L MILLIMETERS MAX A Q SEATING PLANE MIN M (b) D BASE PLANE SYMBOL b1 SECTION A-A D S INCHES (c) NOTES: 9. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 105o 90o 105o - 10. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. α 90o aaa - 0.015 - 0.38 - 11. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 12. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. N 14 14 13. This dimension allows for off-center lid, meniscus, and glass overrun. 8 Rev. 0 4/94 14. Dimension Q shall be measured from the seating plane to the base plane. 15. Measure dimension S1 at all four corners. 16. N is the maximum number of terminal positions. 17. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 18. Controlling dimension: INCH. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11