MOSEL VITELIC INC.
MV20556
Preliminary
July 1997
8 - Bit MCU Mouse Controller
Features
General 8051 instruction family compatible
Operate at voltage 5.0V.
No External Memory is supported
8 bit bus I/O ports
4 K byte ROM
128 byte RAM
128 byte depth stack
Two 16 bit Timers (Event Counters)
15 programmable I/O pins
Five interrupt sources
Programmable serial UART channel
Direct LED drive output
Bit operation instructions
Page free jumps
8 - bit Unsigned Division
8 - bit Unsigned Multiply
BCD arithmatic
Direct Addressing
Indirect Addressing
Nested Interrupt
Two priority level interrupt
A full duplex serial I/O port
Working at 16/25/40 MHz Clock
Full static operation: 3 MHz through 16 MHz
Description
Pin Configuration
The MVI MV20556 is an 8 - bit single chip
microcontroller. It provides hardware features and
powerful instruction set that are necessary to make it a
versatile and cost effective controller for mouse
applications which needs up to 4K byte internal
memory either for program or for data and mixed.
A serial input / output port is provided for I/O
expansion, Inter - processor communications, full
duplex UART.
Ordering Information
RES
1
RXD/P 3.0
2
TXD/P 3.1
3
XTA2
4
20L PDIP
300 mil
(Top View)
VDD
19
P 1.7
18
P 1.6
17
P 1.5
16
P 1.4
15
P 1.3
14
P 1.2
13
P 1.1
XTAL1
5
#INT0/P 3.2
6
#INT1/P 3.3
7
T0/P 3.4
8
T1/P 3.5
9
12
P 1.0
10
11
P 3.7
VSS
MV20556ajk - pqrs
MV20556
20
20L SOP
(Top View)
a: process identifier. { C:=COMS }
jk: working clock in MHz. { 16 }
pqr: production code { 001, ..., 999 }
s: package type. { P: 20L 300 mil PDIP }
Pin/Pad
Postfix
Package
blank
Logo Size at
Configuration
Dimension
dice
page 25
page 25
-
N
20L PDIP
page 1
page 23
4.5 x 3.8 mm
S
20L SOP
page 1
page 24
4.0 x 3.4 mm
Top Marking
Specifications subject to change without notice, contact your sales representatives for the most recent information.
1/27
PID256** 07/97
MOSEL VITELIC INC.
MV20556
Preliminary
Block Diagram
Timer 1
RES
Reset
Circuit
Timer 0
Stack
Decoder &
128 bytes
4K bytes
Pointer
Register
RAM
ROM
128
bits
SFR
includes
Acc &
PSW,
etc.
to pertinent blocks
to whole chip
Vdd
Vss
Power
Circuit
Buffer1
Buffer2
Interrupt
Circuit
Timming
Generator
Buffer
DPTR
to pertinent blocks
ALU
XTAL2
XTAL1
Register
Program
Counter
to whole system
Port 3
Latch
Port 1
Latch
Port 3
Driver
Port 1
Driver
7
PC
Increamenter
8
Specifications subject to change without notice, contact your sales representatives for the most recent information.
2/27
PID256** 07/97
MOSEL VITELIC INC.
Preliminary
MV20556
Pin Descriptions
dice
Symbol
Pin#
1
Pad#
4
RES
2
5
20L
20L
PDIP
SOP
Pin#
1
2
3
3
Active
I/O
Names
i
Reset
6
RXD/P3.0
TXD/P3.1
i
Crystal out
o
Crystal in
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
bit 2 of Port 3 & low true Interrupt 0
bit 3 of Port 3 & low true Interrupt 1
bit 4 of Port 3 & external input to Timer 0
bit 5 of Port 3 & external input to Timer 1
Sink Voltage, Ground
bit 7 of Port 3
bit 0 of Port 1
bit 1 of Port 1
bit 2 of Port 1
bit 3 of Port 1
bit 4 of Port 1
bit 5 of Port 1
bit 6 of Port 1
bit 7 of Port 1
Drive Voltage, +5 Vcc
4
4
7
XTAL2
5
5
8
XTAL1
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
9
10
11
12
13-15
17
18
19
20
21
22
23
24
1
2, 3
#INT0/P3.2
#INT1/P3.3
T0/P3.4
T1/P3.5
VSS
P3.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
VDD
L/L/-
i/o
bit 0 of Port 3 & Receive data
i/o
bit 1 of Port 3 & Transmit data
Signal Descriptions
Vss
Circuit ground potential.
VDD
+5V power supply during operation.
PORT 1
Port 1 is an 8-bit quasi-bidirectional I/O port.
There is a pull-up resistance when operating at either
input or output.
PORT 3
Port 3 is an 7-bit quasi-bidirectinal I/O port. It also
contains the interrupt and timer as well as serial port
pins that are used by various options. The output latch
corresponding to a secondary function must be
programmed to one (1) for that function to operate.
The secondary functions are assigned to the pins of port
3, as follows:
- RXD/data (P3.0). Serial port's transmitter data input
(asynchronous) or data input/output (asynchronous).
- TXD/clock (P3.1). Serial port's transmitter data output
(asynchronous) or data input/output (asynchronous).
- #INT0 (P3.2). Interrupt 0 input or gate control input
for counter 0.
- #INT1 (P3.3). Interrupt 1 input or gate control input
for counter 1.
- T0 (P3.4). Input to counter 0.
- T1 (P3.5). Input to counter 1.
There is a pull-up resistance when operating at either
input or output.
RES
A low to high transition on this pin (V IH1) while the
oscillator is not running resets the MV20556. Holding
high signal (higher than V IH1) on this pin for two
machine cycles (24 clocks) or longer while the oscillator
is running, resets the device.
XTAL 1
Input to the oscillator's high gain amplifier. A crystal or
external source can be used.
XTAL 2
Output from the oscillator's amplifier. Required when a
crystal is used.
Specifications subject to change without notice, contact your sales representatives for the most recent information.
3/27
PID256** 07/97
MOSEL VITELIC INC.
Preliminary
MV20556
Function Overall
The CPU of MV20556 manipulates versatile operands in
four memory spaces. They are 4 KB program ROM,
128-byte internal Data RAM, 20 SFRs and 16-bit program
counter.
The Internal Data Memory address space is further
divided into the 128-byte Internal Data RAM and 128-byte
Special Function Register (SFR) address spaces shown in
latter Figures. Four Register Banks (each with eight
registers), 128 addressable bits, and the stack reside in
the Internal Data RAM. The stack depth is limited only by
the available Internal Data RAM and its location is
determined by the 8-bit Stack Pointer. All registers except
the Program Counter and the four 8-Register Banks reside
in the Special Function Register address space.
wide. The MV20556 performs operation on bit, nibble,
byte and double-byte data types.
The MV20556 has extensive facilities for byte transfer,
logic, and integer arithmetic operations. It excells at bit
handling since data transfer, logic and conditional branch
operantions can be performed directly on Boolean
variables.
These memory mapped registers include arithmetic
registers, pointers, I/O ports, and registers for the interrupt
system, timers and serial channel. 128 bit locations in the
SFR address space are addressable as bits. The
MV20556 contains 128 bytes of Internal Data RAM and 20
SFRs.
The MV20556 provides a non-paged Program Memory
address space to accommodate relocatable code.
Conditional branches are performed relative to the
Program Counter. The register-indirect jump permits
branching relative to a 16-bit base register with an offset
provided by an 8-bit index register. Sixteen-bit jumps and
calls permit branching to any location in the contiguous 4K
Program Memory address space.
The MV20556 has five methods for addressing source
operands: Register, Direct, Register-Indirect, Immediate,
and Base-Register-plus Index-Registe -Indirect
Addressing. The first three methods can be used for
addressing destination operands. Most instructions have
a "destination, source" field that specifies the data type,
addressing methods and operands involved.
For
operations other than moves, the destination operand is
also a source operand.
Any register in the four 8-Register Banks can be accessed
through Register, Direct, or Register-Indirect Addressing;
the 128 bytes of Internal Data RAM through Direct or
Register-Indirect Addressing; and the Special Function
Registers through Direct Addressing. External Data
Memory is accessed through Register-Indirect
Addressing. Look-Up-Tables resident in Program Memory
can be accessed through Base-Register-plus
Index-Register-Indirect Addressing.
The MV20556 is classified as an 8-bit machine since the
internal ROM, RAM, Special Function Registers,
Arithmetic/Logic Unit and external data bus are each 8 bits
Specifications subject to change without notice, contact your sales representatives for the most recent information.
4/27
PID256** 07/97
MOSEL VITELIC INC.
MV20556
Preliminary
Memory Map Overall
The CPU of MV20556 is able to access three memory areas. They are:
(1) 128 bytes data RAM addressed at 00H through 7FH;
(2) 20 SFRs addressed at 80H through FFH;
(3) 4,096 bytes program ROM addressed at 000H through FFFH.
Be noted, MCU MV20556 builds all accessible memory inside, it is unable to access external memory.
4095
255
FFH
255
FFH
128
127
80H
7FH
128
F0H
0
0
00H
Internal
Data
RAM
FFFH
Special
Function
Register
000H
Internal Program ROM
Internal Memory Map
Specifications subject to change without notice, contact your sales representatives for the most recent information.
5/27
PID256** 07/97
MOSEL VITELIC INC.
MV20556
Preliminary
Memory Map Details
Internal RAM
The MV20556 contains a 128-byte Internal Data RAM
(Which includes registers R7-R0 in each of four Banks),
and twenty memory-mapped Special Function
Registers.
Internal Data RAM
The Internal Data RAM provides a convenient 128-byte
scratch pad memory.
128 Addressable Bits
There are 128 addressable software flags in the
Internal Data RAM. They are located in the 16 byte
locations starting at byte address 32 and ending with
byte location 47 of the RAM address space.
Stack
The stack may be located anywhere within the Internal
Data RAM address space. The stack may be as large
as 128 bytes on the MV20556.
7Fh
Register Banks
There are four Register Banks within the Internal Data
RAM. Each Register Bank contains registers R7-R0.
RAM
BYTE (MSB)
(LSB)
7FH
127
scratch
pad
area
2FH
7F
7E
7D
7C
7B
7A
79
78
47
2EH
77
76
75
74
73
72
71
70
46
2DH
6F
6E
6D
6C
6B
6A
69
68
45
2CH
67
66
65
64
63
62
61
60
44
2BH
5F
5E
5D
5C
5B
5A
59
58
43
2AH
57
56
55
54
53
52
51
50
42
29H
4F
4E
4D
4C
4B
4A
49
48
41
28H
47
46
45
44
43
42
41
40
40
27H
3F
3E
3D
3C
3B
3A
39
38
39
26H
37
36
35
34
33
32
31
30
38
25H
2F
2E
2D
2C
2B
2A
29
28
37
24H
27
26
25
24
23
22
21
20
36
23H
1F
1E
1D
1C
1B
1A
19
18
35
22H
17
16
15
14
13
12
11
10
34
21H
0F
0E
0D
0C
0B
0A
09
08
33
20H
07
06
05
04
03
02
01
00
32
31
1FH
18H
17H
10H
0FH
08H
07H
Bank 3
Bank 2
Bank 1
30h
2Fh
bit
addressable
area
RS1 RS0
20h
1Fh
R0
R7
18h
17h
R0
R7
10h
0Fh
R0
R7
08h
07h
R0
00h
11
23
24
10
16
15
Four
bank
area
01
8
7
Bank 0
0
00H
R7
00
128B RAM Bit Address
128B RAM Memory Map
Specifications subject to change without notice, contact your sales representatives for the most recent information.
6/27
PID256** 07/97
MOSEL VITELIC INC.
MV20556
Preliminary
Memory Map Details (Cont'd)
Special Function Registers (SFR)
The Special Function Registers include arithmetic
registers (Acc, B, PSW), pointers (SP, DPH, DPL) and
registers that provide an interface between the CPU
and the on-chip peripheral functions. These are also
128 addressable bits within the Special Function
Registers. The memory-mapped locations of these
registers and bits are shown in right side figure.
Acc Register
The Acc register is the accumulator.
Program Status Word Register
The carry (CY), auxiliary carry (AC), user flag 0 (F0),
register bank select (RS0 and RS1), overflow (OV) and
parity (P) flags reside in the Program Status Word
(PSW) Register. These flags are bit-memory-mapped
within the byte-memory-mapped PSW. The PSW flags
record processor status information and control the
operation of the processor.
The CY, AC, and OV flags generally reflect the status
of the latest arithmetic operations. The P flag always
reflects the parity of the Acc register. The carry flag is
also the Boolean accumulator for bit operations.
B Register
The B register is dedicated during multiply and divide
and serves as both a source and a destination. During
all other operations the B register is simply another
location of the Special Function Register space.
SYMBOLIC
ADDRESS
BIT ADDRESS
255
248
247
240
231
224
215
208
191
184
183
176
175
168
167
160
BYTE
ADDRESS
B
240 (F0H)
Acc
224 (E0H)
PSW
Direct
Byte
Address (MSB)
240
224
208
184
176
F7
Bit Addresses
F6
F5
160
F3
F2
E7
E6
E5
E4
E3
E2
CY
AC
FO
RS1
RS0
OV
D7
D6
D5
D4
D3
D2
-
B7
-
B6
-
B5
EA
168
F4
Hardware
Register
(LSB) Symbol
AF
-
-
F1
E1
F0
E0
B
IPC
D0
PS
PT1
PX1
PT0
PX0
BC
BB
BA
B9
B8
B4
B3
B2
B1
B0
ES
ET1
EX1
ET0
EX0
AC
AB
AA
A9
A8
184 (B8H)
P3
Acc
176 (B0H)
IEC
P
D1
208 (D0H)
PSW
168 (A8H)
P2
160 (A0H)
SBUF
IP
153 (99H)
SCON
P3
152 (98H)
159
152
151
144
P1
IE
P2
A7
A6
A5
A4
A3
A2
A1
A0
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
152
9F
9E
9D
9C
9B
9A
99
98
SCON
144
97
96
95
94
93
92
91
90
P1
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
8F
8E
8D
8C
8B
8A
89
88
144 (90H)
TH1
141 (8DH)
TH0
140 (8CH)
TL1
139 (8BH)
TL0
138 (8AH)
TMOD
137 (89H)
TCON
136
128
87
86
85
84
83
82
81
80
136 (88H)
143
TCON
P0
136
DPH
131 (83H)
DPL
130 (82H)
SP
129 (81H)
P0
128 (80H)
135
SFR Bit Address
SFR's
Containing
Direct
Addressable
Bits
128
SFR Memory Map
Specifications subject to change without notice, contact your sales representatives for the most recent information.
7/27
PID256** 07/97
MOSEL VITELIC INC.
MV20556
Preliminary
Memory Map Details (Cont'd)
Program Status Word Register(Cont'd)
F0 is a general purpose flag which is pushed onto the
stack as part of a PSW save. The two Register Bank
select bits (RS1 or RS0) determine which one of the
four Register Banks is selected.
Interrupt Enable Register
The Interrupt Enable (IEC) register stores the enable
bits for each of the five interrupt sources. Also included
is a global enable/disable bit of the interrupt system.
Timer/Counter Mode Register
Within the Times Mode (TMOD) register are the bits
that select which operations each timer/counter will do.
Stack Pointer
The 8-bit Stack Pointer (SP) contains the address at
which the last byte was pushed onto the stack. This is
also the address of the next byte that will be popped.
The SP is incremented during a push. SP can be read
or written to under software control.
Timer/Counter Control Register
The timer/counters are controlled by the Timer/Counter
Control (TCON) register bits. The start/stop bits for the
timer/counters along with the overflow and interrupt
request flags are mapped in TCON.
Data Pointer (High) and Data Pointer (Low)
The 16-bit Data Pointer (DPTR) register is the
concatenation of registers DPH (data pointer's
high-order byte) and DPL (data pointer's low-order
byte).
The DPTR is used in Register-Indirect
Addressing to move Program Memory constants, to
move External Data Memory variables, and to branch
over the 64K Program Memory address space.
Timer/Counter 1 (High), Timer/Counter 1 (Low),
Timer/Counter 0 (High), Timer/Counter 0 (Low)
There are four register locations for the two 16-bit
timer/counters. These registers can be read or written
to, to give the programmer easy access to the
timer/counters. TH1 and TH0 refer to the 8 high-order
bits of timer/counter 1 and 0, respectively. TL1 and
TL0 refer to the low-order bits of both timer/counter 1
and 0.
Interrupt Priority Register
The Interrupt Priority (IPC) register contains the control
bits to set an interrupt to a desired level. A bit set to a
one gives the particular interrupt a high priority listing.
Serial Control Register
The Serial Data Buffer (SBUF) register is used to hold
serial port input or output data depending on whether
the serial port is receiving or transmitting data.
PSW definition
MSB
CY
CY
AC
F0
RS1
RS0
OV
P
RS1
0
0
1
1
LSB
AC
PSW.7
PSW.6
PSW.5
PSW.4
PSW.3
PSW.2
PSW.1
PSW.0
RS0
0
1
0
1
F0
RS1
RS0
OV
-
P
Carry flag
Auxiliary carry flag
Flag 0 available to the user for general purpose
Register bank selector bit 1.
Register bank selector bit 0.
Overflow flag
Usable as a general purpose flag
Parity flag. Set/clear by hardware at each instruction cycle to indicate an odd/
even number of "1" bus in the accumulator
REGISTER BANK
0
1
2
3
ADDRESS
00H-07H
08H-0FH
10H-17H
18H-1FH
Specifications subject to change without notice, contact your sales representatives for the most recent information.
8/27
PID256** 07/97
MOSEL VITELIC INC.
Interrupt System
A sophisticated multiple-source, two-priority-level,
nested interrupt system is provided. The interrupt
system is shown as below diagram. The interrupt
request flag and program memory location of interrupt
service program is shown in table on next page.
Five interrupt sources
Each interrupt can be individually enabled/disabled
Enabled interrupts can be globally enabled/disabled
Each interrupt can be assigned to either of two
priority levels
Each interrupt vectors to a separate location in
program memory
Interrupt nesting to two levels
External interrupt requests can be programmmed to
be level- or transition- activated
Interrupt Overall
External events and the real-time driven onchip
peripherals require service by the CPU asynchronous
to the execution of any particular section of code. To
tie the asynchronous activities of these functions to
normal program execution, a sophisticated
multiple-source, two-priority-level, nested interrupt
system is provided. Interrupt response latency ranges
from 3µs to 7µs when using a 12 MHz crystal.
The MV20556 acknowledges interrupt requests from
INPUT LEVEL AND
INTERRUPT REQUEST
FLAG REGISTER:
SOURCE
ENABLE
MV20556
Preliminary
five sources: Two from external sources via the #INT0
and INT1 pins, one from each of the two internal
counters and one from the serial I/O port. Each
interrupt vectors to a separate location in Program
Memory for its service program. Each of the five
sources can be assigned to either of two priority levels
and can be independently enabled and disabled.
Additionally all enabled sources can be globally
disabled or enabled. Each external interrupt is
programmable as either level- or transition-activated
and is active-low to allow the "wire or-ing" of several
interrupt sources to the input pin. The interrupt system
is shown diagrammatically in below figure.
Interrupt System Functional Description
Interrupts result in a transfer of control to a new
program location. The program servicing the request
begins at this address. In the MV20556 there are five
hardware sources that can generate an interrupt
request. The starting address of the interrupt service
program for each interrupt source is shown in table on
next page.
A resource requests an interrupt by setting its
associated interrupt request flag in the TCON or SCON
register, as detailed in following table. The interrupt
request will be acknowledged if its interrupt enable bit
in the Interrupt Enable register is set and if it is the
highest priority resource requesting an interrupt. A
resource's interrupt priority level is established as
INTERRUPT
PRIORITY
REGISTER:
GLOBAL
ENABLE
TCON.1
IE.0
IE0
TCON.5
EX0
IE.1
PX0
IP.1
TF0
TCON.3
ET0
IE.2
PT0
IP.2
IE1
TCON.7
EX1
IE.3
PX1
IP.3
TF1
SCON.0
TI
SCON.1
RX
IP.0
IE.7
ET1
IE.4
ES
POLLING
HARDWARE
HIGH PRIORITY
INTERRUPT
REQUEST
SOURCE
I.D.
LOW PRIORITY
INTERRUPT
REQUEST
PT1
IP.4
PS
EA
VECTOR
SOURCE
I.D.
VECTOR
Specifications subject to change without notice, contact your sales representatives for the most recent information.
9/27
PID256** 07/97
MOSEL VITELIC INC.
Interrupt System(Cont'd)
Interrupt System Functional Description (Cont'd)
high or low by the polarity of a bit in the Interrupt
Priority register. These bit assignments are shown in
IP definition. Setting the resource's associated bit to a
one (1) programs it to the higher level. The priority of
multiple interrupt requests occurring simultaneously
and assigned to the same priority level is also shown in
below table.
The servicing of a resources's interrupt request occurs
at the end of the instruction-in-progress. The processor
transfers control to the starting address of this
resource's interrupt service program and begins
execution. Within the Interrupt Enable register (IE)
there are six addressable flags.
Five flags
enable/disable the five interrupt sources when
set/cleared. Setting/clearing the sixth flag permits a
global enable/disable of each enabled interrupt request.
Setting/clearing a bit in the Interrupt Priority register
(IP) establishes its associated interrupt request as a
high/low priority (Table on next page). If a low-priority
level interrupt is being serviced, a high-priority level
interrupt will interrupt it. However, an interrupt source
cannot interrupt a service program of the same or
higher level.
The processor records the active priority level(s) by
setting internal flip-flop(s).
One of these
non-addressable flip-flops is set while a low-level
interrupt is being serviced. The other flip-flop is set
while the high-level interrupt is being serviced. The
appropriate flip-flop is set when the processor transfers
control to the service program.
The flip-flop
corresponding to the interrupt level being serviced is
reset when the processor executes an RETI Instruction.
To summarize, the sequence of events for an interrupt
Interrupt Source
External Request 0
Internal timer 0/ counter 0
External request 1
Internal timer 1/ counter 1
Internal Serial Port (Xmit)
Internal Serial Port (Rcvr)
MV20556
Preliminary
Request Flag
IE0
TF0
IE1
TF1
TI
RI
is: A resource provokes an interrupt by setting its
associated interrupt request bit to let the processor
know an interrupt condition has occurred. The CPU's
internal hardware latches the interrupt request near the
falling-edge of ALE internal signal in the tenth (10th),
twenty-second (22nd), thirty-fourth (34th) and forty-six
(46th) oscillator period of the instruction-in-progress.
The interrupt request is conditioned by bits in the
interrupt enable and interrupt priority registers. The
processor acknowledges the interrupt by setting one of
the two internal "priority-level active" flip-flops and
performing a hardware subroutine call. The call pushes
the PC (but not the PSW) onto the stack and, for most
sources, clears the interrupt request flag. The service
program is then executed. Control is returned to the
main program when the RETI instruction is executed.
The RETI instruction also clears one of the internal
"priority-level active" flip-flops.
Most interrupt request flags (IE0, IE1, TF0 and TF1)
are cleared when the processor transfers control to the
first instruction of the interrupt service program. The TI
and RI interrupt request flags are the exceptions and
must be cleared as part of the serial port's interrupt
service program.
The process whereby a high-level interrupt request
interrupt a low-level interrupt service program is called
nesting. In this case the address of the next instruction
in the low-priority service program is pushed onto the
stack, the stack pointer is incremented by two (2) and
processor control is transferred to the Program Memory
location of the first instruction of the high-level service
program. The last instruction of the high-priority
interrupt service program must be an RETI instruction.
This instruction clears the high "priority-level-active"
flip-flop. RETI also returns processor control to the
next instruction of the low-level interrupt service
program. Since the lower "priority-level-active" flip-flop
has remained set, high priority interrupts are re-enable
while further low priority interrupts remain disabled.
Bit Location
TCON.1
TCON.5
TCON.3
TCON.7
SCON.1
SCON.0
Priority Flags
.0 (highest)
.1
.2
.3
.4
(lowest)
Start address
Decimal
HEX
3
0003H
11
000Bh
19
0013H
27
001Bh
35
0023h
Interrupt flags & addresses
Specifications subject to change without notice, contact your sales representatives for the most recent information.
10/27
PID256** 07/97
MOSEL VITELIC INC.
MV20556
Preliminary
Interrupt System(Cont'd)
The highest-priority interrupt request gets serviced at
the end of the instruction-in progress unless the
request is made in the last fourteen oscillator periods of
the instruction-in-progress. Under this circumstance,
the next instruction will also execute before the
interrupt's subroutine call is made. The first instruction
of the service program will begin execution twenty-four
oscillator periods (the time required for the hardware
subroutine call) after the completion of the
instruction-in-progress or, under the circumstances
mentioned earlier, twenty-four oscillator periods after
the next instruction.
Thus, the greatest delay in response to an interrupt
request is 86 oscillator periods (approximately 7µsec @
12 MHz). Examples of the best and worst case
conditions are illustrated in right side table.
External Interrupts
The external interrupt request inputs (#INT0 and
#INT1) can be programmed for either transitionactivated or level-activated operation. Control of the
external interrupts is provided by the four low-order bits
of TCON. When IT0 and IT1 are set to one (1),
interrupt requests on #INT0 and #INT1 are
transition-activated (high-to-low); or else they are
low-level activated. IE0 and IE1 are the interrupt
request flags. These flags are set when their
corresponding interrupt request inputs at #INT0 and
#INT1, respectively, are low when sampled by the
MV20556 and the transition activated scheme is
selected by IT0 and IT1. When IT0 and IT1 are
programmed for level-activated interrupts, the IE0 and
IE1 flags are not affected by the inputs #INT0 and
INT1, respectively.
Transition-Activated Interrupts
The external interrupt request inputs (#INT0 and
#INT1) can be programmed for high-to-low
transition-activated operation. For transition-activated
operation, the input must remain low for greater than
twelve oscillator periods, but need not be synchronous
with the oscillator. It is internally latched by the
MV20556 near the falling-edge of ALE during an
instruction's tenth, twenty-second, thirty-fourth and
forty-sixth oscillator periods and, if the input is low, IE0
or IE1 is set.
The upward transition of a transition- activated input
may occur at any time after the twelve oscillator period
latching time, but the input must remain high for twelve
oscillator periods before reactivation.
Level-Activated Interrupt
The external interrupt request inputs (#INT0 and
#INT1)can be programmed for level-activated
operation. The input is sampled by the MV20556 near
the falling-edge of internal signal ALE during the
instruction's tenth (10th), twenty-second (22nd), thirtyfourteen (34th) and forty-sixth (46th) oscillator periods.
MSB
LSB
EA
-
EA
IE.7
ES
ET1
IE.6
IE.5
IE.4
IE.3
EX0
IE.2
ET0
IE.1
EX1
IE.0
-
ES
ET1
EX1
ET0
EX0
Disable all interrupts. If EA=0, no interrupt will be acknowledged. If EA=1, each interrupt source is
individually enabled or disabled by setting or clearing its enable bit. Cleared by software to disable all
interrupts, independent of the state of IE. 4-IE.0
Reserve for future use.
Reserve for future use.
Enable Serial port control bit. Set/cleared by software to enable/disable interrupts from TI or RI flags.
Enable or disable the timer 1 overflow interrupt. Set/cleared by software to enable/disable interrupts
from timer/counter 1
Reserve for future use. Enable External interrupt 1 control bit. Set/cleared by software to
enable/disable interrupts from INT1.
Enable or disable the timer 0 overflow interrupt. Set/cleared by software to enable/disable interrupts
from timer/counter 0
Enable External interrupt 0 control bit. Set/cleared by software to enable/disable interrupts from INT0
IE definition
Specifications subject to change without notice, contact your sales representatives for the most recent information.
11/27
PID256** 07/97
MOSEL VITELIC INC.
MV20556
Preliminary
Interrupt System (Cont'd)
that occurs fourteen oscillator periods before the end of
the instruction in progress, an interrupt subroutine call
is made. The level-activated input need be low only
during the sampling that occurs fourteen oscillator
periods before the end of the instruction-in-progress
and may remain low during the entire execution of the
service program. However, the input must be raised
before the service program completes to avoid possible
envoking a second interrupt.
MSB
LSB
-
-
PS
IP.7
IP.6
IP.5
IP.4
PT1
IP.3
PX0
IP.2
PT0
IP.1
PX1
IP.0
-
PS
PT1
PX1
PT0
PX0
Reserve for future use.
Reserve for future use.
Reserve for future use.
Serial Port Priority control bit. Set/cleared by software to specify high/low priority interrupts for Serial
port.
Defines the idle or power down mode interrupt priority level. Set/cleared by software to specify high/low
priority interrupts for timer/counter1.
External interrupt 1 Priority control bit. Set/cleared by software to specify high/low priority interrupts for
INT1.
Defines the timer 0 interrupt priority level. Set/cleared by software to specify high/low priority interrupts
for timer/counter0.
External interrupt 0 Priority control bit. Set/cleared by software to specify high/low priority interrupts for
INT0.
IP definition
Specifications subject to change without notice, contact your sales representatives for the most recent information.
12/27
PID256** 07/97
MOSEL VITELIC INC.
MV20556
Preliminary
counter. TH1 holds the reload value. TL1 is
incremented. The value in TH1 is reload onto TL1 when
TL1 overflows from all ones.
Timer/Counter
Timer/Counter Overall
The MV20556 contains two 16-bit counters for
measuring time internals, measuring pulse widths,
counting events and generating precise, periodic
interrupt requests.
Each can be programmed
independently to operate as an 8048 8-bit timer with
divide by 32 prescaler or as an 8-bit counter with divide
by 32 prescaler (Mode 0), as a 16-bit time-interval or
event counter (Mode 1), or as an 8-bit time-interval or
event counter with automatic reload upon overflow
(Mode 2).
Additionally, counter 0 can be programmed to a mode
that divides it into one 8-bit time-internal or event
counter and one 8-bit time-interval counter (Mode 3).
When counter 0 is in Mode 3, counter 1 can be
programmed to any of the three aforementioned
modes, although it cannot set an interrupt request flag
or generate an interrupt. This mode is useful because
counter 1's overflow can be used to pulse the serial
port's transmission-rate generator. Along with their
multiple operating modes and 16-bit precision, the
counters can also handle very high input frequencies.
These range from 3 MHz to 40 MHz (for 3 MHz to 40
MHz crystal) when programmed for an input that is a
division by 12 of the oscillator frequency and from 0 Hz
to an upper limit of 1 MHz (for 25 MHz crystal) when
programmed for external inputs. Both internal and
external inputs can be gated to the counter by a second
external source for directly measuring pulse widths.
The counters are started and stopped under software
control. Each counter sets its interrupt request flag
when it overflows from all ones to all zeros (or
auto-reload value). The operating modes and input
sources are summarized in right side Figures.
Mode 3: Prevents incrementing of timer/counter
When counter 1's mode is reprogrammed to mode 3
(from mode 0, 1 or 2), it disables the incrementing of
crystal
oscillator
÷12
TIMER 0
exteranl
source
8
TH0
8
TL0
MODE 0: 8-bit timer/counter with prescaler
MODE 1: 16-bit timer/counter
MODE 2: 8-bit auto-reload timer/couner
crystal
oscillator
÷12
TIMER 1
8
TH1
exteranl
source
8
TL1
pulse
to
serial
port
Mode 0, 1 and 2
crystal
oscillator
÷12
exteranl
source
8
TL0
8
TH0
crystal
oscillator
Overflow
(Interrupt
request)
flag 1
Overflow
(Interrupt
request)
flag 0
MODE 3: 8-bit timer/counter
Mode 0: 8-bit timer/counter with prescaler
Provides an 8-bit counter with a divide-by-32 prescaler
or an 8-bit timer with a divideby-32 prescaler.
Overflow
(Interrupt
request)
flag 1
MODE 0: 8-bit timer/counter with prescaler
MODE 1: 16-bit timer/counter
MODE 2: 8-bit auto-reload timer/couner
Counter 1/Timer 1
Counter 1/Timer 1 can be configured in one of four
modes by software program code on the fly:
Overflow
(Interrupt
request)
flag 0
÷12
TIMER 1
exteranl
source
Mode 1: 16-bit timer/counter
Configures counter 1 as a 16-bit timer/counter.
8
TH1
MODE 0: 8-bit timer/counter with prescaler
MODE 1: 16-bit timer/counter
MODE 2: 8-bit auto-reload timer/couner
Mode 2: 8-bit auto-reload timer/counter
Configures counter 1 as an 8-bit auto-reload timer/
8
TL1
pulse
to
serial
port
Mode 3
Specifications subject to change without notice, contact your sales representatives for the most recent information.
13/27
PID256** 07/97
MOSEL VITELIC INC.
MV20556
Preliminary
Timer/Counter (Cont'd)
the counter. This mode is provided as an alternative to
use TR1 bit (TCON.6) to start and stop counter 1. The
serial port receives a pulse each time that counter 1
overflows. The standard UART modes divide this pulse
rate to generate the transmission rate.
mode 3: stop
Counter 0/Timer 0
Counter 0/Timer 0 can also be configured in one of four
modes software program code on the fly:
Mode 0-2:
Mode 0-2 are the same as those for counter 1.
Mode 3: 8-bit timer/counter (TL1)
In mode 3, the configuration of TH0 is not affected by
the bits in TMOD or TCON. It is configured solely as
an 8-bit timer that is enabled for incrementing by
TCON's TR1 bit. Upon TH0's overflows, the TF1 flag
gets set. Thus, neither TR1 nor TF1 is available to
counter 1 when counter 0 is in mode 3. The function of
TR1 can be done by placing counter 1 in mode 3, so
only the function of TF1 is actually given up by counter
1. In mode 3, TL0 is configured as an 8-bit
timer/counter and is controlled, as usual, by the GATE
(TMOD.3), C/#T(TMOD.2), TR0 (TCON.4) and TF0
(TCON.5) control bits.
Configuring of Timer/Counter
The use of the timer/counters is determined by two 8bit registers, TMOD (timer mode) and TCON (timer
control). The input to the counter circuitry from an
external reference (for use as a counter), or from the
on-chip oscillator (for use as a counter), or from the onchip oscillator (for use as a timer), depending on whether
TMOD's C/#T bit is set or cleared, respectively. When
used as a timer base, the on-chip oscillator frequency is
divided by twelve (12) before being input to the counter
circuitry. When TMOD's Gate bit is set (1), the external
reference input (T1, T0) or the oscillator input is gated to
the counter conditional upon a second external input
(#INT0, #INT1) being high. When the Gate bit is zero (0),
the external reference or oscillator input is unconditionally
enabled. In either case, the normal interrupt function of
#INT0 and #INT1 is not affected by the counter's
operation. If enabled, an interrupt will occur when the
input at #INT0 or #INT1 is low. The counters are enabled
for incrementing when TCON's TR1 and TR0 bits are set.
When the counters overflow the TF1 and TF0 bits in
TCON get set and interrupt requests are generated. The
functions of the bits in TCON are shown in below table.
The functions of the bits in TMOD are shown in table on
next page.
Operation
The counter circuitry counts up to all 1's and then
overflows to either 0's or the reload value. Upon
overflow, TF1 or TF0 gets set. When an instruction
MSB
TF1
LSB
TR1
TF1
TCON.7
TR1
TF0
TCON.6
TCON.5
TR0
TCON.4
IE1
TCON.3
IT1
TCON.2
IE0
TCON.1
IT0
TCON.0
TF0
TR0
-
-
IDF
-
Timer 1 overflow flag. Set by hardware when the timer/counter 1 overflows. Cleared by hardware as
processor vectors to the interrupt service routine.
Timer 1 run control bit. Set/cleared by software to turn timer/counter 1 ON/OFF.
Timer 0 overflow flag. Set by hardware when the timer/counter 0 overflows. Cleared by hardware as
processor vectors to the interrupt service routine.
Timer 0 run control bit. Set/cleared by software to turn timer/counter 0 ON/OFF.
Interrupt 1 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt
processed.
Interrupt 1 Type control bit. Set/cleared by software to specify falling edge/low level triggered external
interrupts.
Interrupt 0 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt
processed.
Interrupt 1 Type control bit. Set/cleared by software to specify falling edge/low level triggered external
interrupts.
TCON definition
Specifications subject to change without notice, contact your sales representatives for the most recent information.
14/27
PID256** 07/97
MOSEL VITELIC INC.
MV20556
Preliminary
Timer/Counter (Cont'd)
changes the timer's mode or alters its control bits, the
actual change occurs at the end of the instruction's
execution.
The T1 and T0 inputs are sampled near the fallingedge of ALE in the tenth(10th), twenty-second(22nd),
thirty-fourth(34th) and forty-sixth(46th) oscillator periods
of the instruction-in-progress. They are also sampled
in the twenty-second oscillator period of MOVX despite
the absence of internal signal ALE. Thus, an external
reference's high and low times must each be a
minimum of twelve oscillator periods in duration. There
is a twelve oscillator period delay from when a toggled
input (transition from high to low) is sampled to when
the counter is ineremented.
Reading/Reloading
The timer/counters can be read and reloaded on the fly.
However, the 16-bit timer/counters must be read and
loaded as two 8-bit bytes. During a read the potential
"phasing error" can be programmed around, as follows:
RTC
MOV A, TH0
MOV B, TL0
CJNE A, TH0, RTC
Timer 1
Timer 0
MSB
LSB
GATE
GATE
C/#T
M1
M0
C/#T
M1
M0
GATE
C/#T
M1
M0
When TRx (in TCON) is set and GATE=1, TIMER/COUNTERx will run only while INTx pin is
high (hardware control). When GATE=0, TIMER/COUNTERx will run only while TRx=1
(software control).
Timer or counter selector. Cleared for timer operation (input from internal system clock).
Set for counter operation (input form Tx input pin).
Mode selector bit.
Mode selector bit.
M1
0
0
1
1
M0
0
1
0
1
1
1
Operating mode
Mode 0. (13-bit timer, by prescaled.)
Mode 1. (16-bit timer/counter)
Mode 2. (8-bit auto-load timer/counter)
Mode 3. (TL0 is an 8-bit timer/counter controlled by the standard timer 0
control bits. TH0 is an 8-bit timer and is controlled by timer 1 control bits.)
Mode 3. (Timer/counter 1 stopped).
TMOD definition
Specifications subject to change without notice, contact your sales representatives for the most recent information.
15/27
PID256** 07/97
MOSEL VITELIC INC.
MV20556
Preliminary
External Interface
MV20556
Reset
Processor initialization is accomplished with acitivation
of the RES pin. To reset the processor, this pin should
be held high for at least twenty-four oscillator periods.
Upon powering up, RES should be held high for at least
1 ms after the power supply stabilizes to allow the
oscillator to stabilize. Upon receipt of RES, the
processor ceases instruction execution and remains
dormant for the duration of the pulse. The pins assume
their initialization states within 2 machine cycles clocks.
The low-going transition then initiates a sequence
which requires approximately twelve oscillator periods
to execute before ALE(internal signal) is generated and
normal operation commences with the instruction at
absolute location 0000H. This sequence ends with
registers initialized as shown in right table.
30µF
RES
R RES
Power-on Reset
MV20556
1K ohm
RES
RRES
When the processor is reset all ports are immediately
written with ones (1's).
MV20556
The Schimitt-trigger input has a small internal pull down
resistor which permits power-on reset (as shown in
right to Figure) using only a small capacitor tied to
VDD. A conventional external reset circuit, such as
that in right Figure, can also be used.
I OL
Output low current.
For port 1 and port 3, MV20556 provided I OL up to
18mA per pin typicallly at VOL=0.45V. User are free to
choose any one of these 15 pins to perform this high
current sink capability. But they are restricted: no more
than 80 mA I OLs for all output pins.
1K ohm
30µF
RES
RRES
External Reset
Register
Content after
Content after
Reset at Power on Reset while running
PC
SP
PSW
DPH, DPL
A, B
0000H
07H
00H
00H
00H
IP
E0H or 00H
IE
60H or 00H
SCON
00H
TMOD
00H
TCON
00H
TH1, TH0
00H
TL1, TL0
00H
SBUF
indeterminate
Port 1 & 3
FFH (*1)
Internal RAM indeterminate
*1 configures all i/o pins as inputs
0000H
07H
00H
00H
00H
E0H or 00H
60H or 00H
00H
00H
00H
00H
00H
indeterminate
FFH (*1)
unchanged
Register vs Reset
Specifications subject to change without notice, contact your sales representatives for the most recent information.
16/27
PID256** 07/97
MOSEL VITELIC INC.
MV20556
Preliminary
External Interface (Cont'd)
routine and then returns to PC+1 address after the
program wakes up.
Idle Mode
During idle mode, the CPU is stopped but below blocks
are kept functioning:clock generator, RAM, timer/
counters, serial port and interrupt block.
During idle mode, the CPU is stopped but below blocks
are kept functioning: clock generator, RAM, timer/
counters, serial port and interrupt block. To save power
consumption, user's software program can invoke this
mode. The on-chip data RAM retains the values during
this mode, but the processor stops executing instructions.
In Idle mode (IDL=1), the oscillator continues to run and
the interrput, and timer blocks continue to be clocked but
the clock signal is gated off to the CPU. The activities of
the CPU no longer exist unless waiting for an interrupt
request.
-An instruction that sets flag (PCON.0) causes that to be
the last instruction executed before going into the Idle
Mode.
-In the Idle Mode, the internal clock signal is gated off to
the CPU, but not to the interrupt, Timer function.
-The CPU status is entirely preserved in its:
the Stack Pointer, Program Counter, Program Status
Word, Accumulator, and all other registers maintain
their data during Idle mode.
-There are two ways to terminate the Idle Mode.
1) By interrupt
Activation of any enabled interrupt will cause flag
(PCON.0) to be cleared by hardware, termination the
Idle Mode. After the program wakes up, the PC value
will point as interrupt vector (if enable IE register) and
execute interrupt service routine then return to PC+1
address after the program wakes up.
2) By hardware reset
Since the clock oscillator is still running, the hardware
reset needs to be held active for only two machine
cycles (24 clocks) to complete the reset. All
SFR and PC value will be cleared to reset value.
After the program wakes up, the PC value will be 0023h
(if enable IE register) and execute interrupt service
Vdd
Power Down Mode
It saves the RAM content, stops the clock generator and
disables every other blocks' function until the coming
hardware reset. To save even more power consumption,
user's software program can invoke this mode. The
SFRs and the on-chip data RAM retain their values
during this mode, but the porcessor stops executing
instructions. In Power-Down mode (PD=1) the oscillator
is frozen.
-An instruction that sets flag (PCON.1) causes that to
be the last instruction executed before going into the
Power Down Mode.
-In the Power Down Mode, the on-chip oscillator is
stopped.
With the clock frozen, all functions are stopped, but
the on-chip RAM and Special Function Registers are
held.
-Reset redefines all the SFRs, but does not change the
on-chip RAM.
-There is only one way to terminate the Power Down
Mode - by hardware reset.
All SFR and PC value will be cleared to reset value.
After the program wakes up, the PC value will be
0023h (if enable IE register) and execute interrupt
service routine and then returns to PC+1 address after
the program wakes up.
-Care must be taken, however, to ensure that Vdd is
not reduced before the Power Down Mode is invoked,
and that Vdd is restored to its normal operating level
before the Power Down Mode is terminated.
-The hardware reset must be held active long enough
to allow the oscillator to restart and stabilize.
Data can be maintained valid in the Internal Data RAM
while the remainder of the MV20556 is powered down.
When powered down, the MV20556 consumes about
10% of normal operating power. During normal operation
both the CPU and the internal RAM derive their power
from VDD. However, the internal RAM will derive its
power from RES when the voltage on VDD is more than
a diode drop below that on RES.
When a power-supply failure is imminent, the user's
system generates a "power-failure" signal to interrupt the
#INTx
(power fail)
Interrupt
Mode
Program
memory
Idle
Power Down
Internal
Internal
RES
Normal
Operation
service
routine
Normal
Operation
Port 3
Data
Data
Specifications subject to change without notice, contact your sales representatives for the most recent information.
17/27
PID256** 07/97
MOSEL VITELIC INC.
Preliminary
MV20556
External Interface (Cont'd)
processor via #INT0 or #INT1. This power-failure signal
must be early enough to allow the MV20556 before VDD
falls below its operating limit. The program servicing the
power-failure interrupt request must save any important
data and machine status into Internal Data RAM. The
service program must also enable the backup power
supply to the RES pin. Applying power to the RES pin
resets the MV20556 and retains the internal RAM data
valid as the VDD power supply falls below limit. Normal
operation resumes when RES is returned low. Figure on
last page left column shows the waveforms for the
power-down sequence.
Timing Generation
Timing generation for the MV20556 completely selfcontained, except for the frequency reference which can
be a crystal or external clock source. The on-board
oscillator is a parallel anti-resonant circuit with a frequency
range of 3 M to 40 MHz. The XTAL2 pin is the output of a
high-gain amplifier, while XTAL1 is its input. A crystal
connedted between XTAL1 and XTAL2 provides the
feedback and phase shift required for oscillation. The 3 to
40 MHz range is also accomodated when an external TTL
compatible clock is applied to XTAL1 as the frequency
source.
The I/O Circuit
WRENB
L Q
DB
D
SD
Pn
RES
RDENB
P1, P3
Specifications subject to change without notice, contact your sales representatives for the most recent information.
18/27
PID256** 07/97
MOSEL VITELIC INC.
MV20556
Preliminary
Absolute Maximal Rating
Symbol
Name
VDD - Vss
DC supply Voltage
VIN
VOUT
Input voltage
output voltage
Rating
Unit
-0.5 - +7.0
V
Vss-0.3 - V DD +0.3
V
T(Operating) Operating Temperature
Storage Temperature
T(Storage)
Vss - VDD
0 - +70
-55 - +125
C
C
* Note: Operation beyond Absolute Maximal Rating can adversely
affect device reliability.
Operating Conditions
Symbol
TA
Vdd
fosc 16
fosc 25
fosc 40
Description
Ambient temperature under bias
Supply voltage
Oscillator Frequency of MV20556C16
Oscillator Frequency of MV20556C25
Oscillator Frequency of MV20556C40
Min.
0
4.5
3
3
3
Typ.
25
5.0
16
25
40
Max
70
5.5
16
25
40
Unit Test Condition
C
V Vss=0V
MHz
MHz
MHz
Max
Unit
V
V
V
V
V
uA
uA
uA
mA
mA
Kohm
pF
mA
mA
uA
DC Characteristics
(16 MHz, typical operating conditions)
Symbol
VIL
VIH
VIH1
VOH
Parameter
Input Low Voltage
Input High Voltage
Input High Voltage
Output High Voltage
Valid
I IL
I TL
I LI
I OL
I OL1+3
R RES
C IO
I CC
Logical 0 Input Cruuent
Logical 1 To 0 Transition Current
Input Leakage Current
Output Low Current
Output low current of 15 pins
Reset Pulldown R
Pin Capacitance
Power Supply Current
Ports 1,3
Ports 1,3
Port 1
Port 1,3
Port 1 & 3
* note 2
XTAL, RES
Port 1,3
Min.
Typ.
0.2Vcc-0.1
Vcc+0.5
Vcc+0.5
-0.5
0.2Vc+0.9
0.7Vcc
2.4
0.9Vcc
-50
-650
10
18
50
Vdd
Vdd
Vdd
5
3
80
150
10
8
5
1
Test Conditions
IOH=-60uA
IOH=-10uA
Vin=0.45V
Vin=2V
0.45<Vin<Vcc
V OL=0.45V
Freq=1MHz, Ta=25 J
¢
Active mode, 16MHz
Idle mode, 16MHz
Power down mode
Note 2:=Except XTAL, RES
DC Characteristics at 25 MHz
to be available
DC Characteristics at 40 MHz
to be available
Specifications subject to change without notice, contact your sales representatives for the most recent information.
19/27
PID256** 07/97
MOSEL VITELIC INC.
MV20556
Preliminary
AC Characteristics
(16 MHz, typical operating conditions)
Symbol
Parameter
Valid Cycle
Min.
Typ.
Max
T CLCL
Remarks
nS
nS
nS
Clock period
T SCLK serial port clock cycle
T QVCH Output data Setup to clock rise
T CHQX Output data hold after clock rise
T CHDV Clock rise to input data valid
T CHDX Input data hold after clock rise
T POR Power On reset time
T WAKE Oscillator wake up time
Reset pulse width
T RES
Unit
nS
T CHCL Clock fall time
T CLCX Clock low time
T CLCH Clock rise time
T CHCX Clock high time
nS
62
uS
nS
Power on
Power Down Mode
Running
nS
nS
nS
nS
nS
uS
1.5
24* T CLCH
AC Characteristics
(25 MHz, typical operating conditions)
Symbol
T CHCL
T CLCX
T CLCH
T CHCX
T CLCL
T SCLK
T QVCH
T CHQX
T CHDV
T CHDX
T POR
T WAKE
T RES
Parameter
Clock fall time
Clock low time
Clock rise time
Clock high time
Clock period
serial port clock cycle
Output data Setup to clock rise
Output data hold after clock rise
clock rise to input data valid
Input data hold after clock rise
Power On reset time
Oscillator wake up time
Reset pulse width
Valid Cycle
Min.
Typ.
40
Power on
Power Down Mode
Running
960
Max
Unit
nS
nS
nS
nS
nS
uS
nS
nS
nS
nS
nS
nS
nS
Remarks
24* T CLCH
Specifications subject to change without notice, contact your sales representatives for the most recent information.
20/27
PID256** 07/97
MOSEL VITELIC INC.
MV20556
Preliminary
AC Characteristics
(40 MHz, typical operating conditions)
Symbol
Valid Cycle
Parameter
Min.
Typ.
Max
T CLCL
Unit
Remarks
nS
T CHCL Clock fall time
T CLCX Clock low time
T CLCH Clock rise time
T CHCX Clock high time
nS
nS
nS
Clock period
nS
25
T SCLK serial port clock cycle
T QVCH Output data Setup to clock rise
T CHQX Output data hold after clock rise
T CHDV clock rise to input data valid
T CHDX Input data hold after clock rise
T POR Power On reset time
T WAKE Oscillator wake up time
Reset pulse width
T RES
uS
Power on
Power Down Mode
Running
nS
nS
nS
nS
nS
nS
nS
600
24* T CLCH
Application Reference
X'tal 3 MHz
6 MHz 16 MHz
25 MHz
40 MHz
C1
39 pF
39 pF
30 pF
15 pF
5 pF
C2
39 pF
39 pF
30 pF
15 pF
5 pF
R
open
open
open
62 Kohm
4700 ohm
X1
X'tal
MV20556
R
X2
C1
C2
Specifications subject to change without notice, contact your sales representatives for the most recent information.
21/27
PID256** 07/97
MOSEL VITELIC INC.
MV20556
Preliminary
Emulation Board
Model number: M9257
Two layers
There is a 74373 chip soldered under chip 27C512
The 4 KB program code should be programmed into the first 4 KB address location of EPROM 27C512-150
which is inserted into U4 location.
When applying at different working clock, this M9257 demands different speed of EPROM chip
16 MHz: 27C512-200 or faster
25 MHz: 27C512-100 or faster
40 MHz: 27C512-60 or faster
0
1
2 cm
28
15
TOP
VIEW
27C512-mm
U4
40
21
MSU2031Cnn
U1
20
PROFILE
Timing Critical, Requirement of External Clock
(Vss=0.0V is assumed)
T CLCL
Vdd-0.5V
70%Vdd
0.45V
20%Vdd-0.1V
T CHCX
T CLCX
T CHCL
T CLCH
Specifications subject to change without notice, contact your sales representatives for the most recent information.
22/27
PID256** 07/97
MOSEL VITELIC INC.
MV20556
Preliminary
20L 300mil PDIP Information
E
D
S
E1
A1
A2
C
A
L
e1
eA
B1
B
£\
Note:
1.Dimension D Max & S include mold flash or tie bar
burrs.
2.Dimension E1 does not include interlead flash.
3.Dimenseion D & E1 include mold mismatch and are
determined at the mold parting line.
4.Dimension B1 does not include dambar protrusion/
infrusion.
5.Controlling dimension is inch.
6.General appearance spec. should base on final visual
inspection spec.
Symbol
A
A1
A2
B
B1
C
D
E
E1
e1
L
£\
eA
S
Dimension Inch
minimal/maximal
- / 0.175
0.010 / 0.125 / 0.135
0.016 / 0.022
0.058 / 0.064
0.008 / 0.014
- / 1.040
0.290 / 0.310
0.245 / 0.255
0.090 / 0.110
0.120 / 0.140
0 / 15
0.335 / 0.375
- / 0.075
Dimension in mm
minimal/maximal
- / 4.45
0.25 / 3.18 / 3.43
0.41 / 0.56
1.47 / 1.63
0.20 / 0.36
- / 26.42
7.37 / 7.87
6.22 / 6.48
2.29 / 2.79
3.05 / 3.58
0 / 15
8.51 / 9.53
- / 1.91
Specifications subject to change without notice, contact your sales representatives for the most recent information.
23/27
PID256** 07/97
MOSEL VITELIC INC.
MV20556
Preliminary
20L Small Outline Gull Wing Package
01
C
L
L1
E
R1
H
A1
A2
G
03
R2
A
0
D
01
Y
B
Note:
1. Dimension D does not include mold flash, protrustions
or gate burrs. Allowance protrusion is 0.25mm per
side. Dimensions E does not include inter-lead flash
or protrusions.
Dimension in Inch
minimal/maximal
- / 0.100
0.004 / 0.012
0.091
0.013 / 0.020
0.007 / 0.011
Dimension in mm
minimal/maximal
2.36 / 2.64
0.10 / 0.30
2.31
0.33 / 0.51
0.18 / 0.21
0.496 / 0.508
0.291 / 0.299
0.050
0.020 x 45
0.394 / 0.419
0.015 / 0.050
12.60 / 12.94
7.39 / 7.51
1.27
10.01 / 10.64
0
01
03
0 / 8
7 REF
7 REF
C
0.004
as left
as left
as left
0.10
Symbol
A
A1
A2
B
C
D
E
e
G
H
L
L1
R1
R2
0.38 / 1.21
Specifications subject to change without notice, contact your sales representatives for the most recent information.
24/27
PID256** 07/97
MOSEL VITELIC INC.
MV20556
Preliminary
Bonding Information
PAD-NAME
Index
1
2
3
4
5
6
7
8
9
10
11
12
Y-COORD
X-COORD
168
168
168
168
168
168
632
954
1186
1413
1638
2244
540
738
889
1085
1306
1527
1934
1934
1934
1934
1934
1735
P0.7
VDD
VDD
RES
RxD / P3.0
TxD / P3.1
XTAL2
XTAL1
#INT0 / P3.2
#INT1 / P3.3
T0 / P3.4
T1 / P3.5
Index
13
14
15
16
17
18
19
20
21
22
23
24
PAD-NAME
VSSGND
VSSGND
VSSGND
NC
P3.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
X-COORD
Y-COORD
1536
1385
1234
1037
816
595
374
168
168
168
168
168
2244
2244
2244
2244
2244
2244
2244
1906
1678
1453
1226
1001
Logo
19
18
17
16
15
14
13
12
20
21
MV20556
22
11
2200 x 3160 (µm)
10
PAD SIZE : 90 x 90 (µm)
23
substrate should be bonded to Vss (Gnd)
9
8
24
pid 256* 11/96 (6)
pid 256** 07/97 (27)
7
1
Taiwan
#1 Creation Road I,
Science - based Industrial Park,
Hsinchu, 30077
Taiwan, ROC
"[email protected]"
TEL: 886-3-577-0055
FAX: 886-3-577-2788
FAX: 886-3-578-4732
Mdm: 886-3-578-0493
2
3
4
5
Taipei
7F, #102 Section 3,
Ming Chung E. Road,
Taipei,105
Taiwan, ROC
TEL: 886-2-545-1213
FAX: 886-2-545-1214
Mdm: 886-2-545-1464
6
China
(Vitelic HKG ShenZhen)
Room #209
San Da building,
#19 ZhenHua Road,
Futian, ShenZhen city,
P.R.China
TEL: 86-755-334-5766
FAX: 86-755-332-3995
Mdm: 86-755-332-3995
Hongkong
#19 Dai Fu Street,
Taipo Industrial Estate,
Taipo, N.T.
Hongkong
TEL: 852-2388-8277(MKO)
TEL: 852-2665-4883
FAX: 852-2664-2406
FAX: 852-2770-8011(MKO)
Mdm: 852-2388-0244
U.S.A.
#3910 North First Street,
San Jose,
CA. 65134-1501
U.S.A.
Japan
Room 302, Annex-G,
Higashi-Nakano,
Nakano-Ku, Tokyo 164
Japan
TEL: 1-408-433-6000
FAX: 1-408-433-0952
TEL: 81-3-3365-2851
FAX: 81-3-3365-2836
http:\\www.moselvitelic.com
Specifications subject to change without notice, contact your sales representatives for the most recent information.
25/27
PID256** 07/97
MOSEL VITELIC INC.
MV20556
Preliminary
3-digit production code
To:
Mosel Vitelic Inc.
886-3-5772788
Attn: Sales & Marketing Department
filled by MVI only
Product Request Form
We hereby request MVI to start producing MV20556 which is specified below .
Please send us the product code and a hardcopy of data code as well as data code file duplicated on
floppy diskette. No further confirmation is necessary.
Production will start automatically once you receive our data code and verify that the checksum is
match.
Mass Production of the captioned device shall be done in accordance with the purchase order(s)
issued by us or a company specified by us. All terms and conditions are based on the development
agreement and/or contract signed between MVI and us.
Data Code Descriptions
IC descriptions
20L-SOP
Dice form
20L-PDIP
Code Length
File Length
Top Marking (fill only for packaged)
File Name
Checksum
Unused
Data Byte
Format
Media
16 MHz
25 MHz
40 MHz
h
00h filled
FFh filled
HEX format
Binary code format
EPROM
8751 chip
File on Floppy
E-mail file
Use MVI logo, date code and part number
Use my specifications as described below
Specify below fields only for customer top marking
Date code location descriptions
Use regular date code as MVI's
Leave it as blank
use right side five letters
Logo Specifications
Leave it blank
Use my specifications as attachment
Part number specified, less than 15 digits
Phone # :
Fax # :
Company Name :
Signature :
Name (Typed) :
Position Title :
Department, Section :
Signature Date :
Specifications subject to change without notice, contact your sales representatives for the most recent information.
26/27
PID256** 07/97
MOSEL VITELIC INC.
Preliminary
MV20556
To:
Mosel Vitelic Inc.
886-3-5772788
Attn: Sales & Marketing Department
Logo Top Marking Request & spec.
We hereby request MVI to have our logo printed on top of the device package. Below is the
specification of our logo in 20:1 scale base. This logo diagram is clear enough and is able to be shrunk
directly to fit into available top marking area described on page.
Phone # :
Fax # :
Company Name :
Signature :
Name (Typed) :
Position Title :
Department, Section :
Signature Date :
Specifications subject to change without notice, contact your sales representatives for the most recent information.
27/27
PID256** 07/97