Filtronic FPD750SOT89CE Low noise high linearity packaged phemt Datasheet

FPD750SOT89
Datasheet 3.0
LOW NOISE HIGH LINEARITY PACKAGED PHEMT
PACKAGE:
FEATURES (1.85GHZ):
•
•
•
•
•
•
RoHS
25 dBm Output Power (P1dB)
9
18 dB Small-Signal Gain (SSG)
0.6 dB Noise Figure
39 dBm Output IP3
55% Power-Added Efficiency
FPD750SOT89E: RoHS compliant
(Directive 2002/95/EC)
GENERAL DESCRIPTION:
TYPICAL APPLICATIONS:
The FPD750SOT89 is a packaged depletion
mode AlGaAs/InGaAs pseudomorphic High
Electron Mobility Transistor (pHEMT). It
utilizes a 0.25 µm x 750 µm Schottky barrier
Gate, defined by high-resolution stepperbased photolithography. The double recessed
gate structure minimizes parasitics to optimize
performance, with an epitaxial structure
designed for improved linearity over a range of
bias conditions and i/p power levels.
•
•
•
Drivers or output stages in PCS/Cellular
base station transmitter amplifiers
High intercept-point LNAs
WLL and WLAN systems, and other types
of wireless infrastructure systems.
ELECTRICAL SPECIFICATIONS:
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Power at 1dB Gain Compression
P1dB
VDS = 5 V; IDS = 50% IDSS
23
25
dBm
Small-Signal Gain
SSG
VDS = 5 V; IDS = 50% IDSS
16.5
18
dB
Power-Added Efficiency
PAE
VDS = 5 V; IDS = 50% IDSS;
50
%
POUT = P1dB
Noise Figure
Output Third-Order Intercept Point
NF
IP3
(from 15 to 5 dB below P1dB)
VDS = 5 V; IDS = 50% IDSS
0.8
VDS = 5 V; IDS = 25% IDSS
0.6
1.0
dB
VDS = 5V; IDS = 50% IDSS
Matched for optimal power
36
Matched for best IP3
38
dBm
39
Saturated Drain-Source Current
IDSS
VDS = 1.3 V; VGS = 0 V
185
230
280
mA
Maximum Drain-Source Current
IMAX
VDS = 1.3 V; VGS ≅ +1 V
375
mA
Transconductance
GM
VDS = 1.3 V; VGS = 0 V
200
mS
Gate-Source Leakage Current
IGSO
VGS = -5 V
1
15
µA
Pinch-Off Voltage
|VP|
VDS = 1.3 V; IDS = 0.75 mA
0.7
1.0
1.3
V
Gate-Source Breakdown Voltage
|VBDGS|
IGS = 0.75 mA
12
16
V
Gate-Drain Breakdown Voltage
|VBDGD|
IGD = 0.75 mA
12
16
V
Thermal Resistance
RθJC
83
°C/W
Note: TAMBIENT = 22°C; RF specification measured at f = 1850 MHz using CW signal (except as noted)
1
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FPD750SOT89
Datasheet v3.0
1
ABSOLUTE MAXIMUM RATING :
PARAMETER
SYMBOL
TEST CONDITIONS
ABSOLUTE MAXIMUM
Drain-Source Voltage
VDS
-3V < VGS < +0V
8V
Gate-Source Voltage
VGS
0V < VDS < +8V
-3V
Drain-Source Current
IDS
For VDS < 2V
IDSS
Gate Current
IG
Forward or reverse current
7.5mA
RF Input Power
PIN
Under any acceptable bias state
175mW
Channel Operating Temperature
TCH
Under any acceptable bias state
175°C
Storage Temperature
TSTG
Non-Operating Storage
-55°C to 150°C
Total Power Dissipation
PTOT
See De-Rating Note below
1.8W
Comp.
Under any bias conditions
5dB
2
Gain Compression
Simultaneous Combination of Limits
3
2 or more Max. Limits
Notes:
1
TAmbient = 22°C unless otherwise noted; exceeding any one of these absolute maximum ratings may cause
permanent damage to the device
2
Max. RF Input Limit must be further limited if input VSWR > 2.5:1
3
Users should avoid exceeding 80% of 2 or more Limits simultaneously
4
Total Power Dissipation defined as: PTOT ≡ (PDC + PIN) – POUT,
where PDC: DC Bias Power, PIN: RF Input Power, POUT: RF Output Power
Total Power Dissipation to be de-rated as follows above 22°C:
PTOT= 1.8 - (0.012W/°C) x TPACK
where TPACK= source tab lead temperature above 22°C
(coefficient of de-rating formula is the Thermal Conductivity)
Example: For a 65°C carrier temperature: PTOT = 1.8W – (0.012 x (65 – 22)) = 1.28W
BIASING GUIDELINES:
•
•
•
Active bias circuits provide good performance stabilization over variations of operating
temperature, but require a larger number of components compared to self-bias or dual-biased.
Such circuits should include provisions to ensure that Gate bias is applied before Drain bias,
otherwise the pHEMT may be induced to self-oscillate
Dual-bias circuits are relatively simple to implement, but will require a regulated negative voltage
supply for depletion-mode devices.
For standard class A operation, a 50% of IDSS bias point is recommended. A small amount of
RF gain expansion prior to the onset of compression is normal for this operating point. A class
A/B Bias of 25-33% of IDSS to achieve better OIP3, and Noise Figure performance is suggested.
2
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FPD750SOT89
Datasheet v3.0
FREQUENCY RESPONSE:
Biased @ 5V, 100mA
Biased @ 5V 50%IDSS
35
1.2
MSG
S21
Noise Figure (dB)
MSG
20
Mag S21
25
&
30
15
1
0.8
0.6
0.4
10
N.F. (dB)
0.2
5
5.7
5.3
4.9
4.5
4.1
3.7
3.3
8
2.9
7.5
2.5
6.5
2.1
3.5
4.5
5.5
Frequency (GHz)
1.7
2.5
1.3
1.5
0.5
0.5
0.9
0
0
Frequency (GHz)
Note: Device tuned for minimum noise figure
TEMPERATURE RESPONSE:
Biased @ 5V,50%IDSS
Data taken on Eval Board at 1.85GHz
Biased @ 5V, 33% IDSS
Data taken on Eval board @ 1.85GHz
0.80
N.F.
0.60
(dB)
Temperature (C)
Note: Data Taken on Evaluation board tuned for maximum power. Achievable noise figure is lower when
optimized.
3
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90
80
70
60
50
40
-20
Temperature (C)
30
0.40
90
80
70
60
50
40
30
20
0
10
-10
-20
14.0
1.00
20
SSG
(dB)
P1dB (dBm)
15.0
1.20
10
16.0
1.40
0
17.0
1.60
-10
18.0
1.80
Noise Figure (dB)
SSG (dB)
19.0
P1dB (dBm)
26.0
25.0
24.0
23.0
22.0
21.0
20.0
19.0
18.0
17.0
16.0
20.0
FPD750SOT89
Datasheet v3.0
TYPICAL TUNED RF PERFORMANCE:
Drain Efficiency and PAE
Power Transfer Characteristic
VDS = 5V IDS = 50% IDSS at f = 1.85 GHz
26.0
3.50
60.0%
25.5
Pout (dBm)
60.0%
PAE
3.00
Comp Point
Eff.
24.0
1.50
23.5
1.00
23.0
0.50
22.5
0.00
22.0
PAE (%)
2.00
-0.50
4
5
6
7
8
9
10
11
50.0%
50.0%
40.0%
40.0%
30.0%
30.0%
20.0%
20.0%
10.0%
12
Drain Efficiency (%)
2.50
24.5
Gain Compression (dB)
Output Power (dBm)
25.0
10.0%
1
3
5
Input Power (dBm)
7
9
11
Input Power (dBm)
NOTE: Typical power and efficiency is shown above. The devices were biased nominally at VDS = 5V, IDS = 50%
of IDSS, at a test frequency of 1.85 GHz. The test devices were tuned (input and output tuning) for maximum
output power at 1dB gain compression.
Typical Intermodulation Performance
VDS = 5V IDS = 50% IDSS at f = 1.85GHz
-23.00
20
3rds (dBc)
Output Power (dBm)
18
-28.00
16
-33.00
14
-38.00
3rd Order IM Products (dBc)
Pout (dBm)
12
10
-43.00
-7.1
-6.0
-5.0
-4.0
-3.0
-2.1
-1.0
0.0
1.0
1.9
Input Power (dBm)
Note:
pHEMT
devices have
enhanced
intermodulation performance. This yields OIP3
values of about P1dB + 14dBm. This IMD
enhancement is affected by the quiescent bias and
the matching applied to the device.
DC IV Curves FPD750SOT89
0.30
Drain-Source Current (A)
0.25
0.20
Note: The recommended method for measuring IDSS, or
any particular IDS, is to set the Drain-Source voltage (VDS)
at 1.3V. This measurement point avoids the onset of
spurious self-oscillation which would normally distort the
current measurement (this effect has been filtered from
the I-V curves presented above). Setting the VDS > 1.3V
will generally cause errors in the current measurements,
even in stabilized circuits.
VG=-1.50
VG=-1.25V
VG=-1.00V
VG=-0.75V
VG=-0.50V
VG=-0.25V
VG=0V
0.15
0.10
0.05
0.00
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Drain-Source Voltage (V)
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4.5
5.0
5.5
6.0
4
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Filtronic Compound Semiconductors Ltd
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Website: www.filtronic.com
FPD750SOT89
Datasheet v3.0
TYPICAL OUTPUT PLANE POWER CONTOURS (VDS = 5v, IDS = 50%IDSS):
FPD750SOT89 POWER CONTUORS 900MHz
2.
0
0.6
0.8
1.0
Swp Max
151
0.
4
0
3.
4.0
5.0
0.2
10.0
5.0
4.0
3.0
2.0
1.0
0.8
0.6
0.4
0
0.2
10.0
19dBm
25dBm
-10.0
20dBm
-0.2
21dBm
-5.0
24dBm
-4.0
22dBm
1850 MHz
Contours swept with a constant input power, set so that
optimum P1dB is achieved at the point of output match.
Input (Source plane) Γs:
Swp Min
1
-1.0
-0.8
-0.6
.0
-2
-3
.0
23dBm
.4
-0
900 MHz
Contours swept with a constant input power, set so that
optimum P1dB is achieved at the point of output match.
Input (Source plane) Γs:
0.79 ∠ 36.9º
1.0 + j 2.6(normalized)
50 + j130 Ω
Nominal IP3 performance is obtained with this input
plane match, and the output plane match as shown.
0.50 ∠ 142.8º
0.37 + j0.35 (normalized)
18.5 + j17.5 Ω
Nominal IP3 performance is obtained with this input
plane match, and the output plane match as shown.
TYPICAL SCATTERING PARAMETERS (50Ω SYSTEM):
FPD750SOT89 5V / 50%IDSS
4.
2.
0
6 GHz
10.0
10.0
5.0
4.0
3.0
2.0
1.0
0.8
0.6
0.4
0.2
0
10.0
4.0
5.0
3.0
2.0
1.0
0.8
0.6
0.4
4 GHz
3 GHz
-3
-1.0
-0 .8
6
.0
-2
S22
Swp Min
0.5GHz
-0
.
.0
-1.0
4
.0
-2
.0
-0 .8
.0
.
-0
-3
.0
-4
6
-5
.0
-0
.
1 GHz
.0
1 GHz
2
-4
-10. 0
1.5 GHz
2 GHz
- 0.
-5
0 .2
S11
0
-10. 0
4
7 GHz
5 GHz
2 GHz
.
-0
1.0
0 .8
0 .2
2
0
5.
2.5 GHz
- 0.
0
4.
10.0
3 GHz
0.2
3.
0
5.0
3.5 GHz
0
6
0.
2.
0
1.0
0. 8
6
0.
0.
4
.0
3
7 GHz
4 GHz
Swp Max
8GHz
0.
4
6 GHz
5 GHz
FPD750SOT89 5V / 50%IDSS
Swp Max
8GHz
Swp Min
0.5GHz
5
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FPD750SOT89
Datasheet v3.0
REFERENCE DESIGN (0.9GHZ):
FREQUENCY
GHZ
0.9
Gain
P1dB
OIP31
N.F.
S11
S22
Vd
Vg
Id
dB
dBm
dBm
dB
dB
dB
V
V
mA
23
23.5
35
0.6
-5
-20
5
-0.4 to -0.6
100
1. Measured at 10dBm per tone
Board Layout
Vg
Vd
33pF
0.01uF
33pF
20O
Lg
33pF
+ 1.0uF
+
Ld
Q1
L1
0.01uF
L2
33pF
0.63"
C2
C1
1.45"
Component Values
Component
Value
Description
Lg
56nH
LL1608 Toko chip inductor
Ld
56nH
LL1608 Toko chip inductor
L1
12nH
LL1608 Toko chip inductor
L2
6.8nH
LL1608 Toko chip inductor
C1
0.5pF
ATC 600S chip capacitor
FPD750SOT89 EVAL Board -Vg
Schematic
0.01uF
@ 0.9GHz
33pF
Vd
1.0uF
0.01uF
33pF
20 Ohm
33pF
56 nH
L1
RF IN
C2
1.2pF
ATC 600S chip capacitor
Eval board material - 31mil thick FR4 with 1/2 Ounce Cu on
both sides
C1
56 nH
L2
33pF
C2
D.C. Blocking capacitors are ATC series 600S. A tantalum 1.0µF is used at the drain terminal. All
other capacitors are 0603 and 0805 standard chip capacitors. A 0603 size 20 Ohm Chip resistor from
Vishay is used on the gate D.C. bias line for stability.
6
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RF OUT
FPD750SOT89
Datasheet v3.0
REFERENCE DESIGN (1.85GHZ):
FREQUENCY
GHZ
1.85
Gain
P1dB
OIP31
N.F.
S11
S22
Vd
Vg
Id
dB
dBm
dBm
dB
dB
dB
V
V
mA
17.2
24
35
0.7
-5
-10
5
-0.4 to -0.6
100
1. Measured at 10dBm per tone
Board Layout
Vg
Vd
+ 1.0uF
+
33pF
0.01uF
33pF
20O
Lg
33pF
Ld
Q1
C1
0.01uF
L2
33pF
0.63"
C2
L1
1.45"
Component Values
Component
Value
Description
Lg
27nH
LL1608 Toko chip inductor
Ld
27nH
LL1608 Toko chip inductor
L1
6.8nH
LL1005 Toko chip inductor
L2
1.8nH
LL1005 Toko chip inductor
C1
2.7pF
ATC 600S chip capacitor
FPD750SOT89 EVAL Board -Vg
Schematic
0.01uF
@ 1.85GHz
33pF
Vd
1.0uF
0.01uF
33pF
20 Ohm
33pF
C1
RF IN
C2
0.5pF
ATC 600S chip capacitor
Eval board material - 31mil thick FR4 with 1/2 Ounce Cu
on both sides
L1
27 nH
27 nH
L2
33pF
C2
RF OUT
D.C. Blocking capacitors are ATC series 600S. A tantalum 1.0µF is used at the drain terminal. All
other capacitors are 0603 and 0805 standard chip capacitors. A 0603 size 20 Ohm Chip resistor from
Vishay is used on the gate D.C. bias line for stability.
7
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Filtronic Compound Semiconductors Ltd
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Email: [email protected]
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FPD750SOT89
Datasheet v3.0
REFERENCE DESIGN (2.4GHZ TO 2.6GHZ):
Frequency
(GHz)
SSG (dB)
2.4
2.5
2.6
15.4
15.2
15.0
P1dB (dBm)
24.3
24.3
24.4
1
34.0
35.0
34.0
N.F. (dB)
0.95
0.95
1.0
S11 (dB)
-5.0
-5.5
-6.0
S22 (dB)
-9.5
-10.0
-10.0
OIP3 (dBm)
VD (V)
5
VG (V)
-0.4 to -0.6
ID (mA)
100
1. Measured at 10dBm per tone
Board Layout
Vg
Vd
33pF
0.01uF
33pF
20O
Lg
33pF
+ 1.0uF
+
Ld
Q1
C1
0.01uF
Tab
33pF
0.63"
C2
L1
1.45"
Component Values
Component
Value
Description
Lg
22nH
LL1608 Toko chip inductor
Ld
22nH
LL1608 Toko chip inductor
L1
8.2nH
LL1005 Toko chip inductor
C1
2.0pF
ATC 600S chip capacitor
C2
0.8pF
ATC 600S chip capacitor
FPD750SOT89 EVAL Board -Vg
Schematic
0.01uF
@2.4 to 2.6GHz
33pF
Vd
1.0uF
0.01uF
33pF
20 Ohm
33pF
C1
RF IN
Tab
Copper tab (no component)
Eval board material - 31mil thick FR4 with 1/2 Ounce Cu
on both sides
L1
22 nH
22 nH
C2
33pF
RF OUT
D.C. Blocking capacitors are ATC series 600S. A tantalum 1.0µF is used at the drain terminal. All
other capacitors are 0603 and 0805 standard chip capacitors. A 0603 size 20 Ohm Chip resistor from
Vishay is used on the gate D.C. bias line for stability.
8
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Filtronic Compound Semiconductors Ltd
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Email: [email protected]
Website: www.filtronic.com
FPD750SOT89
Datasheet v3.0
STATISTICAL SAMPLE OF RF PERFORMANCE:
Small Signal Gain
Noise Figure
18000
16000
6000
5000
12000
Frequency
10000
8000
6000
4000
4000
3000
2000
1000
2000
1.3
1.22
1.14
1.06
0.98
0.9
0.82
0.74
0.5
More
19.8
19
19.4
18.6
18.2
17.8
17
17.4
16.6
16.2
15.8
15
15.4
0.66
0
0
0.58
Frequency
14000
NF (dB)
SSG (dB)
Output Power at 1dB gain
Compression
10000
9000
8000
10000
7000
8000
Frequency
6000
4000
6000
5000
4000
3000
2000
2000
1000
24.8
40
38
37
35
34
32
31
29
P1dB (dBm)
28
0
25
24.2
23.6
23
22.4
21.8
21.2
20.6
20
0
26
Frequency
Output 3rd Order Intercept Point
OIP3 - (dBm)
Note: The devices were tested by a high-speed automatic test system, in a matched circuit based on an
Evaluation Board design. This circuit is a dual-bias single-pole low pass topology, and the devices were biased at
VDS = 4.0V, IDS = 100mA, Test frequency = 2.0GHz.
9
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Email: [email protected]
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FPD750SOT89
Datasheet v3.0
S-PARAMETERS: BIASED @ 5V, 50%IDSS:
FREQ[GHz]
S11m
S11a
S21m
S21a
S12m
S12a
S22m
S22a
0.050
0.300
0.550
0.800
1.050
1.300
1.550
1.800
2.050
2.300
2.550
2.800
3.050
3.300
3.550
3.800
4.050
4.300
4.550
4.800
5.050
5.300
5.550
5.800
6.050
6.300
6.550
6.800
7.050
7.300
7.550
7.800
8.050
8.300
8.550
8.800
9.050
9.300
9.550
9.800
10.050
10.300
10.550
0.998
0.959
0.868
0.809
0.755
0.713
0.679
0.653
0.634
0.62
0.613
0.603
0.611
0.614
0.619
0.627
0.636
0.659
0.663
0.666
0.68
0.695
0.706
0.719
0.732
0.741
0.754
0.766
0.779
0.793
0.809
0.823
0.839
0.851
0.86
0.871
0.881
0.889
0.895
0.904
0.913
0.909
0.903
-5.6
-30.9
-52.5
-72.3
-90.2
-106.5
-121.5
-135.6
-148.8
-161.8
-173.5
175.0
164.6
154.5
145.1
136.2
127.9
119.7
110.6
104.1
96.9
89.7
82.6
75.9
69.2
62.7
56.9
51.1
45.4
39.9
34.4
28.9
23.6
18.8
14.2
9.8
5.7
2.0
-1.5
-4.6
-8.3
-12.0
-15.2
19.465
16.931
15.126
13.452
12.024
10.762
9.707
8.828
8.080
7.441
6.890
6.407
5.948
5.557
5.194
4.873
4.594
4.345
4.138
3.892
3.690
3.511
3.342
3.190
3.041
2.898
2.766
2.634
2.507
2.387
2.267
2.151
2.036
1.925
1.825
1.728
1.640
1.563
1.494
1.433
1.384
1.323
1.264
172.4
154.5
137.7
124.3
112.1
101.4
91.8
82.7
74.1
66.0
58.1
50.2
43.0
35.7
28.7
21.9
15.4
8.8
1.8
-4.8
-11.0
-17.4
-23.7
-30.1
-36.5
-42.8
-49.1
-55.3
-61.6
-67.8
-73.9
-79.9
-85.7
-91.3
-96.7
-102.0
-106.9
-111.8
-116.6
-121.2
-126.5
-132.0
-136.8
0.003
0.016
0.028
0.038
0.046
0.052
0.057
0.062
0.066
0.069
0.073
0.076
0.078
0.080
0.082
0.084
0.085
0.086
0.089
0.090
0.091
0.092
0.093
0.094
0.095
0.096
0.096
0.095
0.095
0.095
0.093
0.092
0.091
0.089
0.087
0.084
0.083
0.082
0.081
0.080
0.078
0.075
0.074
94.4
77.5
64.7
55.2
47.2
40.7
35.1
29.2
24.3
19.4
14.9
10.5
6.0
2.2
-2.4
-6.0
-10.3
-13.3
-17.5
-21.4
-25.1
-29.2
-32.6
-36.8
-41.0
-45.1
-49.1
-53.0
-57.4
-61.4
-65.7
-70.0
-74.0
-78.3
-81.9
-85.5
-89.4
-93.9
-98.4
-101.8
-107.1
-111.9
-116.6
0.448
0.438
0.406
0.379
0.352
0.324
0.294
0.267
0.241
0.214
0.188
0.169
0.14
0.123
0.113
0.11
0.114
0.133
0.138
0.153
0.167
0.182
0.196
0.208
0.222
0.237
0.252
0.27
0.291
0.314
0.337
0.363
0.387
0.412
0.436
0.457
0.477
0.496
0.514
0.531
0.548
0.552
0.557
-8.1
-20.6
-37.7
-51.8
-64.3
-74.4
-83.0
-91.1
-98.8
-106.3
-115.6
-125.9
-140.7
-156.6
-175.2
164.9
146.6
132.4
115.2
107.8
99.7
92.6
85.4
78.5
71.6
65.0
58.0
51.3
44.6
38.5
33.2
28.4
24.3
20.3
17.1
14.0
11.0
8.6
6.0
3.1
-0.1
-3.6
-6.7
10
Tel: +44 (0) 1325 301111
Specifications subject to change without notice
Filtronic Compound Semiconductors Ltd
Fax: +44 (0) 1325 306177
Email: [email protected]
Website: www.filtronic.com
FPD750SOT89
Datasheet v3.0
PACKAGE OUTLINE:
(dimensions in millimeters – mm)
TAPE DIMENSIONS AND PART ORIENTATION:
FWYN
● Also available with horizontal
part orientation
● Hub diameter = 80mm
● Devices per reel = 1000
11
Tel: +44 (0) 1325 301111
Specifications subject to change without notice
Filtronic Compound Semiconductors Ltd
Fax: +44 (0) 1325 306177
Email: [email protected]
Website: www.filtronic.com
FPD750SOT89
Datasheet v3.0
DEVICE FOOT PRINT:
The device has a MSL rating of Level 2. To
determine this rating, preconditioning was
performed to the device per, the Pb-free solder
profile defined within IPC/JEDEC J-STD-020C,
Moisture / Reflow sensitivity classification for
non-hermatic solid state surface mount
devices.
APPLICATION NOTES & DESIGN DATA:
Application Notes and design data including Sparameters, noise parameters and device
model are available on request.
RELIABILITY:
Units in inches
A MTTF of 7.4 million hours at a channel
temperature of 150°C is achieved for the
process used to manufacture this device.
NOTE: Drawing available on Website
DISCLAIMERS:
PREFERRED ASSEMBLY INSTRUCTIONS:
This product is not designed for use in any
space based or life sustaining/supporting
equipment.
This package is compatible with both lead free
and leaded solder reflow processes as defined
within IPC/JEDEC J-STD-020C. The maximum
package temperature should not exceed
260°C.
ORDERING INFORMATION:
PART NUMBER
HANDLING PRECAUTIONS:
To avoid damage to
the
devices
care
should be exercised
during
handling.
Proper
Electrostatic
Discharge
(ESD)
precautions should be observed at all stages
of storage, handling, assembly, and testing.
DESCRIPTION
FPD750SOT89
Packaged pHEMT
FPD750SOT89E
Lead free Packaged pHEMT
RoHS Compliant Packaged pHEMT with
FPD750SOT89CE
enhanced passivation (Recommended for
New Designs)
ESD/MSL RATING:
These devices should be treated as Class 1A
(250-500 V) using the human body model as
defined in JEDEC Standard No. 22-A114.
EB750SOT89(E)-BB
0.9 GHz evaluation board
EB750SOT89(E)-BA
1.85 GHz evaluation board
EB750SOT89(E)-BC
2.0 GHz evaluation board
EB750SOT89(E)-BE
2.4 GHz evaluation board
EB750SOT89(E)-BG
2.6 GHz evaluation board
EB750SOT89(E)-AH
3.5 GHz evaluation board
EB750SOT89(E)-AJ
5.0 – 5.75 GHz evaluation board
12
Tel: +44 (0) 1325 301111
Specifications subject to change without notice
Filtronic Compound Semiconductors Ltd
Fax: +44 (0) 1325 306177
Email: [email protected]
Website: www.filtronic.com