Intersil ISL76534 14-channel gamma reference Datasheet

DATASHEET
Ultra-Low Power 14-Channel Programmable Gamma
Buffer with Integrated EEPROM
ISL76534
Features
The ISL76534 is a programmable gamma buffer for TFT-LCDs
featuring ultra-low power operation. The ISL76534 contains an
I2C programmable, 10-bit, 14-channel gamma reference
voltage generator with buffered outputs, a 10-bit
programmable VCOM calibrator, a high output current VCOM
amplifier, and internal EEPROM to store all reference voltage
data. The EEPROM features an endurance of 10,000 write
cycles and a data retention of 20 years at 105°C.
• 14-channel gamma references, 10-bit resolution with
buffered outputs
• 1-channel VCOM calibrator with 10-bit resolution
• High output current VCOM amplifier
• Ultra-low power operation, ideal for automotive displays:
Typical quiescent power, 12mW at 8V AVDD
• EEPROM data retention: 20 years at 105°C
• EEPROM endurance: 10,000 write cycles
- Read/write capable over 2.25V to 3.6V DVDD range
Combining gamma and VCOM reference voltage generators
with low power operation and EEPROM, the ISL76534 provides
a complete reference voltage solution ideal for TFT-LCD
displays.
• 6.3V to 19V analog supply operating range
• 2.25V to 3.6V digital supply operating range
The ISL76534 is available in a super thin (height = 0.4mm
maximum) 28 Ld 4mmx5mm X2QFN thermally enhanced
package. The device is specified for operation across the
ambient temperature -40°C to +105°C.
• Power Supply Rejection Ratio (PSRR): 75dB typical
• 28 Ld 4mmx5mm super thin X2QFN package
• Pb-free (RoHS compliant)
Applications
• AEC-Q100 qualified
• Automotive infotainment display
• Automotive Center Information Display (CID)
• Automotive smart mirrors
• Automotive instrument cluster display
• Automotive TFT-LCD display
GAMMA
T F T -L C D P A N E L
T IM IN G
CO NTRO L
(T C O N )
C O L U M N D R IV E R S
T F T -L C D S C R E E N
IS L 7 6 5 3 4
G A M M A B U F F E R (C O L U M N
D R IV E R D A C R E F E R E N C E
V O L T A G E S ), A N D V C O M
REFERENCES
V COM
C A L IB R A T O R
V COM
D R IV E R
DATA
L IN E
G A TE
D R IV E R S
STO RAGE
C A P A C IT O R
SELECT
L IN E
L C P IX E L
TFT
COMMON
(V C O M )
FIGURE 1. TYPICAL APPLICATION: TFT-LCD GAMMA REFERENCE VOLTAGE GENERATOR
July 27, 2016
FN8866.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL76534
Table of Contents
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
I2C Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
START and STOP Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Byte Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Acknowledge (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Not Acknowledge (NACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Address and R/W Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
12
12
12
12
13
13
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
ISL76534 Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Register Description and Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Word (WRITE/READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DAC Transfer Function of OUT1-OUT14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DAC Output Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DAC Reference Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DAC Channel Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCOM Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Protection (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Writing to the EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recalling The EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UVLO and Output Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Bypassing and Printed Circuit Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
19
19
19
19
19
19
20
20
20
20
20
21
21
21
21
21
General PowerPAD Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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FN8866.0
July 27, 2016
ISL76534
Block Diagram
AVDD
DVDD
REFIN
DAC/OUTx
BUFFER
ANALOG
POWER
SUPPLY
10
DIGITAL
POWER
SUPPLY
10
10
10
10
EEPROM
10
CONTROL
BYTE
10
14x10
DAC1
OUT1
DAC2
OUT2
DAC3
OUT3
DAC4
OUT4
DAC5
OUT5
DAC6
OUT6
DAC7
OUT7
DAC8
OUT8
DAC9
OUT9
DAC10
OUT10
DAC11
OUT11
DAC12
OUT12
DAC13
OUT13
DAC14
OUT14
RAM
10
A0
10
10
SCL
2
10
I C
INTERFACE
SDA
10
10
WP
10
WP: ACTIVE LOW
REFIN
10
DAC15
GND
AVDD_AMP
+
-
GND
OUTCOM
GND
INN_COM
VCOM DAC
VCOM AMPLIFIER
GND
FIGURE 2. BLOCK DIAGRAM
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FN8866.0
July 27, 2016
ISL76534
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
ISL76534ARXZ
76534 ARXZ
ISL76534EVAL1Z
Evaluation Board
TEMP. RANGE
(°C)
-40 to +105
PACKAGE
(RoHS COMPLIANT)
28 Ld X2QFN
PKG.
DWG. #
L28.4x5D
NOTES:
1. Add “-T13” suffix for 6k unit or “-T7A” suffix for 250 unit Tape and Reel options. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu-Ag plate
- e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL76534. For more information on MSL please see tech brief TB363.
Pin Configuration
AVDD_AMP
OUTCOM
GND
INN_COM
NC
GND
ISL76534
(28 LD 4mmx5mm X2QFN)
TOP VIEW
28
27
26
25
24
23
OUT1
1
22
OUT14
OUT2
2
21
OUT13
OUT3
3
20
OUT12
OUT4
4
19
OUT11
OUT5
5
18
OUT10
OUT6
6
17
OUT9
OUT7
7
16
OUT8
AVDD
8
15
DVDD
10
11
12
13
A0
GND
SCL
SDA
14
WP
9
REFIN
THERMAL
PAD
Note: Thermal pad is electrically connected to GND
Pin Descriptions
PIN NAME
1, 2, 3, 4, 5,
6, 7, 16, 17,
18, 19, 20,
21, 22
OUTx
Analog Output 10-bit Programmable DAC outputs
5
8
AVDD
Analog Power Analog power supply. Include a bulk 4.7µF capacitor, and a local 0.1µF ceramic bypass
capacitor to the system ground. Place the 0.1µF as close to the pin as possible; the bulk
capacitor may be placed farther away from the IC.
1
9
REFIN
Analog Input
High-impedance, buffered reference voltage input for 10-bit DACs. Include a local 0.1µF
ceramic bypass capacitor to the system ground; place as close to the pin as possible.
4
10
A0
Digital Input
Determines the device’s 7-bit I2C device address:
0: Device Address = 0x74 (this is the default setting if pin is left floating)
1: Device Address = 0x75 (pull-up pin externally)
Note: pin has an internal pull-down to GND of 10MΩ (typical)
2
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PIN TYPE
4
PIN FUNCTION
EQUIVALENT
CIRCUIT
PIN #
FN8866.0
July 27, 2016
ISL76534
Pin Descriptions (Continued)
PIN #
PIN NAME
PIN TYPE
11, 23, 26
GND
Power
12
SCL
Digital Input
13
SDA
Digital I/O
14
WP
Digital Input
15
DVDD
24
NC
25
INN_COM
27
OUTCOM
28
AVDD_AMP
-
THERMAL PAD
AVDD,
A VDD_AMP,
D VDD
EQUIVALENT
CIRCUIT
PIN FUNCTION
Ground
I2C clock (high impedance input)
3
I2C data (high impedance input/open-drain output)
3
I2C Write Protection, active low:
0: Prevent I2C data writes to internal DAC registers and EEPROM
(this is the default setting if pin is left floating)
1: Allow I2C data writes to internal DAC registers and EEPROM
(pull-up pin externally)
Note: pin has an internal pull-down to GND of 10MΩ (typical)
2
Digital Power Digital power supply. Include a local 0.1µF ceramic bypass capacitor to the system ground;
place as close to the pin as possible.
1
Not Connected Internally. Acceptable to leave pin floating.
Analog Input
VCOM amplifier inverting input
6
Analog Output VCOM amplifier output
7
Analog Power Analog power supply for VCOM amplifier. It is acceptable that AVDD_AMP is tied to AVDD, or
set to a lower voltage: AVDD_AMP ≤ AVDD. Include a bulk 4.7µF capacitor (or share with the
AVDD bulk), and a local 0.1µF ceramic bypass capacitor to the system ground. Place the
0.1µF as close to the pin as possible; the bulk capacitor may be placed farther away from
the IC.
1
GND
ACTIVE
CLAMP
Thermal pad. Electrically connected to GND (pins 11, 23, 26). Connect to ground plane on
PCB to maximize thermal performance.
DVDD
DVDD
WP, A0
SCL, SDA
0.5µA
SNAPBACK
GND
GND
GND
CIRCUIT 3
CIRCUIT 2
CIRCUIT 1
AVDD
AVDD
AVDD_AMP
OUT1-OUT14
REFIN
GND
INN_COM
GND
GND
CIRCUIT 6
CIRCUIT 5
CIRCUIT 4
AVDD_AMP
OUTCOM
GND
CIRCUIT 7
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FN8866.0
July 27, 2016
ISL76534
Absolute Maximum Ratings
Thermal Information
(TA = +25°C)
Supply Voltage
Between AVDD and GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +21V
AVDD_AMP to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVDD +0.3V
Between DVDD and GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V
Maximum Output Voltage
[OUT1-OUT14] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVDD
OUTCOM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .AVDD_AMP
SDA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+4.5V
Maximum Input Voltage
REFIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVDD
INN_COM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .AVDD_AMP
SCL, SDA, A0, WP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+4.5V
Maximum Continuous Output Current per Channel
OUT1-OUT14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA
OUTCOM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100mA
Maximum Total Output Current
OUT1-OUT14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±250mA
ESD Ratings
Human Body Model (Tested per AEC-Q100-002) . . . . . . . . . . . . . . . . 3kV
Machine Model (Tested per AEC-Q100-003) . . . . . . . . . . . . . . . . . . . 250V
Charged Device Model (Tested per AEC-Q100-011). . . . . . . . . . . . . . 2kV
Latch-up (Tested per AEC-Q100-004). . . . . . . . . . . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
28 Ld X2QFN (Notes 4, 5) . . . . . . . . . . . . . .
37
1.5
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See page 21
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Operating Range
AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3V to 19V
AVDD_AMP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to AVDD
DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25V to 3.6V
Reference Voltage Range
REFIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V to AVDD
Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
AVDD = AVDD_AMP = 15V, DVDD = 3.3V, REFIN = 14.75V, TA = +25°C, unless otherwise specified. Boldface limits
apply across the operating temperature range, -40°C to +105°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
MAX
(Note 6)
UNIT
6.3
19
V
TYP
SUPPLY
Analog Supply Voltage
AVDD
AVDD_AMP
4.5
AVDD
V
Digital Supply Voltage
Analog Supply Voltage for VCOM Amp
DVDD
2.25
3.6
V
Analog Supply Current
IAVDD
Digital Supply Current
IDVDD
DAC High Reference Voltage
VREFIN
UVLO
Undervoltage Lockout for AVDD
AVDD = 8V, no load
1.00
1.8
mA
AVDD_AMP = 8V, no load
0.40
0.75
mA
AVDD = 15V, no load
1.30
2.5
mA
AVDD_AMP = 15V, no load
0.60
1.2
mA
190
330
µA
AVDD
V
AVDD rising - OUTCOM, OUTx enabled
3.9
4.3
4.5
V
AVDD falling - OUTCOM, OUTx disabled
3.7
4.0
4.3
V
Hysteresis
200
330
500
mV
ANALOG
Highest Output Voltage for
OUT1-OUT14
VOH
Highest Output Voltage for
OUTCOM
Lowest Output Voltage for
OUT1-OUT14
VOL
Lowest Output Voltage for
OUTCOM
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REFIN = AVDD, DAC = 1023,
ILOAD = +5mA
REFIN - 0.150 REFIN - 0.100
V
REFIN = AVDD, DAC = 1023, AV = +1,
ILOAD = +5mA
REFIN - 0.100 REFIN - 0.050
V
DAC = 0, ILOAD = -5mA
GND + 0.085 GND + 0.150
V
DAC = 0, AV = +1, ILOAD = -5mA
GND + 0.050 GND + 0.100
V
FN8866.0
July 27, 2016
ISL76534
Electrical Specifications
AVDD = AVDD_AMP = 15V, DVDD = 3.3V, REFIN = 14.75V, TA = +25°C, unless otherwise specified. Boldface limits
apply across the operating temperature range, -40°C to +105°C. (Continued)
PARAMETER
MIN
(Note 6)
TYP
OUT1-OUT14: OUTx = 0.5*AVDD
AVDD varied from 14V to 16V
55
75
dB
OUTCOM: OUTCOM = 0.5*AVDD
AVDD_AMP varied from 14V to 16V
50
70
dB
DAC1 through DAC14
-2
0
2
LSB
DAC15 (OUTCOM)
-2
0
2
LSB
SYMBOL
Power Supply Rejection Ratio
PSRR
DAC Integral Non-Linearity
INL
TEST CONDITIONS
MAX
(Note 6)
UNIT
Input Leakage Current of REFIN
IL_REF
REFIN = 0.5*AVDD
-1
0
1
µA
Input Leakage Current of VCOM
Amplifier
IL_INN
VCOM Amplifier: INN = 0.5*AVDD
-1
0
1
µA
OUT1-OUT14: OUTx = VOH, OUTx short to
GND (source) through 10Ω
170
230
400
mA
OUT1-OUT14: OUTx = VOL, OUTx short to
AVDD (sink) through 10Ω
150
200
400
mA
VCOM Amplifier (OUTCOM):
OUTx = 0.5*AVDD_AMP, short to GND
(source) through 10Ω
400
530
700
mA
VCOM Amplifier (OUTCOM):
OUTx = 0.5*AVDD_AMP, short to
AVDD_AMP (sink) through 10Ω
450
570
750
mA
0
1.5
5
mV/mA
Short-Circuit Current
ISC
Load Regulation
REG
OUT1-OUT14: ILOAD = ±5mA step
OUTCOM: ILOAD = ±5mA step
0
1.5
5
mV/mA
Slew Rate
SR
OUT1-OUT14: Full-scale DAC code
change
2
5
40
V/µs
VCOM amplifier: AV = -1,
0.5V ≤ OUTx ≤ 5.5V, CL = 10pF to GND
4
10
40
V/µs
VCOM Amplifier Bandwidth
BW
Time to Load EEPROM Data to DAC
Registers at Power-ON
AV = -1, OUTx = 4V,
RL = 10kΩ || CL = 10pF to GND
tData_loading Start of EEPROM loading to when OUTx is
enabled, (Note 7)
5
MHz
6
ms
DIGITAL
Logic ‘1’ Input Voltage
VIH
SCL, SDA, A0, WP
Logic ‘0’ Input Voltage
VIL
SCL, SDA, A0, WP
I2C SCL Clock Frequency
fCLK
Input Leakage Current
IL
0.8*DVDD
V
0.2 * DVDD
V
400
kHz
0
1
µA
-1
0
1
µA
0.10
0.55
1
µA
(Note 8)
SCL, SDA, A0, WP: at GND
SCL, SDA: at DVDD
A0, WP: at DVDD
-1
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. The “tData_loading” parameter is determined by IC design, and simulation.
8. For more detailed information regarding I2C timing characteristics, refer to Table 1 on page 13.
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ISL76534
Typical Performance Curves TA = +25°C, unless otherwise specified.
1.50
2.0
1.8
-40°C
1.6
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
DVDD = 3.3V
+25°C
+105°C
1.4
1.2
1.0
0.8
1.30
AVDD = 15V
1.10
AVDD = 8V
0.90
0.6
0.70
-50
0.4
0
5
10
15
20
25
0
50
VDD (V)
750
1.0
AVDD = 3.3V
0.9
0.8
SUPPLY CURRENT (µA)
SUPPLY CURRENT (mA)
150
FIGURE 4. AVDD SUPPLY CURRENT vs TEMPERATURE
FIGURE 3. AVDD SUPPLY CURRENT vs VOLTAGE
0.7
0.6
0.5
0.4
0.3
+25°C
0.2
-40°C
0.1
+105°C
0.0
0
5
10
15
20
650
AVDD_AMP = 15V
550
450
AVDD_AMP = 8V
350
250
-50
25
0
50
100
150
TEMPERATURE (°C)
VDD (V)
FIGURE 5. AVDD_AMP SUPPLY CURRENT vs VOLTAGE
FIGURE 6. AVDD_AMP SUPPLY CURRENT vs TEMPERATURE
300
250
230
+25°C
210
+105°C
190
-40°C
NO LOAD ON OUTPUT
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
100
TEMPERATURE (°C)
170
150
130
110
90
250
200
DVDD = 3.3V
150
100
70
50
2.2
2.6
3
3.4
3.8
4.2
SUPPLY VOLTAGE
FIGURE 7. DVDD SUPPLY CURRENT vs VOLTAGE
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4.6
50
-50
0
50
100
150
TEMPERATURE (°C)
FIGURE 8. DVDD SUPPLY CURRENT vs TEMPERATURE
FN8866.0
July 27, 2016
ISL76534
Typical Performance Curves TA = +25°C, unless otherwise specified. (Continued)
AVDD = 15V
DVDD = 3.3V
VREF = 14.75V
OUTPUT (V)
CODE = x341
CODE = x3FF
CODE = x3FF
CODE = x341
AVDD = 15V
DVDD = 3.3V
VREF = 14.75V
CODE = x22B
OUTPUT (V)
5V/DIV
5V/DIV
0V
0V
CODE = x22B
CODE = x115
CODE = x115
2µs/DIV
2µs/DIV
FIGURE 9. OUT1-OUT14 POSITIVE SLEW RATE (DAC CODE CHANGE)
FIGURE 10. OUT1-OUT14 NEGATIVE SLEW RATE (DAC CODE CHANGE)
OUTPUT (V)
OUTPUT (V)
5V/DIV
5V/DIV
AVDD = AVDD_AMP = 15V
DVDD = 3.3V
0V
0V
AVDD = AVDD_AMP = 15V
DVDD = 3.3V
REFIN = 14.75V
REFIN = 14.75V
2µs/DIV
2µs/DIV
FIGURE 11. VCOM AMPLIFIER POSITIVE SLEW RATE
FIGURE 12. VCOM AMPLIFIER NEGATIVE SLEW RATE
15.0
20
AVDD_AMP = 15V
DAC15 = 4V
DACx = 0x3FF (SOURCING)
14.0
10
CL = 480pF
VOLTAGE (V)
GAIN (dB)
OUTCOM
14.5
CL = 10pF
0
OUT1-OUT4
13.5
REFIN = AVDD = AVDD_AMP
1.5
1.0
-10
DACx = 0x000(SINKING)
0.5
-20
OUT1-OUT4
OUTCOM
0.0
100k
1M
FREQUENCY (Hz)
10M
FIGURE 13. VCOM AMPLIFIER BANDWIDTH vs CAPACITIVE LOADING
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0
10
20
30
40
CURRENT (mA)
50
60
FIGURE 14. OUT1-OUT14 AND OUTCOM OUTPUT VOLTAGE vs OUTPUT
CURRENT (VOH AND VOL)
FN8866.0
July 27, 2016
ISL76534
Typical Performance Curves TA = +25°C, unless otherwise specified. (Continued)
0.10
0.8
TYPICAL PRODUCTION UNIT
AVDD = REFIN = 15V
DVDD = 3.3V
0.06
0.4
NO LOAD
0.04
0.08
DNL (LSB)
LINEARITY (LSB)
1.2
0.0
-0.4
0.02
0.00
-0.02
-0.04
TYPICAL PRODUCTION UNIT
AVDD = REFIN = 15V
-0.06
-0.8
DVDD = 3.3V
NO LOAD
-0.08
-1.2
-0.10
0
128
256
768
896
1024
0
128
256
384
512
640
768
896
1024
DAC CODE (DEC)
FIGURE 15. DAC1-DAC15 INL (REFIN = AVDD = 15V) AT +25°C
FIGURE 16. DAC1-DAC15 DNL (REFIN = AVDD = 15V) AT +25°C
1.2
0.10
TYPICAL PRODUCTION UNIT
AVDD = REFIN = 15V
0.8
0.08
0.06
DVDD = 3.3V
0.4
0.04
NO LOAD
DNL (LSB)
LINEARITY (LSB)
384
512
640
DAC CODE (DEC)
0.0
-0.4
0.02
0.00
-0.02
-0.04
TYPICAL PRODUCTION UNIT
AVDD = REFIN = 15V
-0.06
-0.8
DVDD = 3.3V
-0.08
-1.2
NO LOAD
-0.10
0
128
256
384
512
640
768
896
1024
0
128
256
DAC CODE (DEC)
FIGURE 17. DAC1-DAC15 TYPICAL INL (REFIN = AVDD = 15V) AT -40°C
384
512
640
DAC CODE (DEC)
768
896
1024
FIGURE 18. DAC1-DAC15 TYPICAL DNL (REFIN = AVDD = 15V) AT -40°C
0.10
1.2
0.08
0.06
0.04
0.4
DNL (LSB)
LINEARITY (LSB)
0.8
0.0
-0.4
TYPICAL PRODUCTION UNIT
AVDD = REFIN = 15V
-0.8
DVDD = 3.3V
256
384
512
640
DAC CODE (DEC)
10
DVDD = 3.3V
-0.08
NO LOAD
-0.10
768
896
1024
FIGURE 19. DAC1-DAC15 INL (REFIN = AVDD = 15V) AT +105°C
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TYPICAL PRODUCTION UNIT
AVDD = REFIN = 15V
-0.06
-1.2
128
0.00
-0.02
-0.04
NO LOAD
0
0.02
0
128
256
384
512
640
768
896
1024
DAC CODE (DEC)
FIGURE 20. DAC1-DAC15 DNL (REFIN = AVDD = 15V) AT +105°C
FN8866.0
July 27, 2016
ISL76534
Typical Performance Curves TA = +25°C, unless otherwise specified. (Continued)
DVDD = 3.3V
AVDD = 15V
AVDD = 15V
VREF = 14.75V
CH1 = 5V/DIV
CH2 = CH3 = CH4 = 2V/DIV
OUT14 = 12V
DVDD = 3.3V
VREF = 14.75V
OUT14 = 12V
CH1 = 5V/DIV
CH2 = CH3 = CH4 = 2V/DIV
OUT7 = 8V
OUT7 = 8V
OUT1 = 2V
OUT1 = 2V
2ms/DIV
100µs/DIV
FIGURE 21. OUT1-OUT7-OUT14 AT POWER-ON
FIGURE 22. OUT1-OUT7-OUT14 AT POWER-ON (ZOOMED IN)
JEDEC JESD51-7 - HIGH EFFECTIVE THERMAL
CONDUCTIVITY (4-LAYER) TEST BOARD
QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5
JEDEC JESD51-3 (2-LAYER) TEST BOARD
2.0
4
POWER DISSIPATION (W)
POWER DISSIPATION (W)
5
3.38W
3
X2QFN28
+37°C/W
2
1
1.6
1.36W
1.2
X2QFN28
+92°C/W
0.8
0.4
0.0
0
0
25
50
75
100
125
AMBIENT TEMPERATURE (°C)
FIGURE 23. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE (4-LAYER BOARD)
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150
0
25
50
75
100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 24. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE (2-LAYER BOARD)
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July 27, 2016
ISL76534
General Description
START and STOP Condition
All I2C communication begins with a START condition, indicating
the beginning of a transaction, and ends with a STOP condition,
signaling the end of the transaction.
The Voltage/Transmission (V/T) transfer curve or gamma curve
of LCD panels require adjustment to achieve the desired optimal
visual response (often called gamma correction).
A START condition is signified by a HIGH to LOW transition on the
Serial Data line (SDA) while the Serial Clock Line (SCL) is HIGH. A
STOP condition is signified by a LOW to HIGH transition on the
SDA line while SCL is HIGH. See timing specifications in Table 1.
The ISL76534 has a total of 15 channels (14xgamma channels +
1xVCOM channel) independent, programmable reference voltage
outputs whose output voltage can be set with 10-bit resolution. The
ISL76534 has integrated EEPROM to store all gamma and VCOM
data.
The master always initiates START and STOP conditions. After a
START condition, the bus is considered “busy.” After a STOP
condition, the bus is considered “free.” The ISL76534 also
supports repeated STARTs, where the bus will remain busy for
continued transaction(s).
In addition to the 14-channel gamma DACs, the ISL76534
provides a VCOM calibrator DAC with 10-bit resolution and a high
output current operational amplifier to drive the VCOM voltage
also required by the LCD panel.
Byte Format
I2C Digital Interface
Every byte on the SDA must be 8 bits in length. After every byte of
data sent by the transmitter, there must be an acknowledge bit
(from the receiver) to signify that the previous 8 bits were
transferred successfully. Data is always transferred on the SDA
with the Most Significant Bit (MSB) first. If the data is larger than
8 bits then it can be separated into multiple 8-bit bytes. See
“Data Word (WRITE/READ)” on page 19.
The ISL76534 uses a standard I2C interface bus for
communication. The two-wire interface links a master(s) and
uniquely addressable slave devices. The master generates clock
signals and is responsible for initiating data transfers. The serial
clock is on the SCL line and the serial data (bidirectional) is on
the SDA line. The ISL76534 supports clock rates up to 400kHz
(fast-mode), and is backwards compatible with standard 100kHz
clock rates (standard-mode).
Acknowledge (ACK)
Each 8-bit data transfer is followed by an Acknowledge (ACK) bit
from the receiver. The Acknowledge bit signifies that the previous
8 bits of data was transferred successfully (master-slave or
slave-master).
The SDA and SCL lines must be HIGH when the bus if free - not in
use. An external pull-up resistor (typically 2.2kΩto4.7kΩ) or
current source is required for SDA and SCL.
The ISL76534 meets standard I2C timing specifications; see
Figure 25 and Table 1, which show the standard timing
definitions and specifications for I2C communication.
When the master sends data to the slave (e.g. during a WRITE
transaction), after the 8th bit of a data byte is transmitted, the
master tri-states the SDA line during the 9th clock. The slave
device acknowledges that it received all 8 bits by pulling down
the SDA line, generating an ACK bit.
Data Validity
The data on the SDA line must be stable (clearly defined as HIGH
or LOW) during the HIGH period of the clock signal. The state of
the SDA line can only change when the SCL line is low (except to
create a START or STOP condition). See timing specifications on
Table 1 on page 13.
When the master receives data from the slave (e.g. during a data
READ transaction), after the 8th bit is transmitted, the slave tri-states
the SDA line during the 9th clock. The master acknowledges that it
received all 8 bits by pulling down the SDA line, generating an ACK bit.
The voltage levels used to indicate a logical ‘0’ (LOW) and logical
‘1’ (HIGH) are determined by the VIL and VIH thresholds,
respectively; see the “Electrical Specifications” table on page 6.
tBUF
VIH
SDA
VIL
tr
tHD:STA
tSU:STA
tr
tf
tf
tSU:STO
VIH
SCL
VIL
START
tSU:DAT
tHD:DAT
STOP
START
FIGURE 25. I2C TIMING DEFINITIONS
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ISL76534
TABLE 1. I2C TIMING CHARACTERISTICS
FAST-MODE
PARAMETER
SCL Clock Frequency
STANDARD-MODE
SYMBOL
MIN
MAX
MIN
MAX
UNIT
fSCL
0
400
0
100
kHz
Set-Up Time for a START Condition
tSU:STA
0.6
4.7
µs
Hold Time for a START Condition
tHD:STA
0.6
4.0
µs
Set-Up Time for a STOP Condition
tSU:STO
0.6
4.0
µs
tBUF
1.3
4.7
µs
Data Set-Up Time
tSU:DAT
100
250
ns
Data Hold Time
tHD:DAT
0
0
µs
Rise Time of SDA and SCL (Note 9)
tr
20 + 0.1Cb
300
1000
ns
Fall Time of SDA and SCL (Note 9)
tf
20 + 0.1Cb
300
300
ns
Bus Free Time between a STOP and START Condition
NOTE:
9. Cb = total capacitance of one bus line in pF
Not Acknowledge (NACK)
A Not Acknowledge (NACK) is generated when the receiver does
not pull down the SDA line during the acknowledge clock (i.e.,
SDA line remains HIGH during the 9th clock). This indicates to the
master that it can generate a STOP condition to end the
transaction and free the bus.
A NACK can be generated for various reasons, for example:
• After an I2C device address is transmitted, there is NO receiver
with that address on the bus to respond.
• The receiver is busy performing an internal operation (e.g.
reset, recall, etc.), and cannot respond.
• The master (acting as a receiver) needs to indicate the end of a
transfer with the slave (acting as a transmitter).
Device Address and R/W Bit
Data transfers follow the format shown in Figures 26 through 27.
After a valid START condition, the first byte sent in a transaction
contains the 7-bit device (slave) Address plus a direction (R/W)
bit. The Device Address identifies which device (of up to 127
devices on the I2C bus) the master wishes to communicate with.
After a START condition, the ISL76534 monitors the first 8 bits
(Device Address byte) and checks for it is 7-bit Device Address in
the MSBs. If it recognizes the correct Device Address it will ACK,
and becomes ready for further communication. If it does not see
it is Device Address, it will sit idle until another START condition is
issued on the bus.
To access the ISL76534 DACs, the Device Addresses allowed are
0x74 hex (1110100x), or 0x75 hex (1110101x). The first 6 bits (b7
to b2, MSBs) of the 7-bit device address have been factory
programmed and are always 111010. Only the least significant bit
of the Device Address (bit b1, LSB) is allowed to change. The value of
the LSB (bit b1) is set by the hardware “A0” pin. When A0 = HIGH,
the device will only respond to a Device Address of 0x75. When
A0 = LOW, the device will only respond to a Device Address of 0x74.
This allows for two ISL76534 devices to be used on the same I2C
bus, each with a different Device Address.
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Note: The eighth bit of the Device Address byte (bit b0) indicates
the direction of transfer, READ or WRITE (R/W). A “0” indicates a
WRITE operation- the master will transmit data to the ISL76534
(receiver). A “1” indicates a Read operation- the master will
receive data from the ISL76534 (transmitter).
Application Information
ISL76534 Communication Protocol
The ISL76534 allows the user to sequentially read or write all the
registers with a single multi-byte I2C READ or WRITE operation
(“Burst Mode”).
The ISL76534 also allows the user to READ or WRITE to a specific
register only (or a specific range of registers), using Register Pointer
addressing (“Register Mode”). With Register Mode, a specific VCOM
value, Gamma DAC value or range of values may be read or written
without having to read or write the other registers.
Register Description and Pointer
Table 2 contains a detailed register description. All registers
contain 10 bits, which span over two data bytes (16 bits) and the
data is latched-in after the 16th bit (LSB) is received. The only
exception is the Control Register, where the data is latched in
after the first 8 bits are received.
Reading/writing always begins at location specified by the Register
Pointer. The Register Pointer automatically increments by 0x01 with
every two bytes transferred. For example, when using Register
Pointer 0x01 to address DAC1 (MSB and LSB), the device
automatically increments the pointer to 0x02, 0x03... after every
two data bytes are received. This enables Burst Mode operation
where only the first Register Pointer for a given sequence of
registers is needed.
To address separate or non-sequential register locations, a full
I2C START, Device Address, Register Pointer, Data..., STOP
sequence must be used to address each register location; see
“WRITE TRANSACTION” on page 15.
The Control Register is located at Register Pointer 0x00, while
the 10-bit DAC data is at Register Pointers 0x01 though 0x0F.
FN8866.0
July 27, 2016
ISL76534
TABLE 2. REGISTER DESCRIPTION
REGISTER
POINTER
0x00
REGISTER
BIT(S)
Control Byte
15:14 Reserved
(data latched in after each byte, b[15:8]
13:12 Reserved
and b[7:0], is received by I2C)
11
0x01 ~ 0x0F
FUNCTION NAME
Gamma Data
Output Enable (active low)
Reserved
Set to 0
Set to 0
0: Outputs Enabled, default at power-ON
1: Outputs Disabled
10:9 Recall EEPROM
00: Normal Operation
11: When Register Pointer 0x00 = 0x06; “Software
Reset.” Recalls stored EEPROM data to DAC registers.
Device will NACK during the 9th SCL pulse when a Reset
command is issued.
8:0
Reserved
Set to 0
15
Reserved
Set to 0
14
Write EEPROM
0: Write data to DAC only
1: Write data to DAC and EEPROM
13:10 Reserved
0x10 ~ 0xFF
DESCRIPTION
Set to 0
9:0
DAC data
10-bit data for DACs 1 through 15
15:0
Reserved
Do not write data to these registers
NOTES:
10. Any Register Pointers not indicated in Table 2 are Reserved Registers, and should not be used.
11. A write to an EEPROM register can take up to 35ms to complete. To avoid errors and ensure correct EEPROM data, any writes to EEPROM registers
should be spaced at least 35ms apart. For more information, refer to “Writing to the EEPROM” on page 20.
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ISL76534
Write Operation
Table 3 describes a write operation and Figures 26 and 27 shows
the write timing diagram.
TABLE 3. WRITE TRANSACTION
I2C DATA
I2C DATA
FROM MASTER
FROM ISL76534
NOTES
I2C START Signal
START
0xE8 or 0xEA
ACK
Send Device Address + R/W bit (depends on the state of A0 pin)
1110100 + 0, if A0 = LOW
1110101 + 0, if A0 = HIGH
Register Pointer
ACK
Register Pointer indicating starting register location to write to.
Register Pointer = 0x00 for Control Byte
Register Pointer = 0x01 for DAC 1 MSB/LSB data
Register Pointer = 0x02 for DAC 2 MSB/LSB data
...
Register Pointer = 0x0E for DAC 14 MSB/LSB data
Register Pointer = 0x0F for DAC 15 MSB/LSB data
For more information on the Register Pointer see Table 2 on page 14.
Byte 1
ACK
If Register Pointer = 0x00, Byte 1 is the Control Byte. When Register Pointer = 0x00 and Byte 1 = 0x06,
data is recalled from EEPROM and written into the DAC registers (RAM).
If Register Pointer = 0x01 or more, Byte 1 is the MSB byte of the DAC word
Byte 2
ACK
If Register Pointer = 0x00, Byte 2 is a null byte and will be ignored
If Register Pointer = 0x01 or more, Byte 2 is the LSB of the DAC word
Byte 3
ACK
MSB of DAC (1 + Register Pointer). Ex) Register Pointer = 0x00, MSB of DAC1
Byte 4
ACK
LSB of DAC (1 + Register Pointer). Ex) Register Pointer = 0x00, LSB of DAC1
Byte 5
ACK
MSB of DAC (2 + Register Pointer)
Byte 6
ACK
LSB of DAC (2 + Register Pointer)
...
...
I2C STOP Signal
STOP
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The WRITE operation can be stopped at any time after a register has been written. The DAC channel output
is updated after ALL 10-bit channel data is received.
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ISL76534
Write Timing Diagrams
START DEVICE ADDRESS W
SDA
(FROM MASTER)
7 6 5 4 3 2 1 0
SDA
START of
(FROM SLAVE)
WRITE
SDA
(FROM SLAVE)
SCL
(FROM MASTER)
DATA M (LSB)
DATA M+1 (MSB)
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
A
A
A
A
7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A
SDA
(FROM MASTER)
END of
WRITE
7 6 5 4 3 2 1 0
A
SCL
(FROM MASTER)
DATA M (MSB)
REGISTER POINTER
DATA M+1 (LSB)
DATA M+2 (MSB)
DATA M+2 (LSB)
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
A
A
A
NOTE: A WRITE transaction may be stopped
at any time, after the 2-byte (10-bit) DAC data
is sent, by issuing a STOP condition
STOP
A
A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A
FIGURE 26. WRITE DATA BYTES
START
SDA
(FROM MASTER)
DEVICE ADDRESS W
REGISTER POINTER
DATA
STOP
7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0
SOFTWARE
SDA
RESET (FROM SLAVE)
A
SCL
(FROM MASTER)
A
A
NOTE: Data in the EEPROM is
automatically loaded into the DAC
registers when the device is
powered-ON.
This I2C command for software
reset will recall the EEPROM data
anytime after initial power-ON.
7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A
FIGURE 27. RECALL DATA FROM EEPROM (SOFTWARE RESET)
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ISL76534
Read Operation
Table 4 describes a Read operation and Figure 28 shows the
read timing diagram.
TABLE 4. READ TRANSACTION
I2C DATA
I2C DATA
FROM MASTER
FROM ISL76534
NOTES
I2C START Signal
START
0xE8 or 0xEA
ACK
Send Device Address + R/W Bit (depends on the state of A0 pin)
1110100 + 0, if A0 = LOW
1110101 + 0, if A0 = HIGH
Register Pointer
ACK
Register Pointer indicating starting register location to write to.
Register Pointer = 0x00 for Control Byte
Register Pointer = 0x01 for DAC 1 MSB/LSB data
Register Pointer = 0x02 for DAC 2 MSB/LSB data
...
Register Pointer = 0x0E for DAC 14 MSB/LSB data
Register Pointer = 0x0F for DAC 15 MSB/LSB data
For more information on the Register Pointer see Table 2 on page 14.
STOP
I2C STOP signal
START
I2C START signal
0xE9
ACK
Send Device Address + R/W Bit
1110100 + 1
0xE9 or 0xEB
ACK
Send Device Address + R/W Bit (depends on the state of A0 pin)
1110100 + 1, if A0 = LOW
1110101 + 1, if A0 = HIGH
ACK
Byte 1
If Register Pointer = 0x00, Byte 1 is a Null Byte
If Register Pointer = 0x01 or more, Byte 1 is the MSB byte of the DAC word
...
ACK
Byte 2
If Register Pointer = 0x00, Byte 2 is a Null Byte
If Register Pointer = 0x01 or more, Byte 2 is the LSB byte of the DAC word
...
ACK
Byte 3
MSB of DAC (1 + Register Pointer). Ex) Register Pointer = 0x00, MSB of DAC1
ACK
Byte 4
LSB of DAC (1 + Register Pointer). Ex) Register Pointer = 0x00, LSB of DAC1
ACK
Byte 5
MSB of DAC (2 + Register Pointer)
ACK
Byte 6
LSB of DAC (2 + Register Pointer)
...
...
NAK
DAC 15 LSB
8 LSBs of DAC 15’s 10-bit value: dddd dddd
I2C STOP Signal
STOP
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The READ operation can be stopped at any time after a register has been read
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ISL76534
Read Timing Diagram
START DEVICE ADDRESS W
SDA
(FROM MASTER)
A
SCL
(FROM MASTER)
START
DATA M (MSB)
DATA M (LSB)
7 6 5 4 3 2 1 0
DATA M+1 (MSB)
A
A
DATA M+1 (LSB)
A
A
Note: If REGISTER POINTER = 0x00:
Byte 1 is NULL, Byte 2 is NULL
A
SCL
(FROM MASTER)
7 6 5 4 3 2 1 0
A
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A
DATA M+2 (MSB)
SCL
(FROM MASTER)
A
DEVICE ADDRESSR
SDA
START OF
(FROM SLAVE)
READ
SDA
(FROM SLAVE)
Note: Send register pointer first to
indicate the READ-back starting location
7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A
SDA
(FROM MASTER)
END OF
READ
STOP
7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A
WRITE
SDA
REGISTER
(FROM SLAVE)
POINTER
SDA
(FROM MASTER)
REGISTER POINTER
DATA M+2 (LSB)
A
A
STOP
A
(No ACK)
7 6 5 4 3 2 1 0
Note: MSB Byte bits b7:b2
will always READ-back zero
7 6 5 4 3 2 1 0
A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A
NOTE: The READ operation can be stopped at any time after the DAC register data has been read by sending a STOP condition.
FIGURE 28. READ TIMING DIAGRAM
TABLE 5. DAC CALCULATION
b15
b14
b13
9
b12
b11
8
b10
7
6
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
0
1
1
1
0
1
0
1
0
5
4
3
2
1
0
2  1 + 2  0 + 2  1 + 2  1 + 2  1 + 2  0 + 2  1 + 2  0 + 2  1 + 2  0
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ISL76534
Data Word (WRITE/READ)
Data Words contain the data written or read from the
10-bit DACs. Each 10-bit DAC data is transmitted in one word
(e.g. two bytes, 16-bits), as shown in Table 5. Bits [b9:b0]
represent the 10-bit data. Bits [b15:b10] are “do not cares” and
will default to zero when reading data, however, when writing
data bit b14 indicates the type of write. If b14 = ‘0’: WRITE data
to the DAC register; if b14 = ‘1’: WRITE data to the DAC and
EEPROM (program).
For any DAC, the first data byte of the word is called the Upper
Byte (or MSB), and the two LSBs of this byte represent the MSBs
of the 10-bit data, [b9:b8]. The second data byte of the word, or
Lower Byte (LSB), contains the remaining 8-bits (LSBs) of the
10-bit DAC data, [b7:b0]. These data words provide the DAC
values that ultimately determine the output voltages of the
ISL76534.
Refer to Table 2 for more information about the byte structure,
and refer to the following sections for information about the
expected DAC output voltage.
DAC Transfer Function of OUT1-OUT14
Equation 1 shows the transfer function for each 10-bit DAC
channel (expected output voltage). The transfer function relates
the REFIN voltage and a DAC_CODE to a DAC output voltage,
“VOUT.” The DAC_CODE is the decimal value of the 10-bit data
written to a given DAC channel.
DAC_CODE
V OUT = REF IN  ---------------------------------1024
(EQ. 1)
gamma calibration methods. Ensuring accurate gamma
references is also important for optimizing pixel/panel reliability.
DAC Reference Voltage
The REFIN pin is the reference voltage input for the 10-bit DACs. It
is a high impedance input. The voltage can be set using an
external resistor divider, regulated voltage, or tied directly to the
AVDD power rail. The REFIN pin should always be well bypassed to
minimize noise, and provide the best DAC performance. Use a
0.1µF ceramic capacitor (to GND), placed as close to the pin as
possible.
See example of the typical application circuits in Figures 30 and
31.
DAC Channel Outputs
The DAC output buffers are optimized to drive rail-to-rail for
optimal flexibility. Generally, in a TFT-LCD half of the required
gamma reference voltages will lie between VCOM and AVDD (or
REFIN), and the other half will lie between VCOM and GND. For
maximum flexibility, all ISL76534 outputs (OUT1-OUT14) can
drive to within 100mV of REFIN (AVDD = REFIN) and to within
85mV of GND (with ±5mA load). See “Electrical Specifications”
table on page 6 for more details about output channel
capabilities.
Each DAC is updated as soon as the entire 10-bit value for that
DAC is received via I2C. DAC data is latched, and the respective
DAC responds, on the falling edge of the 8th SCL clock (which
corresponds to the DAC LSB data bit, bit b0).
DAC_CODE: 0 ~ 1023
VCOM Amplifier
Example calculation to find the expected VOUT:
The ISL76534 VCOM amplifier is capable of rail-to-rail output
swings and the ability to drive highly capacitive loads. It can
source/sink up to 100mA of continuous current and over 500mA
of peak current. The output capability of the VCOM amplifier is
described in detail in “Electrical Specifications” table on page 6.
A VDD = 15V
REF IN = 14.75V
14.75V
1LSB = ------------------- = 14.40mV
1024
V OUT = 14.40mV  DAC_CODE
The VCOM amplifier is powered from a separate power supply
than the rest of the IC, called AVDD_AMP. This allows AVDD_AMP
to be set at a voltage lower than AVDD, to save system power.
Though it is acceptable to set AVDD_AMP = AVDD.
V OUT  DAC_CODE = 512  = 14.40mV  512 = 7.375V
DAC Output Accuracy
The relationship between the actual/measured DAC output
voltage and the expected voltage is the “Output Accuracy”
(OUTAC). Equation 2 shows how to determine output accuracy:
OUT AC = V OUT  exp ected  – V OUT  measured 
(EQ. 2)
The ISL76534 features are very good and have consistent output
accuracy across all DAC codes and REFIN voltages, ±15mV
(typical). Some competitor devices have diverging accuracy
performance near the high rail and have significantly larger
output accuracy variances compared to ISL76534.
The output accuracy performance of the ISL76534 provides
highly accurate reference voltages ideal for TFT-LCD applications.
This is important in TFT-LCD applications that require the
DACs/EEPROM to be programmed with the same digital codes
(e.g. gamma references determined from gamma calibration) on
a production line, and especially when using reflected code
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AVDD_AMP is not required for the rest of the IC to operate, so if
an application is not utilizing the VCOM Amplifier in the ISL76534
(OUTCOM), then AVDD_AMP can be tied to GND to disable the
function and save IC and system power. If AVDD_AMP is powered
but not connected in the application, then the VCOM amplifier
should be set in a buffer (AV = +1) configuration (INN_COM tied
to OUTCOM). See example typical application circuits in
Figures 30 and 31.
The device offers access to the inverting pin of the amplifier,
INN_COM, which enables various types of circuit configurations
depending on the requirements of the TFT-LCD panel
architecture. Most common applications either buffer the
amplifier for direct driving and response (INN_COM tied to
OUTCOM), or they may utilize feedback from the TFT-LCD panel
as an input to the INN_COM pin.
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ISL76534
Output Stability
OUT1-OUT14 AND OUTCOM BEHAVIOR
The ISL76534 outputs are designed to drive capacitive loads,
such as in TFT-LCD panel. However, purely capacitive loads
should not exceed 1nF without appropriate external load
isolation and/or amplifier compensation.
During the EEPROM writing/programming cycle the ISL76534
gamma outputs (OUT1-OUT14) and VCOM amplifier output
(OUTCOM) remain enabled.
As load capacitance increases, the -3dB bandwidth will decrease
and peaking can occur. Depending on the application, it may be
necessary to reduce peaking and improve device stability. To do
this, a snubber circuit (compensation) or a series resistor
(isolation) may be added to the output of the ISL76534.
A snubber is a shunt load consisting of a resistor in series with a
capacitor. An optimized snubber can improve the phase margin
and the stability of the ISL76534 by adding a zero in the loop
response. The advantage of a snubber circuit is that it does not
draw any DC load current or reduce the gain.
Recalling The EEPROM
There are two ways to initiate a recall of the stored EEPROM data:
• Automatic recall - Power cycle (or power-ON) the device
• Manual recall - Perform a “software reset” using I2C
The recall operation will overwrite all current DAC register values
with the values stored in EEPROM.
AUTOMATIC RECALL
Another method to reduce peaking is to add a series output
resistor (typically between 1Ω to 10Ω). Depending on the
capacitive loading, a small value resistor may be the most
appropriate choice to minimize any reduction in gain.
When the device is powered-ON, the ISL76534 automatically
recalls the EEPROM data and loads it into the DAC registers
(RAM) after DVDD reaches ~2.2V. The time for the EEPROM recall
to complete is the “tData_loading” time and is 6ms (typical) by
design. This operation restores all DAC registers to the values
stored in EEPROM.
Write Protection (WP)
MANUAL RECALL
The ISL76534 has an I2C write protection (WP) pin. WP is a logic
level input pin and is active low.
• WP = 0 (LOW): Protected, device ignores I2C data writes to the
internal DAC registers and EEPROM
• WP = 1 (HIGH): Not Protected, device allows I2C data writes to
the internal DAC registers and EEPROM
Whether WP is set HIGH or LOW, the device will ACK to proper I2C
commands, however, when WP = LOW the device internally
ignores the data bytes.
The logic state of WP can be changed during device operation.
However, WP should not be changed during the EEPROM write
procedure time.
Writing to the EEPROM
During an I2C transaction, setting bit b14 of a Data Word HIGH
indicates to the device that the data in that same Data Word
should be written to both the DAC and EEPROM. The EEPROM
programming cycle for the appropriate channel(s) is started as
soon as a subsequent STOP command is issued on the I2C bus.
After the STOP condition is issued, it takes up to 35ms
(maximum) for a single EEPROM Register Write, and 420ms
(maximum) to write all registers to EEPROM. To ensure EEPROM
data validity, wait at least 35ms between single EEPROM
Register Writes, and before sending any other I2C commands.
When writing all registers to EEPROM, wait at least 420ms
before sending any other I2C commands. During the EEPROM
programming cycle time, the device's I2C bus is internally busy
and will NACK I2C commands.
Note, the normal DAC writes (bit b14 = ‘0’) can be written to as
quickly as the I2C bus can support.
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A recall can be initiated by performing a software reset using I2C.
A software reset is done by writing data 0x06 to Register Pointer
0x00 (Control Byte), and then on the falling edge of 8th SCL clock
(of the Control Byte), the recall operation will be started. The
device will then issue a NACK on the 9th SCL clock.
Recalling the ISL76534 EEPROM data to the output DACs takes
6ms typical) to complete. During the EEPROM recall time
(power-ON or during a software reset), OUT1-OUT14 and OUTCOM
will be set to high impedance and the device will NACK to any I2C
commands. Once the EEPROM recall is complete OUT1-OUT14
and OUTCOM will enable simultaneously and the outputs will
slew to the correct level. If some or all of the outputs
(OUT1-OUT14, OUTCOM) need to be defined (not high impedance)
during this delay time, an external resistor divider may be used to
set a “coarse” voltage until the DAC outputs are enabled.
Note, the ISL76534 EEPROM values are pre-programmed to the
default values explained in the “DEFAULT EEPROM VALUES”
section.
EEPROM Default Values
The ISL76534 has factory programmed (default) EEPROM values
for the output channels, which will be recalled from EEPROM and
loaded to the DAC registers at initial power-ON. The default
EEPROM values are shown in Table 6.
TABLE 6. DEFAULT EEPROM VALUES
DAC #
CHANNEL
CODE (hex)
EXPECTED OUTPUT
VOLTAGE (V)
DAC1-14
OUT1-14
0x000
GND
DAC15
OUTCOM
0x200
REFIN/2
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ISL76534
UVLO and Output Enable
The ISL76534 includes an Undervoltage Lock-Out (UVLO) for
AVDD. At power-ON the output drivers, OUTx and OUTCOM, are
initially in a high impedance (disabled) state, AVDD < UVLO.
The OUT1-OUT14 outputs are ENABLED when the internal
EEPROM recall has been completed (see “Recalling The
EEPROM” on page 20), and AVDD rises above 4.5V (maximum).
Although OUTCOM is powered from AVDD_AMP, it is internally
linked to the AVDD UVLO function. The OUTCOM will be enabled
when AVDD and AVDD_AMP rise above 4.5V (maximum).
The OUT1-OUT14 and OUTCOM outputs are DISABLED if AVDD
falls below 3.5V (minimum).
Power Sequencing
The ISL76534 has no restrictions on power supply sequencing of
AVDD and DVDD. AVDD_AMP should not exceed AVDD. AVDD_AMP
can also be set to GND to disable the function.
The DAC reference, REFIN, voltage should not exceed AVDD. This
ensures the ESD protection diodes from REFIN to AVDD do not
become forward biased. If REFIN does exceed AVDD, then the
current flow through the ESD diode should not exceed 10mA.
Thermal Shutdown
The ISL76534 features thermal shutdown, which protects the
device from damage due to overheating. When the junction (die)
temperature rises to 160°C (typical) all outputs, OUTx and
OUTCOM, are disabled (high-impedance). When the die
temperature cools by 20°C (typical) all outputs are re-enabled.
Power Dissipation
Power Supply Bypassing and Printed Circuit
Board Layout
Good Printed Circuit Board (PCB) layout is necessary for optimum
performance. The following are recommendations to achieve
optimum high frequency performance from your PCB.
• To optimize thermal performance, solder the ISL76534’s
exposed thermal pad to GND. PCB vias should be placed below
the device’s exposed thermal pad and connected to GND to
transfer heat away from the device (see “General PowerPAD
Design Considerations”). If the thermal pad is not connected to
GND then it should be electrically isolated.
• Maximize use of AC decoupled PCB layers. All signal I/O lines
should be routed over continuous ground planes (i.e., no split
planes or PCB gaps under these lines). Avoid vias in the signal
I/O lines.
• When testing, use good quality connectors and cables, match
cable types and keep cable lengths to a minimum.
• A minimum of two power supply decoupling capacitors are
recommended (typically 4.7µF and 0.1µF) per supply and
placed as close to the IC as possible. Avoid placing vias
between the capacitor and the device because vias add
unwanted inductance. Larger value capacitors can be placed
farther away.
General PowerPAD Design
Considerations
Figure 29 is an example of how to use vias to distribute heat
away from an IC.
With high short-circuit and continuous output current capability
for each channel, it is possible to exceed the +150°C absolute
maximum junction (die) temperature. Therefore, it is important
to calculate the maximum junction temperature for the
application to determine if load or circuit conditions need to be
modified to keep the device in a safe operating region.
The maximum power dissipation allowed in a package is
determined according to Equation 3:
T JMAX – T AMAX
P DMAX = -------------------------------------------- JA
FIGURE 29. PCB VIA PATTERN
(EQ. 3)
Where:
• TJMAX = Maximum junction temperature
• TAMAX = Maximum ambient temperature
• JA = Thermal resistance of the package
• PDMAX = Maximum power dissipation in the package
For more details on the allowable package power dissipation,
refer to Figures 23 and 24.
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For optimal thermal performance, use vias to distribute heat
away from the IC and to a system power plane. Fill the thermal
pad area with vias that are spaced 3x their radius (typically),
center-to-center, from each other. The via diameters should be
kept small, but they should be large enough to allow solder
wicking during reflow. To optimize heat transfer efficiency, do not
connect vias using “thermal relief” patterns. Vias should be
directly connected to the plane with plated through-holes.
Connect all vias to the correct voltage potential (power plane)
indicated in the datasheet. For the ISL76534, the thermal pad
potential is ground (GND).
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ISL76534
Typical Applications
AVDD
PMIC
4.7nF~10nF
DVDD
AVDD
4.7nF
0.1F
AVDD
REFIN = AVDD*[RB/(RA+RB)]
DVDD
0.1F
0.1F
0.1F
DVDD
AVDD_AMP
RA
AVDD
TCON
SCL
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
ISL76534
SDA
DVDD
WP
OPTION:
USE GPIO
DVDD
TFT-LCD
GAMMA
REFERENCES
OUTCOM
TFT-LCD
VCOM
INN_COM
A0
OPTION:
USE GPIO
TFT-LCD
PANEL
REFIN
4.7k 
4.7k 
RB
PAD
GND
FIGURE 30. TFT-LCD GAMMA and VCOM REFERENCE GENERATOR
AVDD
PMIC
4.7nF~10nF
DVDD
0.1F
AVDD
4.7nF
REFIN = AVDD*[RB/(RA+RB)]
DVDD
0.1F
GND
0.1F
DVDD
AVDD_AMP
AVDD
4.7k 
4.7k 
TCON
SCL
ISL76534
SDA
DVDD
WP
OPTION:
USE GPIO
DVDD
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
INN_COM
PAD
TFT-LCD
PANEL
REFIN
OUTCOM
A0
OPTION:
USE GPIO
RB
RA
TFT-LCD
GAMMA
REFERENCES
VCOM AMPLIFIER
NOT USED
GND
FIGURE 31. TFT-LCD GAMMA REFERENCE GENERATOR: VCOM AMPLIFIER DISABLED
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ISL76534
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
July 27, 2016
FN8866.0
CHANGE
Initial release
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FN8866.0
July 27, 2016
ISL76534
Package Outline Drawing
L28.4x5D
28 LEAD SUPER THIN QUAD FLAT NO LEAD PLASTIC PACKAGE
Rev 0, 3/11
PIN 1
INDEX AREA
4.00
A
0.25 MIN
B
0.400 ± 0.10
23
PIN #1
INDEX AREA
28
22
1
0.50
3.6 +0.10/-0.15
EXP DAP
5.00
0.20 ±0.05
8
15
0.05 C
4x
14
0.10
0.05
4
CAB
C
9
2.60 +0.10/0.15
EXP DAP
TOP VIEW
BOTTOM VIEW
SEE DETAIL “X''
0.10 C
5
0.38 +0.02/-0.08
0.08 C
C
C
0.00 MIN
0.05 MAX
0.127 REF
SEATING PLANE
SIDE VIEW
DETAIL "X"
(3.20)
PACKAGE
BOUNDARY
NOTES:
28 x (0.20)
(4.20)
(3.60)
24 x (0.50)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal. If terminal has a
radius on its end, dimension should not be measured in that
radius area.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
(28 x 0.50)
(2.60)
TYPICAL RECOMMENDED LAND PATTERN
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24
either a mold or mark feature.
7.
Reference Document: JEDEC MO-228.
FN8866.0
July 27, 2016