HT9200A/B DTMF Generators Features • • • • • • Operating voltage: 2.0V~5.5V Serial mode for the HT9200A Serial/parallel mode for the HT9200B Low standby current Low total harmonic distortion 3.58MHz crystal or ceramic resonator General Description selectable serial/parallel mode interface for various applications such as security systems, home automation, remote control through telephone lines, communication systems, etc. The HT9200A/B tone generators are designed for µC interfaces. They can be instructed by a µC to generate 16 dual tones and 8 single tones from the DTMF pin. The HT9200A provides a serial mode whereas the HT9200B contains a Selection Table Block Diagram 1 21st Aug ’98 HT9200A/B Pin Assignment Pad Assignment Unit: µm Pad Coordinates Pad No. X Y Pad No. X Y 1 –553.30 430.40 8 553.30 –523.50 2 3 –553.30 –133.50 –553.30 –328.50 9 10 553.30 553.30 –190.30 4.70 4 5 –553.30 –523.50 –220.10 –523.50 11 12 553.30 374.90 340.30 523.50 6 –25.10 –523.50 13 –279.30 523.50 7 308.10 –523.50 Chip size: 1460 × 1470 (µm)2 * The IC substrate should be connected to VSS in the PCB layout artwork. Pin Description I/O Internal Connection CE I CMOS IN Pull-high Chip enable, active low X2 O Oscillator X1 I The system oscillator consists of an inverter, a bias resistor, and the required load capacitor on chip. The oscillator function can be implemented by Connect a standard 3.579545MHz crystal to the X1 and X2 terminals. VSS — — Negative power supply NC — — No connection Pin Name Description 2 21st Aug ’98 HT9200A/B I/O Internal Connection Description D0~D3 I CMOS IN Pull-high or floating Data inputs for the parallel mode When the IC is operating in the serial mode, the data input terminals (D0~D3) are included with a pull-high resistor. When the IC is operating in the parallel mode, these pins become floating. S/P I CMOS IN Operation mode selection input S/P=“H”: Parallel mode S/P=“L”: Serial mode I CMOS IN Pull-high or floating Data synchronous clock input for the serial mode When the IC is operating in the parallel mode, the input terminal (CLK) is included with a pull-high resistor. When the IC is operating in the serial mode, this pin becomes floating. DATA I CMOS IN Pull-high or floating Data input terminal for the serial mode When the IC is operating in the parallel mode, the input terminal (DATA) is included with a pull-high resistor. When the IC is operating in the serial mode, this pin becomes floating. DTMF O CMOS OUT VDD — — Pin Name CLK Output terminal of the DTMF signal Positive power supply, 2.0V~5.5V for normal operation Approximate internal connection circuits 3 21st Aug ’98 HT9200A/B Absolute Maximum Ratings* Supply Voltage ................................. –0.3V to 6V Storage Temperature................. –50°C to 125°C Input Voltage.................... VSS–0.3 to VDD+0.3V Operating Temperature............... –20°C to 75°C *Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings” may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Ta=25°C Electrical Characteristics Symbol Parameter Test Conditions VDD Conditions — — Min. Typ. Max. Unit 2 — 5.5 V — 240 2500 — 950 3000 VDD Operating Voltage IDD Operating Current VIL “Low” Input Voltage — — VSS — 0.2VDD V VIH “High” Input Voltage — — 0.8VDD — VDD V ISTB Standby Current — — 1 — — 2 RP Pull-high Resistance 120 180 270 45 68 100 tDE DTMF Output Delay Time (Parallel Mode) — tUP+6 tUP+8 ms VTDC DTMF Output DC Level 2V~ DTMF Output 5.5V 0.45VDD — 0.75VDD V ITOL DTMF Sink Current 2.5V VDTMF=0.5V –0.1 — — mA VTAC DTMF Output AC Level 2.5V Row group, RL=5kΩ 0.12 0.15 0.18 Vrms ACR Column Pre-emphasis 2.5V Row group=0dB 1 2 3 dB RL DTMF Output Load 2.5V tHD ≤ –23dB 5 — — kΩ tHD Tone Signal Distortion 2.5V RL=5kΩ — –30 –23 dB fCLK Clock Input Rate (Serial Mode) — 100 500 kHz tUP The time from CE Oscillator Starting 5.0V falling edge to normal Time (When CE is low) oscillator operation — — 10 ms fOSC System Frequency 3.5831 MHz 2.5V S/P=VDD,D0~D3=VSS, 5.0V CE=VSS, No load 2.5V S/P=VDD,CE=VDD, 5.0V No load 2.5V 5.0V VOL=0V 5V — — — — Crystal=3.5795MHz 4 3.5759 3.5795 µA µA kΩ 21st Aug ’98 HT9200A/B Functional Description The HT9200A/B are DTMF generators for µC interfaces. They are controlled by a µC in the serial mode or the parallel mode (for the HT9200B only). DTMF signal. Every digit of a phone number to be transmitted is selected by a series of inputs which consist of 5-bit data. Of the 5 bits, the D0(LSB) is the first received bit. The HT9200A/B will latch data on the falling edge of the clock (CLK pin). The relationship between the digital codes and the tone output frequency is shown in Table 1. As for the control timing diagram, refer to Figure 1. Serial mode (HT9200A/B) The HT9200A/B employ a data input, a 5-bit code, and a synchronous clock to transmit a Table 1: Digits vs. input data vs. tone output frequency (serial mode) Digit D4 D3 D2 D1 D0 Tone Output Frequency (Hz) 1 0 0 0 0 1 2 0 0 0 1 0 697+1209 697+1336 3 4 5 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1 697+1477 770+1209 770+1336 6 7 8 0 0 0 0 0 1 1 1 0 1 1 0 0 1 0 770+1477 852+1209 852+1336 9 0 ∗ 0 0 0 1 1 1 0 0 0 0 1 1 1 0 1 852+1477 941+1336 941+1209 # A 0 0 1 1 1 1 0 0 0 1 941+1477 697+1633 B C 0 0 1 1 1 1 1 1 0 1 770+1633 852+1633 D — — 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 941+1633 697 770 — — — 1 1 1 0 0 0 0 0 1 1 1 0 0 1 0 852 941 1209 — — — 1 1 1 0 0 0 1 1 1 0 1 1 1 0 1 1336 1477 1633 DTMF OFF 1 1 1 1 1 — *Notes: The codes not listed in Table 1 are not used D4 is MSB 5 21st Aug ’98 HT9200A/B connected low to transmit the DTMF signal from the DTMF pin. When the system is operating in the serial mode a pull-high resistor is attached to D0~D3 (for parallel mode) on the input terminal. The TDE time (about 6ms) will be delayed from the CE falling edge to the DTMF signal output. For the HT9200B, the S/P pin has to be connected low for serial mode operation. The relationship between the digital codes and the tone output frequency is illustrated in Table 2. As for the control timing diagram, see Figure 2. Parallel mode ( HT9200B) The HT9200B provides four data inputs D0~D3 to generate their corresponding DTMF signals. The S/P has to be connected high to select the parallel operation mode. Then the input data codes should be determined. Finally, the CE is When the system is operating in the parallel mode, D0~D3 are all in the floating state. Thus, these data input pins should not float. Figure 1 Table 2: Digits vs. input data vs. tone output frequency (parallel mode) Digit D3 D2 D1 D0 Tone Output Frequency (Hz) 1 0 0 0 1 697+1209 2 0 0 1 0 697+1336 3 0 0 1 1 697+1477 4 0 1 0 0 770+1209 5 0 1 0 1 770+1336 6 0 1 1 0 770+1477 7 0 1 1 1 852+1209 8 1 0 0 0 852+1336 6 21st Aug ’98 HT9200A/B Digit D3 D2 D1 D0 Tone Output Frequency (Hz) 9 1 0 0 1 852+1477 0 1 0 1 0 941+1336 ∗ 1 0 1 1 941+1209 # 1 1 0 0 941+1477 A 1 1 0 1 697+1633 B 1 1 1 0 770+1633 C 1 1 1 1 852+1633 D 0 0 0 0 941+1633 Figure 2 Tone frequency Output Frequency (Hz) %Error Specified Actual 697 699 +0.29% 770 766 –0.52% 852 847 –0.59% 941 948 +0.74% 1209 1215 +0.50% 1336 1332 –0.30% 1477 1472 –0.34% % Error does not contain the crystal frequency drift 7 21st Aug ’98 HT9200A/B Application Circuits Serial mode Serial/parallel mode 8 21st Aug ’98