Cypress CY8C29466-24SXI Mixed signal array Datasheet

PSoC™ Mixed Signal Array
Preliminary Data Sheet
CY8C29466, CY8C29566,
CY8C29666, and CY8C29866
Features
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 24 MHz
❐ Two 8x8 Multiply, 32-Bit Accumulate
❐ Low Power at High Speed
❐ 3.0V to 5.25V Operating Voltage
❐ Operating Voltages Down to 1.0V Using OnChip Switch Mode Pump (SMP)
❐ Industrial Temperature Range: -40°C to +85°C
■ Advanced Peripherals (PSoC Blocks)
❐ 12 Rail-to-Rail Analog PSoC Blocks Provide:
- Up to 14-Bit ADCs
- Up to 9-Bit DACs
- Programmable Gain Amplifiers
- Programmable Filters and Comparators
❐ 16 Digital PSoC Blocks Provide:
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
- Up to 4 Full-Duplex UARTs
- Multiple SPI™ Masters or Slaves
- Connectable to all GPIO Pins
❐ Complex Peripherals by Combining Blocks
■ Precision, Programmable Clocking
❐ Internal ±2.5% 24/48 MHz Oscillator
❐ 24/48 MHz with Optional 32.768 kHz Crystal
❐ Optional External Oscillator, up to 24 MHz
❐ Internal Oscillator for Watchdog and Sleep
■ Flexible On-Chip Memory
❐ 32K Bytes Flash Program Storage 50,000
Erase/Write Cycles
❐ 2K Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP™)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
■ Programmable Pin Configurations
❐ 25 mA Sink on all GPIO
❐ Pull up, Pull down, High Z, Strong, or Open
Drain Drive Modes on all GPIO
❐ Up to 12 Analog Inputs on GPIO
❐ Four 40 mA Analog Outputs on GPIO
❐ Configurable Interrupt on all GPIO
Port 7 Port 6 Port 5 Port 4 Port 3 Port 2 Port 1 Port 0
SRAM
2K
Global Analog Interconnect
SROM
Flash 32K
PSoC CORE
CPU Core (M8C)
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital
Clocks
Analog
Block
Array
(4 Rows,
16 Blocks)
(4 Columns,
12 Blocks)
Two
Multiply
Accum.
POR and LVD
Decimator
I 2C
System Resets
SYSTEM RESOURCES
August 3, 2004
Analog
Ref
Analog
Input
Muxing
Internal
Voltage
Ref.
■ Complete Development Tools
❐ Free Development Software
(PSoC™ Designer)
❐ Full-Featured, In-Circuit Emulator and
Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128K Bytes Trace Memory
❐ Complex Events
❐ C Compilers, Assembler, and Linker
The PSoC™ family consists of many Mixed Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components
with one, low cost single-chip programmable device. PSoC
devices include configurable blocks of analog and digital logic,
as well as programmable interconnects. This architecture
allows the user to create customized peripheral configurations
that match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable IO are included in a range of convenient pinouts and packages.
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: PSoC Core, Digital System, Analog System,
and System Resources. Configurable global busing allows all
the device resources to be combined into a complete custom
system. The PSoC CY8C29x66 family can have up to eight IO
ports that connect to the global digital and analog interconnects,
providing access to 16 digital blocks and 12 analog blocks.
ANALOG SYSTEM
Digital
Block
Array
❐ I2C™ Slave, Master, and Multi-Master to
400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
PSoC™ Functional Overview
Analog
Drivers
SYSTEM BUS
Global Digital Interconnect
■ Additional System Resources
The PSoC Core
Switch
Mode
Pump
The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO (General Purpose IO).
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU utilizes an interrupt controller with 25 vec-
© Cypress MicroSystems, Inc. 2004 — Document No. 38-12013 Rev. *F
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CY8C29x66 Preliminary Data Sheet
PSoC™ Overview
tors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).
Port 7
Memory encompasses 32 KB of Flash for program storage, 2
KB of SRAM for data storage, and up to 2 KB of EEPROM emulated using the Flash. Program Flash utilizes four protection levels on blocks of 64 bytes, allowing customized software IP
protection.
Port 6
Port 5
Port 4
Port 3
To System Bus
Digital Clocks
From Core
Port 2
Port 1
Port 0
To Analog
System
DIGITAL SYSTEM
Digital PSoC Block Array
Row Input
Configuration
Row 0
DBB00
DBB01
DCB02
4
DCB03
4
Row Output
Configuration
The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate
to 2.5% over temperature and voltage. The 24 MHz IMO can
also be doubled to 48 MHz for use by the digital system. A low
power 32 kHz ILO (internal low speed oscillator) is provided for
the Sleep timer and WDT. If crystal accuracy is desired, the
ECO (32.768 kHz external crystal oscillator) is available for use
as a Real Time Clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a System
Resource), provide the flexibility to integrate almost any timing
requirement into the PSoC device.
8
8
Row Input
Configuration
Row Input
Configuration
The Digital System is composed of 16 digital PSoC blocks.
Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals,
which are called user module references. Digital peripheral configurations include those listed below.
DBB11
DCB12
DCB13
4
Row 2
DBB20
DBB21
DCB22
4
DCB23
4
Row 3
DBB30
DBB31
DCB32
4
DCB33
4
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
8
Row Output
Configuration
The Digital System
DBB10
4
Row Output
Configuration
PSoC GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read.
Row 1
Row Output
Configuration
Row Input
Configuration
8
GOE[7:0]
GOO[7:0]
■
PWMs (8 to 32 bit)
■
PWMs with Dead band (8 to 32 bit)
■
Counters (8 to 32 bit)
■
Timers (8 to 32 bit)
The Analog System
■
UART 8 bit with selectable parity (up to 4)
■
SPI master and slave (up to 4 each)
■
I2C slave and master (1 available as a System Resource)
■
Cyclical Redundancy Checker/Generator (8 to 32 bit)
■
IrDA (up to 4)
The Analog System is composed of 12 configurable blocks,
each comprised of an opamp circuit allowing the creation of
complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application
requirements. Some of the more common PSoC analog functions (most available as user modules) are listed below.
■
Pseudo Random Sequence Generators (8 to 32 bit)
■
Analog-to-digital converters (up to 4, with 6- to 14-bit resolution, selectable as Incremental, Delta Sigma, and SAR)
■
Filters (2, 4, 6, or 8 pole band-pass, low-pass, and notch)
■
Amplifiers (up to 4, with selectable gain to 48x)
■
Instrumentation amplifiers (up to 2, with selectable gain to
93x)
■
Comparators (up to 4, with 16 selectable thresholds)
■
DACs (up to 4, with 6- to 9-bit resolution)
■
Multiplying DACs (up to 4, with 6- to 9-bit resolution)
■
High current output drivers (four with 40 mA drive as a Core
Resource)
Digital System Block Diagram
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows you the optimum choice of system resources for your application. Family
resources are shown in the table titled “PSoC Device Characteristics” on page 3.
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CY8C29x66 Preliminary Data Sheet
PSoC™ Overview
■
1.3V reference (as a System Resource)
■
DTMF dialer
■
Modulators
■
Correlators
■
Peak detectors
■
Many other topologies possible
Additional System Resources
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems. Additional resources include a multiplier, decimator, switch mode
pump, low voltage detection, and power on reset. Brief statements describing the merits of each system resource are presented below.
Analog blocks are provided in columns of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks, as shown in the figure below.
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
AGNDIn RefIn
P0[7]
P2[3]
P2[1]
■
Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to
both the digital and analog systems. Additional clocks can be
generated using digital PSoC blocks as clock dividers.
■
Two multiply accumulates (MACs) provide fast 8-bit multipliers with 32-bit accumulate to assist in both general math as
well as digital filters.
■
The decimator provides a custom hardware filter for digital
signal, processing applications including the creation of Delta
Sigma ADCs.
■
The I2C module provides 100 and 400 kHz communication
over two wires. Slave, master, and multi-master modes are
all supported.
■
Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
■
An internal 1.3 voltage reference provides an absolute reference for the analog system, including ADCs and DACs.
■
An integrated switch mode pump (SMP) generates normal
operating voltages from a single 1.2V battery cell, providing a
low cost boost converter.
P2[6]
P2[4]
P2[2]
P2[0]
Array Input Configuration
PSoC Device Characteristics
ACI0[1:0]
ACI1[1:0]
ACI2[1:0]
ACI3[1:0]
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
3 analog blocks. The following table lists the resources
available for specific PSoC device groups. The PSoC device
covered by this data sheet is shown in the first row of the table.
Block Array
ACB00
ACB01
ACB02
ACB03
ASC10
ASD11
ASC12
ASD13
ASD20
ASC21
ASD22
ASC23
Analog
Columns
Analog
Blocks
M8C Interface (Address Bus, Data Bus, Etc.)
AGNDIn
RefIn
Bandgap
Analog
Outputs
Reference
Generators
Analog
Inputs
RefHi
RefLo
AGND
Digital
Blocks
Interface to
Digital System
Digital
Rows
Analog Reference
PSoC Part
Number
Digital
IO
PSoC Device Characteristics
CY8C29x66
up to
64
4
16
12
4
4
12
CY8C27x43
up to
44
2
8
12
4
4
12
CY8C24x23
up to
24
1
4
12
2
2
6
CY8C24x23A
up to
24
1
4
12
2
2
6
CY8C22x13
up to
16
1
4
8
1
1
3
Analog System Block Diagram
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Document No. 38-12013 Rev. *F
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CY8C29x66 Preliminary Data Sheet
PSoC™ Overview
Getting Started
Development Tools
The quickest path to understanding the PSoC silicon is by reading this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin,
register, and electrical specifications. For in-depth information,
along with detailed programming information, reference the
PSoC™ Mixed Signal Array Technical Reference Manual.
The Cypress MicroSystems PSoC Designer is a Microsoft®
Windows-based, integrated development environment for the
Programmable System-on-Chip (PSoC) devices. The PSoC
Designer IDE and application runs on Windows NT 4.0, Windows 2000, Windows Millennium (Me), or Windows XP. (Reference the PSoC Designer Functional Flow diagram below.)
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
at http://www.onfulfillment.com/cypressstore/ contains development kits, C compilers, and all accessories for PSoC development. Click on PSoC (Programmable System-on-Chip) to view
a current list of available items.
Tele-Training
PSoC Designer also supports a high-level C language compiler
developed specifically for the devices in the family.
Importable
Design
Database
Technical Support
PSoC application engineers take pride in fast and accurate
response. They can be reached with a 4-hour guaranteed
response at http://www.cypress.com/support/login.cfm.
Application Notes
A long list of application notes will assist you in every aspect of
your design effort. To locate the PSoC application notes, go to
http://www.cypress.com/design/results.cfm.
August 3, 2004
PSoC
Configuration
Sheet
Device
Database
PSoCTM
Designer
Core
Engine
Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant, go to the following Cypress support web site:
http://www.cypress.com/support/cypros.cfm.
Context
Sensitive
Help
Graphical Designer
Interface
PSoCTM
Designer
Results
Free PSoC "Tele-training" is available for beginners and taught
by a live marketing or application engineer over the phone. Five
training classes are available to accelerate the learning curve
including introduction, designing, debugging, advanced design,
advanced analog, as well as application-specific classes covering topics like PSoC and the LIN bus. For days and times of the
tele-training, see http://www.cypress.com/support/training.cfm.
PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the
PSoC, and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
Commands
For up-to-date Ordering, Packaging, and Electrical Specification
information, reference the latest PSoC device data sheets on
the web at http://www.cypress.com/psoc.
Application
Database
Manufacturing
Information
File
Project
Database
User
Modules
Library
Emulation
Pod
Document No. 38-12013 Rev. *F
In-Circuit
Emulator
Device
Programmer
PSoC Designer Subsystems
4
CY8C29x66 Preliminary Data Sheet
PSoC™ Overview
PSoC Designer Software Subsystems
Device Editor
Debugger
The Device Editor subsystem allows the user to select different
onboard analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters.
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the designer to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time.
PSoC Designer sets up power-on initialization tables for
selected PSoC block configurations and creates source code
for an application framework. The framework contains software
to operate the selected components and, if the project uses
more than one operating configuration, contains routines to
switch between different sets of PSoC block configurations at
run time. PSoC Designer can print out a configuration sheet for
a given project configuration for use during application programming in conjunction with the Device Data Sheet. Once the
framework is generated, the user can add application-specific
code to flesh out the framework. It’s also possible to change the
selected components and regenerate the framework.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
Hardware Tools
In-Circuit Emulator
Design Browser
The Design Browser allows users to select and import preconfigured designs into the user’s project. Users can easily browse
a catalog of preconfigured designs to facilitate time-to-design.
Examples provided in the tools include a 300-baud modem, LIN
Bus master and slave, fan controller, and magnetic card reader.
Application Editor
In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble, compile, link, and build.
A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability
to program single devices.
The emulator consists of a base unit that connects to the PC by
way of the USB port. The base unit is universal and will operate
with all PSoC devices. Emulation pods for each device family
are available separately. The emulation pod takes the place of
the PSoC device in the target board and performs full speed (24
MHz) operation.
Assembler. The macro assembler allows the assembly code
to be merged seamlessly with C code. The link libraries automatically use absolute addressing or can be compiled in relative
mode, and linked with other software modules to get absolute
addressing.
C Language Compiler. A C language compiler is available
that supports Cypress MicroSystems’ PSoC family devices.
Even if you have never worked in the C language before, the
product quickly allows you to create complete C programs for
the PSoC family devices.
The embedded, optimizing C compiler provides all the features
of C tailored to the PSoC architecture. It comes complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.
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CY8C29x66 Preliminary Data Sheet
PSoC™ Overview
Designing with User Modules
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture
a unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
Each block has several registers that determine its function and
connectivity to other blocks, multiplexers, buses, and to the IO
pins. Iterative development cycles permit you to adapt the hardware as well as the software. This substantially lowers the risk
of having to select a different part to meet the final design
requirements.
Device Editor
User
Module
Selection
The API functions are documented in user module data sheets
that are viewed directly in the PSoC Designer IDE. These data
sheets explain the internal operation of the user module and
provide performance specifications. Each data sheet describes
the use of each user module parameter and documents the setting of each register controlled by the user module.
The development process starts when you open a new project
and bring up the Device Editor, a graphical user interface (GUI)
for configuring the hardware. You pick the user modules you
need for your project and map them onto the PSoC blocks with
point-and-click simplicity. Next, you build signal chains by interconnecting user modules to each other and the IO pins. At this
stage, you also configure the clock source connections and
enter parameter values directly or by selecting values from
drop-down menus. When you are ready to test the hardware
configuration or move on to developing code for the project, you
perform the “Generate Application” step. This causes PSoC
Designer to generate source code that automatically configures
the device to your specification and provides the high-level user
module API functions.
August 3, 2004
Source
Code
Generator
Generate
Application
Application Editor
To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a library of
pre-built, pre-tested hardware peripheral functions, called “User
Modules.” User modules make selecting and implementing
peripheral devices simple, and come in analog, digital, and
mixed signal varieties. The standard User Module library contains over 50 common peripherals such as ADCs, DACs Timers, Counters, UARTs, and other not-so common peripherals
such as DTMF Generators and Bi-Quad analog filter sections.
Each user module establishes the basic register settings that
implement the selected function. It also provides parameters
that allow you to tailor its precise configuration to your particular
application. For example, a Pulse Width Modulator User Module configures one or more digital PSoC blocks, one for each 8
bits of resolution. The user module parameters permit you to
establish the pulse width and duty cycle. User modules also
provide tested software to cut your development time. The user
module application programming interface (API) provides highlevel functions to control and respond to hardware events at
run-time. The API also provides optional interrupt service routines that you can adapt as needed.
Placement
and
Parameter
-ization
Project
Manager
Source
Code
Editor
Build
Manager
Build
All
Debugger
Interface
to ICE
Storage
Inspector
Event &
Breakpoint
Manager
User Module and Source Code Development Flows
The next step is to write your main program, and any sub-routines using PSoC Designer’s Application Editor subsystem.
The Application Editor includes a Project Manager that allows
you to open the project source code files (including all generated code files) from a hierarchal view. The source code editor
provides syntax coloring and advanced edit features for both C
and assembly language. File search capabilities include simple
string searches and recursive “grep-style” patterns. A single
mouse click invokes the Build Manager. It employs a professional-strength “makefile” system to automatically analyze all
file dependencies and run the compiler and assembler as necessary. Project-level options control optimization strategies
used by the compiler and linker. Syntax errors are displayed in
a console window. Double clicking the error message takes you
directly to the offending line of source code. When all is correct,
the linker builds a HEX file image suitable for programming.
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE) where it
runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and allows you define complex
breakpoint events that include monitoring address and data bus
values, memory locations and external signals.
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CY8C29x66 Preliminary Data Sheet
PSoC™ Overview
Document Conventions
Table of Contents
Acronyms Used
For an in depth discussion and more information on your PSoC
device, obtain the PSoC Mixed Signal Array Technical Reference Manual. This document encompasses and is organized
into the following chapters and sections.
The following table lists the acronyms that are used in this document.
Acronym
Description
AC
alternating current
ADC
analog-to-digital converter
API
application programming interface
CPU
central processing unit
CT
continuous time
DAC
digital-to-analog converter
DC
direct current
ECO
external crystal oscillator
EEPROM
electrically erasable programmable read-only memory
FSR
full scale range
GPIO
general purpose IO
GUI
graphical user interface
HBM
human body model
ICE
in-circuit emulator
ILO
internal low speed oscillator
IMO
internal main oscillator
IO
input/output
IPOR
imprecise power on reset
LSb
least-significant bit
LVD
low voltage detect
MSb
most-significant bit
PC
program counter
PLL
phase-locked loop
POR
power on reset
PPOR
precision power on reset
PSoC™
Programmable System-on-Chip™
PWM
pulse width modulator
RAM
random access memory
SC
switched capacitor
SLIMO
slow IMO
SMP
switch mode pump
1.
Pin Information ............................................................. 8
1.1 Pinouts ................................................................... 8
1.1.1 28-Pin Part Pinout ...................................... 8
1.1.2 44-Pin Part Pinout ...................................... 9
1.1.3 48-Pin Part Pinouts ................................... 10
1.1.4 100-Pin Part Pinout .................................. 12
2.
Register Reference ..................................................... 14
2.1 Register Conventions ........................................... 14
2.1.1 Abbreviations Used .................................. 14
2.2 Register Mapping Tables ..................................... 14
3.
Electrical Specifications ............................................ 17
3.1 Absolute Maximum Ratings ................................. 18
3.2 Operating Temperature ........................................ 18
3.3 DC Electrical Characteristics ................................ 19
3.3.1 DC Chip-Level Specifications ................... 19
3.3.2 DC General Purpose IO Specifications .... 19
3.3.3 DC Operational Amplifier Specifications ... 20
3.3.4 DC Analog Output Buffer Specifications ... 21
3.3.5 DC Switch Mode Pump Specifications ..... 22
3.3.6 DC Analog Reference Specifications ....... 23
3.3.7 DC Analog PSoC Block Specifications ..... 24
3.3.8 DC POR, SMP, and LVD Specifications ... 24
3.3.9 DC Programming Specifications ............... 25
3.4 AC Electrical Characteristics ................................ 26
3.4.1 AC Chip-Level Specifications ................... 26
3.4.2 AC General Purpose IO Specifications .... 28
3.4.3 AC Operational Amplifier Specifications ... 29
3.4.4 AC Digital Block Specifications ................. 30
3.4.5 AC Analog Output Buffer Specifications ... 31
3.4.6 AC External Clock Specifications ............. 32
3.4.7 AC Programming Specifications ............... 32
3.4.8 AC I2C Specifications ............................... 33
4.
Packaging Information ............................................... 34
4.1 Packaging Dimensions ......................................... 34
4.2 Thermal Impedances ........................................... 38
4.3 Capacitance on Crystal Pins ................................ 38
5.
Ordering Information .................................................. 39
5.1 Ordering Code Definitions .................................... 39
6.
Sales and Service Information .................................. 40
6.1 Revision History ................................................... 40
6.2 Copyrights and Code Protection .......................... 40
Units of Measure
A units of measure table is located in the Electrical Specifications section. Table 3-1 on page 17 lists all the abbreviations
used to measure the PSoC devices.
Numeric Naming
Hexidecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexidecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’).
Numbers not indicated by an ‘h’, ‘b’, or 0x are decimal.
August 3, 2004
Document No. 38-12013 Rev. *F
7
1. Pin Information
This chapter describes, lists, and illustrates the CY8C29x66 PSoC device pins and pinout configurations.
1.1
Pinouts
The CY8C29x66 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port
pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO.
1.1.1
28-Pin Part Pinout
Table 1-1. 28-Pin Part Pinout (PDIP, SSOP, SOIC)
Pin
No.
1
2
3
4
5
6
7
8
9
Type
Digital Analog
IO
I
IO
IO
IO
IO
IO
I
IO
IO
IO
I
IO
I
Power
10
11
12
13
14
15
16
17
18
19
IO
IO
IO
IO
20
21
22
23
24
25
26
27
28
IO
IO
IO
IO
IO
IO
IO
IO
Pin
Name
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
SMP
P1[7]
P1[5]
P1[3]
P1[1]
Vss
P1[0]
P1[2]
P1[4]
P1[6]
XRES
Power
IO
IO
IO
IO
Input
I
I
I
IO
IO
I
Power
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Description
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Direct switched capacitor block input.
Direct switched capacitor block input.
Switch Mode Pump (SMP) connection to
external components required.
I2C Serial Clock (SCL)
I2C Serial Data (SDA)
Crystal (XTALin), I2C Serial Clock (SCL)
Ground connection.
Crystal (XTALout), I2C Serial Data (SDA)
CY8C29466 28-Pin PSoC Device
AI, P0[7]
AIO, P0[5]
AIO, P0[3]
AI, P0[1]
P2[7]
P2[5]
AI, P2[3]
AI, P2[1]
SMP
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PDIP
SSOP
SOIC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vdd
P0[6], AI
P0[4], AIO
P0[2], AIO
P0[0], AI
P2[6], External VREF
P2[4], External AGND
P2[2], AI
P2[0], AI
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
Optional External Clock Input (EXTCLK)
Active high external reset with internal pull
down.
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND)
External Voltage Reference (VREF)
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Supply voltage.
LEGEND: A = Analog, I = Input, and O = Output.
August 3, 2004
Document No. 38-12013 Rev. *F
8
CY8C29x66 Preliminary Data Sheet
1.1.2
1. Pin Information
44-Pin Part Pinout
Table 1-2. 44-Pin Part Pinout (TQFP)
I
IO
IO
I
Power
IO
IO
IO
IO
IO
I
IO
IO
I
P0[6]
Vdd
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P0[7], AI
Vdd
P0[6],
P0[4],
P0[2],
P0[0],
P2[6], External VREF
43
42
41
40
39
38
37
36
35
34
AI
AIO
AIO
AI
P0[3], AIO
P0[5], AIO
P2[7]
P0[1], AI
44
Active high external reset with internal pull
down.
22
IO
I
I
P4[0]
P4[2]
P4[4]
P4[6]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
Optional External Clock Input (EXTCLK)
33
32
31
30
29
28
27
26
25
24
23
P2[4], External AGND
P2[2], AI
P2[0], AI
P4[6]
P4[4]
P4[2]
P4[0]
XRES
P3[6]
P3[4]
P3[2]
P1[6]
P3[0]
38
39
40
41
42
43
44
Input
11
TQFP
I2C SDA, XTALout, P1[0]
P1[2]
EXTCLK, P1[4]
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
P1[4]
P1[6]
P3[0]
P3[2]
P3[4]
P3[6]
XRES
Crystal (XTALin), I2C Serial Clock (SCL)
Ground connection.
Crystal (XTALout), I2C Serial Data (SDA)
1
2
3
4
5
6
7
8
9
10
16
17
18
19
20
21
27
28
29
30
31
32
33
34
35
36
37
IO
IO
I2C Serial Clock (SCL)
I2C Serial Data (SDA)
P2[5]
AI, P2[3]
AI, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
I2C SCL, XTALin, P1[1]
Vss
IO
IO
IO
IO
IO
IO
Power
Switch Mode Pump (SMP) connection to
external components required.
14
15
20
21
22
23
24
25
26
P3[7]
P3[5]
P3[3]
P3[1]
P1[7]
P1[5]
P1[3]
P1[1]
Vss
P1[0]
P1[2]
Direct switched capacitor block input.
Direct switched capacitor block input.
I2C SDA, P1[5]
P1[3]
IO
IO
IO
IO
IO
IO
IO
IO
P2[5]
P2[3]
P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
CY8C29566 44-Pin PSoC Device
Description
12
13
9
10
11
12
13
14
15
16
17
18
19
Pin
Name
P3[1]
1
2
3
4
5
6
7
8
Type
Digital Analog
IO
IO
I
IO
I
IO
IO
IO
IO
Power
I2C SCL, P1[7]
Pin
No.
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND)
External Voltage Reference (VREF)
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Supply voltage.
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
LEGEND: A = Analog, I = Input, and O = Output.
August 3, 2004
Document No. 38-12013 Rev. *F
9
CY8C29x66 Preliminary Data Sheet
1.1.3
1. Pin Information
48-Pin Part Pinouts
Table 1-3. 48-Pin Part Pinout (SSOP)
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
Type
Digital Analog
IO
I
IO
IO
IO
IO
IO
I
IO
IO
IO
I
IO
I
IO
IO
IO
IO
Power
14
15
16
17
18
19
20
21
22
23
24
25
26
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
27
28
29
30
31
32
33
34
35
IO
IO
IO
IO
IO
IO
IO
IO
36
37
38
39
40
41
42
43
44
45
46
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
47
48
IO
Pin
Name
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
P5[1]
P1[7]
P1[5]
P1[3]
P1[1]
Vss
P1[0]
P1[2]
Power
IO
IO
P1[4]
P1[6]
P5[0]
P5[2]
P3[0]
P3[2]
P3[4]
P3[6]
XRES
Input
I
I
I
IO
IO
I
Power
CY8C29666 48-Pin PSoC Device
Description
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Direct switched capacitor block input.
Direct switched capacitor block input.
Switch Mode Pump (SMP) connection to
external components required.
I2C Serial Clock (SCL)
I2C Serial Data (SDA)
Crystal (XTALin), I2C Serial Clock (SCL)
Ground connection.
Crystal (XTALout), I2C Serial Data (SDA)
AI, P0[7]
AIO, P0[5]
AIO, P0[3]
AI, P0[1]
P2[7]
P2[5]
AI, P2[3]
AI, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
P5[1]
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Vdd
P0[6], AI
P0[4], AIO
P0[2], AIO
P0[0], AI
P2[6], External VREF
P2[4], External AGND
P2[2], AI
P2[0], AI
P4[6]
P4[4]
P4[2]
P4[0]
XRES
P3[6]
P3[4]
P3[2]
P3[0]
P5[2]
P5[0]
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
Optional External Clock Input (EXTCLK)
Active high external reset with internal pull
down.
P4[0]
P4[2]
P4[4]
P4[6]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND)
External Voltage Reference (VREF)
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
P0[6]
Vdd
Analog column mux input.
Supply voltage.
LEGEND: A = Analog, I = Input, and O = Output.
August 3, 2004
Document No. 38-12013 Rev. *F
10
CY8C29x66 Preliminary Data Sheet
1. Pin Information
Table 1-4. 48-Pin Part Pinout (MLF*)
Direct switched capacitor block input.
P2[1]
Direct switched capacitor block input.
3
IO
P4[7]
4
IO
P4[5]
5
IO
P4[3]
6
IO
P3[7]
9
IO
P3[5]
10
IO
P3[3]
11
IO
P3[1]
12
IO
P5[3]
13
IO
P5[1]
14
IO
P1[7]
I2C Serial Clock (SCL)
15
IO
P1[5]
I2C Serial Data (SDA)
16
IO
P1[3]
17
IO
18
Power
P1[1]
Crystal (XTALin), I2C Serial Clock (SCL)
Vss
Ground connection.
Crystal (XTALout), I2C Serial Data (SDA)
19
IO
P1[0]
20
IO
P1[2]
21
IO
P1[4]
22
IO
P1[6]
23
IO
P5[0]
24
IO
P5[2]
25
IO
P3[0]
26
IO
P3[2]
27
IO
P3[4]
28
IO
29
Optional External Clock Input (EXTCLK)
(Top View)
P2[4], External AGND
P2[2], AI
P2[0], AI
P4[6]
P4[4]
P4[2]
P4[0]
XRES
P3[6]
P3[4]
P3[2]
P3[0]
P3[6]
Input
XRES
Active high external reset with internal pull
down.
30
IO
P4[0]
31
IO
P4[2]
32
IO
P4[4]
33
IO
34
IO
I
P2[0]
35
IO
I
P2[2]
Direct switched capacitor block input.
36
IO
P2[4]
External Analog Ground (AGND)
37
IO
P2[6]
External Voltage Reference (VREF)
38
IO
I
P0[0]
Analog column mux input.
39
IO
IO
P0[2]
Analog column mux input and column output.
40
IO
IO
P0[4]
Analog column mux input and column output.
41
IO
I
P0[6]
Analog column mux input.
Vdd
Supply voltage.
42
MLF
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
17
18
19
20
21
22
23
24
IO
1
2
3
4
5
6
I2C SCL, XTALin, P1[1]
Vss
I2C SDA, XTALout, P1[0]
P1[2]
EXTCLK, P1[4]
P1[6]
P5[0]
P5[2]
8
AI, P2[3]
AI, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
15
16
Switch Mode Pump (SMP) connection to
external components required.
I2C SDA, P1[5]
P1[3]
SMP
48
47
46
45
44
43
P4[1]
Power
38
37
P2[3]
I
Vdd
P0[6], AI
P0[4], AIO
P0[2], AIO
P0[0], AI
P2[6], External VRef
I
IO
42
41
40
39
IO
2
P2[5]
P2[7]
P0[1], AI
1
7
CY8C29666 48-Pin PSoC Device
Description
P0[3], AIO
P0[5], AIO
P0[7], AI
Pin
Name
Analog
13
14
Type
Digital
P5[1]
I2C SCL, P1[7]
Pin
No.
P4[6]
Power
Direct switched capacitor block input.
43
IO
I
P0[7]
Analog column mux input.
44
IO
IO
P0[5]
Analog column mux input and column output.
45
IO
IO
P0[3]
Analog column mux input and column output.
46
IO
I
P0[1]
Analog column mux input.
47
IO
P2[7]
48
IO
P2[5]
LEGEND: A = Analog, I = Input, and O = Output.
* The MLF package has a center pad that must be connected to ground (Vss).
August 3, 2004
Document No. 38-12013 Rev. *F
11
CY8C29x66 Preliminary Data Sheet
1.1.4
1. Pin Information
100-Pin Part Pinout
Table 1-5. 100-Pin Part Pinout (TQFP)
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
Type
Digital
IO
IO
IO
IO
IO
IO
IO
IO
IO
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Analog
I
I
I
Power
Power
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Power
Power
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Name
Description
NC
NC
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
NC
No connection.
No connection.
Analog column mux input.
NC
SMP
No connection.
Switch Mode Pump (SMP) connection to
external components required.
Ground connection.
Vss
P3[7]
P3[5]
P3[3]
P3[1]
P5[7]
P5[5]
P5[3]
P5[1]
P1[7]
NC
NC
NC
P1[5]
P1[3]
P1[1]
NC
Vdd
NC
Vss
NC
P7[7]
P7[6]
P7[5]
P7[4]
P7[3]
P7[2]
P7[1]
P7[0]
P1[0]
P1[2]
P1[4]
P1[6]
NC
NC
NC
Direct switched capacitor block input.
Direct switched capacitor block input.
No connection.
I2C Serial Clock (SCL)
No connection.
No connection.
No connection.
I2C Serial Data (SDA)
Crystal (XTALin), I2C Serial Clock (SCL)
No connection.
Supply voltage.
No connection.
Ground connection.
No connection.
Crystal (XTALout), I2C Serial Data (SDA)
Optional External Clock Input (EXTCLK)
No connection.
No connection.
No connection.
Pin
No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Type
Digital
Analog
Name
NC
P5[0]
P5[2]
P5[4]
P5[6]
P3[0]
P3[2]
P3[4]
P3[6]
NC
NC
XRES
IO
IO
IO
IO
IO
IO
IO
IO
Input
IO
IO
Description
No connection.
No connection.
No connection.
Active high external reset with internal pull
down.
P4[0]
P4[2]
Power
IO
IO
IO
IO
IO
I
I
IO
IO
I
IO
IO
IO
IO
IO
I
Power
Power
Power
Power
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
IO
IO
IO
IO
Vss
P4[4]
P4[6]
P2[0]
P2[2]
P2[4]
NC
P2[6]
NC
P0[0]
NC
NC
P0[2]
NC
P0[4]
NC
P0[6]
Vdd
Vdd
Vss
Vss
P6[0]
P6[1]
P6[2]
P6[3]
P6[4]
P6[5]
P6[6]
P6[7]
NC
P0[7]
NC
P0[5]
NC
P0[3]
NC
Ground connection.
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND)
No connection.
External Voltage Reference (VREF)
No connection.
Analog column mux input.
No connection.
No connection.
Analog column mux input and column output.
No connection.
Analog column mux input and column output.
No connection.
Analog column mux input.
Supply voltage.
Supply voltage.
Ground connection.
Ground connection.
No connection.
Analog column mux input.
No connection.
Analog column mux input and column output.
No connection.
Analog column mux input and column output.
No connection.
LEGEND: A = Analog, I = Input, and O = Output.
August 3, 2004
Document No. 38-12013 Rev. *F
12
CY8C29x66 Preliminary Data Sheet
1. Pin Information
August 3, 2004
NC
P0[2], AIO
NC
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
47
48
49
50
NC
NC
Document No. 38-12013 Rev. *F
46
43
44
45
P7[0]
54
53
52
51
XTALout, I2C SDA, P1[0]
P1[2]
EXTCLK, P1[4]
P1[6]
NC
42
P7[1]
P7[3]
P7[2]
39
40
41
36
37
38
P7[7]
P7[6]
P7[5]
P7[4]
32
33
34
35
NC
Vss
NC
Vdd
31
28
29
30
TQFP
26
27
77
76
79
78
80
Vdd
Vdd
P0[6], AI
NC
P0[4], AIO
82
81
P6[0]
Vss
Vss
85
84
83
P6[2]
P6[1]
87
86
90
89
88
P6[7]
P6[6]
P6[5]
P6[4]
P6[3]
NC
P0[7], AI
NC
95
94
93
92
91
96
P0[3], AIO
NC
P0[5], AIO
98
97
75
74
NC
I2C SDA, P1[5]
P1[3]
XTALin, I2C SCL, P1[1]
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
NC
NC
NC
AI, P0[1]
P2[7]
P2[5]
AI, P2[3]
AI, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
NC
NC
SMP
Vss
P3[7]
P3[5]
P3[3]
P3[1]
P5[7]
P5[5]
P5[3]
P5[1]
I2C SCL, P1[7]
NC
100
99
NC
CY8C29866 100-Pin PSoC Device
NC
P0[0], AI
NC
P2[6], External VREF
NC
P2[4], External AGND
P2[2], AI
P2[0], AI
P4[6]
P4[4]
Vss
P4[2]
P4[0]
XRES
NC
NC
P3[6]
P3[4]
P3[2]
P3[0]
P5[6]
P5[4]
P5[2]
P5[0]
NC
13
2. Register Reference
This chapter lists the registers of the CY8C29x66 PSoC device. For detailed register information, reference the PSoC™ Mixed Signal Array Technical Reference Manual.
2.1
2.1.1
Register Conventions
2.2
Abbreviations Used
The register conventions specific to this section are listed in the
following table.
Convention
Description
R
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
August 3, 2004
Register Mapping Tables
The PSoC device has a total register address space of 512
bytes. The register space is referred to as IO space and is
divided into two banks. The XOI bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XOI
bit is set the user is in bank 1.
Note In the following register mapping tables, blank fields are
reserved and should not be accessed.
Document No. 38-12013 Rev. *F
14
CY8C29x66 Preliminary Data Sheet
2. Register Reference
Register Map Bank 0 Table: User Space
RDI3RI
RDI3SYN
RDI3IS
RDI3LT0
RDI3LT1
RDI3RO0
RDI3RO1
CUR_PP
STK_PP
IDX_PP
MVR_PP
MVW_PP
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR2
INT_CLR3
INT_MSK3
INT_MSK2
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_DH
DEC_DL
DEC_CR0
DEC_CR1
MUL0_X
MUL0_Y
MUL0_DH
MUL0_DL
ACC0_DR1
ACC0_DR0
ACC0_DR3
ACC0_DR2
CPU_F
RW
RW
RW
RW
RW
RW
RW
CPU_SCR1
CPU_SCR0
Document No. 38-12013 Rev. *F
Access
W
W
R
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RDI2RI
RDI2SYN
RDI2IS
RDI2LT0
RDI2LT1
RDI2RO0
RDI2RO1
Addr
(0,Hex)
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
MUL1_X
A8
MUL1_Y
A9
MUL1_DH
AA
MUL1_DL
AB
ACC1_DR1
AC
ACC1_DR0
AD
ACC1_DR3
AE
ACC1_DR2
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDIOLT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
RDI1RI
B8
RDI1SYN
B9
RDI1IS
BA
RDI1LT0
BB
RDI1LT1
BC
RDI1RO0
BD
RDI1RO1
BE
BF
# Access is bit specific.
Access
RW
#
#
RW
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
ASC12CR0
ASC12CR1
ASC12CR2
ASC12CR3
ASD13CR0
ASD13CR1
ASD13CR2
ASD13CR3
ASD20CR0
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
ASD22CR0
ASD22CR1
ASD22CR2
ASD22CR3
ASC23CR0
ASC23CR1
ASC23CR2
ASC23CR3
Addr
(0,Hex)
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
RW
Name
August 3, 2004
Access
Addr
(0,Hex)
Name
Access
Addr
(0,Hex)
Name
PRT0DR
00
RW
DBB20DR0
40
PRT0IE
01
RW
DBB20DR1
41
PRT0GS
02
RW
DBB20DR2
42
PRT0DM2
03
RW
DBB20CR0
43
PRT1DR
04
RW
DBB21DR0
44
PRT1IE
05
RW
DBB21DR1
45
PRT1GS
06
RW
DBB21DR2
46
PRT1DM2
07
RW
DBB21CR0
47
PRT2DR
08
RW
DCB22DR0
48
PRT2IE
09
RW
DCB22DR1
49
PRT2GS
0A
RW
DCB22DR2
4A
PRT2DM2
0B
RW
DCB22CR0
4B
PRT3DR
0C
RW
DCB23DR0
4C
PRT3IE
0D
RW
DCB23DR1
4D
PRT3GS
0E
RW
DCB23DR2
4E
PRT3DM2
0F
RW
DCB23CR0
4F
PRT4DR
10
RW
DBB30DR0
50
PRT4IE
11
RW
DBB30DR1
51
PRT4GS
12
RW
DBB30DR2
52
PRT4DM2
13
RW
DBB30CR0
53
PRT5DR
14
RW
DBB31DR0
54
PRT5IE
15
RW
DBB31DR1
55
PRT5GS
16
RW
DBB31DR2
56
PRT5DM2
17
RW
DBB31CR0
57
PRT6DR
18
RW
DCB32DR0
58
PRT6IE
19
RW
DCB32DR1
59
PRT6GS
1A
RW
DCB32DR2
5A
PRT6DM2
1B
RW
DCB32CR0
5B
PRT7DR
1C
RW
DCB33DR0
5C
PRT7IE
1D
RW
DCB33DR1
5D
PRT7GS
1E
RW
DCB33DR2
5E
PRT7DM2
1F
RW
DCB33CR0
5F
DBB00DR0
20
#
AMX_IN
60
DBB00DR1
21
W
61
DBB00DR2
22
RW
62
DBB00CR0
23
#
ARF_CR
63
DBB01DR0
24
#
CMP_CR0
64
DBB01DR1
25
W
ASY_CR
65
DBB01DR2
26
RW
CMP_CR1
66
DBB01CR0
27
#
67
DCB02DR0
28
#
68
DCB02DR1
29
W
69
DCB02DR2
2A
RW
6A
DCB02CR0
2B
#
6B
DCB03DR0
2C
#
TMP0_DR
6C
DCB03DR1
2D
W
TMP1_DR
6D
DCB03DR2
2E
RW
TMP2_DR
6E
DCB03CR0
2F
#
TMP3_DR
6F
DBB10DR0
30
#
ACB00CR3
70
DBB10DR1
31
W
ACB00CR0
71
DBB10DR2
32
RW
ACB00CR1
72
DBB10CR0
33
#
ACB00CR2
73
DBB11DR0
34
#
ACB01CR3
74
DBB11DR1
35
W
ACB01CR0
75
DBB11DR2
36
RW
ACB01CR1
76
DBB11CR0
37
#
ACB01CR2
77
DCB12DR0
38
#
ACB02CR3
78
DCB12DR1
39
W
ACB02CR0
79
DCB12DR2
3A
RW
ACB02CR1
7A
DCB12CR0
3B
#
ACB02CR2
7B
DCB13DR0
3C
#
ACB03CR3
7C
DCB13DR1
3D
W
ACB03CR0
7D
DCB13DR2
3E
RW
ACB03CR1
7E
DCB13CR0
3F
#
ACB03CR2
7F
Blank fields are Reserved and should not be accessed.
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
#
RW
#
RW
RW
RW
RW
RW
RW
RW
RW
RC
W
RC
RC
RW
RW
W
W
R
R
RW
RW
RW
RW
RL
#
#
15
CY8C29x66 Preliminary Data Sheet
2. Register Reference
Register Map Bank 1 Table: Configuration Space
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
C0
C1
C2
C3
C4
C5
C6
C7
RDI3RI
C8
RDI3SYN
C9
RDI3IS
CA
RDI3LT0
CB
RDI3LT1
CC
RDI3RO0
CD
RDI3RO1
CE
CF
GDI_O_IN
D0
GDI_E_IN
D1
GDI_O_OU
D2
GDI_E_OU
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
OSC_GO_EN DD
OSC_CR4
DE
OSC_CR3
DF
OSC_CR0
E0
OSC_CR1
E1
OSC_CR2
E2
VLT_CR
E3
VLT_CMP
E4
E5
E6
DEC_CR2
E7
IMO_TR
E8
ILO_TR
E9
BDG_TR
EA
ECO_TR
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
CPU_F
F7
F8
F9
FLS_PR1
FA
FB
FC
FD
CPU_SCR1
FE
CPU_SCR0
FF
Document No. 38-12013 Rev. *F
Access
RW
RW
RW
RDI2RI
RDI2SYN
RDI2IS
RDI2LT0
RDI2LT1
RDI2RO0
RDI2RO1
Addr
(1,Hex)
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
RW
RW
RW
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDIOLT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
RDI1RI
B8
RDI1SYN
B9
RDI1IS
BA
RDI1LT0
BB
RDI1LT1
BC
RDI1RO0
BD
RDI1RO1
BE
BF
# Access is bit specific.
Access
RW
RW
RW
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
ASC12CR0
ASC12CR1
ASC12CR2
ASC12CR3
ASD13CR0
ASD13CR1
ASD13CR2
ASD13CR3
ASD20CR0
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
ASD22CR0
ASD22CR1
ASD22CR2
ASD22CR3
ASC23CR0
ASC23CR1
ASC23CR2
ASC23CR3
Addr
(1,Hex)
August 3, 2004
RW
RW
RW
Name
00
RW
DBB20FN
40
01
RW
DBB20IN
41
02
RW
DBB20OU
42
03
RW
43
04
RW
DBB21FN
44
05
RW
DBB21IN
45
06
RW
DBB21OU
46
07
RW
47
08
RW
DCB22FN
48
09
RW
DCB22IN
49
0A
RW
DCB22OU
4A
0B
RW
4B
0C
RW
DCB23FN
4C
0D
RW
DCB23IN
4D
0E
RW
DCB23OU
4E
0F
RW
4F
10
RW
DBB30FN
50
11
RW
DBB30IN
51
12
RW
DBB30OU
52
13
RW
53
14
RW
DBB31FN
54
15
RW
DBB31IN
55
16
RW
DBB31OU
56
17
RW
57
18
RW
DCB32FN
58
19
RW
DCB32IN
59
1A
RW
DCB32OU
5A
1B
RW
5B
1C
RW
DCB33FN
5C
1D
RW
DCB33IN
5D
1E
RW
DCB33OU
5E
1F
RW
5F
20
RW
CLK_CR0
60
21
RW
CLK_CR1
61
22
RW
ABF_CR0
62
23
AMD_CR0
63
DBB01FN
24
RW
64
DBB01IN
25
RW
65
DBB01OU
26
RW
AMD_CR1
66
27
ALT_CR0
67
DCB02FN
28
RW
ALT_CR1
68
DCB02IN
29
RW
CLK_CR2
69
DCB02OU
2A
RW
6A
2B
6B
DCB03FN
2C
RW
TMP0_DR
6C
DCB03IN
2D
RW
TMP1_DR
6D
DCB03OU
2E
RW
TMP2_DR
6E
2F
TMP3_DR
6F
DBB10FN
30
RW
ACB00CR3
70
DBB10IN
31
RW
ACB00CR0
71
DBB10OU
32
RW
ACB00CR1
72
33
ACB00CR2
73
DBB11FN
34
RW
ACB01CR3
74
DBB11IN
35
RW
ACB01CR0
75
DBB11OU
36
RW
ACB01CR1
76
37
ACB01CR2
77
DCB12FN
38
RW
ACB02CR3
78
DCB12IN
39
RW
ACB02CR0
79
DCB12OU
3A
RW
ACB02CR1
7A
3B
ACB02CR2
7B
DCB13FN
3C
RW
ACB03CR3
7C
DCB13IN
3D
RW
ACB03CR0
7D
DCB13OU
3E
RW
ACB03CR1
7E
3F
ACB03CR2
7F
Blank fields are Reserved and should not be accessed.
Access
Addr
(1,Hex)
Name
Access
Addr
(1,Hex)
Name
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
PRT3DM0
PRT3DM1
PRT3IC0
PRT3IC1
PRT4DM0
PRT4DM1
PRT4IC0
PRT4IC1
PRT5DM0
PRT5DM1
PRT5IC0
PRT5IC1
PRT6DM0
PRT6DM1
PRT6IC0
PRT6IC1
PRT7DM0
PRT7DM1
PRT7IC0
PRT7IC1
DBB00FN
DBB00IN
DBB00OU
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
RW
W
W
RW
W
RL
RW
#
#
16
3. Electrical Specifications
This chapter presents the DC and AC electrical specifications of the CY8C29x66 PSoC device. For the most up to date electrical
specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc.
Specifications are valid for -40oC ≤ TA ≤ 85oC and TJ ≤ 100oC, except where noted.
Refer to Table 3-16 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode.
5.25
4.75
Vdd Voltage
Vdd Voltage
lid ng
V a r at i n
p e io
O eg
R
4.75
SLIMO Mode = 0
5.25
3.60
SLIMO
Mode=1
SLIMO
Mode=0
SLIMO
Mode=1
SLIMO
Mode=0
3.00
3.00
93 kHz
12 MHz
24 MHz
93 kHz
6 MHz
12 MHz
24 MHz
IMO Frequency
CPU Frequency
Figure 3-1a. Voltage versus CPU Frequency
Figure 3-1b. IMO Frequency Trim Options
The following table lists the units of measure that are used in this chapter.
Table 3-1: Units of Measure
Symbol
Unit of Measure
Symbol
Unit of Measure
degree Celsius
µW
micro watts
dB
decibels
mA
milli-ampere
fF
femto farad
ms
milli-second
Hz
hertz
mV
milli-volts
KB
1024 bytes
nA
nano ampere
Kbit
1024 bits
ns
nanosecond
kHz
kilohertz
nV
nanovolts
kΩ
kilohm
Ω
ohm
MHz
megahertz
pA
pico ampere
MΩ
megaohm
pF
pico farad
µA
micro ampere
pp
peak-to-peak
µF
micro farad
ppm
µH
micro henry
ps
picosecond
µs
microsecond
sps
samples per second
µV
micro volts
σ
sigma: one standard deviation
micro volts root-mean-square
V
volts
o
C
µVrms
August 3, 2004
parts per million
Document No. 38-12013 Rev. *F
17
CY8C29x66 Preliminary Data Sheet
3.1
3. Electrical Specifications
Absolute Maximum Ratings
Table 3-2: Absolute Maximum Ratings
Symbol
Description
Min
Typ
Max
Units
TSTG
Storage Temperature
-55
–
+100
oC
TA
Ambient Temperature with Power Applied
-40
–
+85
o
Vdd
Supply Voltage on Vdd Relative to Vss
-0.5
–
+6.0
V
VIO
DC Input Voltage
Vss - 0.5
–
Vdd + 0.5 V
–
DC Voltage Applied to Tri-state
Vss - 0.5
–
Vdd + 0.5 V
IMIO
Maximum Current into any Port Pin
-25
–
+50
mA
IMAIO
Maximum Current into any Port Pin Configured as Analog
Driver
-50
–
+50
mA
ESD
Electro Static Discharge Voltage
2000
–
–
V
–
Latch-up Current
–
–
200
mA
3.2
Notes
Higher storage temperatures will reduce data
retention time.
C
Human Body Model ESD
Operating Temperature
Table 3-3: Operating Temperature
Symbol
Description
Min
Typ
Max
Units
TA
Ambient Temperature
-40
–
+85
oC
TJ
Junction Temperature
-40
–
+100
oC
August 3, 2004
Document No. 38-12013 Rev. *F
Notes
The temperature rise from ambient to junction is
package specific. See “Thermal Impedances”
on page 38. The user must limit the power consumption to comply with this requirement.
18
CY8C29x66 Preliminary Data Sheet
3.3
3.3.1
3. Electrical Specifications
DC Electrical Characteristics
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-4: DC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
Vdd
Supply Voltage
3.00
–
5.25
V
IDD
Supply Current
–
8
14
mA
Conditions are 5.0V, TA = 25 oC, CPU = 3 MHz,
48 MHz disabled. VC1 = 1.5 MHz, VC2 = 93.75
kHz, VC3 = 0.366 kHz.
IDD3
Supply Current
–
5
9
mA
Conditions are Vdd = 3.3V, TA = 25 oC, CPU = 3
MHz, 48 MHz = Disabled, VC1 = 1.5 MHz, VC2
= 93.75 kHz, VC3 = 0.366 kHz.
IDDP
Supply current when IMO = 6 MHz using SLIMO mode.
–
2
3
mA
Conditions are Vdd = 3.3V, TA = 25 oC, CPU =
0.75 MHz, 48 MHz = Disabled, VC1 = 0.375
MHz, VC2 = 23.44 kHz, VC3 = 0.09 kHz.
ISB
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,
and internal slow oscillator active.
–
3
10
µA
Conditions are with internal slow speed oscillator, Vdd = 3.3V, -40 oC ≤ TA ≤ 55 oC.
ISBH
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,
and internal slow oscillator active.
–
4
25
µA
Conditions are with internal slow speed oscillator, Vdd = 3.3V, 55 oC < TA ≤ 85 oC.
ISBXTL
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,
internal slow oscillator, and 32 kHz crystal oscillator active.
–
4
12
µA
Conditions are with properly loaded, 1 µW max,
32.768 kHz crystal. Vdd = 3.3V, -40 oC ≤ TA ≤ 55
oC.
ISBXTLH
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,
and 32 kHz crystal oscillator active.
–
5
µA
27
Conditions are with properly loaded, 1 µW max,
32.768 kHz crystal. Vdd = 3.3V, 55 oC < TA ≤ 85
oC.
VREF
3.3.2
Reference Voltage (Bandgap)
1.28
1.3
1.32
V
Trimmed for appropriate Vdd.
DC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-5: DC GPIO Specifications
Symbol
Description
Min
4
Typ
5.6
Max
8
Units
Notes
kΩ
RPU
Pull up Resistor
RPD
Pull down Resistor
4
5.6
8
kΩ
VOH
High Output Level
Vdd - 1.0
–
–
V
IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads,
4 on even port pins (for example, P0[2], P1[4]),
4 on odd port pins (for example, P0[3], P1[5])).
VOL
Low Output Level
–
–
0.75
V
IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads,
4 on even port pins (for example, P0[2], P1[4]),
4 on odd port pins (for example, P0[3], P1[5])).
0.8
V
Vdd = 3.0 to 5.25
V
Vdd = 3.0 to 5.25
VIL
Input Low Level
–
–
VIH
Input High Level
2.1
–
VH
Input Hysterisis
–
60
–
mV
IIL
Input Leakage (Absolute Value)
–
1
–
nA
Gross tested to 1 µA.
CIN
Capacitive Load on Pins as Input
–
3.5
10
pF
Package and pin dependent. Temp = 25oC.
COUT
Capacitive Load on Pins as Output
–
3.5
10
pF
Package and pin dependent. Temp = 25oC.
August 3, 2004
Document No. 38-12013 Rev. *F
19
CY8C29x66 Preliminary Data Sheet
3.3.3
3. Electrical Specifications
DC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor
PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to
5V at 25°C and are for design guidance only.
Table 3-6: 5V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Min
Typ
Max
Units
Notes
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
–
1.6
10
mV
Power = Medium, Opamp Bias = High
–
1.3
8
mV
Power = High, Opamp Bias = High
–
1.2
7.5
mV
TCVOSOA
Average Input Offset Voltage Drift
–
7.0
35.0
µV/oC
IEBOA
Input Leakage Current (Port 0 Analog Pins)
–
200
–
pA
Gross tested to 1 µA.
CINOA
Input Capacitance (Port 0 Analog Pins)
–
4.5
9.5
pF
Package and pin dependent. Temp = 25 oC.
VCMOA
Common Mode Voltage Range. All Cases, except highest.
0.0
–
Vdd
V
V
Power = High, Opamp Bias = High
0.5
–
Vdd - 0.5
CMRROA
Common Mode Rejection Ratio
60
–
–
dB
GOLOA
Open Loop Gain
80
–
–
dB
VOHIGHOA
High Output Voltage Swing (internal signals)
Vdd - .01
–
–
V
VOLOWOA
Low Output Voltage Swing (internal signals)
–
–
0.1
V
ISOA
Supply Current (including associated AGND buffer)
Power = Low, Opamp Bias = Low
–
150
200
µA
Power = Low, Opamp Bias = High
–
300
400
µA
Power = Medium, Opamp Bias = Low
–
600
800
µA
Power = Medium, Opamp Bias = High
–
1200
1600
µA
Power = High, Opamp Bias = Low
–
2400
3200
µA
Power = High, Opamp Bias = High
–
4600
6400
µA
Supply Voltage Rejection Ratio
67
–
–
dB
PSRROA
0V ≤ VIN ≤ (Vdd - 2.25) or
(Vdd - 1.25V) ≤ VIN ≤ Vdd.
Table 3-7: 3.3V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Min
Typ
Max
Units
Notes
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
–
1.65
10
mV
Power = Medium, Opamp Bias = High
–
1.32
8
mV
–
7.0
35.0
µV/oC
High Power is 5 Volts Only
TCVOSOA
Average Input Offset Voltage Drift
IEBOA
Input Leakage Current (Port 0 Analog Pins)
–
200
–
pA
Gross tested to 1 µA.
CINOA
Input Capacitance (Port 0 Analog Pins)
–
4.5
9.5
pF
Package and pin dependent. Temp = 25 oC.
VCMOA
Common Mode Voltage Range
0
–
Vdd
V
CMRROA
Common Mode Rejection Ratio
60
–
–
dB
GOLOA
Open Loop Gain
80
–
–
dB
VOHIGHOA
High Output Voltage Swing (internal signals)
Vdd - .01
–
–
V
VOLOWOA
Low Output Voltage Swing (internal signals)
–
–
.01
V
August 3, 2004
Document No. 38-12013 Rev. *F
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CY8C29x66 Preliminary Data Sheet
3. Electrical Specifications
Table 3-7: 3.3V DC Operational Amplifier Specifications (continued)
ISOA
PSRROA
3.3.4
Supply Current (including associated AGND buffer)
Power = Low, Opamp Bias = Low
–
150
200
µA
Power = Low, Opamp Bias = High
–
300
400
µA
Power = Medium, Opamp Bias = Low
–
600
800
µA
Power = Medium, Opamp Bias = High
–
1200
1600
µA
Power = High, Opamp Bias = Low
–
2400
3200
µA
Power = High, Opamp Bias = High
–
–
–
Supply Voltage Rejection Ratio
54
–
–
Not Allowed
0V ≤ VIN ≤ (Vdd - 2.25) or
(Vdd - 1.25V) ≤ VIN ≤ Vdd.
dB
DC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-8: 5V DC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
VOSOB
Input Offset Voltage (Absolute Value)
–
3
12
mV
TCVOSOB
Average Input Offset Voltage Drift
–
+6
–
µV/°C
VCMOB
Common-Mode Input Voltage Range
0.5
–
Vdd - 1.0
V
ROUTOB
Output Resistance
Power = Low
–
–
1
Ω
Power = High
–
–
1
Ω
High Output Voltage Swing (Load = 32 ohms to Vdd/2)
Power = Low
0.5 x Vdd + 1.3 –
–
V
0.5 x Vdd + 1.3 –
–
V
VOHIGHOB
Power = High
VOLOWOB
ISOB
PSRROB
Notes
Low Output Voltage Swing (Load = 32 ohms to Vdd/2)
Power = Low
–
–
0.5 x Vdd - 1.3
V
Power = High
–
–
0.5 x Vdd - 1.3
V
Power = Low
–
1.1
2
mA
Power = High
–
2.6
5
mA
Supply Voltage Rejection Ratio
40
–
–
dB
Supply Current Including Bias Cell (No Load)
Table 3-9: 3.3V DC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
VOSOB
Input Offset Voltage (Absolute Value)
–
3
12
mV
TCVOSOB
Average Input Offset Voltage Drift
–
+6
–
µV/°C
VCMOB
Common-Mode Input Voltage Range
0.5
-
Vdd - 1.0
V
ROUTOB
Output Resistance
Power = Low
–
–
10
Ω
Power = High
–
–
10
Ω
VOHIGHOB
VOLOWOB
Notes
High Output Voltage Swing (Load = 1k ohms to Vdd/2)
Power = Low
0.5 x Vdd + 1.0 –
–
V
Power = High
0.5 x Vdd + 1.0 –
–
V
Power = Low
–
–
0.5 x Vdd - 1.0
V
Power = High
–
–
0.5 x Vdd - 1.0
V
Low Output Voltage Swing (Load = 1k ohms to Vdd/2)
August 3, 2004
Document No. 38-12013 Rev. *F
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CY8C29x66 Preliminary Data Sheet
3. Electrical Specifications
Table 3-9: 3.3V DC Analog Output Buffer Specifications (continued)
ISOB
Supply Current Including Bias Cell (No Load)
Power = Low
PSRROB
3.3.5
0.8
1
mA
Power = High
–
2.0
5
mA
Supply Voltage Rejection Ratio
60
–
–
dB
DC Switch Mode Pump Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-10: DC Switch Mode Pump (SMP) Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
VPUMP 5V
5V Output Voltage at Vdd from Pump
4.75
5.0
5.25
V
Configuration of footnote a. Average, neglecting ripple. SMP
trip voltage is set to 5.0V.
VPUMP 3V
3V Output Voltage at Vdd from Pump
3.00
3.25
3.60
V
Configuration of footnote a. Average, neglecting ripple. SMP
trip voltage is set to 3.25V.
IPUMP
Available Output Current
VBAT = 1.5V, VPUMP = 3.25V
8
–
–
mA
SMP trip voltage is set to 3.25V.
VBAT = 1.8V, VPUMP = 5.0V
5
–
–
mA
SMP trip voltage is set to 5.0V.
VBAT5V
Input Voltage Range from Battery
1.8
–
5.0
V
Configuration of footnote a. SMP trip voltage is set to 5.0V.
VBAT3V
Input Voltage Range from Battery
1.0
–
3.3
V
Configuration of footnote a. SMP trip voltage is set to 3.25V.
VBATSTART
Minimum Input Voltage from Battery to
Start Pump
1.2
–
–
V
Configuration of footnote a. 0oC ≤ TA ≤ 100. 1.25V at TA = -
∆VPUMP_Line
Line Regulation (over VBAT range)
–
5
–
%VO
Configuration of footnote a. VO is the “Vdd Value for PUMP
Trip” specified by the VM[2:0] setting in the DC POR and
LVD Specification, Table 3-14 on page 24.
∆VPUMP_Load
Load Regulation
–
5
–
%VO
Configuration of footnote a. VO is the “Vdd Value for PUMP
Trip” specified by the VM[2:0] setting in the DC POR and
LVD Specification, Table 3-14 on page 24.
∆VPUMP_Ripple Output Voltage Ripple (depends on capaci- –
tor/load)
100
–
mVpp
Configuration of footnote a. Load is 5 mA.
E3
Efficiency
50
–
%
Configuration of footnote a. Load is 5 mA. SMP trip voltage
is set to 3.25V.
FPUMP
Switching Frequency
–
1.4
–
MHz
DCPUMP
Switching Duty Cycle
–
50
–
%
Configuration of footnote a.
40oC.
35
a. L1 = 2 µH inductor, C1 = 10 µF capacitor, D1 = Schottky diode. See Figure 3-2.
D1
Vdd
L1
VBAT
+
VPUMP
C1
SMP
Battery
PSoCTM
Vss
Figure 3-2. Basic Switch Mode Pump Circuit
August 3, 2004
Document No. 38-12013 Rev. *F
22
CY8C29x66 Preliminary Data Sheet
3.3.6
3. Electrical Specifications
DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Reference control power is high.
Table 3-11: 5V DC Analog Reference Specifications
Symbol
VBG5
Description
Bandgap Voltage Reference 5V
1.28
1.30
1.32
V
–
AGND = Vdd/2a
Vdd/2 - 0.02
Vdd/2
Vdd/2 + 0.02
V
2.52
2.60
2.72
V
P2[4] - 0.013
P2[4]
P2[4] + 0.013
V
1.27
1.3
1.34
V
–
AGND = 2 x
–
BandGapa
AGND = P2[4] (P2[4] =
–
AGND =
Min
Vdd/2)a
BandGapa
Typ
Max
Units
–
AGND = 1.6 x
2.03
2.08
2.13
V
–
-0.034
0.000
0.034
V
–
AGND Block to Block Variation (AGND = Vdd/2)a
RefHi = Vdd/2 + BandGap
Vdd/2 + 1.21
Vdd/2 + 1.3
Vdd/2 + 1.382
V
–
–
–
–
–
–
–
RefHi = 3 x BandGap
RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
RefHi = 2 x BandGap
RefHi = 3.2 x BandGap
RefLo = Vdd/2 – BandGap
3.75
P2[6] + 2.478
P2[4] + 1.218
P2[4] + P2[6] - 0.058
2.50
4.02
3.9
P2[6] + 2.6
P2[4] + 1.3
P2[4] + P2[6]
2.60
4.16
4.05
P2[6] + 2.722
P2[4] + 1.382
P2[4] + P2[6] + 0.058
2.70
4.29
Vdd/2 - 1.369
Vdd/2 - 1.30
Vdd/2 - 1.231
V
V
V
V
V
V
V
–
–
–
–
RefLo = BandGap
RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
1.20
2.489 - P2[6]
P2[4] - 1.368
P2[4] - P2[6] - 0.042
1.30
2.6 - P2[6]
P2[4] - 1.30
P2[4] - P2[6]
1.40
2.711 - P2[6]
P2[4] - 1.232
P2[4] - P2[6] + 0.042
V
V
V
V
BandGapa
a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V.
Table 3-12: 3.3V DC Analog Reference Specifications
Symbol
VBG33
Description
Bandgap Voltage Reference 3.3V
1.28
1.30
1.32
V
–
AGND = Vdd/2a
Vdd/2 - 0.02
Vdd/2
Vdd/2 + 0.02
V
P2[4] - 0.009
1.27
P2[4]
1.30
P2[4] + 0.009
1.34
V
V
2.03
2.08
2.13
V
-0.034
0.000
0.034
mV
P2[4] + P2[6]
2.60
P2[4] + P2[6] + 0.042
2.70
V
V
P2[4] - P2[6]
P2[4] - P2[6] + 0.036
V
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Min
BandGapa
Typ
Max
Units
Not Allowed
AGND = 2 x
AGND = P2[4] (P2[4] = Vdd/2)
AGND = BandGapa
AGND = 1.6 x BandGapa
Vdd/2)a
AGND Block to Block Variation (AGND =
RefHi = Vdd/2 + BandGap
RefHi = 3 x BandGap
RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
RefHi = 2 x BandGap
RefHi = 3.2 x BandGap
RefLo = Vdd/2 - BandGap
RefLo = BandGap
RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
Not Allowed
Not Allowed
Not Allowed
Not Allowed
P2[4] + P2[6] - 0.042
2.50
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
P2[4] - P2[6] - 0.036
a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V.
August 3, 2004
Document No. 38-12013 Rev. *F
23
CY8C29x66 Preliminary Data Sheet
3.3.7
3. Electrical Specifications
DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-13: DC Analog PSoC Block Specifications
Symbol
Description
Min
Typ
Max
Units
RCT
Resistor Unit Value (Continuous Time)
–
12.2
–
kΩ
CSC
Capacitor Unit Value (Switch Cap)
–
80
–
fF
3.3.8
Notes
DC POR, SMP, and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-14: DC POR, SMP, and LVD Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
Vdd Value for PPOR Trip (positive ramp)
VPPOR0R
PORLEV[1:0] = 00b
VPPOR1R
PORLEV[1:0] = 01b
VPPOR2R
PORLEV[1:0] = 10b
2.91
–
4.39
V
–
4.55
V
V
Vdd Value for PPOR Trip (negative ramp)
VPPOR0
PORLEV[1:0] = 00b
VPPOR1
PORLEV[1:0] = 01b
VPPOR2
PORLEV[1:0] = 10b
2.82
–
4.39
V
–
4.55
V
V
PPOR Hysteresis
VPH0
PORLEV[1:0] = 00b
–
92
–
mV
VPH1
PORLEV[1:0] = 01b
–
0
–
mV
VPH2
PORLEV[1:0] = 10b
–
0
–
mV
Vdd Value for LVD Trip
VLVD0
VM[2:0] = 000b
2.86
2.92
2.98a
V
VLVD1
VM[2:0] = 001b
2.96
3.02
3.08
VLVD2
VM[2:0] = 010b
3.07
3.13
3.20
VLVD3
VM[2:0] = 011b
3.92
4.00
4.08
VLVD4
VM[2:0] = 100b
4.39
4.48
4.57
VLVD5
VM[2:0] = 101b
4.55
4.64
4.74b
VLVD6
VM[2:0] = 110b
4.63
4.73
4.82
VLVD7
VM[2:0] = 111b
4.72
4.81
4.91
V
V
V
V
V
V
V
V
Vdd Value for SMP Trip
VPUMP0
VM[2:0] = 000b
2.96
3.02
3.08
VPUMP1
VM[2:0] = 001b
3.03
3.10
3.16
VPUMP2
VM[2:0] = 010b
3.18
3.25
3.32
VPUMP3
VM[2:0] = 011b
4.11
4.19
4.28
VPUMP4
VM[2:0] = 100b
4.55
4.64
4.74
VPUMP5
VM[2:0] = 101b
4.63
4.73
4.82
VPUMP6
VM[2:0] = 110b
4.72
4.82
4.91
VPUMP7
VM[2:0] = 111b
4.90
5.00
5.10
V
V
V
V
V
V
V
V
V
a. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.
b. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.
August 3, 2004
Document No. 38-12013 Rev. *F
24
CY8C29x66 Preliminary Data Sheet
3.3.9
3. Electrical Specifications
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-15: DC Programming Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
IDDP
Supply Current During Programming or Verify
–
10
30
mA
VILP
Input Low Voltage During Programming or Verify
–
–
0.8
V
VIHP
Input High Voltage During Programming or Verify
2.2
–
–
V
IILP
Input Current when Applying Vilp to P1[0] or P1[1] During
Programming or Verify
–
–
0.2
mA
Driving internal pull-down resistor.
IIHP
Input Current when Applying Vihp to P1[0] or P1[1] During
Programming or Verify
–
–
1.5
mA
Driving internal pull-down resistor.
VOLV
Output Low Voltage During Programming or Verify
–
–
Vss + 0.75 V
VOHV
Output High Voltage During Programming or Verify
Vdd - 1.0
–
Vdd
V
FlashENPB
Flash Endurance (per block)
50,000
–
–
–
Erase/write cycles per block.
1,800,000
–
–
–
Erase/write cycles.
10
–
–
Years
FlashENT
Flash Endurance
FlashDR
Flash Data Retention
(total)a
a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of
25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than
50,000 cycles).
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to
the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
August 3, 2004
Document No. 38-12013 Rev. *F
25
CY8C29x66 Preliminary Data Sheet
3.4
3. Electrical Specifications
AC Electrical Characteristics
3.4.1
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Note See the individual user module data sheets for information on maximum frequencies for user modules.
Table 3-16: AC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
FIMO24
Internal Main Oscillator Frequency for 24 MHz
23.4
24
24.6a,b,c
MHz
Trimmed for 5V or 3.3V operation using
factory trim values. See Figure 3-1b on
page 17. SLIMO Mode = 0.
FIMO6
Internal Main Oscillator Frequency for 6 MHz
5.75
6
6.35a,b,c
MHz
Trimmed for 5V or 3.3V operation using
factory trim values. See Figure 3-1b on
page 17. SLIMO Mode = 1.
FCPU1
CPU Frequency (5V Nominal)
0.93
24
24.6a,b
MHz
FCPU2
CPU Frequency (3.3V Nominal)
0.93
12
12.3b,c
MHz
F48M
Digital PSoC Block Frequency
0
48
49.2a,b,d
MHz
F24M
Digital PSoC Block Frequency
0
24
24.6b, d
MHz
F32K1
Internal Low Speed Oscillator Frequency
15
32
64
kHz
F32K2
External Crystal Oscillator
–
32.768
–
kHz
Accuracy is capacitor and crystal dependent.
50% duty cycle.
FPLL
PLL Frequency
–
23.986
–
MHz
A multiple (x732) of crystal frequency.
Jitter24M2
24 MHz Period Jitter (PLL)
–
–
600
ps
TPLLSLEW
PLL Lock Time
0.5
–
10
ms
TPLLSLEWLOW
PLL Lock Time for Low Gain Setting
0.5
–
50
ms
TOS
External Crystal Oscillator Startup to 1%
–
250
500
ms
TOSACC
External Crystal Oscillator Startup to 100 ppm
–
300
600
ms
Jitter32k
32 kHz Period Jitter
–
100
TXRST
External Reset Pulse Width
10
–
–
µs
DC24M
24 MHz Duty Cycle
40
50
60
%
Step24M
24 MHz Trim Step Size
–
50
–
kHz
Fout48M
48 MHz Output Frequency
46.8
48.0
49.2a,c
MHz
Jitter24M1
24 MHz Period Jitter (IMO)
–
600
FMAX
Maximum frequency of signal on row input or row output.
–
–
12.3
MHz
TRAMP
Supply Ramp Time
0
–
–
µs
a.
b.
c.
d.
Refer to the AC Digital Block Specifications below.
The crystal oscillator frequency is within 100 ppm
of its final value by the end of the Tosacc period.
Correct operation assumes a properly loaded 1 uW
maximum drive level 32.768 kHz crystal. 3.0V ≤
Vdd ≤ 5.5V, -40 oC ≤ TA ≤ 85 oC.
ns
Trimmed. Utilizing factory trim values.
ps
4.75V < Vdd < 5.25V.
Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
3.0V < Vdd < 3.6V.
See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for 3.3V operation.
August 3, 2004
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CY8C29x66 Preliminary Data Sheet
3. Electrical Specifications
PLL
Enable
TPLLSLEW
24 MHz
FPLL
PLL
Gain
0
Figure 3-3. PLL Lock Timing Diagram
PLL
Enable
TPLLSLEWLOW
24 MHz
FPLL
PLL
Gain
1
Figure 3-4. PLL Lock for Low Gain Setting Timing Diagram
32K
Select
32 kHz
TOS
F32K2
Figure 3-5. External Crystal Oscillator Startup Timing Diagram
Jitter24M1
F24M
Figure 3-6. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter32k
F32K2
Figure 3-7. 32 kHz Period Jitter (ECO) Timing Diagram
August 3, 2004
Document No. 38-12013 Rev. *F
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CY8C29x66 Preliminary Data Sheet
3.4.2
3. Electrical Specifications
AC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-17: AC GPIO Specifications
Symbol
FGPIO
Description
Min
Typ
Max
Units
Notes
GPIO Operating Frequency
0
–
12
MHz
TRiseF
Rise Time, Normal Strong Mode, Cload = 50 pF
3
–
18
ns
Vdd = 4.75 to 5.25V, 10% - 90%
TFallF
Fall Time, Normal Strong Mode, Cload = 50 pF
2
–
18
ns
Vdd = 4.75 to 5.25V, 10% - 90%
TRiseS
Rise Time, Slow Strong Mode, Cload = 50 pF
10
27
–
ns
Vdd = 3 to 5.25V, 10% - 90%
TFallS
Fall Time, Slow Strong Mode, Cload = 50 pF
10
22
–
ns
Vdd = 3 to 5.25V, 10% - 90%
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
TFallF
TFallS
Figure 3-8. GPIO Timing Diagram
August 3, 2004
Document No. 38-12013 Rev. *F
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CY8C29x66 Preliminary Data Sheet
3.4.3
3. Electrical Specifications
AC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Power = High and Opamp Bias = High is not supported at 3.3V.
Table 3-18: 5V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
ENOA
Description
Min
Typ
Max
Units
Notes
Rising Settling Time to 0.1% for a 1V Step (10 pF load,
Unity Gain)
Power = Low, Opamp Bias = Low
–
–
3.9
µs
Power = Medium, Opamp Bias = High
–
–
0.72
µs
Power = High, Opamp Bias = High
–
–
0.62
µs
Power = Low, Opamp Bias = Low
–
–
5.9
µs
Power = Medium, Opamp Bias = High
–
–
0.92
µs
Power = High, Opamp Bias = High
–
–
0.72
µs
Power = Low, Opamp Bias = Low
0.15
–
–
V/µs
Power = Medium, Opamp Bias = High
1.7
–
–
V/µs
Power = High, Opamp Bias = High
6.5
–
–
V/µs
Power = Low, Opamp Bias = Low
0.01
–
–
V/µs
Power = Medium, Opamp Bias = High
0.5
–
–
V/µs
Power = High, Opamp Bias = High
4.0
–
–
V/µs
Power = Low, Opamp Bias = Low
0.75
–
–
MHz
Power = Medium, Opamp Bias = High
3.1
–
–
MHz
Power = High, Opamp Bias = High
5.4
–
–
MHz
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
–
100
–
nV/rt-Hz
Falling Settling Time to 0.1% for a 1V Step (10 pF load,
Unity Gain)
Rising Slew Rate (20% to 80%) of a 1V Step (10 pF load,
Unity Gain)
Falling Slew Rate (20% to 80%) of a 1V Step (10 pF load,
Unity Gain)
Gain Bandwidth Product
Table 3-19: 3.3V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
ENOA
Description
Min
Typ
Max
Units
Notes
Rising Settling Time to 0.1% of a 1V Step (10 pF load, Unity
Gain)
Power = Low, Opamp Bias = Low
–
–
3.92
µs
Power = Medium, Opamp Bias = High
–
–
0.72
µs
Power = Low, Opamp Bias = Low
–
–
5.41
µs
Power = Medium, Opamp Bias = High
–
–
0.72
µs
Power = Low, Opamp Bias = Low
0.31
–
–
V/µs
Power = Medium, Opamp Bias = High
2.7
–
–
V/µs
Power = Low, Opamp Bias = Low
0.24
–
–
V/µs
Power = Medium, Opamp Bias = High
1.8
–
–
V/µs
Power = Low, Opamp Bias = Low
0.67
–
–
MHz
Power = Medium, Opamp Bias = High
2.8
–
–
MHz
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
–
100
–
nV/rt-Hz
Falling Settling Time to 0.1% of a 1V Step (10 pF load,
Unity Gain)
Rising Slew Rate (20% to 80%) of a 1V Step (10 pF load,
Unity Gain)
Falling Slew Rate (20% to 80%) of a 1V Step (10 pF load,
Unity Gain)
Gain Bandwidth Product
August 3, 2004
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CY8C29x66 Preliminary Data Sheet
3.4.4
3. Electrical Specifications
AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-20: AC Digital Block Specifications
Function
Description
Min
Typ
Max
Units
All
Functions
Maximum Block Clocking Frequency (> 4.75V)
Timer
Capture Pulse Width
50a
–
–
ns
Maximum Frequency, No Capture
–
–
49.2
MHz
Maximum Frequency, With Capture
–
–
24.6
MHz
Enable Pulse Width
50a
–
–
ns
Maximum Frequency, No Enable Input
–
–
49.2
MHz
Maximum Frequency, Enable Input
–
–
24.6
MHz
Asynchronous Restart Mode
20
–
–
ns
Synchronous Restart Mode
50a
–
–
ns
a
–
–
ns
Counter
Dead Band
49.2
Maximum Block Clocking Frequency (< 4.75V)
Notes
4.75V < Vdd < 5.25V.
24.6
3.0V < Vdd < 4.75V.
4.75V < Vdd < 5.25V.
4.75V < Vdd < 5.25V.
Kill Pulse Width:
Disable Mode
50
–
–
49.2
MHz
4.75V < Vdd < 5.25V.
CRCPRS
Maximum Input Clock Frequency
(PRS Mode)
Maximum Frequency
–
–
49.2
MHz
4.75V < Vdd < 5.25V.
CRCPRS
Maximum Input Clock Frequency
(CRC Mode)
–
–
24.6
MHz
SPIM
Maximum Input Clock Frequency
–
–
8.2
MHz
SPIS
Maximum Input Clock Frequency
–
–
4.1
ns
Width of SS_ Negated Between Transmissions
50a
–
–
ns
Transmitter
Maximum Input Clock Frequency
–
–
24.6
MHz
Maximum data rate at 3.08 MHz due to 8 x over
clocking.
Receiver
Maximum Input Clock Frequency
–
–
24.6
MHz
Maximum data rate at 3.08 MHz due to 8 x over
clocking.
Maximum data rate at 4.1 MHz due to 2 x over
clocking.
a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
August 3, 2004
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CY8C29x66 Preliminary Data Sheet
3.4.5
3. Electrical Specifications
AC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-21: 5V AC Analog Output Buffer Specifications
Symbol
TROB
TSOB
SRROB
SRFOB
BWOB
BWOB
Description
Min
Typ
Max
Units
Notes
Rising Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
–
–
4
µs
Power = High
–
–
4
µs
Power = Low
–
–
3.4
µs
Power = High
–
–
3.4
µs
Power = Low
0.5
–
–
V/µs
Power = High
0.5
–
–
V/µs
Power = Low
0.55
–
–
V/µs
Power = High
0.55
–
–
V/µs
Power = Low
0.8
–
–
MHz
Power = High
0.8
–
–
MHz
Power = Low
300
–
–
kHz
Power = High
300
–
–
kHz
Falling Settling Time to 0.1%, 1V Step, 100pF Load
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load
Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load
Table 3-22: 3.3V AC Analog Output Buffer Specifications
Symbol
TROB
TSOB
SRROB
SRFOB
BWOB
BWOB
Description
Min
Typ
Max
Units
Notes
Rising Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
–
–
4.7
µs
Power = High
–
–
4.7
µs
Power = Low
–
–
4
µs
Power = High
–
–
4
µs
Power = Low
.36
–
–
V/µs
Power = High
.36
–
–
V/µs
Power = Low
.4
–
–
V/µs
Power = High
.4
–
–
V/µs
Power = Low
0.7
–
–
MHz
Power = High
0.7
–
–
MHz
Power = Low
200
–
–
kHz
Power = High
200
–
–
kHz
Falling Settling Time to 0.1%, 1V Step, 100pF Load
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load
Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load
August 3, 2004
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CY8C29x66 Preliminary Data Sheet
3.4.6
3. Electrical Specifications
AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-23: 5V AC External Clock Specifications
Symbol
FOSCEXT
Description
Min
Frequency
Typ
Max
0.093
–
24.6
Units
Notes
MHz
–
High Period
20.6
–
5300
ns
–
Low Period
20.6
–
–
ns
–
Power Up IMO to Switch
150
–
–
µs
Table 3-24: 3.3V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
FOSCEXT
Frequency with CPU Clock divide by 1
0.093
–
12.3
MHz
Maximum CPU frequency is 12 MHz at 3.3V.
With the CPU clock divider set to 1, the
external clock must adhere to the maximum
frequency and duty cycle requirements.
FOSCEXT
Frequency with CPU Clock divide by 2 or greater
0.186
–
24.6
MHz
If the frequency of the external clock is
greater than 12 MHz, the CPU clock divider
must be set to 2 or greater. In this case, the
CPU clock divider will ensure that the fifty
percent duty cycle requirement is met.
–
High Period with CPU Clock divide by 1
41.7
–
5300
ns
–
Low Period with CPU Clock divide by 1
41.7
–
–
ns
–
Power Up IMO to Switch
150
–
–
µs
3.4.7
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-25: AC Programming Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
TRSCLK
Rise Time of SCLK
1
–
20
ns
TFSCLK
Fall Time of SCLK
1
–
20
ns
TSSCLK
Data Set up Time to Falling Edge of SCLK
40
–
–
ns
THSCLK
Data Hold Time from Falling Edge of SCLK
40
–
–
ns
FSCLK
Frequency of SCLK
0
–
8
MHz
TERASEB
Flash Erase Time (Block)
–
10
–
ms
TWRITE
Flash Block Write Time
–
10
–
ms
TDSCLK
Data Out Delay from Falling Edge of SCLK
–
–
45
ns
Vdd > 3.6
TDSCLK3
Data Out Delay from Falling Edge of SCLK
–
–
50
ns
3.0 ≤ Vdd ≤ 3.6
August 3, 2004
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CY8C29x66 Preliminary Data Sheet
3.4.8
3. Electrical Specifications
AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-26: AC Characteristics of the I2C SDA and SCL Pins
Standard Mode
Symbol
Description
Min
Fast Mode
Max
Min
Max
Units
FSCLI2C
SCL Clock Frequency
0
100
0
400
kHz
THDSTAI2C
Hold Time (repeated) START Condition. After this
period, the first clock pulse is generated.
4.0
–
0.6
–
µs
TLOWI2C
LOW Period of the SCL Clock
4.7
–
1.3
–
µs
THIGHI2C
HIGH Period of the SCL Clock
4.0
–
0.6
–
µs
TSUSTAI2C
Set-up Time for a Repeated START Condition
4.7
–
0.6
–
µs
THDDATI2C
Data Hold Time
0
–
0
–
µs
TSUDATI2C
Data Set-up Time
250
–
100
–
ns
TSUSTOI2C
Set-up Time for STOP Condition
4.0
–
0.6
–
µs
TBUFI2C
Bus Free Time Between a STOP and START Condition 4.7
–
1.3
–
µs
TSPI2C
Pulse Width of spikes are suppressed by the input filter.
–
0
50
ns
–
a
Notes
a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be
the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data
bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
SDA
TLOWI2C
TSUDATI2C
THDSTAI2C
TSPI2C
TBUFI2C
SCL
S THDSTAI2C THDDATI2C THIGHI2C
TSUSTAI2C
Sr
TSUSTOI2C
P
S
Figure 3-9. Definition for Timing for Fast/Standard Mode on the I2C Bus
August 3, 2004
Document No. 38-12013 Rev. *F
33
4. Packaging Information
This chapter illustrates the packaging specifications for the CY8C29x66 PSoC device, along with the thermal impedances for each
package and the typical package capacitance on crystal pins.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/support/link.cfm?mr=poddim.
4.1
Packaging Dimensions
51-85014 - *D
Figure 4-1. 28-Lead (300-Mil) Molded DIP
August 3, 2004
Document No. 38-12013 Rev. *F
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CY8C29x66 Preliminary Data Sheet
4. Packaging Information
51-85079 - *C
Figure 4-2. 28-Lead (210-Mil) SSOP
51-85026 - *C
Figure 4-3. 28-Lead (300-Mil) SOIC
August 3, 2004
Document No. 38-12013 Rev. *F
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CY8C29x66 Preliminary Data Sheet
4. Packaging Information
51-85064 - *B
Figure 4-4. 44-Lead TQFP
51-85061 - *C
51 -850 61-C
Figure 4-5. 48-Lead (300-Mil) SSOP
August 3, 2004
Document No. 38-12013 Rev. *F
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CY8C29x66 Preliminary Data Sheet
4. Packaging Information
51-85152-*B
Figure 4-6. 48-Lead (7x7 mm) MLF
51-85161 - **
Figure 4-7. 100-Lead TQFP
August 3, 2004
Document No. 38-12013 Rev. *F
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CY8C29x66 Preliminary Data Sheet
4.2
4. Packaging Information
Thermal Impedances
Table 4-1. Thermal Impedances per Package
Package
Typical
θJA *
28 PDIP
69
28 SSOP
96 oC/W
28 SOIC
74 oC/W
oC/W
44 TQFP
60 oC/W
48 SSOP
69 oC/W
48 MLF
28 oC/W
100 TQFP
48 oC/W
* TJ = TA + POWER x θJA
4.3
Capacitance on Crystal Pins
Table 4-2: Typical Package Capacitance on Crystal Pins
Package
Package Capacitance
28 PDIP
3.5 pF
28 SSOP
2.8 pF
28 SOIC
2.7 pF
44 TQFP
2.6 pF
48 SSOP
3.3 pF
48 MLF
1.8 pF
100 TQFP
3.1 pF
August 3, 2004
Document No. 38-12013 Rev. *F
38
5. Ordering Information
The following table lists the CY8C29x66 PSoC device family’s key package features and ordering codes.
5.1
Digital IO
Pins
Analog
Inputs
Analog
Outputs
XRES Pin
(Columns of 3)
Temperature
Range
Analog PSoC
Blocks
Switch Mode
Pump
32
32
2K
2K
Yes
Yes
-40C to +85C
-40C to +85C
16
16
12
12
24
24
12
12
4
4
Yes
Yes
CY8C29466-24PVXIT
32
2K
Yes
-40C to +85C
16
12
24
12
4
Yes
CY8C29466-24SXI
32
2K
Yes
-40C to +85C
16
12
24
12
4
Yes
CY8C29466-24SXIT
32
2K
Yes
-40C to +85C
16
12
24
12
4
Yes
CY8C29566-24AXI
32
2K
Yes
-40C to +85C
16
12
40
12
4
Yes
CY8C29566-24AXIT
32
2K
Yes
-40C to +85C
16
12
40
12
4
Yes
CY8C29666-24PVXI
32
2K
Yes
-40C to +85C
16
12
44
12
4
Yes
CY8C29666-24PVXIT
32
2K
Yes
-40C to +85C
16
12
44
12
4
Yes
CY8C29666-24LFXI
CY8C29866-24AXI
32
32
2K
2K
Yes
Yes
-40C to +85C
-40C to +85C
16
16
12
12
44
64
12
12
4
4
Yes
Yes
(Rows of 4)
RAM
(Bytes)
CY8C29466-24PXI
CY8C29466-24PVXI
Digital PSoC
Blocks
Flash
(Kbytes)
28 Pin (300 Mil) DIP
28 Pin (210 Mil) SSOP
28 Pin (210 Mil) SSOP
(Tape and Reel)
28 Pin (300 Mil) SOIC
28 Pin (300 Mil) SOIC
(Tape and Reel)
44 Pin TQFP
44 Pin TQFP
(Tape and Reel)
48 Pin (300 Mil) SSOP
48 Pin (300 Mil) SSOP
(Tape and Reel)
48 Pin MLF
100 Pin TQFP
Ordering
Code
Package
Table 5-1. CY8C29x66 PSoC Device Family Key Features and Ordering Information
Ordering Code Definitions
CY 8 C 29 xxx-SPxx
Package Type:
PX = PDIP Pb Free
SX = SOIC Pb Free
PVX = SSOP Pb Free
LFX = MLF Pb Free
AX = TQFP Pb Free
Thermal Rating:
C = Commercial
I = Industrial
E = Extended
Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress MicroSystems
Company ID: CY = Cypress
August 3, 2004
Document No. 38-12013 Rev. *F
39
6. Sales and Service Information
To obtain information about Cypress MicroSystems or PSoC sales and technical support, reference the following information or go to
the section titled “Getting Started” on page 4 in this document.
Cypress MicroSystems
2700 162nd Street SW
Building D
Lynnwood, WA 98037
Phone:
800.669.0557
Facsimile:
425.787.4641
Web Sites:
6.1
Company Information – http://www.cypress.com
Sales – http://www.cypress.com/aboutus/sales_locations.cfm
Technical Support – http://www.cypress.com/support/login.cfm
Revision History
Table 6-1. CY8C29X66 Data Sheet Revision History
Document Title:
CY8C29466, CY8C29566, CY8C29666, and CY8C29866 PSoC Mixed Signal Array Preliminary Data Sheet
Document Number:
Revision
38-12013
ECN #
Issue Date
Origin of Change
Description of Change
**
131151
11/13/2003
New Silicon
New document (Revision **).
*A
132848
01/21/2004
NWJ
New information. First edition of preliminary data sheet.
*B
133205
01/27/2004
NWJ
Changed part numbers, increased SRAM data storage to 2K bytes.
*C
133656
02/09/2004
SFV
Changed part numbers and removed a 28-pin SOIC.
*D
227240
06/01/2004
SFV
Changes to Overview section, 48-pin MLF pinout, and significant changes to the Electrical Specifications section.
*E
240108
See ECN
SFV
Added a 28-lead (300 mil) SOIC part.
*F
247492
See ECN
SFV
New information added to the Electrical Specifications chapter.
Distribution: External/Public
6.2
Posting: None
Copyrights and Code Protection
Copyrights
© Cypress MicroSystems, Inc. 2000 – 2004. All rights reserved. PSoC™, PSoC Designer™, and Programmable System-on-Chip™ are trademarks of Cypress MicroSystems, Inc. All other trademarks or registered trademarks referenced herein are property of the respective corporations.
The information contained herein is subject to change without notice. Cypress MicroSystems assumes no responsibility for the use of any circuitry other than circuitry
embodied in a Cypress MicroSystems product. Nor does it convey or imply any license under patent or other rights. Cypress MicroSystems does not authorize its products
for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of
Cypress MicroSystems products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress
MicroSystems against all charges. Cypress MicroSystems products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety
applications, unless pursuant to an express written agreement with Cypress MicroSystems.
Flash Code Protection
Note the following details of the Flash code protection features on Cypress MicroSystems devices.
Cypress MicroSystems products meet the specifications contained in their particular Cypress MicroSystems Data Sheets. Cypress MicroSystems believes that its family of
products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress MicroSystems,
that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress MicroSystems nor any
other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
Cypress MicroSystems is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress MicroSystems are committed to continuously improving the code protection features of our products.
August 3, 2004
© Cypress MicroSystems, Inc. 2004 — Document No. 38-12013 Rev. *F
40