IDT IDT71P79104 18mb pipelined ddrâ ¢ii sio sram burst of 2 Datasheet

IDT71P79204
IDT71P79104
IDT71P79804
IDT71P79604
18Mb Pipelined
DDR™II SIO SRAM
Burst of 2
Features
Description
◆
◆
The IDT DDRIITM Burst of two SIO SRAMs are high-speed synchronous memories with independent, double-data-rate (DDR), read
and write data ports with two data items passed with each read or write.
Using independent ports for read and write data access, simplifies
system design by eliminating the need for bi-directional buses. All buses
associated with the DDRII SIO are unidirectional and can be optimized
for signal integrity at very high bus speeds. Memory bandwidth is higher
than DDR SRAM with bi-directional data buses as separate read and
write ports eliminate bus turn around cycle. Separate read and write
ports also enable easy depth expansion. Each port can be selected
independantly with a R/W input shared among all SRAMs and provide
a new LD load control signal for each bank. The DDRII SIO has scalable output impedance on its data output bus and echo clocks, allowing
the user to tune the bus for low noise and high performance.
The DDRII SIO has a single SDR address bus with multiplexed
read and write addresses. The read/write and load control inputs are
received on the first half of the clock cycle. The byte and nibble write
signals are received on both halves of the clock cycle simultaneously
with the data they are controlling on the data input bus.
The DDRII SIO has echo clocks, which provide the user with a
clock that is precisely timed to the data output, and tuned with matching
impedance and signal quality. The user can use the echo clock for
downstream clocking of the data. Echo clocks eliminate the need for the
user to produce alternate clocks with precise timing, positioning, and
signal qualities to guarantee data capture. Since the echo clocks are
18Mb Density (2Mx8, 2Mx9, 1Mx18, 512Kx36)
Separate, Independent Read and Write Data Ports
- Supports concurrent transactions
◆ Dual Echo Clock Output
◆ 2-Word Burst on all SRAM accesses
◆ Multiplexed Address Bus
- One Read or one Write request per clock cycle
◆ DDR (Double Data Rate) Data Bus
- Two word burst data per clock
◆ Depth expansion through Control Logic
◆ HSTL (1.5V) inputs that can be scaled to receive signals from 1.4V
to 1.9V.
◆ Scalable output drivers
- Can drive HSTL, 1.8V TTL or any voltage level from 1.4V to 1.9V.
- Output Impedance adjustable from 35 ohms to 70 ohms
◆ 1.8V Core Voltage (V DD)
◆ 165-ball, 1.0mm pitch, 15mm x 17mm fBGA Package
◆ JTAG Interface
Functional Block Diagram
(Note1)
D
DATA
REG
DATA
REG
(Note1)
K
K
C
C
CTRL
LOGIC
(Note2)
18M
MEMORY
ARRAY
CLK
GEN
(Note4)
(Note4)
OUTPUT SELECT
(Note3)
ADD
REG
OUTPUT REG
LD
R/W
BWx
(Note2)
SENSE AMPS
SA
WRITE/READ DECODE
WRITE DRIVER
(Note1)
Q
CQ
CQ
SELECT OUTPUT CONTROL
6432 drw 16
Notes:
1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36
2) Represents 20 address signal lines for x8 and x9, 19 address signal lines for x18, and 18 address signal lines for x36.
3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the BW is a “nibble write” and there are 2
signal lines.
4) Represents 16 data signal lines for x8, 18 signal lines for x9, 36 signal lines for x18, and 72 signal lines for x36.
1
NOVEMBER 2005
©2005 Integrated Device Technology, Inc. QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc.DSC-6432/01
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
generated by the same source that drives the data output, the relationship to the data is not significantly affected by voltage, temperature and
process, as would be the case if the clock were generated by an outside
source.
All interfaces of the DDR II SIO are HSTL, allowing speeds beyond
SRAM devices that use any form of TTL interface. The interface can be
scaled to higher voltages (up to 1.9V) to interface with 1.8V systems if
necessary. The device has a VDDQ and a separate Vref, allowing the
user to designate the interface operational voltage, independent of the
device core voltage of 1.8V VDD. The output impedance control allows
the user to adjust the drive strength to adapt to a wide range of loads and
transmission lines.
Clocking
The DDRII SIO SRAM has two sets of input clocks, namely the K,
K clocks and the C, C clocks. In addition, the DDRII SIO has an output
“echo” clock, CQ, CQ.
The K and K clocks are the primary device input clocks. The K
clock is, used to clock in the control signals (LD, R/W and BWx or NWx),
the address, and the first word of the data burst during a write operation.
The K clock is used to clock in the control signals (BWx or NWx) and the
second word of the data burst during a write operation. The K and K
clocks are also used internally by the SRAM. In the event that the user
disables the C and C clocks, the K and K clocks will also be used to clock
the data out of the output register and generate the echo clocks.
The C and C clocks may be used to clock the data out of the output
register during read operations and to generate the echo clocks. C and
C must be presented to the SRAM within the timing tolerances. The
output data from the DDRII SIO will be closely aligned to the C and C
input, through the use of an internal DLL. When C is presented to the
DDRII SIO SRAM, the DLL will have already internally clocked the data
to arrive at the device output simultaneously with the arrival of the C
clock. The C and second data item of the burst will also correspond.
Single Clock Mode
The DDRII SIO SRAM may be operated with a single clock pair. C
and C may be disabled by tying both signals high, forcing the outputs
and echo clocks to be controlled instead by the K and K clocks.
DLL Operation
The DLL in the output structure of the DDRII SIO SRAM can be
used to closely align the incoming clocks C and C with the output of the
data, generating very tight tolerances between the two. The user may
disable the DLL by holding Doff low. With the DLL off, the C and C (or
K and K if C and C are not used) will directly clock the output register of
the SRAM. With the DLL off, there will be a propagation delay from the
time the clock enters the device until the data appears at the output.
the correlation of the rising and falling edges of the echo clock and will
improve the duty cycle of the individual signals.
The echo clock is very closely aligned with the data, guaranteeing
that the echo clock will remain closely correlated with the data, within the
tolerances designated.
Read and Write Operations
DDRII SIO devices internally store the two words of the burst as a
single wide word and the words will retain their burst order. There is no
ability to address an individual word level in a burst, as is possible in the
DDRII common I/O devices. The byte and nibble write signals can be
used to prevent writing to any individual bytes, or combined to prevent
writing word(s) of the burst.
Read operations are initiated by holding Read/Write control input
(R/W) high, the load control input (LD) low and presenting the read
address to the address port during the rising edge of K, which will latch
the address. The data will then be read and will appear at the device
output at the designated time in correspondence with the C and C clocks.
Write operations are initiated by holding the Read/Write control input
(R/W) low, the load control input (LD) low and presenting the write
address to the address port during the rising edge of K, which will latch
the address. On the following rising edge of K, the first word of the two
word burst must be present on the data input bus DQ[x:O], along with the
appropriate byte write or nibble write (BWx or NWx) inputs. On the
following rising edge of K, the second half of the data write burst will be
accepted at the device input with the designated (BWx or NWx) inputs.
Output Enables
The DDRII SIO SRAM automatically enables and disables the Q[X:0]
outputs. When a valid read is in progress, and data is present at the
output, the output will be enabled. If no valid data is present at the output
(read not active), the output will be disabled (high impedance). The
echo clocks will remain valid at all times and cannot be disabled or turned
off. During power-up the Q outputs will come up in a high impedance
state.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on
the SRAM and Vss to allow the SRAM to adjust its output drive impedance. The value of RQ must be 5X the value of the intended drive
impedance of the SRAM. The allowable range of RQ to guarantee
impedance matching with a tolerance of +/- 10% is between 175 ohms
and 350 ohms, with VDDQ = 1.5V. The output impedance is adjusted
every 1024 clock cycles to correct for drifts in supply voltage and temperature. If the user wishes to drive the output impedance of the SRAM
to it’s lowest value, the ZQ pin may be tied to VDDQ.
Echo Clock
The echo clocks, CQ and CQ, are generated by the C and C clocks
(or K, K if C, C are disabled). The rising edge of C generates the rising
edge of CQ, and the falling edge of CQ. The rising edge of C generates
the rising edge of CQ and the falling edge of CQ. This scheme improves
6.42
2
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
Pin Definitions
Symbol
Pin Function
Description
Input
Synchronous
Data input signals, sampled on the rising edge of K and K clocks during valid write operations
2M x 8 -- D[7:0]
2M x 9 -- D[8:0]
1M x 18 -- D[17:0]
512K x 36 -- D[35:0]
Input
Synchronous
Byte Write Select 0, 1, 2, and 3 are active LOW. Sampled on the rising edge of the K and again on the rising
edge of K clocks during write operations. Used to select which byte is written into the device during the current
portion of the write operations. Bytes not written remain unaltered. All the byte writes are sampled on the same
edge as the data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and
not written in to the device.
2M x 9 -- BW0 controls DQ[8:0]
1M x 18 -- BW0 controls DQ[8:0] and BW1 controls DQ[17:9]
512K x 36 -- BW0 controls DQ[8:0], BW1 controls DQ[17:9], BW2 controls DQ[26:18] and BW3 controls DQ[35:27]
NW0 NW1
Input
Synchronous
Nibble Write Select 0 and 1 are active LOW. Available only on x8 bit parts instead of Byte Write Selects.
Sampled on the rising edge of the K and K clocks during write operations. Used to select which nibble is written
into the device during the current portion of the write operations. Nibbles not written remain unaltered. All the
nibble writes are sampled on the same edge as the data. Deselecting a Nibble Write Select will cause the
corresponding nibble of data to be ignored and not written in to the device.
2M x 8--NW0 controls D[3:0] and NW1 controls D[7:4]
SA
Input
Synchronous
Address Inputs. Addresses are sampled on the rising edge of K clock during active read or write operations.
Q[X:0]
Output
Synchronous
Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on
the rising edge of both the C and C clocks during Read operations or K and K when operating in single clock
mode. When the Read port is deselect ed, Q[X:0] are automatically three-stated.
LD
Input
Synchronous
Load Control Logic. Sampled on the rising edge of K. If LD is low, a two word burst read or write operation will
be initiated as designated by the R/W input. If LD is high during the rising edge of K, operations in progress will
complete, but new operations will not be initiated.
R/W
Input
Synchronous
Read or Write Control Logic. If LD is low during the rising edge of K, the R/W indicates whether a new operation
should be a read or write. If R/W is high, a read operation will be initiated, if R/W is low, a write operation will be
initiated. If the LD input is high during the rising edge of K, the R/W input will be ignored.
C
Input Clock
Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and
C can be used together to deskew the flight times of various devices on the board back to the controller. See
application example for further details.
C
Input Clock
Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and
C can be used together to deskew the flight times of various devices on the board back to the controller. See
application example for further details.
K
Input Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive
out data through Q[X:0] when in single clock mode. All accesses are initiated on the rising edge of K.
K
Input Clock
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive
out data through Q[X:0] when in single clock mode.
CQ, CQ
Output Clock
Synchronous Echo clock outputs. The rising edges of these outputs are tightly matched to the synchronous data
outputs and can be used as a data valid indication. These signals are free running and do not stop when the
output data is three stated.
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus
impedance. Q[X:0] output impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and
ground. Alternately, this pin can be connected directly to V DDQ, which enables the minimum impedance mode.
This pin cannot be connected directly to GND or left unconnected.
D[X:0]
BW0, BW1
BW2, BW3
ZQ
6432 tbl 02a
6.42
3
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
Pin Definitions continued
Symbol
Pin Function
Description
Doff
Input
DLL Turn Off. When low this input will turn off the DLL inside the device. The AC timings with the DLL
turned off will be different from those listed in this data sheet. There will be an increased propagation delay
from the incidence of C and C to Q, or K and K to Q as configured. The propagation delay is not a tested
parameter, but will be similar to the propagation delay of other SRAM devices in this speed grade.
TDO
Output
TDO pin for JTAG.
TCK
Input
TCK pin for JTAG.
TDI
Input
TDI pin for JTAG. An internal resistor will pull TDI to V DD when the pin is unconnected.
TMS
Input
TMS pin for JTAG. An internal resistor will pull TMS to V DD when the pin is unconnected.
NC
No connects inside the package. Can be tied to any voltage level.
VREF
Input
Reference
Reference Voltage input. Static input used to set the reference level for HSTL inputs and Outputs as well
as AC measurement points.
VDD
Power
Supply
Power supply inputs to the core of the device. Should be connected to a 1.8V power supply.
VSS
Ground
Ground for the device. Should be connected to ground of the system.
VDDQ
Power
Supply
Power supply for the outputs of the device. Should be connected to a 1.5V power supply for HSTL or
scaled to the desired output voltage.
6432 tbl 02b
6.42
4
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
Pin Configuration IDT71P79204 (2M x 8)
1
2
3
4
5
6
7
8
9
10
11
A
CQ
VSS/
SA (2)
SA
R/W
NW1
K
NC
LD
SA
VSS/
SA (1)
CQ
B
NC
NC
NC
SA
NC
K
NW0
SA
NC
NC
Q3
C
NC
NC
NC
VSS
SA
SA
SA
VSS
NC
NC
D3
D
NC
D4
NC
VSS
VSS
VSS
V SS
VSS
NC
NC
NC
E
NC
NC
Q4
VDDQ
VSS
VSS
V SS
VDDQ
NC
D2
Q2
F
NC
NC
NC
VDDQ
VDD
VSS
V DD
VDDQ
NC
NC
NC
G
NC
D5
Q5
VDDQ
VDD
VSS
V DD
VDDQ
NC
NC
NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
V DD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
V DD
VDDQ
NC
Q1
D1
K
NC
NC
NC
VDDQ
VDD
VSS
V DD
VDDQ
NC
NC
NC
L
NC
Q6
D6
VDDQ
VSS
VSS
V SS
VDDQ
NC
NC
Q0
M
NC
NC
NC
VSS
VSS
VSS
V SS
VSS
NC
NC
D0
N
NC
D7
NC
VSS
SA
SA
SA
VSS
NC
NC
NC
P
NC
NC
Q7
SA
SA
C
SA
SA
NC
NC
NC
R
TDO
TCK
SA
SA
SA
C
SA
SA
SA
TMS
TDI
6432 tbl 12
165-ball FBGA Pinout
TOP VIEW
NOTES:
1. A10 is reserved for the 36Mb expansion address.
2. A2 is reserved for the 72Mb expansion address.
6.42
5
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
Pin Configuration IDT71P79104 (2M x 9)
1
2
3
4
5
6
7
8
9
10
11
A
CQ
V SS/
SA (2)
SA
R/W
NC
K
NC
LD
SA
V SS/
SA (1)
CQ
B
NC
NC
NC
SA
NC
K
BW
SA
NC
NC
Q3
C
NC
NC
NC
VSS
SA
SA
SA
VSS
NC
NC
D3
D
NC
D4
NC
VSS
V SS
V SS
VSS
VSS
NC
NC
NC
E
NC
NC
Q4
VDDQ
V SS
V SS
VSS
VDDQ
NC
D2
Q2
F
NC
NC
NC
VDDQ
V DD
V SS
VDD
VDDQ
NC
NC
NC
G
NC
D5
Q5
VDDQ
V DD
V SS
VDD
VDDQ
NC
NC
NC
H
Doff
VREF
VDDQ
VDDQ
V DD
V SS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
V DD
V SS
VDD
VDDQ
NC
Q1
D1
K
NC
NC
NC
VDDQ
V DD
V SS
VDD
VDDQ
NC
NC
NC
L
NC
Q6
D6
VDDQ
V SS
V SS
VSS
VDDQ
NC
NC
Q0
M
NC
NC
NC
VSS
V SS
V SS
VSS
VSS
NC
NC
D0
N
NC
D7
NC
VSS
SA
SA
SA
VSS
NC
NC
NC
P
NC
NC
Q7
SA
SA
C
SA
SA
NC
D8
Q8
R
TDO
TCK
SA
SA
SA
C
SA
SA
SA
TMS
TDI
6432 tbl 12a
165-ball FBGA Pinout
Top View
NOTES:
1. A10 is reserved for the 36Mb expansion address.
2. A2 is reserved for the 72Mb expansion address.
6.42
6
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
Pin Configuration IDT71P79804 (1M x 18)
1
2
3
4
5
6
7
8
9
10
11
A
CQ
VSS/
SA(3)
NC/
SA(1)
R/W
BW1
K
NC
LD
SA
VSS/
SA(2)
CQ
B
NC
Q9
D9
SA
NC
K
BW0
SA
NC
NC
Q8
C
NC
NC
D10
VSS
SA
SA
SA
VSS
NC
Q7
D8
D
NC
D11
Q10
VSS
VSS
VSS
VSS
VSS
NC
NC
D7
E
NC
NC
Q11
VDDQ
VSS
VSS
VSS
VDDQ
NC
D6
Q6
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
Q5
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
D5
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q4
D4
K
NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
D3
Q3
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q2
M
NC
NC
D16
VSS
VSS
VSS
VSS
VSS
NC
Q1
D2
N
NC
D17
Q16
VSS
SA
SA
SA
VSS
NC
NC
D1
P
NC
NC
Q17
SA
SA
C
SA
SA
NC
D0
Q0
R
TDO
TCK
SA
SA
SA
C
SA
SA
SA
TMS
TDI
6432 tbl 12b
165-ball FBGA Pinout
Top View
NOTES:
1. A3 is reserved for the 36Mb expansion address.
2. A10 is reserved for the 72Mb expansion address. This must be tied or driven to VSS on the 1M x 18 DDRII SIO Burst of 2 (71P79804) devices.
3. A2 is reserved for the 144Mb expansion address. This must be tied or driven to VSS on the 1M x 18 DDRII SIO Burst of 2 (71P79804) devices.
6.42
7
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
Pin Configuration IDT71P79604 (512K x 36)
1
2
3
4
5
6
7
8
9
10
11
A
CQ
VSS/
SA (4)
NC/
SA (2)
R/W
BW2
K
BW1
LD
NC/
SA (1)
VSS/
SA (3)
CQ
B
Q27
Q18
D18
SA
BW3
K
BW0
SA
D17
Q17
Q8
C
D27
Q28
D19
VSS
SA
SA
SA
VSS
D16
Q7
D8
D
D28
D20
Q19
VSS
VSS
VSS
VSS
VSS
Q16
D15
D7
E
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
D6
Q6
F
Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
Q5
G
D30
D22
Q22
VDDQ
VDD
VSS
VDD
VDDQ
Q13
D13
D5
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q4
D4
K
Q32
D32
Q23
VDDQ
VDD
VSS
VDD
VDDQ
Q12
D3
Q3
L
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
M
D33
Q34
D25
VSS
VSS
VSS
VSS
VSS
D10
Q1
D2
N
D34
D26
Q25
VSS
SA
SA
SA
VSS
Q10
D9
D1
P
Q35
D35
Q26
SA
SA
C
SA
SA
Q9
D0
Q0
R
TDO
TCK
SA
SA
SA
C
SA
SA
SA
TMS
TDI
6432 tbl 12c
165-ball FBGA Pinout
TOP VIEW
NOTES:
1. A9 is reserved for the 36Mb expansion address.
2. A3 is reserved for the 72Mb expansion address.
3. A10 is reserved for the 144Mb expansion address. This must be tied or driven to VSS on the 512K x 36 DDRII SIO Burst of 2 (71P79604)
devices.
4. A2 is reserved for the 288Mb expansion address. This must be tied or driven to VSS on the 512K x 36 DDRII SIO Burst of 2 (71P79604)
devices.
6.42
8
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings(1) (2)
Symbol
Rating
Capacitance (TA = +25°C, f = 1.0MHz)(1)
Value
Unit
Symbol
V
CIN
VTERM
Supply Voltage on VDD with
Respect to GND
–0.5 to +2.9
VTERM
Supply Voltage on VDDQ with
Respect to GND
–0.5 to VDD+0.3
CCLK
V
CO
Conditions
Max.
Unit
5
pF
6
pF
Input Capacitance
Clock Input Capacitance
VDD = 1.8V
V DDQ = 1.5V
Output Capacitance
7
pF
6432 tbl 06
V
Note:
1. Tested at characterization and retested after any design or process change that
may affect these parameters.
–55 to +125
°C
–65 to +150
°C
Recommended DC Operating
Conditions
+ 20
mA
VTERM
Voltage on Input terminals with
respect to GND
–0.5 to VDD +0.3
VTERM
Voltage on output and I/O
terminals with respect to GND
–0.5 to VDDQ +0.3
TBIAS
Temperature Under Bias
TSTG
Storage Temperature
IOUT
Continuous Current into Outputs
Symbol
6432 tbl 05
Notes:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. VDDQ must not exceed VDD during normal operation.
Parameter
Min.
Typ.
Max.
Unit
VDD
Power Supply Voltage
1.7
1.8
1.9
V
VDDQ
I/O Supply Voltage
1.4
1.5
1.9
V
VSS
Ground
0
0
0
V
VREF
Input Reference Voltage
-
VDDQ/2
-
V
TA
Ambient
Temperature (1)
Commercial
0 to +70
o
c
Industrial
-40 to +85
o
c
Note:
1. During production testing, the case temperature equals the ambient
temperature.
Write Descriptions(1,2)
BW0
BW1
BW2
BW3
NW0
NW1
Write Byte 0
L
X
X
X
X
X
Write Byte 1
X
L
X
X
X
X
Write Byte 2
X
X
L
X
X
X
Write Byte 3
X
X
X
L
X
X
Write Nibble 0
X
X
X
X
L
X
Write Nibble 1
X
X
X
X
X
L
Signal
Parameter
6432 tbl 09
Notes:
1) All byte write (BWx) and nibble write (NWx) signals are sampled on
the rising edge of K and again on K. The data that is present on the data bus\
in the designated byte/nibble will be latched into the input if the corresponding
BWx or NWx is held low. The rising edge of K will sample the first byte/nibble
of the two word burst and the rising edge of K will sample the second byte
nibble of the two word burst.
2) The availability of the BWx or NWx on designated devices is described in the
pin description table.
3) The DDRII SIO Burst of two SRAM has data forwarding. A read request that
is initiated on cycle following a write request to the same address will produce
the newly written data in response to the read request.
6.42
9
6432 tbl 04
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
Application Example
SRAM #1
VT
SRAM #4
D
ZQ
Q
SA LD R/W BW0 BW1 C C
KK
250
Ω
D
SA LD R/W BW0 BW1 C C
ZQ
Q
KK
250
R
Data In
Data Out
Address
LD
R/W
BWx/NWx
MEMORY
CONTROLLER
Return CLK
Source CLK
Return CLK
Source CLK
R
R
R
R
R
VT VT
R
R
R = 50Ω
VT = VREF
6432 drw 20
6.42
10
VT
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range (VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V)
Parameter
Symbol
Test Conditions
Min
Max
Unit
Input Leakage Current
IIL
VDD = Max VIN = VSS to V DDQ
-2
+2
uA
Output Leakage Current
IOL
Output Disabled
-2
+2
uA
Operating Current
(x36): DDR
Operating Current
(x18): DDR
Operating Current
(x9,x8): DDR
Standby Current: NOP
IDD
IDD
IDD
ISB1
VDD = Max,
IOUT = 0mA (outputs open),
Cycle Time > tKHKH Min
VDD = Max,
IOUT = 0mA (outputs open),
Cycle Time > tKHKH Min
VDD = Max,
IOUT = 0mA (outputs open),
Cycle Time > tKHKH Min
Device Deselected (in NOP state)
IOUT = 0mA (outputs open),
f=Max,
All Inputs <0.2V or > VDD -0.2V
Com'l
Ind
250MHZ
-
1050
1100
200MHz
-
950
1000
167MHz
-
850
900
267MHz
-
950
980
250MHZ
-
850
900
200MHz
-
750
800
167MHz
-
650
700
250MHZ
-
800
850
200MHz
-
700
750
167MHz
-
600
650
267MHz
-
420
450
250MHZ
-
375
410
200MHz
-
335
370
167MHz
-
300
335
Note
mA
1
mA
1
mA
1
mA
2
Output High Voltage
VOH1
RQ = 250Ω, IOH = -15mA
V DDQ/2-0.12
VDDQ/2+0.12
V
3,7
Output Low Voltage
VOL1
RQ = 250Ω, IOL = 15mA
V DDQ/2-0.12
VDDQ/2+0.12
V
4,7
Output High Voltage
V OH2
IOH = -0.1mA
VDDQ-0.2
V DDQ
V
5
Output Low Voltage
VOL2
IOL = 0.1mA
VSS
0.2
V
6
6432 tbl 10c
NOTES:
1. Operating Current is calculated with 50% read cycles and 50% write cycles.
2. Standby Current is only after all pending read and write burst operations are completed.
3. Outputs are impedance-controlled. IOH = -(VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω < RQ < 350Ω. This
parameter is tested at RQ = 250Ω, which gives a nominal 50Ω output impedance.
4. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω < RQ < 350Ω. This
parameter is tested at RQ = 250Ω, which gives a nominal 50Ω output impedance.
5. This measurement is taken to ensure that the output has the capability of pulling to the VDDQ rail, and is not intended to be used as an
impedance measurement point.
6. This measurement is taken to ensure that the output has the capability of pulling to Vss, and is not intended to be used as an impedance
measurement point.
7. Programmable Impedance Mode.
6.42
11
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
Input Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range (VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V)
Parameter
Symbol
Min
Max
Unit
Notes
Input High Voltage, DC
VIH (DC)
VREF +0.1
VDDQ +0.3
V
1,2
Input Low Voltage, DC
VIL (DC)
-0.3
VREF -0.1
V
1,3
Input High Voltage, AC
VIH (AC)
VREF +0.2
-
V
4,5
Input Low Voltage, AC
VIL (AC)
-
VREF -0.2
V
4,5
6432 tbl 10d
NOTES:
1. These are DC test criteria. DC design criteria is VREF + 50mV. The AC VIH/VIL levels are defined separately for measuring timing
parameters.
2. VIH (Max) DC = VDDQ+0.3, VIH (Max) AC = VDD +0.5V (pulse width <20% tKHKH (min))
3. VIL (Min) DC = -0.3V, VIL (Min) AC = -0.5V (pulse width <20% tKHKH (min))
4. This conditon is for AC function test only, not for AC parameter test.
5. To maintain a valid level, the transitioning edge of the input must:
a) Sustain a constant slew rate from the current AC level through the target AC level, VIL(AC) or VIH(AC)
b) Reach at least the target AC level.
c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC)
Overshoot Timing
Undershoot Timing
20% tKHKH (MIN)
VIH
VDD +0.5
VDD +0.25
VSS
VDD
VSS-0.25V
VSS-0.5V
VIL
6432 drw 22
6432 drw 21
20% tKHKH (MIN)
6.42
12
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
AC Test Conditions
Parameter
Symbol
Value
Unit
Core Power Supply Voltage
V DD
1.7-1.9
V
Output Power Supply Voltage
VDDQ
1.4-1.9
V
Input High Level
VIH
(V DDQ/2) + 0.5
V
Input Low Level
VIL
(VDDQ/2) - 0.5
V
Input Reference Level
VREF
VDDQ/2
V
Input Rise/Fall Time
TR/TF
0.3/0.3
ns
VDDQ/2
V
Output Timing Reference Level
6432 tbl 11a
NOTE:
1. Parameters are tested with RQ=250Ω
Input Waveform
(VDDQ /2) + 0.5V
VDDQ /2
Test points
VDDQ /2
(VDDQ /2) - 0.5V
6432 drw 07
Output Waveform
Test points
VDDQ/2
V DDQ /2
6432 drw 08
AC Test Loads
VDDQ/2
VREF
R L = 50Ω
VDDQ/2
OUTPUT
Device
Under
Test
ZQ
Z0 =50Ω
RQ = 250 Ω
6432 drw 04
6.42
13
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V, Commercial and Industrial Temperature Ranges)(3,7)
267MHz
Symbol
Parameter
250MHz
200MHz
167MHz
Min.
Max
Min.
Max
Min.
Max
Min.
Max
Unit
Notes
Clock Parameters
tKHKH
Clock Cycle Time (K,K,C,C)
3.75
6.30
4.00
6.30
5.00
7.88
6.00
8.40
ns
tKC var
Clock Phase Jitter (K,K,C,C)
-
-
-
0.20
-
0.20
-
0.20
ns
1,5
tKHKL
Clock High Time (K,K,C,C)
1.50
-
1.60
-
2.00
-
2.40
-
ns
8
tKLKH
Clock LOW Time (K,K,C,C)
1.50
-
1.60
-
2.00
-
2.40
-
ns
8
tKHKH
Clock to clock (K→K,C→C)
1.69
-
1.80
-
2.20
-
2.70
-
ns
9
tKHKH
Clock to clock (K→K,C→C)
1.69
-
1.80
-
2.20
-
2.70
-
ns
9
tKHCH
Clock to data clock (K→C,K→C)
0.00
1.69
0.00
1.80
0.00
2.30
0.00
2.80
ns
tKC lock
DLL lock time (K, C)
1024
-
1024
-
1024
-
1024
-
cycles
tKC reset
K static to DLL reset
30
-
30
-
30
-
30
-
ns
2
Output Parameters
tCHQV
C,C HIGH to output valid
-
0.45
-
0.45
-
0.45
-
0.50
ns
3
tCHQX
C,C HIGH to output hold
-0.45
-
-0.45
-
-0.45
-
-0.50
-
ns
3
tCHCQV
C,C HIGH to echo clock valid
-
0.45
-
0.45
-
0.45
-
0.50
ns
3
tCHCQX
C,C HIGH to echo clock hold
-0.45
-
-0.45
-
-0.45
-
-0.50
-
ns
3
tCQHQV
CQ,CQ HIGH to output valid
-
0.30
-
0.30
-
0.35
-
0.40
ns
tCQHQX
CQ,CQ HIGH to output hold
-0.30
-
-0.30
-
-0.35
-
-0.40
-
ns
tCHQZ
C HIGH to output High-Z
-
0.45
-
0.45
-
0.45
-
0.50
ns
3,4,5
tCHQX1
C HIGH to output Low-Z
-0.45
-
-0.45
-
-0.45
-
-0.50
-
ns
3,4,5
6
Set-Up Times
tAVKH
Address valid to K,K rising edge
0.50
-
0.50
-
0.60
-
0.70
-
ns
tIVKH
R/W inputs valid to K,K rising edge
0.50
-
0.50
-
0.60
-
0.70
-
ns
tDVKH
Data-in and BWx/NWx valid to K, K
rising edge
0.35
-
0.35
-
0.40
-
0.50
-
ns
Hold Times
tKHAX
K,K rising edge to address hold
0.50
-
0.50
-
0.60
-
0.70
-
ns
tKHIX
K,K rising edge to R/W inputs hold
0.50
-
0.50
-
0.60
-
0.70
-
ns
tKHDX
K, K rising edge to data-in and
BWx/NWx hold
0.35
-
0.35
-
0.40
-
0.50
-
ns
6
6432 tbl 11
NOTES:
1. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
2. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
3. If C,C are tied High, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention
because tCHQX1 is a MIN parameter that is worse case at totally different test conditions (0°C, 1.9V) than tCHQZ, which is a MAX parameter
(worst case at 70°C, 1.7V) It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
5. This parameter is guaranteed by device characterization, but not production tested.
6. All address inputs must meet the specified setup and hold times for all latching clock edges.
7. During production testing, the case temperature equals TA.
8. Clock High Time (tKHKL) and Clock Low Time (tKLKH) should be within 40% to 60% of the cycle time (tKHKH).
9. Clock to clock time (tKHKH) and Clock to clock time (tKHKH) should be within 45% to 55% of the cycle time (tKHKH).
6.42
14
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Read and Write Cycles
NOP
Read A0
(burst of 2)
2
1
Read A1
(burst of 2)
3
Write A2
Write A3
(burst of 2) (burst of 2)
4
5
Read A4
(burst of 2)
6
NOP
8
7
K
tKHKL
tKLKH
tKHKH
tKHKH
K
LD
tIVKH
tKHIX
R/W
A
A0
A1
A3
A2
A4
tKHDX
tKHDX
tAVKH tKHAX
tDVKH
tDVKH
D
Q
Q00
Qx1
Q01
D20
D21
Q10
Q11
tCHQV
tKHCH
tCHQV
tCHQX
tKHCH
D30
D31
Q41
Q40
tCQHQV
tCHQZ
tCHQX
tCHQX1
C
tKHKL
tKLKH
tKHKH
tKHKH
C
tCHCQV
tCHCQX
CQ
tCHCQV
tCHCQX
CQ
6432 drw 09a
6.42
15
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access
Port (TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during
manufacturing and system diagnostics. In conformance with IEEE 1149.1,
the SRAM contains a TAP controller, Instruction register, Bypass Register and ID register. The TAP controller has a standard 16-state machine
that resets internally upon power-up; therefore, the TRST signal is not
required. It is possible to use this device without utilizing the TAP. To
disable the TAP controller without interfacing with normal operation of the
SRAM, TCK must be tied to VSS to preclude a mid level input. TMS and
TDI are designed so an undriven input will produce a response identical
to the application of a logic 1, and may be left unconnected, but they may
also be tied to VDD through a resistor. TDO should be left unconnected.
JTAG Block Diagram
JTAG Instruction Coding
A,D
K,K
C,C
IR2
IR1
IR0
0
0
0
EXTEST
Boundary Scan Register
0
0
1
IDCODE
Identification register
2
0
1
0
SAMPLE-Z
Boundary Scan Register
1
0
1
1
RESERVED
Do Not Use
5
1
0
0
1
0
1
RESERVED
Do Not Use
5
1
1
0
RESERVED
Do Not Use
5
1
1
1
BYPASS
SRAM
CORE
Q
CQ
CQ
TDI
BYPASS Reg.
TDO
Identification Reg.
TAP Controller
6432 drw 18
TAP Controller State Diagram
Test Logic Reset
0
Run Test Idle
1
Select DR
0
1
Select IR
1
Capture DR
Shift DR
1
Shift IR
0
Pause DR
1
Update DR
0
0
Exit 1 IR
0
0
1
Exit 2 DR
1
1
Exit 1 DR
0
1
Capture IR
0
0
1
1
0
0
1
Notes
SAMPLE/PRELOAD Boundary Scan register
4
Bypass Register
3
NOTES:
1. Places Qs in Hi-Z in order to sample all input data regardless of
other SRAM inputs.
2. TDI is sampled as an input to the first ID register to allow for the
serial shift of the external TDI data.
3. Bypass register is initialized to Vss when BYPASS instruction is
invoked. The Bypass Register also holds serially loaded TDI
when existing the Shift DR states.
4. SAMPLE instruction does not place output pins in Hi-Z.
5. This instruction is reserved for future use.
Control Signals
1
TDO Output
6432 tbl 13
Instruction Reg.
TMS
TCK
Instruction
0
Pause IR
1
Exit 2 IR
0
0
1
Update IR
0
1
6432 drw 17
6.42
16
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
Scan Register Definition
Part
Instrustion Register
Bypass Register
ID Register
Boundry Scan
512K x36
3 bits
1 bit
32 bits
107 bits
1Mx18
3 bits
1 bit
32 bits
107 bits
2Mx8/x9
3 bits
1 bit
32 bits
107 bits
6432 tbl 14
Identification Register Definitions
INSTRUCTION FIELD
Revision Number (31:29)
Device ID (28:12)
IDT JEDEC ID CODE (11:1)
ID Register Presence Indicator (0)
ALL DEVICES
0x0
0x0298
0x0299
0x029A
0x029B
0x033
1
DESCRIPTION
PART NUMBER
Revision Number
512Kx36
1Mx18
2Mx9
2Mx8
DDRII SIO BURST OF 2 71P79604S
71P79804S
71P79104S
71P79204S
Allows unique identification of SRAM
vendor.
Indicates the presence of an ID register.
6432 tbl 15
6.42
17
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
Boundary Scan Exit Order
ORDER
PIN ID
ORDER
PIN ID
ORDER
PIN ID
1
6R
37
10D
73
2C
2
6P
38
9E
74
3E
3
6N
39
10C
75
2D
4
7P
40
11D
76
2E
5
7N
41
9C
77
1E
6
7R
42
9D
78
2F
7
8R
43
11B
79
3F
8
8P
44
11C
80
1G
9
9R
45
9B
81
1F
10
11P
46
10B
82
3G
11
10P
47
11A
83
2G
12
10N
48
Internal
84
1J
13
9P
49
9A
85
2J
14
10M
50
8B
86
3K
15
11N
51
7C
87
3J
16
9M
52
6C
88
2K
17
9N
53
8A
18
11L
89
1K
54
7A
19
11M
55
7B
90
2L
20
9L
56
6B
91
3L
21
10L
57
6A
92
1M
22
11K
58
5B
93
1L
23
10K
59
5A
94
3N
24
9J
60
4A
95
3M
25
9K
61
5C
96
1N
26
10J
62
4B
97
2M
27
11J
63
3A
98
3P
28
11H
64
1H
99
2N
29
10G
65
1A
100
2P
30
9G
66
2B
101
1P
31
11F
67
3B
102
3R
32
11G
68
1C
103
4R
33
9F
69
1B
104
4P
34
10F
70
3D
105
5P
35
11E
71
3C
106
5N
36
10E
72
1D
107
5R
6432 tbl 16
6432 tbl 17
6.42
18
6432 tbl 18
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
JTAG DC Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Note
Output Power Supply
VDDQ
1.4
-
1.9
V
Power Supply Voltage
VDD
1.7
1.8
1.9
V
Input High Level
VIH
1.3
-
VDD + 0.3
V
Input Low Level
VIL
- 0.3
-
0.5
V
TCK Input Leakage Current
IIL
-5
-
+5
uA
TMS, TDI Input Leakage Current
IIL
- 15
-
+ 15
uA
TDO Output Leakage Current
IOL
-5
-
+5
uA
Output High Voltage (IOH = -1mA)
VOH
VDDQ - 0.2
-
VDDQ
V
1
Output Low Voltage (IOL = 1mA)
VOL
VSS
-
0.2
V
1
NOTE:
1. The output impedance of TDO is set to 50 ohms (nominal process) and does not vary with the external resistor
connected to ZQ.
6432 tbl 19
JTAG AC Test Conditions
Parameter
Symbol
Min
Unit
Input High Level
VIH
1.8
V
Input Low Level
VIL
0
V
TR/TF
1.0/1.0
ns
0.9
V
Input Rise/Fall Time
Input and Output Timing Reference Level
Note
1
6432 tbl 20
Note: 1. For SRAM outputs see AC test output load on page 13.
JTAG Input Test WaveForm
JTAG AC Test Load
1.8 V
0.9 V
0.9 V
Test points
0.9 V
0V
50ohm
6432 drw 23
Z0 = 50ohm
JTAG Output Test WaveForm
TDO
,
6109 drw 24
0.9 V
Test points
0.9 V
6432 drw 23a
6.42
19
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
JTAG AC Characteristics
Parameter
Symbol
Min
Max
Unit
TCK Cycle Time
tCHCH
50
-
ns
TCK High Pulse Width
tCHCL
20
-
ns
TCK Low Pulse Width
tCLCH
20
-
ns
TMS Input Setup Time
tMVCH
5
-
ns
TMS Input Hold Time
tCHMX
5
-
ns
TDI Input Setup Time
tDVCH
5
-
ns
TDI Input Hold Time
tCHDX
5
-
ns
SRAM Input Setup Time
tSVCH
5
-
ns
SRAM Input Hold Time
tCHSX
5
-
ns
Clock Low to Output Valid
tCLQV
0
10
ns
Note
6432 tbl 21
JTAG Timing Diagram
TCK
tCHCH
tCHCL
tMVCH
tCHMX
t DVCH
tCHDX
tSVCH
tCHSX
tCLCH
TMS
TDI/
SRAM
INPUTS
SRAM
OUTPUTS
t CLQV
TDO
6432drw 19
6.42
20
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
Package Diagram Outline for 165-Ball Fine Pitch Grid Array
6.42
21
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
Ordering Information
IDT
XXX
Device
Type
S
XXX
Power
Speed
BQ
X
Package
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
BQ
165 Fine Pitch Ball Grid Array (fBGA)
267*
250
200
167
Clock Frequency in MegaHertz
IDT71P79204
IDT71P79104
IDT71P79804
IDT71P79604
2M x 8 DDR II SIO SRAM
2M x 9 DDR II SIO SRAM
1M x 18 DDR II SIO SRAM
512K x 36 DDR II SIO SRAM
* Only offered in the x18 option.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2774
www.idt.com
6432 drw 15
for Tech Support:
[email protected]
800-345-7015 or 408-284-4555
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc.
6.42
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IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
Revision History
REV
DATE
PAGES
DESCRIPTION
0
07/26/05
p. 1-21
Released Final datasheet
1
11/30/05
p. 11,14,22
Added 267MHz speed grade to the DC and AC Electrical Characteristics tables and ordering
information.
6.42
23