NTHS5404 Power MOSFET 20 V, 7.2 A, N−Channel ChipFET Features • • • • Low RDS(on) for Higher Efficiency Logic Level Gate Drive Miniature ChipFET Surface Mount Package Saves Board Space Pb−Free Package is Available http://onsemi.com V(BR)DSS RDS(on) TYP ID MAX 20 V 25 m @ 4.5 V 7.2 A Applications • Power Management in Portable and Battery−Powered Products; i.e., Cellular and Cordless Telephones and PCMCIA Cards D MAXIMUM RATINGS (TA = 25°C unless otherwise noted) Rating Symbol Steady State 5 Secs Drain−Source Voltage VDS 20 V Gate−Source Voltage VGS 12 V Continuous Drain Current (TJ = 150°C) (Note 1) TA = 25°C TA = 85°C ID IS Maximum Power Dissipation (Note 1) TA = 25°C TA = 85°C PD 7.2 TJ, Tstg A 5.2 A W 2.5 1.3 ChipFET CASE 1206A STYLE 1 1.3 0.7 °C −55 to +150 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Surface Mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces). PIN CONNECTIONS MARKING DIAGRAM D 8 1 D 1 8 D 7 2 D 2 7 D 6 3 D 3 S 5 4 G 4 A2 M Operating Junction and Storage Temperature Range 5.2 3.8 20 IDM Continuous Source Current (Diode Conduction) (Note 1) S N−Channel MOSFET A 7.2 5.2 Pulsed Drain Current G Unit 6 5 A2 = Specific Device Code M = Month Code ORDERING INFORMATION Device Package Shipping† NTHS5404T1 ChipFET 3000/Tape & Reel NTHS5404T1G ChipFET (Pb−Free) 3000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2004 October, 2004 − Rev. 3 1 Publication Order Number: NTHS5404T1/D NTHS5404 THERMAL CHARACTERISTICS Characteristic Symbol Maximum Junction−to−Ambient (Note 2) t 5 sec Steady State RJA Maximum Junction−to−Foot (Drain) Steady State RJF Typ Max 40 80 50 95 15 20 Unit °C/W °C/W ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Symbol Test Condition Min Typ Max Unit VGS(th) VDS = VGS, ID = 250 A 0.6 − − V Gate−Body Leakage IGSS VDS = 0 V, VGS = 12 V − − 100 nA Zero Gate Voltage Drain Current IDSS VDS = 16 V, VGS = 0 V − − 1.0 A VDS = 16 V, VGS = 0 V, TJ = 85°C − − 5.0 ID(on) VDS 5.0 V, VGS = 4.5 V 20 − − A rDS(on) ( ) VGS = 4.5 V, ID = 5.2 A − 0.025 0.030 VGS = 2.5 V, ID = 4.3 A − 0.038 0.045 gfs VDS = 10 V, ID = 5.2 A − 20 − S VSD IS = 5.2 A, VGS = 0 V − 0.8 1.2 V − 12 18 nC − 2.4 − Characteristic Static Gate Threshold Voltage On−State Drain Current (Note 3) Drain−Source On−State Resistance (Note 3) Forward Transconductance (Note 3) Diode Forward Voltage (Note 3) Dynamic (Note 4) Total Gate Charge Gate−Source Charge QG QGS VDS = 10 V, VGS = 4.5 V, ID = 5.2 A Gate−Drain Charge QGD − 3.2 − Turn−On Delay Time td(on) − 20 30 − 40 60 − 40 60 − 15 23 − 30 60 Rise Time Turn−Off Delay Time tr td(off) Fall Time tf Source−Drain Reverse Recovery Time trr VDD = 10 V, RL = 10 ID 1.0 1 0 A, A VGEN = 4 4.5 5V V, RG = 6 IF = 1.1 A, di/dt = 100 A/s 2. Surface Mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces). 3. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 4. Guaranteed by design, not subject to production testing. http://onsemi.com 2 ns NTHS5404 TYPICAL ELECTRICAL CHARACTERISTICS 5V 12 1.8 V 2V ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) 12 10 TJ = 25°C VGS = 2 V − 5 V 8 1.6 V 6 4 1.4 V 2 10 8 6 4 125°C 25°C 2 VGS = 1.2 V TC = −55°C 0 0 0.5 1 2 1.5 2.5 3 1 1.5 2.5 2 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 0.06 ID = 5.2 A TJ = 25°C 0.05 0.04 0.03 0.02 0.01 0 0 2 1 4 3 5 0.040 TJ = 25°C 0.038 0.036 VGS = 2.5 V 0.034 0.032 0.030 VGS = 4.5 V 0.028 VGS = 6 V 0.026 0.024 2 3 4 5 7 6 8 9 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance versus Gate−to−Source Voltage Figure 4. On−Resistance versus Drain Current and Gate Voltage 1.6 10 1E−05 ID = 5.2 A VGS = 4.5 V VGS = 0 V 1.4 IDSS, LEAKAGE (AMPS) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 0.5 0 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) RDS(on), DRAIN−TO−SOURCE RESISTANCE () RDS(on), DRAIN−TO−SOURCE RESISTANCE () 0 1E−06 1.2 1 TJ = 150°C 1E−07 0.8 0.6 −50 TJ = 100°C 1E−08 −25 0 25 50 75 100 125 150 0 4 8 12 16 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 3 20 NTHS5404 5 VGS = 0 V TJ = 25°C 1500 900 9 4 8 7 6 5 2 600 4 ID = 5.2 A TJ = 25°C QGD/QGS = 1.33 0 0 8 12 4 VGS 0 VDS 4 8 12 16 3 2 1 0 0 20 1 2 3 4 5 6 7 8 9 10 11 12 QG, TOTAL GATE CHARGE (nC) GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge Figure 7. Capacitance Variation 100 IS, SOURCE CURRENT (AMPS) 5 td(off) tf t, TIME (ns) QGS QGD 1 Coss 300 td(on) 10 tr VDD = 10 V ID = +1.0 A VGS = 4.5 V 1 4 VGS = 0 V TJ = 25°C 3 2 1 0 1 10 0 100 0.2 0.4 0.6 0.8 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) RG, GATE RESISTANCE (OHMS) Figure 9. Resistive Switching Time Variation versus Gate Resistance NORMALIZED EFFECTIVE TRANSIENT THERMAL IMPEDANCE 10 3 Crss 1200 11 QG VGS, GATE−TO−SOURCE VOLTAGE (V) Ciss 1800 C, CAPACITANCE (pF) VDS = 0 V VDS, DRAIN−TO−SOURCE VOLTAGE (V) TYPICAL ELECTRICAL CHARACTERISTICS Figure 10. Diode Forward Voltage versus Current 1 Duty Cycle = 0.5 0.2 0.1 0.1 PDM PER UNIT BASE = RJA = 80°C/W TJM − TA = PDMZJA(t) SURFACE MOUNTED 0.05 t1 0.02 t2 DUTY CYCLE, D = t1/t2 Single Pulse 0.01 0.0001 0.001 0.01 0.1 1 10 100 SQUARE WAVE PULSE DURATION (sec) Figure 11. Normalized Thermal Transient Impedance, Junction−to−Ambient http://onsemi.com 4 1000 NTHS5404 SOLDERING FOOTPRINT* 2.032 0.08 2.032 0.08 0.457 0.018 0.635 0.025 1.727 0.068 0.457 0.018 0.178 0.007 0.711 0.028 0.711 0.028 0.66 0.026 0.66 0.026 Figure 12. Basic Figure 13. Style 1 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. BASIC PAD PATTERNS confines of the basic footprint. The drain copper area is 0.0054 sq. in. (or 3.51 sq. mm). This will assist the power dissipation path away from the device (through the copper lead−frame) and into the board and exterior chassis (if applicable) for the single device. The addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further. The basic pad layout with dimensions is shown in Figure 12. This is sufficient for low power dissipation MOSFET applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. The minimum recommended pad pattern shown in Figure 13 improves the thermal area of the drain connections (pins 1, 2, 3, 6, 7, 8) while remaining within the http://onsemi.com 5 NTHS5404 PACKAGE DIMENSIONS ChipFET CASE 1206A−03 ISSUE E A 8 7 M 6 K 5 S 5 6 7 8 4 3 2 1 B 1 2 3 L 4 D NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE. 4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL AND VERTICAL SHALL NOT EXCEED 0.08 MM. 5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS. 6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD SURFACE. 7. 1206A−01 AND 1206A−02 OBSOLETE. NEW STANDARD IS 1206A−03. J G DIM A B C D G J K L M S C 0.05 (0.002) MILLIMETERS MIN MAX 2.95 3.10 1.55 1.70 1.00 1.10 0.25 0.35 0.65 BSC 0.10 0.20 0.28 0.42 0.55 BSC 5 ° NOM 1.80 2.00 STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. INCHES MIN MAX 0.116 0.122 0.061 0.067 0.039 0.043 0.010 0.014 0.025 BSC 0.004 0.008 0.011 0.017 0.022 BSC 5 ° NOM 0.072 0.080 DRAIN DRAIN DRAIN GATE SOURCE DRAIN DRAIN DRAIN ChipFET is a trademark of Vishay Siliconix. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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