MX25U8033E MX25U8033E DATASHEET P/N: PM1718 1 REV. 1.4, NOV. 06, 2013 MX25U8033E Contents FEATURES..................................................................................................................................................................5 Table 1. Additional Feature Comparison............................................................................................................7 PIN CONFIGURATIONS .............................................................................................................................................8 PIN DESCRIPTION......................................................................................................................................................8 BLOCK DIAGRAM.......................................................................................................................................................9 DATA PROTECTION..................................................................................................................................................10 Table 2. Protected Area Sizes.......................................................................................................................... 11 Table 3. 4K-bit Secured OTP Definition............................................................................................................ 11 Memory Organization...............................................................................................................................................12 Table 4. Memory Organization........................................................................................................................12 DEVICE OPERATION................................................................................................................................................13 Figure 1. Serial Modes Supported...................................................................................................................13 HOLD FEATURE........................................................................................................................................................14 Figure 2. Hold Condition Operation .................................................................................................................14 COMMAND DESCRIPTION.......................................................................................................................................15 Table 5. Command Set.....................................................................................................................................15 (1) Write Enable (WREN).................................................................................................................................17 (2) Write Disable (WRDI)..................................................................................................................................17 (3) Read Identification (RDID)..........................................................................................................................17 (4) Read Status Register (RDSR)....................................................................................................................17 Program/ Erase Flow with Read Array Data....................................................................................................18 Program/ Erase Flow without Read Array Data (read P_FAIL/E_FAIL flag).....................................................19 WRSR Flow......................................................................................................................................................20 (5) Write Status Register (WRSR)....................................................................................................................22 Table 7. Protection Modes................................................................................................................................22 (6) Read Data Bytes (READ)...........................................................................................................................23 (7) Read Data Bytes at Higher Speed (FAST_READ).....................................................................................23 (8) Dual Read Mode (DREAD).........................................................................................................................23 (9) 2 x I/O Read Mode (2READ)......................................................................................................................24 (10) 4 x I/O Read Mode (4READ)....................................................................................................................24 (11) Performance Enhance Mode....................................................................................................................25 (12) Sector Erase (SE).....................................................................................................................................25 (13) Block Erase (BE32K)................................................................................................................................26 (14) Block Erase (BE)......................................................................................................................................26 (15) Chip Erase (CE)........................................................................................................................................26 (16) Page Program (PP)..................................................................................................................................27 (17) 4 x I/O Page Program (4PP).....................................................................................................................27 (18) Deep Power-down (DP)............................................................................................................................27 P/N: PM1718 2 REV. 1.4, NOV. 06, 2013 MX25U8033E (19) Release from Deep Power-down (RDP), Read Electronic Signature (RES)............................................28 (20) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4)..........................................28 Table 8. ID Definitions .....................................................................................................................................29 (21) Enter Secured OTP (ENSO).....................................................................................................................29 (22) Exit Secured OTP (EXSO)........................................................................................................................29 (23) Read Security Register (RDSCUR)..........................................................................................................29 Table 9. Security Register Definition................................................................................................................30 (24) Write Security Register (WRSCUR)..........................................................................................................30 (25) Write Protection Selection (WPSEL).........................................................................................................30 Figure 3. WPSEL Flow....................................................................................................................................31 (26) Single Block Lock/Unlock Protection (SBLK/SBULK)...............................................................................32 Figure 4. Block Lock Flow................................................................................................................................32 Figure 5. Block Unlock Flow.............................................................................................................................33 (27) Read Block Lock Status (RDBLOCK).......................................................................................................34 (28) Gang Block Lock/Unlock (GBLK/GBULK)................................................................................................34 (29) Read SFDP Mode (RDSFDP)...................................................................................................................35 Figure 6. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence..................................................35 Table 10. Signature and Parameter Identification Data Values .......................................................................36 Table 11. Parameter Table (0): JEDEC Flash Parameter Tables.....................................................................37 Table 12. Parameter Table (1): Macronix Flash Parameter Tables..................................................................39 POWER-ON STATE...................................................................................................................................................41 ELECTRICAL SPECIFICATIONS..............................................................................................................................42 ABSOLUTE MAXIMUM RATINGS...................................................................................................................42 Figure 7. Maximum Negative Overshoot Waveform........................................................................................42 CAPACITANCE TA = 25°C, f = 1.0 MHz...........................................................................................................42 Figure 8. Maximum Positive Overshoot Waveform..........................................................................................42 Figure 9. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL............................................................43 Figure 10. OUTPUT LOADING.......................................................................................................................43 Table 13. DC CHARACTERISTICS (Temperature = -40°C to 85°C, VCC = 1.65V ~ 2.0V) ............................44 Table 14. AC CHARACTERISTICS (Temperature = -40°C to 85°C, VCC = 1.65V ~ 2.0V) ...........................45 Timing Analysis........................................................................................................................................................46 Figure 11. Serial Input Timing...........................................................................................................................46 Figure 12. Output Timing..................................................................................................................................46 Figure 13. Hold Timing.....................................................................................................................................47 Figure 14. WP# Setup Timing and Hold Timing during WRSR when SRWD=1...............................................47 Figure 15. Write Enable (WREN) Sequence (Command 06)...........................................................................47 Figure 16. Write Disable (WRDI) Sequence (Command 04)............................................................................48 Figure 17. Read Identification (RDID) Sequence (Command 9F) ...................................................................48 Figure 18. Read Status Register (RDSR) Sequence (Command 05) .............................................................48 Figure 19. Write Status Register (WRSR) Sequence (Command 01).............................................................49 P/N: PM1718 3 REV. 1.4, NOV. 06, 2013 MX25U8033E Figure 20. Read Data Bytes (READ) Sequence (Command 03) (50MHz).....................................................49 Figure 21. Read at Higher Speed (FAST_READ) Sequence (Command 0B) ...............................................50 Figure 22. Dual Read Mode Sequence (Command 3B)..................................................................................50 Figure 23. 2 x I/O Read Mode Sequence (Command BB)...............................................................................51 Figure 24. 4 x I/O Read Mode Sequence (Command EB) .............................................................................51 Figure 25. 2 x I/O Read Enhance Performance Mode Sequence (Command BB)..........................................52 Figure 26. 4 x I/O Read Enhance Performance Mode Sequence (Command EB)..........................................53 Figure 27. Page Program (PP) Sequence (Command 02) ............................................................................54 Figure 28. 4 x I/O Page Program (4PP) Sequence (Command 38)................................................................54 Figure 29. Sector Erase (SE) Sequence (Command 20)................................................................................55 Figure 30. Block Erase 32KB (BE32K) Sequence (Command 52).................................................................55 Figure 31. Block Erase (BE) Sequence (Command D8).................................................................................55 Figure 32. Chip Erase (CE) Sequence (Command 60 or C7).........................................................................55 Figure 33. Deep Power-down (DP) Sequence (Command B9)......................................................................56 Figure 34. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB) 56 Figure 35. Release from Deep Power-down (RDP) Sequence (Command AB).............................................57 Figure 36. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90/EF/DF)................57 Figure 37. Read Security Register (RDSCUR) Sequence (Command 2B)......................................................58 Figure 38. Write Security Register (WRSCUR) Sequence (Command 2F).....................................................58 Figure 39. Power-up Timing.............................................................................................................................59 Table 15. Power-Up Timing and VWI Threshold..............................................................................................59 INITIAL DELIVERY STATE..............................................................................................................................59 OPERATING CONDITIONS.......................................................................................................................................60 Figure 40. AC Timing at Device Power-Up.......................................................................................................60 Figure 41. Power-Down Sequence..................................................................................................................61 ERASE AND PROGRAMMING PERFORMANCE....................................................................................................62 LATCH-UP CHARACTERISTICS..............................................................................................................................62 ORDERING INFORMATION......................................................................................................................................63 PART NAME DESCRIPTION.....................................................................................................................................64 PACKAGE INFORMATION........................................................................................................................................65 REVISION HISTORY .................................................................................................................................................69 P/N: PM1718 4 REV. 1.4, NOV. 06, 2013 MX25U8033E 8M-BIT [x 1/x 2/x 4] 1.8V CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY FEATURES GENERAL • Single Power Supply Operation - 1.65 to 2.0 volt for read, erase, and program operations • Serial Peripheral Interface compatible -- Mode 0 and Mode 3 • 8M: 8,388,608 x 1 bit structure or 4,194,304 x 2 bits (two I/O read mode) structure or 2,097,152 x 4 bits (four I/O read mode) structure • 256 Equal Sectors with 4K byte each - Any Sector can be erased individually • 32 Equal Blocks with 32K byte each - Any Block can be erased individually • 16 Equal Blocks with 64K byte each - Any Block can be erased individually • Program Capability - Byte base - Page base (256 bytes) • Latch-up protected to 100mA from -1V to Vcc +1V PERFORMANCE • High Performance - Fast read - 1 I/O: 80MHz with 8 dummy cycles - 2 I/O: 80MHz with 4 dummy cycles, equivalent to 160MHz - 4 I/O: 70MHz with 6 dummy cycles, equivalent to 280MHz; - Fast program time: 1.2ms(typ.) and 3.0ms(max.)/page (256-byte per page) - Byte program time: 10us (typ.) - Fast erase time - 30ms(typ.) and 200ms(max.)/sector (4K-byte per sector) - 200ms(typ.) and 1000ms(max.)/block (32K-byte per block) - 500ms(typ.) and 2000ms(max.)/block (64K-byte per block) - 5.0s(typ.) and 10s(max.)/chip • Low Power Consumption - Low active read current: 12mA(max.) at 80MHz, 7mA(max.) at 33MHz - Low active erase/programming current: 25mA (max.) - Low standby current: 8uA (typ.)/30uA (max.) • Low Deep Power Down current: 8uA(max.) • Typical 100,000 erase/program cycles • 20 years data retention SOFTWARE FEATURES • Input Data Format - 1-byte Command code • Advanced Security Features - Block lock protection The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instructions - Additional 4K-bit secured OTP for unique identifier • Auto Erase and Auto Program Algorithm - Automatically erases and verifies data at selected sector or block - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first). P/N: PM1718 5 REV. 1.4, NOV. 06, 2013 MX25U8033E • Status Register Feature • Electronic Identification - JEDEC 1-byte manufacturer ID and 2-byte device ID - RES command for 1-byte Device ID - REMS, REMS2 and REMS4 commands for 1-byte manufacturer ID and 1-byte device ID • Support Serial Flash Discoverable Parameter (SFDP) mode HARDWARE FEATURES • SCLK Input - Serial clock input • SI/SIO0 - Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode • SO/SIO1 - Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode • WP#/SIO2 - Hardware write protection or serial data Input/Output for 4 x I/O read mode • HOLD#/SIO3 - HOLD feature, to pause the device without deselecting the device or serial data Input/Output for 4 x I/O read mode • PACKAGE - 8-land USON (4x4mm) - 8-pin SOP (150mil) - 8-pin SOP (200mil) - 8-land WSON (6x5mm) - All devices are RoHS Compliant and Halogen-free GENERAL DESCRIPTION The MX25U8033E is 8,388,608 bit serial Flash memory, which is configured as 1,048,576 x 8 internally. The MX25U8033E features a serial peripheral interface and software protocol allowing operation on a simple 4-wire bus while it is in single I/O mode. The four bus signals are a clock input (SCLK), a serial data input (SI), a serial data output (SO) and a chip select (CS#). Serial access to the device is enabled by CS# input. When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# pin and HOLD# pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output. The MX25U8033E MXSMIO (Serial Multi I/O) provides sequential read operation on the whole chip. After program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis. Erase command is executed on 4K-byte sector, 32K-byte block, or 64K-byte block, or whole chip basis. To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via the WIP bit. Advanced security features enhance the protection and security functions, please see security features section for more details. When the device is not in operation and CS# is high, it is put in standby mode. The MX25U8033E utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. P/N: PM1718 6 REV. 1.4, NOV. 06, 2013 MX25U8033E Table 1. Additional Feature Comparison Additional Features Part Name MX25U8033E P/N: PM1718 Protection and Security Flexible Block Protection (BP0-BP3) Individual Protect V V Read Performance 4K-bit 2 I/O Read secured OTP V V 7 4 I/O Read V Identifier REMS/ REMS2/ RES RDID REMS4 (Command: (Command: (Command: AB hex) 9F hex) 90/EF/DF hex) C2 34 (hex) C2 25 34 34 (hex) (if ADD=0) (hex) REV. 1.4, NOV. 06, 2013 MX25U8033E PIN CONFIGURATIONS 8-PIN SOP (150mil/200mil) 8-LAND USON (4x4mm) CS# SO/SIO1 WP#/SIO2 GND 1 2 3 4 8 7 6 5 VCC HOLD#/SIO3 SCLK SI/SIO0 CS# SO/SIO1 WP#/SIO2 GND P/N: PM1718 1 2 3 4 8 7 6 5 8 7 6 5 VCC HOLD#/SIO3 SCLK SI/SIO0 PIN DESCRIPTION 8-LAND WSON (6x5mm) CS# SO/SIO1 WP#/SIO2 GND 1 2 3 4 SYMBOL CS# DESCRIPTION Chip Select Serial Data Input (for 1 x I/O)/ Serial SI/SIO0 Data Input & Output (for 2xI/O or 4xI/ O read mode) Serial Data Output (for 1 x I/O)/ Serial SO/SIO1 Data Input & Output (for 2xI/O or 4xI/ O read mode) SCLK Clock Input Hardware write protection: connect to WP#/SIO2 GND or Serial Data Input & Output (for 4xI/O read mode) To pause the device without HOLD#/SIO3 deselecting the device or Serial Data Input & Output (for 4xI/O read mode) VCC + 1.8V Power Supply GND Ground VCC HOLD#/SIO3 SCLK SI/SIO0 8 REV. 1.4, NOV. 06, 2013 MX25U8033E BLOCK DIAGRAM X-Decoder Address Generator Memory Array Page Buffer SI/SIO0 Data Register Y-Decoder SRAM Buffer CS# WP#/SIO2 HOLD#/SIO3 SCLK Mode Logic State Machine HV Generator Clock Generator Output Buffer SO/SIO1 P/N: PM1718 Sense Amplifier 9 REV. 1.4, NOV. 06, 2013 MX25U8033E DATA PROTECTION During power transition, there may be some false system level signals which result in inadvertent erasure or programming. The device is designed to protect itself from these accidental write cycles. The state machine will be reset as standby mode automatically during power up. In addition, the control register architecture of the device constrains that the memory contents can only be changed after specific command sequences have completed successfully. In the following, there are several features to protect the system from the accidental write cycles during VCC powerup and power-down or from system noise. • Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary. • Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before issuing other commands to change data. The WEL bit will return to resetting stage while the following conditions occurred: - Power-up - Completion of Write Disable (WRDI) command - Completion of Write Status Register (WRSR) command - Completion of Page Program (PP) command - Completion of Quad page program (4PP) command - Completion of Sector Erase (SE) command - Completion of Block Erase 32KB (BE32K) command - Completion of Block Erase (BE) command - Completion of Chip Erase (CE) command - Completion of Write Protection Select (WPSEL) command - Completion of Write Security Register (WRSCUR) command - Completion of Single Block Lock/Unlock (SBLK/SBULK) command - Completion of Gang Block Lock/Unlock (GBLK/GBULK) command • Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all commands except Release from deep power down mode command (RDP) and Read Electronic Signature command (RES). • Advanced Security Features: there are some protection and security features which protect content from inadvertent write and hostile access. I. Block lock protection - The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected as read only. The protected area definition is shown as table of "Protected Area Sizes", the protected areas are more flexible which may protect various area by setting value of BP0-BP3 bits. Please refer to table of "Protected Area Sizes". - The Hardware Protected Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and SRWD bit. If the system goes into four I/O read mode, the feature of HPM will be disabled. P/N: PM1718 10 REV. 1.4, NOV. 06, 2013 MX25U8033E Table 2. Protected Area Sizes BP3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Status Bit BP2 BP1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 BP0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Protect Level 8Mb 0 (none) 1 (1block, protected block 15th) 2 (2blocks, protected block 14th~15th) 3 (4blocks, protected block 12nd~15th) 4 (8blocks, protected block 8th~15th) 5 (16blocks, protected all) 6 (16blocks, protected all) 7 (16blocks, protected all) 8 (16blocks, protected all) 9 (16blocks, protected all) 10 (16blocks, protected all) 11 (8blocks, protected block 0th~7th) 12 (12blocks, protected block 0th~11st) 13 (14blocks, protected block 0th~13rd) 14 (15blocks, protected block 0th~14th) 15 (16blocks, protected all) II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit One-Time Program area for setting device unique serial number - Which may be set by factory or system maker. Please refer to Table 3. 4K-bit Secured OTP Definition. - Security register bit 0 indicates whether the chip is locked by factory or not. - To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with ENSO command), and going through normal program procedure, and then exiting 4K-bit secured OTP mode by writing EXSO command. - Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register) command to set customer lock-down bit1 as "1". Please refer to table of "Security Register Definition" for security register bit definition and table of "4K-bit Secured OTP Definition" for address range definition. Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit Secured OTP mode, array access is not allowed. Table 3. 4K-bit Secured OTP Definition Address range Size Standard Factory Lock xxx000~xxx00F 128-bit ESN (electrical serial number) xxx010~xxx1FF 3968-bit N/A P/N: PM1718 11 Customer Lock Determined by customer REV. 1.4, NOV. 06, 2013 MX25U8033E Memory Organization Table 4. Memory Organization Block (64KB) 15 Block (32KB) 31 | 30 14 29 | 28 13 27 | 26 12 25 | 24 11 23 | 22 10 21 | 20 9 19 | 18 8 17 | 16 7 15 | 14 6 13 | 12 5 11 | 10 4 9 | 8 3 7 | 6 2 5 | 4 1 3 | 2 0 P/N: PM1718 1 | 0 Sector (4KB) 255 : 240 239 : 224 223 : 208 207 : 192 191 : 176 175 : 160 159 : 144 143 : 128 127 : 112 111 : 96 95 : 80 79 : 64 63 : 48 47 : 32 31 : 16 15 : 2 1 0 Address Range 0FF000h : 0F0000h 0EF000h : 0E0000h 0DF000h : 0D0000h 0CF000h : 0C0000h 0BF000h : 0B0000h 0AF000h : 0A0000h 09F000h : 090000h 08F000h : 080000h 07F000h : 070000h 06F000h : 060000h 05F000h : 050000h 04F000h : 040000h 03F000h : 030000h 02F000h : 020000h 01F000h : 010000h 00F000h : 002000h 001000h 000000h 0FFFFFh : 0F0FFFh 0EFFFFh : 0E0FFFh 0DFFFFh : 0D0FFFh 0CFFFFh : 0C0FFFh 0BFFFFh : 0B0FFFh 0AFFFFh : 0A0FFFh 09FFFFh : 090FFFh 08FFFFh : 080FFFh 07FFFFh : 070FFFh 06FFFFh : 060FFFh 05FFFFh : 050FFFh 04FFFFh : 040FFFh 03FFFFh : 030FFFh 02FFFFh : 020FFFh 01FFFFh : 010FFFh 00FFFFh : 002FFFh 001FFFh 000FFFh ▲ Individual Sector Lock/Unlock ▼ ▲ Individual Block Lock/Unlock ▼ ▲ Individual Sector Lock/Unlock ▼ 12 REV. 1.4, NOV. 06, 2013 MX25U8033E DEVICE OPERATION 1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. When incorrect command is inputted to this device, it enters standby mode and remains in the standby mode until next CS# falling edge. In standby mode, SO pin of the device is High-Z. 3. When correct command is inputted to this device, it becomes active mode and remains in the active mode until next CS# rising edge. 4. Input data is latched on the rising edge of Serial Clock (SCLK) and data is shifted out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as Figure 1. "Serial Modes Supported". 5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, 2READ, DREAD, 4READ, RES, REMS, REMS2, REMS4 and RDSFDP, the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE32K, BE, CE, PP, 4PP, RDP, DP, WPSEL, SBLK, SBULK, GBLK, GBULK,ENSO, EXSO, and WRSCUR, the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. While a Write Status Register, Program or Erase operation is in progress, to the memory array is neglected and while not affect the current operation of WRSCUR, WPSEL Write Status Register, Program and Erase. Figure 1. Serial Modes Supported CPOL CPHA shift in (Serial mode 0) 0 0 SCLK (Serial mode 3) 1 1 SCLK SI shift out MSB SO MSB Note: CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is supported. P/N: PM1718 13 REV. 1.4, NOV. 06, 2013 MX25U8033E HOLD FEATURE HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the operation of write status register, programming, or erasing in progress. The operation of HOLD requires Chip Select (CS#) keeping low and starts on falling edge of HOLD# pin signal while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not end until Serial Clock being low), see Figure 2. Figure 2. Hold Condition Operation CS# SCLK HOLD# Hold Condition (standard) Hold Condition (non-standard) The Serial Data Output (SO) is high impedance, both Serial Data Input (SI) and Serial Clock (SCLK) are don't care during the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low. P/N: PM1718 14 REV. 1.4, NOV. 06, 2013 MX25U8033E COMMAND DESCRIPTION Table 5. Command Set Read Commands I/O Command (byte) Clock rate (MHz) 1st byte 2nd byte 3rd byte 4th byte 5th byte Action 1 1 1 READ FAST READ RDSFDP (normal read) (fast read data) (Read SFDP) 2 2 4 2READ (2 x I/O read command) DREAD (1I / 2O read command) 4READ (4 x I/O read command) 50 80 80 80 80 70 03 (hex) AD1 AD2 AD3 0B (hex) AD1 AD2 AD3 Dummy n bytes read out until CS# goes high 5A (hex) AD1 AD2 AD3 Dummy Read SFDP mode BB (hex) AD1 AD2 AD3 Dummy n bytes read out by 2 x I/O until CS# goes high 3B (hex) AD1 AD2 AD3 Dummy EB (hex) AD1 AD2 AD3 Dummy n bytes read out by 4 x I/O until CS# goes high RDSR (read status register) 05 (hex) WRSR (write status register) 01 (hex) Values 4PP (Quad page program) DP (Deep power down) n bytes read out until CS# goes high Program/Erase Commands Command (byte) 1st byte 2nd byte 3rd byte 4th byte Action BE 32K BE (block erase (block erase 32KB) 64KB) 06 (hex) 04 (hex) 20 (hex) 52 (hex) D8 (hex) AD1 AD1 AD1 AD2 AD2 AD2 AD3 AD3 AD3 to read out the to write new to erase the to erase the to erase the sets the (WEL) resets the values of the values of the selected sector selected 32KB selected block write enable (WEL) write block latch bit enable latch bit status register status register WREN WRDI (write enable) (write disable) Command (byte) CE (chip erase) 1st byte 2nd byte 3rd byte 4th byte 60 or C7 (hex) Action P/N: PM1718 PP (page program) 02 (hex) 38 (hex) AD1 AD1 AD2 AD2 AD3 AD3 to erase whole to program the quad input to chip selected page program the selected page 15 SE (sector erase) B9 (hex) RDP (Release from deep power down) AB (hex) enters deep power down mode release from deep power down mode REV. 1.4, NOV. 06, 2013 MX25U8033E Security/ID/Mode Setting/Reset Commands Command (byte) RDID (read identification) 1st byte 2nd byte 3rd byte 4th byte 9F (hex) Action Command (byte) 1st byte 2nd byte 3rd byte 4th byte Action Command (byte) 1st byte 2nd byte 3rd byte 4th byte Action Note RES (read electronic ID) REMS (read REMS2 (read electronic ID for 2x I/O manufacturer & mode) device ID) REMS4 (read ID for 4x I/O mode) ENSO (enter EXSO (exit secured OTP) secured OTP) AB (hex) 90 (hex) EF (hex) DF (hex) B1 (hex) C1 (hex) x x X x x x X x x ADD ADD ADD to enter the to exit the outputs JEDEC to read out output the output the output the ID: 1-byte 1-byte Device Manufacturer Manufacturer Manufacturer 4K-bit secured 4K-bit secured OTP mode OTP mode Manufacturer ID ID & Device ID ID & Device ID ID & Device ID ID & 2-byte Device ID RDSCUR (read security register) 2B (hex) to read value of security register WRSCUR (write security register) 2F (hex) SBLK (single block lock 36 (hex) AD1 AD2 AD3 to set the lock- individual block down bit as (64K-byte) or "1" (once lock- sector (4K-byte) down, cannot write protect be update) SBULK RDBLOCK (single block (block protect unlock) read) 39 (hex) 3C (hex) AD1 AD1 AD2 AD2 AD3 AD3 individual block read individual (64K-byte) or block or sector sector (4K-byte) write protect unprotect status GBLK (gang block lock) 7E (hex) GBULK (gang block unlock) 98 (hex) whole chip write protect whole chip unprotect WPSEL (Write Protect Selection) 68 (hex) to enter and enable individal block protect mode 1: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first. 2: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode. P/N: PM1718 16 REV. 1.4, NOV. 06, 2013 MX25U8033E (1) Write Enable (WREN) The Write Enable (WREN) instruction is to set Write Enable Latch (WEL) bit. For those instructions like PP, 4PP, SE, BE32K, BE, CE, WPSEL, WRSCUR, SBLK, SBULK, GBLK, GBULK and WRSR, which are intended to change the device content WEL bit should be set every time after the WREN instruction setting the WEL bit. The sequence of issuing WREN instruction is: CS# goes low→sending WREN instruction code→ CS# goes high. (Please refer to Figure 15) (2) Write Disable (WRDI) The Write Disable (WRDI) instruction is to reset Write Enable Latch (WEL) bit. The sequence of issuing WRDI instruction is: CS# goes low→sending WRDI instruction code→CS# goes high. (Please refer to Figure 16) The WEL bit will be reset while the following conditions occurred: - Power-up - Completion of Write Disable (WRDI) instruction - Completion of Write Status Register (WRSR) instruction - Completion of Page Program (PP) instruction - Completion of Quad page program (4PP) instruction - Completion of Sector Erase (SE) instruction - Completion of Block Erase 32KB (BE32K) instruction - Completion of Block Erase (BE) instruction - Completion of Chip Erase (CE) instruction - Completion of Write Protection Select (WPSEL) instruction - Completion of Write Security Register (WRSCUR) instruction - Completion of Single Block Lock/Unlock (SBLK/SBULK) instruction - Completion of Gang Block Lock/Unlock (GBLK/GBULK) instruction (3) Read Identification (RDID) The RDID instruction is to read the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macronix Manufacturer ID is C2(hex), the memory type ID is 25(hex) as the first-byte device ID, and the individual device ID of second-byte ID are listed as table of "ID Definitions". (Please refer to Table 8) The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code→24-bits ID data out on SO→ to end RDID operation can drive CS# to high at any time during data out. (Please refer to Figure 17) While Program/Erase operation is in progress, it will not decode the RDID instruction, therefore there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage. (4) Read Status Register (RDSR) The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/WPSEL/WRSCUR/write status register condition). It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. P/N: PM1718 17 REV. 1.4, NOV. 06, 2013 MX25U8033E The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data out on SO. (Please refer to Figure 18) For user to check if Program/Erase operation is finished or not, RDSR instruction flow are shown as follows: Program/ Erase Flow with Read Array Data start WREN command RDSR command* WREN=1? No Yes Program/erase command Write program data/address (Write erase address) RDSR command WIP=0? No Yes RDSR command Read WEL=0, BP[3:0], QE, and SRWD data Read array data (same address of PGM/ERS) Verify OK? No Yes Program/erase successfully Program/erase another block? Program/erase fail Yes * Issue RDSR to check BP[3:0]. * If WPSEL = 1, issue RDSLOCK to check the block status. No Program/erase completed P/N: PM1718 18 REV. 1.4, NOV. 06, 2013 MX25U8033E Program/ Erase Flow without Read Array Data (read P_FAIL/E_FAIL flag) start WREN command RDSR command* WREN=1? No Yes Program/erase command Write program data/address (Write erase address) RDSR command WIP=0? No Yes RDSR command Read WEL=0, BP[3:0], QE, and SRWD data RDSCUR command Yes P_FAIL/E_FAIL=1 ? No Program/erase fail Program/erase successfully Program/erase another block? No Yes * Issue RDSR to check BP[3:0]. * If WPSEL = 1, issue RDBLOCK to check the block status. Program/erase completed P/N: PM1718 19 REV. 1.4, NOV. 06, 2013 MX25U8033E WRSR Flow start WREN command RDSR command No WREN=1? Yes WRSR command Write status register data RDSR command No WIP=0? Yes RDSR command Read WEL=0, BP[3:0], QE, and SRWD data No Verify OK? Yes WRSR successfully P/N: PM1718 20 WRSR fail REV. 1.4, NOV. 06, 2013 MX25U8033E The definition of the status register bits is as below: WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. The program/erase command will be ignored if it is applied to a protected memory area. To ensure both WIP bit & WEL bit are both set to 0 and available for next program/ erase/operations, WIP bit needs to be confirm to be 0 before polling WEL bit. After WIP bit confirmed, WEL bit needs to be confirm to be 0. BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as defined in table 2) of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase 32KB (BE32K), Block Erase (BE) and Chip Erase (CE) instructions (only if Block Protect bits (BP3:BP0) set to 0, the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default. Which is un-protected. QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0" (factory default), it performs non-Quad and WP# is enable. While QE is "1", it performs Quad I/O mode and WP# is disabled. In the other word, if the system goes into four I/O mode (QE=1), the features of HPM and HOLD will be disabled. SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only. The SRWD bit defaults to be "0". Table 6. Status Register bit7 bit6 SRWD (status register write protect) QE (Quad Enable) bit5 BP3 (level of protected block) bit4 BP2 (level of protected block) 1=Quad 1=status Enable register write (note 1) (note 1) 0=not Quad disable Enable Non-volatile Non-volatile Non-volatile Non-volatile bit bit bit bit Note 1: see the Table 2 "Protected Area Size". P/N: PM1718 bit3 BP1 (level of protected block) bit2 BP0 (level of protected block) (note 1) (note 1) Non-volatile bit Non-volatile bit 21 bit1 bit0 WEL WIP (write enable (write in latch) progress bit) 1=write 1=write enable operation 0=not write 0=not in write enable operation volatile bit volatile bit REV. 1.4, NOV. 06, 2013 MX25U8033E (5) Write Status Register (WRSR) The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the protected area of memory (as shown in Table 2). The WRSR also can set or reset the Quad enable (QE) bit and set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of the status register. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered. The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register data on SI→CS# goes high. (Please refer to Figure 19) The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset. Table 7. Protection Modes Mode Software protection mode (SPM) Hardware protection mode (HPM) Status register condition WP# and SRWD bit status Memory Status register can be written in (WEL bit is set to "1") and the SRWD, BP0-BP3 bits can be changed WP#=1 and SRWD bit=0, or WP#=0 and SRWD bit=0, or WP#=1 and SRWD=1 The protected area cannot be program or erase. The SRWD, BP0-BP3 of status register bits cannot be changed WP#=0, SRWD bit=1 The protected area cannot be program or erase. Note: 1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 2. As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM). Software Protected Mode (SPM): - When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM). - When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM) Note: If SRWD bit=1 but WP#/SIO2 is low, it is impossible to write the Status Register even if the WEL bit has previously been set. It is rejected to write the Status Register and not be executed. P/N: PM1718 22 REV. 1.4, NOV. 06, 2013 MX25U8033E Hardware Protected Mode (HPM): - When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2, BP1, BP0 and hardware protected mode by the WP#/SIO2 to against data modification. Note: To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered. If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP3, BP2, BP1, BP0. If the system enter Quad I/O QE=1, the feature of HPM will be disabled. (6) Read Data Bytes (READ) The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing READ instruction is: CS# goes low→sending READ instruction code→ 3-byte address on SI→ data out on SO→to end READ operation can use CS# to high at any time during data out. (Please refer to Figure 20) (7) Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→ 3-byte address on SI→1-dummy byte (default) address on SI→ data out on SO→ to end FAST_READ operation can use CS# to high at any time during data out. (Please refer to Figure 21) While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (8) Dual Read Mode (DREAD) The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit. The sequence of issuing DREAD instruction is: CS# goes low → sending DREAD instruction → 3-byte address on SI → 8-bit dummy cycle → data out interleave on SO1 & SO0 → to end DREAD operation can use CS# to high at any time during data out. (Please refer to Figure 22) P/N: PM1718 23 REV. 1.4, NOV. 06, 2013 MX25U8033E While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (9) 2 x I/O Read Mode (2READ) The 2READ instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 24-bit address interleave on SIO1 & SIO0→ 4 dummy cycles on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→ to end 2READ operation can use CS# to high at any time during data out (Please refer to Figure 23 for 2 x I/O Read Mode Timing Waveform). While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (10) 4 x I/O Read Mode (4READ) The 4READ instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. The sequence of issuing 4READ instruction is: CS# goes low→ sending 4READ instruction→ 24-bit address interleave on SIO3, SIO2, SIO1 & SIO0→2+4 dummy cycles→data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end 4READ operation can use CS# to high at any time during data out. (Please refer to Figure 24) While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. P/N: PM1718 24 REV. 1.4, NOV. 06, 2013 MX25U8033E (11) Performance Enhance Mode The device could waive the command cycle bits if the two cycle bits after address cycle toggles. (Please note Figure 25 2xI/O Read Enhance Performance Mode Sequence and Figure 26 4xI/O Read Enhance Performance Mode Sequence) After entering enhance mode, following CS# go high, the device will stay in the read mode and treat CS# go low of the first clock as address instead of command cycle. Another sequence of issuing 2READ (or 4READ) instruction especially useful in random access is: CS# goes low→sending 2READ (or 4READ) instruction→3-bytes address interleave on SIO1, SIO0 (SIO3, SIO2, SIO1 & SIO0)→Performance enhance toggling bit P[3:0] ( P[7:0] )→ 2 (or 4) dummy cycles →data out still CS# goes high → CS# goes low (reduce 2READ or 4READ instruction) →24-bit random access address (Please refer to Figure 25 and Figure 26 for 2x I/O and 4xI/O Read Enhance Performance Mode Timing Waveforms). In the 2xI/O performance-enhancing mode, P[3:2] must be toggling with P[1:0]; likewise P[3:0]=21h, 12h, 30h or 03h can make this mode continue and reduce the next 2READ instruction. Once P[3:2] is no longer toggling with P[1:0]; likewise P[3:0]=33h, 00h, 22h or 11h and afterwards CS# is raised and then lowered, the system then will escape from performance enhance mode and return to normal operation. In the 4xI/O performance-enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh can make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0]; likewise P[7:0]=FFh,00h,AAh or 55h and afterwards CS# is raised and then lowered, the system then will escape from performance enhance mode and return to normal operation. (12) Sector Erase (SE) The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (see table of memory organization) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of the address been latched-in); otherwise, the instruction will be rejected and not executed. Address bits [Am-A12] (Am is the most significant address) select the sector address. The sequence of issuing SE instruction is: CS# goes low→ sending SE instruction code→ 3-byte address on SI→ CS# goes high. (Please refer to Figure 29) The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets during the tSE timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the sector is protected by BP3 ~ 0 (WPSEL=0) or by individual lock (WPSEL=1), the Sector Erase (SE) instruction will not be executed on the sector. P/N: PM1718 25 REV. 1.4, NOV. 06, 2013 MX25U8033E (13) Block Erase (BE32K) The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 32K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE32K). Any address of the block (see table of memory organization) is a valid address for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing BE32K instruction is: CS# goes low→ sending BE32K instruction code→ 3-byte address on SI→CS# goes high. (Please refer to Figure 30) The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while he Block Erase cycle is in progress. The WIP sets during the tBE32K timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the block is protected by BP3 ~ 0 (WPSEL=0) or by individual lock (WPSEL=1), the Block Erase (tBE32K) instruction will not be executed on the block. (14) Block Erase (BE) The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (Please refer to table of memory organization) is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing BE instruction is: CS# goes low→ sending BE instruction code→ 3-byte address on SI→ CS# goes high. (Please refer to Figure 31) The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the tBE timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the block is protected by BP3 ~ 0 (WPSEL=0) or by individual lock (WPSEL=1), the Block Erase (BE) instruction will not be executed on the block. (15) Chip Erase (CE) The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed. The sequence of issuing CE instruction is: CS# goes low→sending CE instruction code→CS# goes high. (Please refer to Figure 32) The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Chip Erase cycle is in progress. The WIP sets during the tCE timing, and clears when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the chip is protected by BP3 ~ 0 (WPSEL=0) or by individual lock (WPSEL=1), the Chip Erase (CE) instruction will not be executed. It will be only executed when BP3, BP2, BP1, BP0 all set to "0". P/N: PM1718 26 REV. 1.4, NOV. 06, 2013 MX25U8033E (16) Page Program (PP) The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed, A7A0 (The eight least significant address bits) should be cleared. The last address byte (the 8 least significant address bits, A7-A0) should be set to 0 for 256 bytes page program. If A7-A0 are not all zero, transmitted data that exceed page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected page. If the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page and previous data will be disregarded. If the data bytes sent to the device has not exceeded 256, the data will be programmed at the request address of the page. There will be no effort on the other data bytes of the same page. The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→ at least 1-byte on data on SI→ CS# goes high. (Please refer to Figure 27) The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte boundary (the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed. The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Page Program cycle is in progress. The WIP sets during the tPP timing, and clears when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the page is protected by BP3 ~ 0 (WPSEL=0) or by individual lock (WPSEL=1), the Page Program (PP) instruction will not be executed. (17) 4 x I/O Page Program (4PP) The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2, and SIO3 as address and data input, which can improve programmer performance and the effectiveness of application of lower clock less than 70MHz. For system with faster clock, the Quad page program cannot provide more actual favors, because the required internal page program time is far more than the time data flows in. Therefore, we suggest that while executing this command (especially during sending data), user can slow the clock speed down to 70MHz below. The other function descriptions are as same as standard page program. The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on SIO[3:0]→ at least 1-byte on data on SIO[3:0]→CS# goes high. (Please refer to Figure 28) If the page protected by BP3 ~ 0 (WPSEL=0) or by individual lock (WPSEL=1), the Quad page program (4PP) instruction will not be executed. (18) Deep Power-down (DP) The Deep Power-down (DP) instruction is for setting the device to minimizing the power consumption, (the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are ignored. The sequence of issuing DP instruction is: CS# goes low→sending DP instruction code→CS# goes high. (Please refer to Figure 33) P/N: PM1718 27 REV. 1.4, NOV. 06, 2013 MX25U8033E Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP) and Read Electronic Signature (RES) instruction. (Those instructions allow the ID being reading out). When Powerdown, or software reset command the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For DP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode. (19) Release from Deep Power-down (RDP), Read Electronic Signature (RES) The Release from Deep Power-down (RDP) instruction is completed by driving Chip Select (CS#) High. When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2(max), as specified in Table 14. AC Characteristics. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. The RDP instruction is only for releasing from Deep Power Down Mode. RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID Definitions on next page. This is not the same as RDID instruction. It is not recommended to use for new design. For new design, please use RDID instruction. The sequence is shown as Figure 34 and Figure 35. Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress. The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. (20) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4) The REMS, REMS2 and REMS4 instruction provides both the JEDEC assigned Manufacturer ID and the specific Device ID. The instruction is initiated by driving the CS# pin low and shift the instruction code "90h", "DFh" or "EFh" followed by two dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for Macronix (C2h) and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 36. The Device ID values are listed in table of ID Definitions. If the one-byte address is initially set to 01h, then the Device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high. P/N: PM1718 28 REV. 1.4, NOV. 06, 2013 MX25U8033E Table 8. ID Definitions Command Type RDID (JEDEC ID) manufacturer ID C2 RES REMS/REMS2/REMS4 manufacturer ID C2 MX25U8033E memory type 25 electronic ID 34 device ID 34 memory density 34 (21) Enter Secured OTP (ENSO) The ENSO instruction is for entering the additional 4K-bit secured OTP mode. While device is in 4K-bit secured OTP mode, main array access is not available. The additional 4K-bit secured OTP is independent from main array, and may be used to store unique serial number for system identifier. After entering the Secured OTP mode, follow standard read or program procedure to read out the data or update data. The Secured OTP data cannot be updated again once it is lock-down. The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP mode→ CS# goes high. Please note that WRSR/WRSCUR/WPSEL commands are not acceptable during the access of secure OTP region, once security OTP is lock down, only read related commands are valid. (22) Exit Secured OTP (EXSO) The EXSO instruction is for exiting the additional 4K-bit secured OTP mode. The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP mode→ CS# goes high. (23) Read Security Register (RDSCUR) The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read at any time (even in program/erase/write status register/write security register condition) and continuously. The sequence of issuing RDSCUR instruction is : CS# goes low→sending RDSCUR instruction→Security Register data out on SO→ CS# goes high. (Please see Figure 37) The definition of the Security Register bits is as below: Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory or not. When it is "0", it indicates non-factory lock; "1" indicates factory-lock. Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured OTP area cannot be updated any more. P/N: PM1718 29 REV. 1.4, NOV. 06, 2013 MX25U8033E Table 9. Security Register Definition Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 WPSEL E_FAIL P_FAIL Reserved Reserved Reserved 0=normal WP mode 1=individual mode (default=0) 0=normal Erase succeed 1=individual Erase failed (default=0) 0=normal Program succeed 1=indicate Program failed (default=0) - - - Non-volatile bit (OTP) Volatile bit Volatile bit Volatile bit Volatile bit Volatile bit Bit1 Bit0 LDSO Secured OTP (indicate if indicator bit lock-down) 0 = not lockdown 0 = non1 = lock-down factory (cannot lock program/ 1 = factory erase lock OTP) Non-volatile Non-volatile bit bit (OTP) (OTP) (24) Write Security Register (WRSCUR) The WRSCUR instruction is for setting the values of Security Register Bits. The WREN (Write Enable) instruction is required before issuing WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO bit) for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area cannot be updated any more. The LDSO bit is an OTP bit. Once the LDSO bit is set, the value of LDSO bit can not be altered any more. The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high. (Please see Figure 38) The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. (25) Write Protection Selection (WPSEL) When the system accepts and executes WPSEL instruction, bit 7 in the security register will be set. The WREN (Write Enable) instruction is required before issuing WPSEL instruction. It will activate SBLK, SBULK, RDBLOCK, GBLK, GBULK etc instructions to conduct block lock protection and replace the original Software Protect Mode (SPM) use (BP3~BP0) indicated block methods. The sequence of issuing WPSEL instruction is: CS# goes low → sending WPSEL instruction to enter the individual block protect mode→ CS# goes high. Every time after the system is powered-on the Security Register bit 7 is checked, if WPSEL=1, then all the blocks and sectors will be write-protected by default. User may only unlock the blocks or sectors via SBULK and GBULK instructions. Program or erase functions can only be operated after the Unlock instruction is executed. Once WPSEL is set, it cannot be changed. P/N: PM1718 30 REV. 1.4, NOV. 06, 2013 MX25U8033E WPSEL instruction function flow is as follows: Figure 3. WPSEL Flow start WREN command RDSCUR(2Bh) command Yes WPSEL=1? No WPSEL disable, block protected by BP[3:0] WPSEL(68h) command RDSR command WIP=0? No Yes RDSCUR(2Bh) command WPSEL=1? No Yes WPSEL set successfully WPSEL set fail WPSEL enable. Block protected by individual lock (SBLK, SBULK, … etc). P/N: PM1718 31 REV. 1.4, NOV. 06, 2013 MX25U8033E (26) Single Block Lock/Unlock Protection (SBLK/SBULK) These instructions are only effective after WPSEL was executed. The SBLK instruction is for write protection a specified block (or sector) of memory, using AMAX-A16 or (AMAX-A12) address bits to assign a 64Kbyte block (or 4K bytes sector) to be protected as read only. The SBULK instruction will cancel the block (or sector) write protection state. This feature allows user to stop protecting the entire block (or sector) through the chip unprotect command (GBULK). The WREN (Write Enable) instruction is required before issuing SBLK/SBULK instruction. The sequence of issuing SBLK/SBULK instruction is: CS# goes low → send SBLK/SBULK (36h/39h) instruction→send 3 address bytes assign one block (or sector) to be protected on SI pin → CS# goes high. The CS# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not be executed. SBLK/SBULK instruction function flow is as follows: Figure 4. Block Lock Flow Start RDSCUR(2Bh) command WPSEL=1? No WPSEL command Yes WREN command SBLK command ( 36h + 24bit address ) RDSR command WIP=0? No Yes RDBLOCK command ( 3Ch + 24bit address ) Data = FFh ? No Yes Block lock successfully Lock another block? Block lock fail Yes No Block lock P/N: PM1718 completed 32 REV. 1.4, NOV. 06, 2013 MX25U8033E Figure 5. Block Unlock Flow start RDSCUR(2Bh) command WPSEL=1? No WPSEL command Yes WREN command SBULK command ( 39h + 24bit address ) RDSR command No WIP=0? Yes Unlock another block? Yes Unlock block completed? P/N: PM1718 33 REV. 1.4, NOV. 06, 2013 MX25U8033E (27) Read Block Lock Status (RDBLOCK) This instruction is only effective after WPSEL was executed. The RDBLOCK instruction is for reading the status of protection lock of a specified block (or sector), using AMAX-A16 (or AMAX-A12) address bits to assign a 64K bytes block (4K bytes sector) and read protection lock status bit which the first byte of Read-out cycle. The status bit is"1" to indicate that this block has be protected, that user can read only but cannot write/program /erase this block. The status bit is "0" to indicate that this block hasn't be protected, and user can read and write this block. The sequence of issuing RDBLOCK instruction is: CS# goes low → send RDBLOCK (3Ch) instruction → send 3 address bytes to assign one block on SI pin → read block's protection lock status bit on SO pin → CS# goes high. (28) Gang Block Lock/Unlock (GBLK/GBULK) These instructions are only effective after WPSEL was executed. The GBLK/GBULK instruction is for enable/disable the lock protection block of the whole chip. The WREN (Write Enable) instruction is required before issuing GBLK/GBULK instruction. The sequence of issuing GBLK/GBULK instruction is: CS# goes low → send GBLK/GBULK (7Eh/98h) instruction →CS# goes high. The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed. P/N: PM1718 34 REV. 1.4, NOV. 06, 2013 MX25U8033E (29) Read SFDP Mode (RDSFDP) The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. The sequence of issuing RDSFDP instruction is CS# goes low→send RDSFDP instruction (5Ah)→send 3 address bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation can use CS# to high at any time during data out. SFDP is a JEDEC Standard, JESD216. Figure 6. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI SO 24 BIT ADDRESS 23 22 21 5Ah 3 2 1 0 High-Z CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Cycle SI 7 6 5 4 3 2 1 0 DATA OUT 2 DATA OUT 1 SO 7 6 5 3 2 1 0 7 MSB MSB P/N: PM1718 4 35 6 5 4 3 2 1 0 7 MSB REV. 1.4, NOV. 06, 2013 MX25U8033E Table 10. Signature and Parameter Identification Data Values Description SFDP Signature Comment Fixed: 50444653h Add (h) DW Add Data (h/b) (Byte) (Bit) (Note1) 00h 07:00 53h Data (h) 53h 01h 15:08 46h 46h 02h 23:16 44h 44h 03h 31:24 50h 50h SFDP Minor Revision Number Start from 00h 04h 07:00 00h 00h SFDP Major Revision Number Start from 01h This number is 0-based. Therefore, 0 indicates 1 parameter header. 05h 15:08 01h 01h 06h 23:16 01h 01h 07h 31:24 FFh FFh 00h: it indicates a JEDEC specified header. 08h 07:00 00h 00h Start from 00h 09h 15:08 00h 00h Start from 01h 0Ah 23:16 01h 01h How many DWORDs in the Parameter table 0Bh 31:24 09h 09h 0Ch 07:00 30h 30h 0Dh 15:08 00h 00h 0Eh 23:16 00h 00h 0Fh 31:24 FFh FFh it indicates Macronix manufacturer ID 10h 07:00 C2h C2h Start from 00h 11h 15:08 00h 00h Start from 01h 12h 23:16 01h 01h How many DWORDs in the Parameter table 13h 31:24 04h 04h 14h 07:00 60h 60h 15h 15:08 00h 00h 16h 23:16 00h 00h 17h 31:24 FFh FFh Number of Parameter Headers Unused ID number (JEDEC) Parameter Table Minor Revision Number Parameter Table Major Revision Number Parameter Table Length (in double word) Parameter Table Pointer (PTP) First address of JEDEC Flash Parameter table Unused ID number (Macronix manufacturer ID) Parameter Table Minor Revision Number Parameter Table Major Revision Number Parameter Table Length (in double word) Parameter Table Pointer (PTP) First address of Macronix Flash Parameter table Unused P/N: PM1718 36 REV. 1.4, NOV. 06, 2013 MX25U8033E Table 11. Parameter Table (0): JEDEC Flash Parameter Tables Description Comment Block/Sector Erase sizes 00: Reserved, 01: 4KB erase, 10: Reserved, 11: not support 4KB erase Write Granularity 0: 1Byte, 1: 64Byte or larger Write Enable Instruction Required 0: not required 1: required 00h to be written to the for Writing to Volatile Status status register Registers Add (h) DW Add Data (h/b) (Byte) (Bit) (Note1) 31h (1-1-2) Fast Read (Note2) 0=not support 1=support Address Bytes Number used in addressing flash array Double Transfer Rate (DTR) Clocking 00: 3Byte only, 01: 3 or 4Byte, 10: 4Byte only, 11: Reserved 01b 02 1b 03 0b 30h 0: use 50h opcode, 1: use 06h opcode Write Enable Opcode Select for Note: If target flash status register Writing to Volatile Status Registers is nonvolatile, then bits 3 and 4 must be set to 00b. Contains 111b and can never be Unused changed 4KB Erase Opcode 01:00 0=not support 1=support 32h E5h 04 0b 07:05 111b 15:08 20h 16 1b 18:17 00b 19 0b 20 1b 0=not support 1=support (1-4-4) Fast Read 0=not support 1=support 21 1b (1-1-4) Fast Read 0=not support 1=support 22 0b 23 1b 33h 31:24 FFh 37h:34h 31:00 Unused Flash Memory Density (1-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states (Note3) Clocks) not support (1-4-4) Fast Read Number of 000b: Mode Bits not support Mode Bits (Note4) 38h (1-4-4) Fast Read Opcode 39h (1-1-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (1-1-4) Fast Read Number of 000b: Mode Bits not support Mode Bits 3Ah (1-1-4) Fast Read Opcode 3Bh P/N: PM1718 37 20h B1h (1-2-2) Fast Read Unused Data (h) FFh 007FFFFFh 04:00 0 0100b 07:05 010b 15:08 EBh 20:16 0 0000b 23:21 000b 31:24 FFh 44h EBh 00h FFh REV. 1.4, NOV. 06, 2013 MX25U8033E Description Comment (1-1-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (1-1-2) Fast Read Number of 000b: Mode Bits not support Mode Bits Add (h) DW Add Data (h/b) (Byte) (Bit) (Note1) 3Ch (1-1-2) Fast Read Opcode 3Dh (1-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (1-2-2) Fast Read Number of 000b: Mode Bits not support Mode Bits 3Eh (1-2-2) Fast Read Opcode 3Fh (2-2-2) Fast Read 0=not support 1=support Unused (4-4-4) Fast Read 0=not support 1=support 40h Unused 04:00 0 1000b 07:05 000b 15:08 3Bh 20:16 0 0100b 23:21 000b 31:24 BBh 00 0b 03:01 111b 04 0b 07:05 111b Data (h) 08h 3Bh 04h BBh EEh Unused 43h:41h 31:08 FFh FFh Unused 45h:44h 15:00 FFh FFh 20:16 0 0000b 23:21 000b (2-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (2-2-2) Fast Read Number of 000b: Mode Bits not support Mode Bits 46h (2-2-2) Fast Read Opcode 47h 31:24 FFh FFh 49h:48h 15:00 FFh FFh 20:16 0 0000b 23:21 000b Unused 00h (4-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (4-4-4) Fast Read Number of 000b: Mode Bits not support Mode Bits 4Ah (4-4-4) Fast Read Opcode 4Bh 31:24 FFh FFh 4Ch 07:00 0Ch 0Ch 4Dh 15:08 20h 20h 4Eh 23:16 0Fh 0Fh 4Fh 31:24 52h 52h 50h 07:00 10h 10h 51h 15:08 D8h D8h 52h 23:16 00h 00h 53h 31:24 FFh FFh Sector Type 1 Size Sector/block size = 2^N bytes (Note5) 0x00b: this sector type doesn't exist Sector Type 1 erase Opcode Sector Type 2 Size Sector/block size = 2^N bytes 0x00b: this sector type doesn't exist Sector Type 2 erase Opcode Sector Type 3 Size Sector/block size = 2^N bytes 0x00b: this sector type doesn't exist Sector Type 3 erase Opcode Sector Type 4 Size Sector/block size = 2^N bytes 0x00b: this sector type doesn't exist Sector Type 4 erase Opcode P/N: PM1718 38 00h REV. 1.4, NOV. 06, 2013 MX25U8033E Table 12. Parameter Table (1): Macronix Flash Parameter Tables Description Comment Add (h) DW Add Data (h/b) (Byte) (Bit) (Note1) Data (h) Vcc Supply Maximum Voltage 2000h=2.000V 2700h=2.700V 3600h=3.600V 61h:60h 07:00 15:08 00h 20h 00h 20h Vcc Supply Minimum Voltage 1650h=1.650V 2250h=2.250V 2350h=2.350V 2700h=2.700V 63h:62h 23:16 31:24 50h 16h 50h 16h H/W Reset# pin 0=not support 1=support 00 0b H/W Hold# pin 0=not support 1=support 01 1b Deep Power Down Mode 0=not support 1=support 02 1b S/W Reset 0=not support 1=support 03 0b S/W Reset Opcode Reset Enable (66h) should be issued before Reset Opcode 11:04 1111 1111b (FFh) Program Suspend/Resume 0=not support 1=support 12 0b Erase Suspend/Resume 0=not support 1=support 13 0b 14 1b 15 0b 66h 23:16 FFh FFh 67h 31:24 FFh FFh 65h:64h Unused Wrap-Around Read mode 0=not support 1=support Wrap-Around Read mode Opcode Wrap-Around Read data length 08h:support 8B wrap-around read 16h:8B&16B 32h:8B&16B&32B 64h:8B&16B&32B&64B Individual block lock 0=not support 1=support 00 1b Individual block lock bit (Volatile/Nonvolatile) 0=Volatile 1=Nonvolatile 01 0b 09:02 0011 0110b (36h) 10 0b 11 1b Individual block lock Opcode 4FF6h Individual block lock Volatile protect bit default protect status 0=protect 1=unprotect Secured OTP 0=not support 1=support Read Lock 0=not support 1=support 12 0b Permanent Lock 0=not support 1=support 13 0b Unused 15:14 11b Unused 31:16 FFh FFh 31:00 FFh FFh Unused P/N: PM1718 6Bh:68h 6Fh:6Ch 39 C8D9h REV. 1.4, NOV. 06, 2013 MX25U8033E Note 1: h/b is hexadecimal or binary. Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x), address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1), (2-2-2), and (4-4-4) Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits. Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system controller if they are specified. (eg,read performance enhance toggling bits) Note 5: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h Note 6: All unused and undefined area data is blank FFh. P/N: PM1718 40 REV. 1.4, NOV. 06, 2013 MX25U8033E POWER-ON STATE The device is at the following states after power-up: - Standby mode (please note it is not deep power-down mode) - Write Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down stage while the VCC reaches the following lev - VCC minimum at power-up stage and then after a delay of tVSL - GND at power-down Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level. An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change during power up state. When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and the flash device has no response to any command. For further protection on the device, after VCC reaching the VWI level, a tPUW time delay is required before the device is fully accessible for commands like write enable (WREN), page program (PP), quad page program (4PP), sector erase (SE), block erase 32KB (BE32K), block erase (BE), chip erase (CE), WRSCUR and write status register (WRSR). If the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The write, erase, and program command should be sent after the below time delay: - tPUW after VCC reached VWI level - tVSL after VCC reached VCC minimum level The device can accept read command after VCC reached VCC minimum and a time delay of tVSL, even time of tPUW has not passed. Please refer to the figure of "power-up timing". Note: - To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uF) - At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to any command. The data corruption might occur during this stage if a write, program, erase cycle is in progress. P/N: PM1718 41 REV. 1.4, NOV. 06, 2013 MX25U8033E ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS RATING VALUE Ambient Operating Temperature Industrial grade -40°C to 85°C Storage Temperature -65°C to 150°C Applied Input Voltage -0.5V to VCC+0.5V Applied Output Voltage -0.5V to VCC+0.5V VCC to Ground Potential -0.5V to 2.5V NOTICE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. 2. Specifications contained within the following tables are subject to change. 3. During voltage transitions, all pins may overshoot to VCC+1.0V or -1.0V for period up to 20ns. Figure 8. Maximum Positive Overshoot Waveform Figure 7. Maximum Negative Overshoot Waveform 20ns 0V VCC+1.0V -1.0V 2.0V 20ns CAPACITANCE TA = 25°C, f = 1.0 MHz SYMBOL PARAMETER CIN COUT P/N: PM1718 MIN. TYP. MAX. UNIT Input Capacitance 6 pF VIN = 0V Output Capacitance 8 pF VOUT = 0V 42 CONDITIONS REV. 1.4, NOV. 06, 2013 MX25U8033E Figure 9. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL Input timing reference level 0.8VCC Output timing reference level 0.7VCC AC Measurement Level 0.3VCC 0.2VCC 0.5VCC Note: Input pulse rise and fall time are <5ns Figure 10. OUTPUT LOADING 25K ohm DEVICE UNDER TEST CL +1.8V 25K ohm CL=30pF Including jig capacitance P/N: PM1718 43 REV. 1.4, NOV. 06, 2013 MX25U8033E Table 13. DC CHARACTERISTICS (Temperature = -40°C to 85°C, VCC = 1.65V ~ 2.0V) SYMBOL PARAMETER NOTES MIN. TYP. MAX. UNITS TEST CONDITIONS ILI Input Load Current 1 ±2 uA VCC = VCC Max, VIN = VCC or GND ILO Output Leakage Current 1 ±2 uA VCC = VCC Max, VOUT = VCC or GND ISB1 VCC Standby Current 1 8 30 uA VIN = VCC or GND, CS# = VCC ISB2 Deep Power-down Current 2 8 uA VIN = VCC or GND, CS# = VCC 12 mA f=80MHz, SCLK=0.1VCC/0.9VCC, SO=Open 7 mA f=33MHz, SCLK=0.1VCC/0.9VCC, SO=Open 20 25 mA 8 20 mA 1 20 25 mA Erase in Progress, CS#=VCC 1 20 25 mA Erase in Progress, CS#=VCC -0.5 0.2VCC V 0.8VCC VCC+0.4 V 0.2 V IOL = 100uA V IOH = -100uA ICC1 VCC Read VIL VCC Program Current (PP) VCC Write Status Register (WRSR) Current VCC Sector/Block (32K, 64K) Erase Current (SE/BE/BE32K) VCC Chip Erase Current (CE) Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage ICC2 ICC3 ICC4 ICC5 1 1 VCC-0.2 Program in Progress, CS# = VCC Program status register in progress, CS#=VCC Note 1. Typical values at VCC = 1.8V, T = 25°C. These currents are valid for all product versions (package and speeds). P/N: PM1718 44 REV. 1.4, NOV. 06, 2013 MX25U8033E Table 14. AC CHARACTERISTICS (Temperature = -40°C to 85°C, VCC = 1.65V ~ 2.0V) Symbol Alt. Parameter fSCLK fC fRSCLK fR fT fQ fTSCLK f4PP tCH(1) tCLH tCL(1) tCLL tCLCH(2) tCHCL(2) tSLCH tCHSL tDVCH tCHDX tCHSH tSHCH tCSS tDSU tDH tSHSL(3) tCSH tSHQZ(2) tHLCH tCHHH tHHCH tCHHL tHHQX tHLQZ tDIS tCLQV tV tCLQX tWHSL tSHWL tDP(2) tRES1(2) tRES2(2) tW tBP tPP tSE tBE32 tBE tCE tHO tLZ tHZ Min. Clock Frequency for the following instructions: FAST_READ, RDSFDP, PP, SE, BE, CE, DP, RES,RDP WREN, WRDI, RDID, RDSR, WRSR Clock Frequency for READ instructions Clock Frequency for 2READ instructions Clock Frequency for 4READ instructions Clock Frequency for 4PP (Quad page program) Serial (fSCLK) Clock High Time Normal Read (fRSCLK) 4PP (70MHz) Serial (fSCLK) Clock Low Time Normal Read (fRSCLK) 4PP (70MHz) Clock Rise Time (3) (peak to peak) Clock Fall Time (3) (peak to peak) CS# Active Setup Time (relative to SCLK) CS# Not Active Hold Time (relative to SCLK) Data In Setup Time Data In Hold Time CS# Active Hold Time (relative to SCLK) CS# Not Active Setup Time (relative to SCLK) Read CS# Deselect Time Write/Erase/Program Output Disable Time HOLD# Active Setup Time (relative to SCLK) HOLD# Active Hold Time (relative to SCLK) HOLD# Not Active Setup Time (relative to SCLK) HOLD# Not Active Hold Time (relative to SCLK) HOLD# to Output Low-Z HOLD# to Output High-Z Loading: 30pF Clock Low to Output Valid Loading: 30pF/15pF Loading: 15pF Output Hold Time Write Protect Setup Time Write Protect Hold Time CS# High to Deep Power-down Mode CS# High to Standby Mode without Electronic Signature Read CS# High to Standby Mode with Electronic Signature Read Write Status Register Cycle Time Byte-Program Page Program Cycle Time Sector Erase Cycle Time Block Erase (32KB) Cycle Time Block Erase (64KB) Cycle Time Chip Erase Cycle Time Typ. D.C. Max. Unit 80 MHz 50 80 70 70 MHz MHz MHz MHz ns 6 9 7 6 9 7 0.1 0.1 7 5 2 5 5 7 12 30 ns ns ns 8 4 4 4 4 8 8 8 6 0 20 100 10 1.2 30 200 500 5 10 10 10 40 30 3 200 1000 2000 10 V/ns V/ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns us us us ms us ms ms ms ms s Notes: 1. tCH + tCL must be greater than or equal to 1/ Frequency. 2. Value guaranteed by characterization, not 100% tested in production. 3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. 4. Test condition is shown as "Figure 9. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL", "Figure 10. OUTPUT LOADING". P/N: PM1718 45 REV. 1.4, NOV. 06, 2013 MX25U8033E Timing Analysis Figure 11. Serial Input Timing tSHSL CS# tCHSL tSLCH tCHSH tSHCH SCLK tDVCH tCHCL tCHDX tCLCH LSB MSB SI High-Z SO Figure 12. Output Timing CS# tCH SCLK tCLQV tCLQX tCL tCLQV tCLQX LSB SO SI P/N: PM1718 tSHQZ ADDR.LSB IN 46 REV. 1.4, NOV. 06, 2013 MX25U8033E Figure 13. Hold Timing CS# tHLCH tCHHL tHHCH SCLK tCHHH tHLQZ tHHQX SO HOLD# Figure 14. WP# Setup Timing and Hold Timing during WRSR when SRWD=1 WP# tSHWL tWHSL CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK 01h SI High-Z SO Figure 15. Write Enable (WREN) Sequence (Command 06) CS# 0 1 2 3 4 5 6 7 SCLK Command SI SO P/N: PM1718 06h High-Z 47 REV. 1.4, NOV. 06, 2013 MX25U8033E Figure 16. Write Disable (WRDI) Sequence (Command 04) CS# 1 0 2 3 4 5 6 7 SCLK Command SI 04h High-Z SO Figure 17. Read Identification (RDID) Sequence (Command 9F) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31 SCLK Command SI 9Fh Manufacturer Identification SO High-Z 7 6 5 3 2 1 Device Identification 0 15 14 13 MSB 3 2 1 0 MSB Figure 18. Read Status Register (RDSR) Sequence (Command 05) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK command 05h SI SO High-Z Status Register Out 7 6 5 4 2 1 0 7 6 5 4 3 2 1 0 7 MSB MSB P/N: PM1718 3 Status Register Out 48 REV. 1.4, NOV. 06, 2013 MX25U8033E Figure 19. Write Status Register (WRSR) Sequence (Command 01) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK command SI Status Register In 01h 7 5 4 3 2 0 1 MSB High-Z SO 6 Figure 20. Read Data Bytes (READ) Sequence (Command 03) (50MHz) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK command SI 03h 24-Bit Address 23 22 21 3 2 1 0 MSB SO Data Out 1 High-Z 7 6 5 4 3 2 Data Out 2 1 0 7 MSB P/N: PM1718 49 REV. 1.4, NOV. 06, 2013 MX25U8033E Figure 21. Read at Higher Speed (FAST_READ) Sequence (Command 0B) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI 24 BIT ADDRESS 23 22 21 0Bh 3 2 1 0 High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Configurable Dummy Cycle 7 SI 6 5 4 3 2 1 0 DATA OUT 2 DATA OUT 1 7 SO 6 5 4 3 2 1 0 7 6 5 4 3 2 1 MSB MSB 0 7 MSB Figure 22. Dual Read Mode Sequence (Command 3B) CS# 0 1 2 3 4 5 6 7 8 SCLK … Command SI/SIO0 SO/SIO1 P/N: PM1718 30 31 32 9 3B … 24 ADD Cycle A23 A22 … 39 40 41 42 43 44 45 A1 A0 High Impedance 8 dummy cycle Data Out 1 Data Out 2 D6 D4 D2 D0 D6 D4 D7 D5 D3 D1 D7 D5 50 REV. 1.4, NOV. 06, 2013 MX25U8033E Figure 23. 2 x I/O Read Mode Sequence (Command BB) CS# 0 1 2 3 4 5 6 7 8 18 19 20 21 22 23 24 25 26 27 9 10 11 SCLK 8 Bit Instruction Notes: Performance 2 Enhance Indicator (Note) High Impedance dummy cycles Data Output P2 P0 data bit6, bit4, bit2...bit0, bit6, bit4.... address bit23, bit21, bit19...bit1 P3 P1 data bit7, bit5, bit3...bit1, bit7, bit5.... address bit22, bit20, bit18...bit0 BBh SI/SIO0 SO/SIO1 12 BIT Address 1. Hi-impedance is inhibited for the two clock cycles. 2. P3≠P1 & P2≠P0 (Toggling) is inhibited. Figure 24. 4 x I/O Read Mode Sequence (Command EB) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 n SCLK 8 Bit Instruction SI/SIO0 SO/SIO1 WP#/SIO2 NC/SIO3 Notes: 6 Address cycles Performance enhance indicator (Note) 4 dummy cycles Data Output address bit20, bit16..bit0 P4 P0 data bit4, bit0, bit4.... High Impedance address bit21, bit17..bit1 P5 P1 data bit5 bit1, bit5.... High Impedance address bit22, bit18..bit2 P6 P2 data bit6 bit2, bit6.... High Impedance address bit23, bit19..bit3 P7 P3 data bit7 bit3, bit7.... EBh 1. Hi-impedance is inhibited for the two clock cycles. 2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited. P/N: PM1718 51 REV. 1.4, NOV. 06, 2013 MX25U8033E Figure 25. 2 x I/O Read Enhance Performance Mode Sequence (Command BB) CS# 0 1 2 3 4 5 6 7 8 18 19 20 21 22 23 24 25 26 27 9 10 11 SCLK 8 Bit Instruction BBh SI/SIO0 SO/SIO1 High Impedance 12 BIT Address Performance 2 Enhance Indicator (Note) dummy cycles Data Output P2 P0 data bit6, bit4, bit2...bit0, bit6, bit4.... address bit23, bit21, bit19...bit1 P3 P1 data bit7, bit5, bit3...bit1, bit7, bit5.... address bit22, bit20, bit18...bit0 CS# n+1 ........... n+12 ....... n+15 .... n+17 ........... SCLK 12 BIT Address Data Output Performance 2 dummy Enhance cycles Indicator (Note) SI/SIO0 address bit22, bit20, bit18...bit0 P2 P0 data bit6, bit4, bit2...bit0, bit6, bit4.... SO/SIO1 address bit23, bit21, bit19...bit1 P3 P1 data bit7, bit5, bit3...bit1, bit7, bit5.... Notes: 1. Performance enhance mode, if P3≠P1 & P2≠P0 (Toggling), ex: 21h, 12h, 30h or 03h. Performance enhance recommend to keep 1 or 0 in performance enhance indicator. 2. Reset the performance enhance mode, if P3=P1 or P2=P0 (Not Toggling), ex: 33h, 00h, 22h or 11h. P/N: PM1718 52 REV. 1.4, NOV. 06, 2013 MX25U8033E Figure 26. 4 x I/O Read Enhance Performance Mode Sequence (Command EB) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 n SCLK 8 Bit Instruction WP#/SIO2 NC/SIO3 Performance enhance indicator (Note) 4 dummy cycles Data Output address bit20, bit16..bit0 P4 P0 data bit4, bit0, bit4.... High Impedance address bit21, bit17..bit1 P5 P1 data bit5 bit1, bit5.... High Impedance address bit22, bit18..bit2 P6 P2 data bit6 bit2, bit6.... High Impedance address bit23, bit19..bit3 P7 P3 data bit7 bit3, bit7.... EBh SI/SIO0 SO/SIO1 6 Address cycles CS# n+1 ........... n+7 ...... n+9 ........... n+13 ........... SCLK 6 Address cycles Performance enhance indicator (Note) 4 dummy cycles Data Output SI/SIO0 address bit20, bit16..bit0 P4 P0 data bit4, bit0, bit4.... SO/SIO1 address bit21, bit17..bit1 P5 P1 data bit5 bit1, bit5.... WP#/SIO2 address bit22, bit18..bit2 P6 P2 data bit6 bit2, bit6.... NC/SIO3 address bit23, bit19..bit3 P7 P3 data bit7 bit3, bit7.... Notes: 1. Performance enhance mode, if P7≠P3 & P6≠P2 & P5≠P1 & P4≠P0 (Toggling), ex: A5h, 5Ah, 0Fh, F0h. Performance enhance recommend to keep 1 or 0 in performance enhance indicator. 2. Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0 (Not Toggling), ex: AAh, 55h, 00h, FFh. P/N: PM1718 53 REV. 1.4, NOV. 06, 2013 MX25U8033E Figure 27. Page Program (PP) Sequence (Command 02) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK 1 0 7 6 5 3 2 1 0 2079 2 2078 3 2077 23 22 21 02h SI Data Byte 1 2076 24-Bit Address 2075 Command 4 1 0 MSB MSB 2074 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2073 2072 CS# SCLK Data Byte 2 SI 7 6 5 4 3 2 Data Byte 3 0 1 MSB 7 6 5 4 3 2 Data Byte 256 7 0 1 MSB 6 5 4 3 2 MSB Figure 28. 4 x I/O Page Program (4PP) Sequence (Command 38) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 SCLK Command 20 16 12 8 4 0 4 0 4 0 4 0 4 0 SO/SIO1 21 17 13 9 5 1 5 1 5 1 5 1 5 1 WP#/SIO2 22 18 14 10 6 2 6 2 6 2 6 2 6 2 NC/SIO3 23 19 15 11 7 3 7 3 7 3 7 3 7 3 SI/SIO0 P/N: PM1718 Data Data Data Data Byte 1 Byte 2 Byte 3 Byte 4 6 Address cycle 38h 54 REV. 1.4, NOV. 06, 2013 MX25U8033E Figure 29. Sector Erase (SE) Sequence (Command 20) CS# 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK 24 Bit Address Command SI 23 22 20h 2 1 0 MSB Figure 30. Block Erase 32KB (BE32K) Sequence (Command 52) CS# 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK Command SI 24 Bit Address 23 22 52h 2 0 1 MSB Figure 31. Block Erase (BE) Sequence (Command D8) CS# 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK Command SI 24 Bit Address 23 22 D8h 2 1 0 MSB Figure 32. Chip Erase (CE) Sequence (Command 60 or C7) CS# 0 1 2 3 4 5 6 7 SCLK Command SI P/N: PM1718 60h or C7h 55 REV. 1.4, NOV. 06, 2013 MX25U8033E Figure 33. Deep Power-down (DP) Sequence (Command B9) CS# 0 1 2 3 4 5 6 tDP 7 SCLK Command B9h SI Deep Power-down Mode Stand-by Mode Figure 34. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 SCLK Command SI ABh tRES2 3 Dummy Bytes 23 22 21 3 2 1 0 MSB SO Electronic Signature Out High-Z 7 6 5 4 3 2 1 0 MSB Deep Power-down Mode P/N: PM1718 56 Stand-by Mode REV. 1.4, NOV. 06, 2013 MX25U8033E Figure 35. Release from Deep Power-down (RDP) Sequence (Command AB) CS# 0 1 2 3 4 5 6 tRES1 7 SCLK Command SI ABh High-Z SO Deep Power-down Mode Stand-by Mode Figure 36. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90/EF/DF) CS# 0 1 2 3 4 5 6 7 8 9 10 SCLK Command SI 2 Dummy Bytes 15 14 13 90h 3 2 1 0 High-Z SO CS# 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK ADD (1) SI 7 6 5 4 3 2 1 0 Manufacturer ID SO 7 6 5 4 3 2 1 Device ID 0 7 6 5 4 3 2 1 MSB MSB 0 7 MSB Note: ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first. P/N: PM1718 57 REV. 1.4, NOV. 06, 2013 MX25U8033E Figure 37. Read Security Register (RDSCUR) Sequence (Command 2B) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK command 2B SI SO Security Register Out High-Z 7 6 5 4 3 2 1 Security Register Out 0 7 6 5 4 3 2 1 0 7 MSB MSB Figure 38. Write Security Register (WRSCUR) Sequence (Command 2F) CS# 0 1 2 3 4 5 6 7 SCLK Command SI P/N: PM1718 2F 58 REV. 1.4, NOV. 06, 2013 MX25U8033E Figure 39. Power-up Timing VCC VCC(max) Program, Erase and Write Commands are Ignored Chip Selection is Not Allowed VCC(min) tVSL Reset State of the Flash Read Command is allowed Device is fully accessible VWI tPUW time Note: VCC (max.) is 2.0V and VCC (min.) is 1.65V. Table 15. Power-Up Timing and VWI Threshold Symbol tVSL(1) tPUW(1) VWI(1) Parameter VCC(min) to CS# low (VCC Rise Time) Time delay to Write instruction Command Inhibit Voltage Min. 300 1 1.0 Max. 10 1.4 Unit us ms V Note: 1. These parameters are characterized only. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). P/N: PM1718 59 REV. 1.4, NOV. 06, 2013 MX25U8033E OPERATING CONDITIONS At Device Power-Up and Power-Down AC timing illustrated in Figure 40 and Figure 41 are for the supply voltages and the control signals at device powerup and power-down. If the timing in the figures is ignored, the device will not operate correctly. During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL. Figure 40. AC Timing at Device Power-Up VCC VCC(min) GND tVR tSHSL CS# tSLCH tCHSL tCHSH tSHCH SCLK tDVCH tCHCL tCHDX LSB IN MSB IN SI High Impedance SO Symbol tVR tCLCH Parameter VCC Rise Time Notes 1 Min. 20 Max. 500000 Unit us/V Notes : 1. Sampled, not 100% tested. 2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC CHARACTERISTICS" table. P/N: PM1718 60 REV. 1.4, NOV. 06, 2013 MX25U8033E Figure 41. Power-Down Sequence During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation. VCC CS# SCLK P/N: PM1718 61 REV. 1.4, NOV. 06, 2013 MX25U8033E ERASE AND PROGRAMMING PERFORMANCE Parameter Min. Typ. (1) Max. (2) Unit 40 ms Write Status Register Cycle Time Sector Erase Cycle Time (4KB) 30 200 ms Block Erase Cycle Time (32KB) 200 1000 ms Block Erase Cycle Time (64KB) 500 2000 ms Chip Erase Cycle Time 5 10 s Byte Program Time (via page program command) 10 30 us Page Program Time 1.2 3 ms Erase/Program Cycle 100,000 cycles Note: 1. Typical program and erase time assumes the following conditions: 25°C, 1.8V, and checkerboard pattern. 2. Under worst conditions of 85°C and 1.65V. 3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command. DATA RETENTION Parameter Condition Min. Data retention 55˚C 20 Max. Unit years LATCH-UP CHARACTERISTICS MIN. MAX. Input Voltage with respect to GND on all power pins, SI, CS# -1.0V 2 VCCmax Input Voltage with respect to GND on SO -1.0V VCC + 1.0V -100mA +100mA Current Includes all pins except VCC. Test conditions: VCC = 1.8V, one pin at a time. P/N: PM1718 62 REV. 1.4, NOV. 06, 2013 MX25U8033E ORDERING INFORMATION CLOCK (MHz) TEMPERATURE MX25U8033EM1I-12G 80 -40°C~85°C MX25U8033EZUI-12G 80 -40°C~85°C MX25U8033EZNI-12G 80 -40°C~85°C MX25U8033EM2I-12G 80 -40°C~85°C PART NO. P/N: PM1718 PACKAGE Remark 8-SOP (150mil) 8-USON (4x4mm) 8-WSON (6x5mm) 8-SOP (200mil) 63 REV. 1.4, NOV. 06, 2013 MX25U8033E PART NAME DESCRIPTION MX 25 U 8033E M1 I 12 G OPTION: G: RoHS Compliant and Halogen-free SPEED: 12: 80MHz TEMPERATURE RANGE: I: Industrial (-40°C to 85°C) PACKAGE: M1: 150mil 8-SOP M2: 200mil 8-SOP ZU: USON ZN: WSON DENSITY & MODE: 8033E: 8Mb TYPE: U: 1.8V DEVICE: 25: Serial Flash P/N: PM1718 64 REV. 1.4, NOV. 06, 2013 MX25U8033E PACKAGE INFORMATION P/N: PM1718 65 REV. 1.4, NOV. 06, 2013 MX25U8033E P/N: PM1718 66 REV. 1.4, NOV. 06, 2013 MX25U8033E P/N: PM1718 67 REV. 1.4, NOV. 06, 2013 MX25U8033E P/N: PM1718 68 REV. 1.4, NOV. 06, 2013 MX25U8033E REVISION HISTORY Rev. No. DescriptionsPageDate 1.0 1. Added 200mil 8SOP Package solution 2. Modified Order Information format P3,5,54,55,57 P54 NOV/09/2011 1.11. Removed Advanced Information from P54DEC/27/2011 Ordering Information 1.2 1. Added SFDP content P12,32~37,42 MAR/20/2012 1.31. Added DREAD functionP13,15,23,37,38,50 2. Modified SFDP wording P35~40 APR/15/2013 1.4 1. Modified ABSOLUTE MAXIMUM RATINGS Table 2. Updated parameters for DC Characteristics. 3. Updated Erase and Programming Performance. NOV/06/2013 P/N: PM1718 69 P42 P5, 44 P5, 45, 62 REV. 1.4, NOV. 06, 2013 MX25U8033E Except for customized products which has been expressly identified in the applicable agreement, Macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. In the event Macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or distributors shall be released from any and all liability arisen therefrom. Copyright© Macronix International Co., Ltd. 2011~2013. All rights reserved, including the trademarks and tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit, NBiit, Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Audio, Rich Book, Rich TV, and FitCAM. The names and brands of third party referred thereto (if any) are for identification purposes only. For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 70