PD - 91319E
IRL3803S/L
l
l
l
l
l
l
l
Logic-Level Gate Drive
Advanced Process Technology
Surface Mount (IRL3803S)
Low-profile through-hole (IRL3803L)
175°C Operating Temperature
Fast Switching
Fully Avalanche Rated
HEXFET® Power MOSFET
D
VDSS = 30V
RDS(on) = 0.006Ω
G
ID = 140A
Description
S
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power MOSFETs
are well known for, provides the designer with an extremely
efficient and reliable device for use in a wide variety of
applications.
The D2Pak is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible onresistance in any existing surface mount package. The
D2Pak is suitable for high current applications because of
its low internal connection resistance and can dissipate
up to 2.0W in a typical surface mount application.
The through-hole version (IRL3803L) is available for lowprofile applications.
D 2 Pak
TO-262
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TA = 25°C
PD @TC = 25°C
V GS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Max.
140
98
Units
A
470
3.8
200
1.3
±16
610
71
20
5.0
-55 to + 175
W
W
W/°C
V
mJ
A
mJ
V/ns
300 (1.6mm from case )
°C
Thermal Resistance
Parameter
RθJC
RθJA
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Junction-to-Case
Junction-to-Ambient ( PCB Mounted,steady-state)**
Typ.
Max.
Units
0.75
40
°C/W
1
11/11/02
IRL3803S/L
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
30
1.0
55
LS
Internal Source Inductance
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V(BR)DSS
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
gfs
Gate Threshold Voltage
Forward Transconductance
IDSS
Drain-to-Source Leakage Current
IGSS
Typ.
0.052
14
230
29
35
Max. Units
Conditions
V
V GS = 0V, ID = 250µA
V/°C Reference to 25°C, ID = 1mA
0.006
V GS = 10V, ID = 71A
Ω
0.009
V GS = 4.5V, ID = 59A
V
V DS = VGS, ID = 250µA
S
V DS = 25V, ID = 71A
25
VDS = 30V, VGS = 0V
µA
250
V DS = 24V, VGS = 0V, T J = 150°C
100
V GS = 16V
nA
-100
VGS = -16V
140
I D = 71A
41
nC
V DS = 24V
78
V GS = 4.5V, See Fig. 6 and 13
V DD = 15V
I D = 71A
R G = 1.3Ω
R D = 0.20Ω, See Fig. 10
Between lead,
7.5
nH
and center of die contact
5000
V GS = 0V
1800
pF
V DS = 25V
880
= 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
IS
I SM
V SD
trr
Q rr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
140
showing the
A
G
integral reverse
470
p-n junction diode.
S
1.3
V
TJ = 25°C, IS = 71A, VGS = 0V
120 180
ns
TJ = 25°C, IF = 71A
450 680
nC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
VDD = 15V, starting TJ = 25°C, L = 180µH
RG = 25Ω, IAS = 71A. (See Figure 12)
Pulse width ≤ 300µs; duty cycle ≤ 2%.
Uses IRL3803 data and test conditions.
Calculated continuous current based on maximum allowable
junction temperature;for recommended current-handling of the
package refer to Design Tip # 93-4
TJ ≤ 175°C
** When mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
ISD ≤ 71A, di/dt ≤ 130A/µs, VDD ≤ V(BR)DSS,
2
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IRL3803S/L
10000
10000
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.0V
1000
ID , Drain-to-Source Current (A)
ID , Drain-to-Source Current (A)
1000
100
10
1
0.1
2.0V
0.01
0.1
20µs PULSE WIDTH
TJ = 25°C
1
10
A
100
100
10
0.1
R DS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
TJ = 25°C
TJ = 175°C
10
1
0.1
V DS = 25V
20µs PULSE WIDTH
4.0
5.0
6.0
7.0
8.0
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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10
A
100
Fig 2. Typical Output Characteristics
2.0
3.0
1
VDS , Drain-to-Source Voltage (V)
1000
2.0
20µs PULSE WIDTH
T J = 175°C
0.01
0.1
Fig 1. Typical Output Characteristics
0.01
2.0V
1
VDS , Drain-to-Source Voltage (V)
100
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.0V
TOP
TOP
A
9.0
I D = 120A
1.5
1.0
0.5
VGS = 10V
0.0
-60 -40 -20
0
20
40
60
A
80 100 120 140 160 180
TJ , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRL3803S/L
8000
V GS = 0V,
f = 1MHz
C iss = Cgs + C gd , Cds SHORTED
C
=C
Ciss C rss = C gd + C
oss
ds
gd
6000
Coss
15
V GS , Gate-to-Source Voltage (V)
C, Capacitance (pF)
10000
4000
Crss
2000
0
A
1
10
I D = 71A
V DS = 24V
V DS = 15V
12
9
6
3
FOR TEST CIRCUIT
SEE FIGURE 13
0
100
0
VDS , Drain-to-Source Voltage (V)
80
120
160
A
200
Q G , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
1000
OPERATION IN THIS AREA LIMITED
BY R DS(on)
10µs
I D , Drain Current (A)
ISD , Reverse Drain Current (A)
40
TJ = 175°C
100
TJ = 25°C
1ms
VGS = 0V
10
0.4
0.8
1.2
1.6
2.0
2.4
2.8
VSD , Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
100µs
100
A
3.2
TC = 25°C
TJ = 175°C
Single Pulse
10
1
10ms
10
A
100
VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRL3803S/L
140
V GS
120
ID , Drain Current (A)
RD
V DS
LIMITED BY PACKAGE
D.U.T.
RG
100
+
V
- DD
4.5V
80
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
60
Fig 10a. Switching Time Test Circuit
40
VDS
20
90%
0
25
50
75
100
125
150
175
TC , Case Temperature ( °C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
1
D = 0.50
0.20
0.1
0.10
PDM
0.05
t1
0.02
t2
SINGLE PULSE
(THERMAL RESPONSE)
0.01
Notes:
1. Duty factor D = t 1 / t 2
2. Peak TJ = P DM x Z thJC + TC
0.01
0.00001
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
L
VDS
D.U.T.
RG
+
V
- DD
IAS
10 V
tp
0.01Ω
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
VDD
EAS , Single Pulse Avalanche Energy (mJ)
IRL3803S/L
1500
TOP
BOTTOM
1200
ID
29A
50A
71A
900
600
300
0
VDD = 15V
25
50
A
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
VDS
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
IAS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
50KΩ
QG
12V
.2µF
.3µF
10 V
QGS
QGD
D.U.T.
+
V
- DS
VGS
VG
3mA
Charge
Fig 13a. Basic Gate Charge Waveform
6
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
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IRL3803S/L
Peak Diode Recovery dv/dt Test Circuit
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D.U.T
+
-
-
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Driver Gate Drive
P.W.
Period
D=
+
-
V DD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
* VGS
ISD
= 5V for Logic Level Devices
Fig 14. For N-Channel HEXFETS
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7
IRL3803S/L
D2Pak Package Outline
10.54 (.415)
10.29 (.405)
1.40 (.055)
MAX.
-A-
1.32 (.052)
1.22 (.048)
2
1.78 (.070)
1.27 (.050)
1
10.16 (.400)
REF.
-B-
4.69 (.185)
4.20 (.165)
6.47 (.255)
6.18 (.243)
3
15.49 (.610)
14.73 (.580)
2.79 (.110)
2.29 (.090)
2.61 (.103)
2.32 (.091)
5.28 (.208)
4.78 (.188)
3X
1.40 (.055)
1.14 (.045)
5.08 (.200)
0.55 (.022)
0.46 (.018)
0.93 (.037)
3X
0.69 (.027)
0.25 (.010)
M
8.89 (.350)
REF.
1.39 (.055)
1.14 (.045)
B A M
MINIMUM RECOMMENDED FOOTPRINT
11.43 (.450)
NOTES:
1
2
3
4
DIMENSIONS AFTER SOLDER DIP.
DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
CONTROLLING DIMENSION : INCH.
HEATSINK & LEAD DIMENSIONS DO NOT INCLUDE BURRS.
LEAD ASSIGNMENTS
1 - GATE
2 - DRAIN
3 - SOURCE
8.89 (.350)
17.78 (.700)
3.81 (.150)
2.08 (.082)
2X
2.54 (.100)
2X
Part Marking Information
D2Pak
INTERNATIONAL
RECTIFIER
LOGO
ASSEMBLY
LOT CODE
8
A
PART NUMBER
F530S
9246
9B
1M
DATE CODE
(YYWW)
YY = YEAR
WW = WEEK
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IRL3803S/L
Package Outline
TO-262 Outline
Part Marking Information
TO-262
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9
IRL3803S/L
Tape & Reel Information
D2Pak
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
FEED DIRECTION 1.85 (.073)
11.60 (.457)
11.40 (.449)
1.65 (.065)
0.368 (.0145)
0.342 (.0135)
15.42 (.609)
15.22 (.601)
24.30 (.957)
23.90 (.941)
TRL
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
3
30.40 (1.197)
MAX.
4
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.11/02
10
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Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/