NSC LM4855IBL Boomer audio power amplifier integrated audio amplifier system Datasheet

LM4855
Integrated Audio Amplifier System
General Description
Key Specifications
The LM4855 is an audio power amplifier system capable of
delivering 1.1W (typ) of continuous average power into a
mono 8Ω bridged-tied load (BTL) with 1% THD+N and
115mW (typ) per channel of continuous average power into
stereo 32Ω BTL loads with 0.5% THD+N, using a 5V power
supply.
n THD+N at 1kHz, 1.1W into 8Ω BTL
n THD+N at 1kHz, 115mW into 32Ω BTL
n Single Supply Operation
The LM4855 features a 32 step digital volume control
eight distinct output modes. The digital volume control
output modes are programmed through a three-wire
serial control interface, that allows flexibility in routing
mixing audio channels.
and
and
SPI
and
The LM4855 is designed for cellular phone, PDA, and other
portable handheld applications. It delivers high quality output
power from a surface-mount package and requires only six
external components.
The industry leading micro SMD package only utilizes 2mm
x 2.3mm of PCB space, making the LM4855 the most space
efficient audio sub system available today.
1.0% (typ)
0.5% (typ)
2.6 to 5.0V
Features
n
n
n
n
n
n
n
n
1.1W (typ) output power with 8Ω mono BTL load
115mW (typ) output power with stereo 32Ω BTL loads
SPI programmable 32 step digital volume control
Eight distinct output modes
micro-SMD and LLP surface mount packaging
"Click and Pop" suppression circuitry
Thermal shutdown protection
Low shutdown current (0.1uA, typ)
Applications
n Moblie Phones
n PDAs
Typical Application
200395D1
FIGURE 1. Typical Audio Amplifier Application Circuit
Boomer ® is a registered trademark of National Semiconductor Corporation.
© 2002 National Semiconductor Corporation
DS200395
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LM4855 Integrated Audio Amplifier System
November 2002
LM4855
Connection Diagrams
18-Bump micro SMD Marking (IBL)
18-Bump micro SMD Marking (ITL)
200395B0
200395E4
Top View
XY- Date Code
TT - Die Traceability
G - Boomer Family
55 - LM4855IBL
Top View
XY- Date Code
TT - Die Traceability
G - Boomer Family
A9 - LM4855ITL
LLP Package
200395A9
Top View
(Bump-side down)
Order Number LM4855ITL, LM4855IBL
See NS Package Number TLA18AAA, BLA18AAB
200395D3
Top View
Order Number LM4855LQ
See NS Package Number LQA24A for Exposed-DAP LLP
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2
θJA (typ) - LQA24A
(Note 2)
θJC (typ) - LQA24A
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
Storage Temperature
ESD Susceptibility (Note 4)
ESD Machine model (Note 7)
Junction Temperature (TJ)
42˚C/W
3.0˚C/W
θJA (typ) - BLA18AAB
48˚C/W (Note 9)
θJC (typ) - BLA18AAB
23˚C/W (Note 9)
6.0V
θJA (typ) - TLA18AAA
48˚C/W (Note 9)
−65˚C to +150˚C
θJC (typ) - TLA18AAA
23˚C/W (Note 9)
2.0kV
200V
Operating Ratings (Note 3)
150˚C
Solder Information (Note 1)
Vapor Phase (60 sec.)
215˚C
Infrared (15 sec.)
220˚C
Temperature Range
−40˚C to 85˚C
Supply Voltage VDD
2.6V ≤ VDD ≤ 5.0V
Note 1: See AN-450 "Surface Mounting and their effects on Product Reliability" for other methods of soldering surface mount devices.
Thermal Resistance
Electrical Characteristics (Notes 3, 8)
The following specifications apply for VDD = 5.0V, TA = 25˚C unless otherwise specified.
Symbol
IDD
Parameter
Supply Current
Conditions
LM4855
Units
(Limits)
Typical
(Note 5)
Limits
(Note 6)
Output mode 1
VIN = 0V; No loads
5.7
8
mA (max)
Output mode 1
VIN = 0V; Loaded (Fig.1)
6.7
9
mA (max)
Output modes 2, 3, 4, 5, 6, 7
VIN = 0V; No loads
7.5
11
mA (max)
Output modes 2, 3, 4, 5, 6, 7
VIN = 0V; Loaded (Fig. 1)
8.5
12
mA (max)
ISD
Shutdown Current
Output mode 0
0.1
2.0
µA (max)
VOS
Output Offset Voltage
VIN = 0V
5.0
40
mV (max)
SPKROUT; RL = 4Ω
THD+N = 1%; f = 1kHz, LM4855LQ
1.5
SPKROUT; RL = 8Ω
THD+N = 1%; f = 1kHz
1.1
0.8
W (min)
ROUT and LOUT; RL = 32Ω
THD+N = 0.5%; f = 1kHz
115
70
mW (min)
PO
Output Power
THD+N
Total Harmonic Distortion Plus
Noise
NOUT
Output Noise
W
SPKROUT
f = 20Hz to 20kHZ
POUT = 400mW; RL = 8Ω
0.5
%
ROUT and LOUT
f = 20Hz to 20kHZ
POUT = 50mW; RL = 32Ω
0.5
%
A-weighted (Note 10)
29
µV
3
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LM4855
Absolute Maximum Ratings
LM4855
Electrical Characteristics (Notes 3, 8)
(Continued)
The following specifications apply for VDD = 5.0V, TA = 25˚C unless otherwise specified.
Symbol
Parameter
PSRR
Power Supply Rejection Ratio
SPKROUT
Power Supply Rejection Ratio
ROUTand LOUT
Conditions
LM4855
Units
(Limits)
Typical
(Note 5)
Limits
(Note 6)
57
54
dB (min)
Output Mode 2, 3
62
59
dB (min)
Output Mode 4, 5
57
54
dB (min)
Output Mode 6, 7
54
VRIPPLE = 200mVPP; f = 217Hz, CB =
1.0µF
All audio inputs terminated into 50Ω;
Output referred Gain (BTL) = 12dB
Output Mode 1, 3, 5, 7
VRIPPLE = 200mVPP; f = 217Hz, CB =
1.0µF
All audio inputs terminated into 50Ω;
Output referred Maximum gain setting
51
dB (min)
VIH
Logic High Input Voltage
1.4
VDD
V (min)
V (max)
VIL
Logic Low Input Voltage
0.4
GND
V (max)
V (min)
Digital Volume Range (RIN and
LIN)
Input referred minimum gain
-34.5
-35.1
-33.9
dB (min)
dB (max)
Input referred maximum gain
12.0
11.4
12.6
dB (min)
dB (max)
± 0.1
± 0.6
dB ( max)
dB (min)
dB (max)
Digital Volume Stepsize
1.5
Digital Volume Stepsize Error
dB
Phone_In_IHF Volume
BTL gain from Phone_In _IHF to
SPKROUT
12
11.4
12.6
Phone _In_IHF Mute Attenuation
Output Mode 2, 4, 6
80
72
dB (min)
20
15
25
kΩ (min)
kΩ (max)
Maximum gain setting
50
37.5
62.5
kΩ (min)
kΩ (max)
Mininum gain setting
100
75
125
kΩ (min)
kΩ (max)
Maximum gain setting
33.5
25
42
kΩ (min)
kΩ (max)
Mininum gain setting
100
75
125
kΩ (min)
kΩ (max)
170
Phone_In_IHF Input Impedance
Phone_In_HS Input Impedance
RIN and LIN Input Impedance
tSD
Thermal Shutdown Temperature
150
˚C (min)
tES
Enable Setup Time (ENB)
20
ns (min)
tEH
Enable Hold Time (ENB)
20
ns (min)
tEL
Enable Low Time (ENB)
30
ns (min)
tDS
Data Setup Time (DATA)
20
ns (min)
tDH
Data Hold Time (DATA)
20
ns (min)
tCS
Clock Setup Time (CLK)
20
ns (min)
tCH
Clock Logic High Time (CLK)
50
ns (min)
tCL
Clock Logic Low Time (CLK)
50
ns (min)
fCLK
Clock Frequency
DC
10
(min)
MHz (max)
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LM4855
Electrical Characteristics (Notes 2, 8)
The following specifications apply for VDD = 3.0V, TA = 25˚C unless otherwise specified.
Symbol
IDD
Parameter
Supply Current
Conditions
LM4855
Units
(Limits)
Typical
(Note 5)
Limits
(Note 6)
Output mode 1
VIN = 0V; No loads
4.5
7
mA (max)
Output mode 1
VIN = 0V; Loaded (Fig.1)
5.0
8
mA (max)
Output modes 2, 3, 4, 5, 6, 7
VIN = 0V; No loads
6.5
10
mA (max)
Output modes 2, 3, 4, 5, 6, 7
VIN = 0V; Loaded (Fig. 1)
7
11
mA (max)
ISD
Shutdown Current
Output mode 0
0.1
2.0
µA (max)
VOS
Output Offset Voltage
VIN = 0V
5.0
40
mV (max)
SPKROUT; RL = 4Ω
THD+N = 1%; f = 1kHz, LM4855LQ
430
SPKROUT; RL = 8Ω
THD+N = 1%; f = 1kHz
340
300
mW (min)
ROUT and LOUT; RL = 32Ω
THD+N = 0.5%; f = 1kHz
25
20
mW (min)
SPKROUT
f = 20Hz to 20kHZ
POUT = 250mW; RL = 8Ω
0.5
%
ROUT and LOUT
f = 20Hz to 20kHZ
POUT = 20mW; RL = 32Ω
0.5
%
PO
Output Power
mW
THD+N
Total Harmonic Distortion Plus
Noise
NOUT
Output Noise
A-weighted (Note 10)
29
58
55
dB (min)
Power Supply Rejection Ratio
SPKROUT
VRIPPLE = 200mVPP; f = 217Hz, CB =
1.0µF
All audio inputs terminated into 50Ω;
Output referred Gain (BTL) = 12dB
Output Mode 1, 3, 5, 7
Power Supply Rejection Ratio
ROUTand LOUT
VRIPPLE = 200mVPP; f = 217Hz, CB =
1.0µF
All audio inputs terminated into 50Ω;
Output referred Maximum gain setting
Output Mode 2, 3
63
60
dB (min)
Output Mode 4, 5
58
55
dB (min)
Output Mode 6, 7
55
52
dB (min)
PSRR
µV
VIH
Logic High Input Voltage
1.4
VDD
V (min)
V (max)
VIL
Logic Low Input Voltage
0.4
GND
V (max)
V (min)
5
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LM4855
Electrical Characteristics (Notes 2, 8)
(Continued)
The following specifications apply for VDD = 3.0V, TA = 25˚C unless otherwise specified.
Symbol
Parameter
Digital Volume Range (RIN and
LIN)
Conditions
LM4855
Units
(Limits)
Typical
(Note 5)
Limits
(Note 6)
Input referred minimum gain
-34.5
-35.1
-33.9
dB (min)
dB (max)
Input referred maximum gain
12.0
11.4
12.6
dB (min)
dB (max)
± 0.1
± 0.6
dB ( max)
dB (min)
dB (max)
Digital Volume Stepsize
1.5
Digital Volume Stepsize Error
dB
Phone_In_IHF Volume
BTL gain from Phone_In _IHF to
SPKROUT
12
11.4
12.6
Phone _In_IHF Mute Attenuation
Output Mode 2, 4, 6
80
72
dB (min)
20
15
25
kΩ (min)
kΩ (max)
Maximum gain setting
50
37.5
62.5
kΩ (min)
kΩ (max)
Mininum gain setting
100
75
125
kΩ (min)
kΩ (max)
Maximum gain setting
33.5
25
42
kΩ (min)
kΩ (max)
Mininum gain setting
100
75
125
kΩ (min)
kΩ (max)
170
Phone_In_IHF Input Impedance
Phone_In_HS Input Impedance
RIN and LIN Input Impedance
tSD
Thermal Shutdown Temperature
150
˚C (min)
tES
Enable Setup Time (ENB)
20
ns (min)
tEH
Enable Hold Time (ENB)
20
ns (min)
tEL
Enable Low Time (ENB)
30
ns (min)
tDS
Data Setup Time (DATA)
20
ns (min)
tDH
Data Hold Time (DATA)
20
ns (min)
tCS
Clock Setup Time (CLK)
20
ns (min)
tCH
Clock Logic High Time (CLK)
50
ns (min)
tCL
Clock Logic Low Time (CLK)
50
ns (min)
fCLK
Clock Frequency
DC
10
(min)
MHz (max)
Note 2: Absolute Maximum Rating indicate limits beyond which damage to the device may occur.
Note 3: Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and
test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
Note 4: Human body model, 100pF discharged through a 1.5kΩ resistor.
Note 5: Typical specifications are specified at +25˚C and represent the most likely parametric norm.
Note 6: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 7: Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200pF cap is charged to the specified voltage, then discharged directly into the
IC with no external series resistor (resistance of discharge path must be under 50Ω).
Note 8: All voltages are measured with respect to the ground pin, unless otherwise specified.
Note 9: The given θJA and θJC are for an LM4855 mounted on a demonstration board with a 4in2 area of 1oz printed circuit board copper ground plane.
Note 10: Please refer to the Output Noise vs Output Mode table in the Typical Performance Characteristics section for more details.
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LM4855
External Components Description
Components
Functional Description
1.
CIN
This is the input coupling capacitor. It blocks the DC voltage and couples the input signal to the amplifier’s
input terminals. CIN also creates a highpass filter with the internal resistor Ri (Input Impedance) at fc =
1/(2πRiCIN).
2.
CS
This is the supply bypass capacitor. It filters the supply voltage applied to the VDD pin and helps maintain
the LM4855’s PSRR.
3.
CB
This is the BYPASS pin capacitor. It filters the VDD / 2 voltage and helps maintain the LM4855’s PSRR.
Typical Performance Characteristics
THD+N vs Frequency
LM4855LQ
THD+N vs Frequency
LM4855LQ
200395F0
200395F1
THD+N vs Frequency
THD+N vs Frequency
200395B1
200395B2
7
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LM4855
Typical Performance Characteristics
(Continued)
THD+N vs Frequency
THD+N vs Frequency
200395B3
200395B4
THD+N vs Frequency
THD+N vs Frequency
200395B5
200395B6
THD+N vs Frequency
THD+N vs Frequency
200395B7
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200395B8
8
LM4855
Typical Performance Characteristics
(Continued)
THD+N vs Output Power
LM4855LQ
THD+N vs Output Power
LM4855LQ
200395F2
200395F3
THD+N vs Output Power
THD+N vs Output Power
200395B9
200395C0
THD+N vs Output Power
THD+N vs Output Power
200395C1
200395C2
9
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LM4855
Typical Performance Characteristics
(Continued)
Power Supply Rejection Ratio
Power Supply Rejection Ratio
200395C3
200395C4
Power Supply Rejection Ratio
Power Supply Rejection Ratio
200395C5
200395C6
Power Supply Rejection Ratio
Power Supply Rejection Ratio
200395C7
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200395C8
10
LM4855
Typical Performance Characteristics
(Continued)
Output Power vs Supply Voltage
Output Power vs Supply Voltage
200395D8
200395D7
Output Power vs Load Resistance
Output Power vs Load Resistance
200395D9
200395E0
Power Dissipation vs Output Power
Power Dissipation vs Output Power
200395E1
200395E2
11
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LM4855
Typical Performance Characteristics
(Continued)
Supply Current vs Supply Voltage
Channel Separation
200395C9
200395D0
Frequency Response
Frequency Response
200395D4
200395D5
Frequency Response
200395D6
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LM4855
Typical Performance Characteristics
(Continued)
Output Noise vs Output Mode (VDD = 3V, 5V)
Output Mode
SPKROUT
Output Noise
(µV)
LOUT/ROUT
Output Noise
(µV)
1
29
X
2
X
28 (G1 = 0dB)
31 (G1 = 6dB)
3
29
28 (G1 = 0dB)
31 (G1 = 6dB)
4
X
28 (G2 = 0dB)
38 (G2 = 12dB)
5
29
28(G2 = 0dB)
38 (G2 = 12dB)
6
X
38 (G2 = 0dB)
41 (G1 = 0dB)
48 (G1 = 6dB)
7
29
38 (G2 = 0dB)
41 (G1 = 0dB)
48 (G1 = 6dB)
G1 = gain from PHS to LOUT/ROUT
G2 = gain from LIN/RIN to LOUT/ROUT
A - weighted filter used
13
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LM4855
APPLICATION INFORMATION
SPI PIN DESCRIPTION
the data bits are written to the DATA pin with the least
significant bit (LSB) first. All serial data are sampled at the
rising edge of the CLK signal. Once all the data bits have
been sampled, ENB transitions from logic-high to logic-low
to complete the SPI sequence. All 8 bits must be received
before any data latch can occur. Any excess CLK and DATA
transitions will be ignored after the eighth rising clock edge
has occurred. For any data sequence longer than 8 bits, only
the first 8 bits will get loaded into the shift register and the
rest of the bits will be disregarded.
DATA: This is the serial data input pin.
CLK: This is the clock input pin.
ENB: This is the SPI enable pin and is active-high.
SPI OPERATION DESCRIPTION
The serial data bits are organized into a field which contains
8 bits of data defined by TABLE 1. The Data 0 to Data 2 bits
determine the output mode of the LM4855 as shown in
TABLE 2. The Data 3 to Data 7 bits determine the volume
level setting as illustrated by TABLE 3. For each SPI transfer,
TABLE 1. Bit Allocation
Data 0
Mode Select
Data 1
Mode Select
Data 2
Mode Select
Data 3
Volume Control
Data 4
Volume Control
Data 5
Volume Control
Data 6
Volume Control
Data 7
Volume Control
TABLE 2. Output Mode Selection
Output Mode #
Data 2
Data 1
Data 0
SPKROUT
ROUT
LOUT
0
0
0
0
SD
SD
SD
1
0
0
1
12dB x PIHF
SD
SD
2
0
1
0
MUTE
G1 x PHS
G1 x PHS
3
0
1
1
12dB x PIHF
G1 x PHS
G1 x PHS
4
1
0
0
MUTE
G2 x R
G2 x L
5
1
0
1
12dB x PIHF
G2 x R
G2 x L
6
1
1
0
MUTE
(G1 x PHS) + (G2 x R)
(G1 x PHS) + (G2 x L)
7
1
1
1
12dB x PIHF
(G1 x PHS) + (G2 x R)
(G1 x PHS) + (G2 x L)
R = Rin
L = Lin
PIHF = Phone_In_IHF
PHS = Phone_In_HS
SD = Shutdown Mode
MUTE = Mute Mode
G1 = gain from PHS to LOUT/ROUT
G2 = gain from LIN/ RIN to LOUT/ROUT
Default Mode upon device power-up is Output Mode 0
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LM4855
APPLICATION INFORMATION
(Continued)
TABLE 3. Volume Control Settings
Gain (dB)
G2
G1
RIN, LIN
to
ROUT, LOUT
Phone_In_HS
to
ROUT, LOUT
Data 7
Data 6
Data 5
Data 4
Data 3
-34.5
-40.5
0
0
0
0
0
-33.0
-39.0
0
0
0
0
1
-31.5
-37.5
0
0
0
1
0
-30.0
-360
0
0
0
1
1
-28.5
-34.5
0
0
1
0
0
-27.0
-33.0
0
0
1
0
1
-25.5
-31.5
0
0
1
1
0
-24.0
-30.0
0
0
1
1
1
-22.5
-28.5
0
1
0
0
0
-21.0
-27.0
0
1
0
0
1
-19.5
-25.5
0
1
0
1
0
-18.0
-24.0
0
1
0
1
1
-16.5
-22.5
0
1
1
0
0
-15.0
-21.0
0
1
1
0
1
-13.5
-19.5
0
1
1
1
0
-12.0
-18.0
0
1
1
1
1
-10.5
-16.5
1
0
0
0
0
-9.0
-15.0
1
0
0
0
1
-7.5
-13.5
1
0
0
1
0
-6.0
-12.0
1
0
0
1
1
-4.5
-10.5
1
0
1
0
0
-3.0
-9.0
1
0
1
0
1
-1.5
-7.5
1
0
1
1
0
0.0
-6.0
1
0
1
1
1
1.5
-4.5
1
1
0
0
0
3.0
-3.0
1
1
0
0
1
4.5
-1.5
1
1
0
1
0
6.0
0
1
1
0
1
1
7.5
1.5
1
1
1
0
0
9.0
3.0
1
1
1
0
1
10.5
4.5
1
1
1
1
0
12.0
6.0
1
1
1
1
1
15
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LM4855
APPLICATION INFORMATION
6. ENB must be logic-high at least 20ns (tES ) before the first
rising edge of CLK, and ENB has to remain logic-high at
least 20ns (tEH) after the eighth rising edge of CLK.
7. If ENB remains logic-low for more than 10ns before all 8
bits are transmitted then the data latch will be aborted.
8. If ENB is logic-high for more than 8 CLK pulses then only
the first 8 data bits will be latched and activated when ENB
transitions to logic-low.
9. ENB must remain logic-low for at least 30ns (tEL ) to latch
in the data.
(Continued)
SPI OPERATIONAL REQUIREMENTS
1. The data bits are transmitted with the LSB first.
2. The maximum clock rate is 10MHz for the CLK pin.
3. CLK must remain logic-high for at least 50ns (tCH ) after
the rising edge of CLK, and CLK must remain logic-low for at
least 50ns (tCL) after the falling edge of CLK.
4. The serial data bits are sampled at the rising edge of CLK.
Any transition on DATA must occur at least 20ns (tDS) before
the rising edge of CLK. Also, any transition on DATA must
occur at least 20ns (tDH) after the rising edge of CLK and
stabilize before the next rising edge of CLK.
10. Coincidental rising or falling edges of CLK and ENB are
not allowed. If CLK is to be held logic-high after the data
transmission, the falling edge of CLK must occur at least
20ns (tCS) before ENB transitions to logic-high for the next
set of data.
5. ENB should be logic-high only during serial data transmission.
200395D2
FIGURE 2. SPI Timing Diagram
share the same PCB layer, a nominal 2.5in2 (min) area is
necessary for 5V operation with a 4Ω load. Heatsink areas
not placed on the same PCB layer as the LM4855 should be
5in2 (min) for the same supply voltage and load resistance.
The last two area recommendations apply for 25˚C ambient
temperature. Increase the area to compensate for ambient
temperatures above 25˚C. In all circumstances and under all
conditions, the junction temperature must be held below
150˚C to prevent activating the LM4855’s thermal shutdown
protection. Further detailed and specific information concerning PCB layout and fabrication and mounting an LD
(LLP) is found in National Semiconductor’s AN1187.
EXPOSED-DAP MOUNTING CONSIDERATIONS
The LM4855’s exposed-DAP (die attach paddle) package
(LD) provides a low thermal resistance between the die and
the PCB to which the part is mounted and soldered. This
allows rapid heat transfer from the die to the surrounding
PCB copper area heatsink, copper traces, ground plane, and
finally, surrounding air. The result is a low voltage audio
power amplifier that produces 1.1W dissipation in a 8Ω load
at ≤ 1% THD+N. This high power is achieved through careful
consideration of necessary thermal design. Failing to optimize thermal design may compromise the LM4855’s high
power performance and activate unwanted, though necessary, thermal shutdown protection.
The LD package must have its DAP soldered to a copper
pad on the PCB. The DAP’s PCB copper pad is then, ideally,
connected to a large plane of continuous unbroken copper.
This plane forms a thermal mass, heat sink, and radiation
area. Place the heat sink area on either outside plane in the
case of a two-sided or multi-layer PCB. (The heat sink area
can also be placed on an inner layer of a multi-layer board.
The thermal resistance, however, will be higher.) Connect
the DAP copper pad to the inner layer or backside copper
heat sink area with 6 (3 X 2) (LD) vias. The via diameter
should be 0.012in - 0.013in with a 1.27mm pitch. Ensure
efficient thermal conductivity by plugging and tenting the vias
with plating and solder mask, respectively.
Best thermal performance is achieved with the largest practical copper heat sink area. If the heatsink and amplifier
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PCB LAYOUT AND SUPPLY REGULATION
CONSIDERATIONS FOR DRIVING 3Ω AND 4Ω LOADS
Power dissipated by a load is a function of the voltage swing
across the load and the load’s impedance. As load impedance decreases, load dissipation becomes increasingly dependent on the interconnect (PCB trace and wire) resistance
between the amplifier output pins and the load’s connections. Residual trace resistance causes a voltage drop,
which results in power dissipated in the trace and not in the
load as desired. For example, 0.1Ω trace resistance reduces
the output power dissipated by a 4Ω load from 1.7W to 1.6W.
The problem of decreased load dissipation is exacerbated
as load impedance decreases. Therefore, to maintain the
16
PDMAX-SPKROUT = 4(VDD)2/(2π2 RL): Bridge Mode
(Continued)
highest load dissipation and widest output voltage swing,
PCB traces that connect the output pins to a load must be as
wide as possible.
Poor power supply regulation adversely affects maximum
output power. A poorly regulated supply’s output voltage
decreases with increasing load current. Reduced supply
voltage causes decreased headroom, output signal clipping,
and reduced output power. Even with tightly regulated supplies, trace resistance creates the same effects as poor
supply regulation. Therefore, making the power supply
traces as wide as possible helps maintain full output voltage
swing.
(2)
The LM4855 also has 2 pairs of bridged-tied amplifiers driving stereo headphones, ROUT and LOUT. The maximum
internal power dissipation for ROUT and LOUT is given by
equation (3) and (4). From Equations (3) and (4), assuming
a 5V power supply and a 32Ω load, the maximum power
dissipation for LOUT and ROUT is 158mW, or 316mW total.
PDMAX-LOUT = 4(VDD)2/(2π2 RL): Bridge Mode
(3)
PDMAX-ROUT = 4(VDD)2/(2π2 RL): Bridge Mode
(4)
BRIDGE CONFIGURATION EXPLANATION
The maximum internal power dissipation of the LM4855
occurs when all 3 amplifiers pairs are simultaneously on; and
is given by Equation (5).
As shown in Figure 1, the LM4855 consists of three pairs of
output amplifier blocks (A4-A6). A4, A5, and A6 consist of
bridged-tied amplifier pairs that drive LOUT, ROUT, and
SPKROUT respectively. The LM4855 drives a load, such as
a speaker, connected between outputs, SPKROUT+ and
SPKROUT-. In the amplifier block A6, the output of the
amplifier that drives SPKROUT- serves as the input to the
unity gain inverting amplifier that drives SPKROUT+.
PDMAX-TOTAL =
PDMAX-SPKROUT + PDMAX-LOUT + PDMAX-ROUT
The maximum power dissipation point given by Equation (5)
must not exceed the power dissipation given by Equation
(6):
This results in both amplifiers producing signals identical in
magnitude, but 180˚ out of phase. Taking advantage of this
phase difference, a load is placed between SPKROUT- and
SPKROUT+ and driven differentially (commonly referred to
as ’bridge mode’). This results in a differential or BTL gain of:
AVD = 2(Rf/Ri) = 2
(5)
PDMAX’ = (TJMAX - TA)/ θJA
(6)
The LM4855’s TJMAX = 150˚C. In the IBL package, the
LM4855’s θJA is 48˚C/W. In the LD package soldered to a
DAP pad that expands to a copper area of 2.5in2 on a PCB,
the LM4855’s θJA is 42˚C/W. At any given ambient temperature TA, use Equation (6) to find the maximum internal power
dissipation supported by the IC packaging. Rearranging
Equation (6) and substituting PDMAX-TOTAL for PDMAX’ results
in Equation (7). This equation gives the maximum ambient
temperature that still allows maximum stereo power dissipation without violating the LM4855’s maximum junction temperature.
(1)
Bridge mode amplifiers are different from single-ended amplifiers that drive loads connected between a single amplifier’s output and ground. For a given supply voltage, bridge
mode has a distinct advantage over the single-ended configuration: its differential output doubles the voltage swing
across the load. Theoretically, this produces four times the
output power when compared to a single-ended amplifier
under the same conditions. This increase in attainable output
power assumes that the amplifier is not current limited and
that the output signal is not clipped.
Another advantage of the differential bridge output is no net
DC voltage across the load. This is accomplished by biasing
SPKROUT- and SPKROUT+ outputs at half-supply. This
eliminates the coupling capacitor that single supply, singleended amplifiers require. Eliminating an output coupling capacitor in a typical single-ended configuration forces a
single-supply amplifier’s half-supply bias voltage across the
load. This increases internal IC power dissipation and may
permanently damage loads such as speakers.
TA = TJMAX - PDMAX-TOTALθJA
(7)
For a typical application with a 5V power supply and an 8Ω
load, the maximum ambient temperature that allows maximum stereo power dissipation without exceeding the maximum junction temperature is approximately 104˚C for the
IBL package.
TJMAX = PDMAX-TOTAL θJA + TA
POWER DISSIPATION
Power dissipation is a major concern when designing a
successful single-ended or bridged amplifier.
A direct consequence of the increased power delivered to
the load by a bridge amplifier is higher internal power dissipation. The LM4855 has a pair of bridged-tied amplifiers
driving a handsfree speaker, SPKROUT. The maximum internal power dissipation operating in the bridge mode is
twice that of a single-ended amplifier. From Equation (2),
assuming a 5V power supply and an 8Ω load, the maximum
SPKROUT power dissipation is 634mW.
(8)
Equation (8) gives the maximum junction temperature TJMAX. If the result violates the LM4855’s 150˚C, reduce the
maximum junction temperature by reducing the power supply voltage or increasing the load resistance. Further allowance should be made for increased ambient temperatures.
The above examples assume that a device is a surface
mount part operating around the maximum power dissipation
point. Since internal power dissipation is a function of output
power, higher ambient temperatures are allowed as output
power or duty cycle decreases. If the result of Equation (5) is
greater than that of Equation (6), then decrease the supply
17
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LM4855
APPLICATION INFORMATION
LM4855
APPLICATION INFORMATION
SELECTING EXTERNAL COMPONENTS
Input Capacitor Value Selection
Amplifying the lowest audio frequencies requires high value
input coupling capacitor (Ci in Figure 2). A high value capacitor can be expensive and may compromise space efficiency
in portable designs. In many cases, however, the speakers
used in portable systems, whether internal or external, have
little ability to reproduce signals below 150Hz. Applications
using speakers with this limited frequency response reap
little improvement by using large input capacitor.
The internal input resistor (Ri) and the input capacitor (Ci)
produce a high pass filter cutoff frequency that is found using
Equation (9).
(Continued)
voltage, increase the load impedance, or reduce the ambient
temperature. If these measures are insufficient, a heat sink
can be added to reduce θJA. The heat sink can be created
using additional copper area around the package, with connections to the ground pin(s), supply pin and amplifier output
pins. External, solder attached SMT heatsinks such as the
Thermalloy 7106D can also improve power dissipation.
When adding a heat sink, the θJA is the sum of θJC, θCS, and
θSA. (θJC is the junction-to-case thermal impedance, θCS is
the case-to-sink thermal impedance, and θSA is the sink-toambient thermal impedance.) Refer to the Typical Performance Characteristics curves for power dissipation information at lower output power levels.
fc = 1 / (2πRiCi)
POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is
critical for low noise performance and high power supply
rejection. Applications that employ a 5V regulator typically
use a 10µF in parallel with a 0.1µF filter capacitors to stabilize the regulator’s output, reduce noise on the supply line,
and improve the supply’s transient response. However, their
presence does not eliminate the need for a local 1.0µF
tantalum bypass capacitance connected between the
LM4855’s supply pins and ground. Keep the length of leads
and traces that connect capacitors between the LM4855’s
power supply pin and ground as short as possible. Connecting a 1µF capacitor, CB, between the BYPASS pin and
ground improves the internal bias voltage’s stability and
improves the amplifier’s PSRR. The PSRR improvements
increase as the bypass pin capacitor value increases. Too
large, however, increases turn-on time and can compromise
the amplifier’s click and pop performance. The selection of
bypass capacitor values, especially CB, depends on desired
PSRR requirements, click and pop performance (as explained in the section, Proper Selection of External Components), system cost, and size constraints.
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(9)
As an example when using a speaker with a low frequency
limit of 150Hz, Ci, using Equation (9) is 0.063µF. The 0.22µF
Ci shown in Figure 1 allows the LM4855 to drive high efficiency, full range speaker whose response extends below
40Hz.
Bypass Capacitor Value Selection
Besides minimizing the input capacitor size, careful consideration should be paid to value of CB, the capacitor connected to the BYPASS pin. Since CB determines how fast
the LM4855 settles to quiescent operation, its value is critical
when minimizing turn-on pops. The slower the LM4855’s
outputs ramp to their quiescent DC voltage (nominally VDD/
2), the smaller the turn-on pop. Choosing CB equal to 1.0µF
along with a small value of Ci (in the range of 0.1µF to
0.39µF), produces a click-less and pop-less shutdown function. As discussed above, choosing Ci no larger than necessary for the desired bandwidth helps minimize clicks and
pops. CB’s value should be in the range of 5 times to 7 times
the value of Ci. This ensures that output transients are
eliminated when power is first applied or the LM4855 resumes operation after shutdown.
18
LM4855
Demonstration Board Layout
200395A7
200395A6
FIGURE 3. Recommended IBL, ITL PC Board Layout:
Top Silkscreen
FIGURE 4. Recommended IBL, ITL PC Board Layout:
Top Layer
200395A5
200395A4
FIGURE 5. Recommended IBL, ITL PC Board Layout:
Middle Layer
FIGURE 6. Recommended IBL, ITL PC Board Layout:
Bottom Layer
19
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LM4855
Demonstration Board Layout
(Continued)
200395E6
200395E5
FIGURE 8. Recommended LD PC Board Layout:
Top Layer
FIGURE 7. Recommended LD PC Board Layout:
Top Silkcreen Layer
200395E7
200395E8
FIGURE 9. Recommended LD PC Board Layout:
Inner Layer 1
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FIGURE 10. Recommended LD PC Board Layout:
Inner Layer 2
20
LM4855
Demonstration Board Layout
(Continued)
200395E9
FIGURE 11. Recommended LD PC Board Layout:
Bottom Layer
21
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LM4855
Physical Dimensions
inches (millimeters) unless otherwise noted
18-Bump mciro SMD
Order Number LM4855IBL
NS Package Number BLA18AAB
Dimensions are in millimeteres
X1 = 1.996 ± 0.03 X2 = 2.225 ± 0.03 X3 = 0.945 ± 0.01
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22
LM4855
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
24-Lead MOLDED PKG, Leadless Leadframe Package LLP
Order Number LM4855LQ
NS Package Number LQA24A
23
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LM4855 Integrated Audio Amplifier System
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
18-Bump micro SMD
Order Number LM4855ITL
NS Package Number TLA18AAA
X1 = 1.996 X2 = 2.225 X3 = 0.600
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
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Email: [email protected]
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Email: [email protected]
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Français Tel: +33 (0) 1 41 91 8790
2. A critical component is any component of a life
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can be reasonably expected to cause the failure of
the life support device or system, or to affect its
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Response Group
Tel: 65-2544466
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Email: [email protected]
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