Integrated Circuit Systems, Inc. ICS9148-32 Pentium/ProTM System Clock Chip General Description Features The ICS9148-32 is a Clock Synthesizer chip for Pentium and PentiumPro CPU based Desktop/Notebook systems that will provide all necessary clock timing. Features include four CPU and eight PCI clocks. Three reference outputs are available equal to the crystal frequency. Additionally, the device meets the Pentium power-up stabilization requirement, assuring that CPU and PCI clocks are stable within 2ms after power-up. PD# pin enables low power mode by stopping crystal OSC and PLL stages. Other power management features include CPU_STOP#, which stops CPU (0:3) clocks, and PCI_STOP#, which stops PCICLK (0:6) clocks. Serial I2C interface allows power management by output clock disabling. High drive CPUCLK outputs typically provide greater than 1 V/ns slew rate into 20pF loads. PCICLK outputs typically provide better than 1V/ns slew rate into 30pF loads while maintaining 50±5% duty cycle. The REF clock outputs typically provide better than 0.5V/ns slew rates. Generates system clocks for CPU, IOAPIC, PCI, 14.314 MHz REF , USB, and Super I/O Supports single or dual processor systems I2C interface Supports Spread Spectrum modulation for CPU & PCI clocks, ±0.255% Center Spread or 0 to -0.6% Down Spread. Skew from CPU (earlier) to PCI clock 1 to 4ns CPU cycle to cycle jitter ±200ps 2.5V or 3.3V output: CPU, IOAPIC 3.3V outputs: PCI, REF, 48MHz No power supply sequence requirements Uses external 14.318MHz crystal, no external load cap required for CL=18pF crystal 48 pin 300 mil SSOP Pin Configuration The ICS9148-32 accepts a 14.318MHz reference crystal or clock as its input and runs on a 3.3V core supply. Block Diagram 48-Pin SSOP Power Groups VDD = Supply for PLL core VDD1 = REF (0:2), X1, X2 VDD2 = PCICLK_F, PCICLK (0:6) VDD3 = 48MHz, 24/48MHz# VDDL1 = IOAPIC (0:1) VDDL2 = CPUCLK (0:3) Ground Groups Pentium is a trademark on Intel Corporation. 9148-32 Rev B 09/09/98 GND = Ground for PLL core GND1 = REF (0:2), X1, X2 GND2 = PCICLK_F, PCICLK (0:6) GND3 = 48MHz, 24/48MHz# GNDL1 = IOAPIC (0:1) GNDL2 = CPUCLK (0:3) ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9148-32 Pin Descriptions PIN NUMBER PIN NAME TYPE 1 REF0/SEL48# OUT/IN 2, 47 3 REF (1:2) GND1 OUT PWR 4 X1 IN 5 6, 12, 18 7 8, 10, 11, 13, 14, 16, 17 9, 15 19, 33 20, 32 21 22 X2 GND2 PCICLK_F PCICLK (0:6) VDD2 VDD GND VDD3 48MHz OUT PWR OUT OUT PWR PWR PWR PWR OUT 23 24/48MHz# OUT 24 GND3 PWR 25 SEL100/66.6# IN 26 27 281 291 301 311 37, 41 34, 38 35, 36, 39, 40 42 43 44, 45 46 SCLK SDATA SPREAD# PD# CPU_STOP# PCI_STOP# VDDL2 GNDL2 CPUCLK (3:0) N/C GNDL1 IOAPIC (0:1) VDDL1 IN IN IN IN IN IN PWR PWR OUT PWR OUT PWR DESCRIPTION 14.318MHz clock output / Latched input at power up. When low, pin 23 is 48MHz. 14.318MHz clock output Ground for REF outputs XTAL_IN 14.318MHz Crystal input, has internal 33pF load cap and feed back resistor from X2 XTAL_OUT Crystal output, has internal load cap 33pF Ground for PCI outputs Free Running PCI output PCI clock outputs. TTL compatible 3.3V Power for PCICLK outputs, nominally 3.3V Isolated power for core, nominally 3.3V Isolated ground for core Power for 48MHz outputs, nominally 3.3V 48MHz output Fixed clock output. 24MHz if pin1=1 at power up 48MHz if pin 1=0 at power up Ground for 48MHz outputs Select pin for enabling 100MHz or 66.6MHz H=100MHz, L=66.6MHz (PCI always synchronous 33.3MHz) Clock input for I2C input Data input for I2C input Enables Spread Spectrum feature when LOW Powers down chip, active low Halts CPU clocks at logic "0" level when low Halts PCI Bus at logic "0" level when low Power for CPU outputs, nominally 2.5V Ground for CPU outputs. CPU and Host clock outputs, nominally 2.5V Not internally connected Ground for IOAPIC outputs IOAPIC outputs (14.318MHz) nominally 2.5V Power for IOAPIC outputs, nominally 2.5V REF IOAPIC Select Functions Functionality CPU PCI, PCI_F 48 MHz Selection Tristate HI - Z HI - Z HI - Z HI - Z HI - Z Testmode TCLK/21 TCLK/61 TCLK1 TCLK1 TCLK/21 Spread Spectrum Modulated2 Modulated2 14.318MHz 14.318MHz 48.0MHz 2 ICS9148-32 Technical Pin Function Descriptions VDD, VDD (1,2,3) This is the power supply to the internal core logic of the device as well as the clock output buffers for REF(0:2), PCICLK_F, PCICLK (0:6), 48MHz0, 48MHz1. 48MHz This is a fixed frequency Clock output that is typically used to drive USB devices. 24/48MHz Fixed frequency clock output. 24MHz output if Pin1=1 at power up. 48MHz if pin1=0 at power up. This pin operates at 3.3V volts. Clocks from the listed buffers that it supplies will have a voltage swing from Ground to this level. For the actual guaranteed high and low voltage levels for the Clocks, please consult the DC parameter table in this data sheet. IOAPIC (0:1) This Output is a fixed frequency Output Clock that runs at the Reference Input (typically 14.31818MHz) . Its voltage level swing is controlled by VDDL1 and may operate at 2.5 or 3.3volts. VDDL (1,2) This is the power supply for the CPUCLK (0:3) and IOAPIC output buffers. The voltage level for these outputs may be 2.5 or 3.3volts. Clocks from the buffers that each supplies will have a voltage swing from Ground to this level. For the actual Guaranteed high and low voltage levels of these Clocks, please consult the DC parameter table in this Data Sheet. REF0/SEL 48# This is an input pin during power up only. During power up if high, then pin 23 is a 24MHz fixed clock during normal operation. If Low during power up, pin 23 is a 48MHz fixed clock during normal operation. During normal operation, REF0 is an output which is a fixed frequency running at 14.318MHz. GND, GND (1,2,3) This is the ground to the internal core logic of the device as well as the clock output buffers for REF(0:2), PCICLK_F, PCICLK (0:6), 48MHz 0, 48MHz1. REF(1:2) The REF Outputs are fixed frequency Clocks that run at the same frequency as the Input Reference Clock X1 or the Crystal (typically 14.31818MHz) attached across X1 and X2. GNDL (1,2) This is the ground for the CPUCLK (0:3) and IOAPIC output buffers. PCICLK_F This Output is equal to PCICLK(0:6) and is FREE RUNNING, and will not be stopped by PCI_STOP#. X1 This input pin serves one of two functions. When the device is used with a Crystal, X1 acts as the input pin for the reference signal that comes from the discrete crystal. When the device is driven by an external clock signal, X1 is the device input pin for that reference clock. This pin also implements an internal Crystal loading capacitor that is connected to ground. With a nominal value of 33pF no external load cap is needed for a CL=17 to 18pF crystal. PCICLK (0:6) These Output Clocks generate all the PCI timing requirements for a Pentium/Pro based system. They conform to the current PCI specification. They run at 33.3 MHz. SEL 100/66.6# This Input pin controls the frequency of the Clocks at the CPUCLK, PCICLK and SDRAM output pins. If a logic 1 value is present on this pin, the 100MHz Clock will be selected. If a logic 0 is used, the 66.6MHz frequency will be selected. The PCI clock is multiplexed to be 33.3MHz for both select cases. PCI is synchronous at the rising edge of PCI to the CPU rising edge (with the skew making CPU early). X2 This Output pin is used only when the device uses a Crystal as the reference frequency source. In this mode of operation, X2 is an output signal that drives (or excites) the discrete Crystal. The X2 pin will also implement an internal Crystal loading capacitor nominally 33pF. CPUCLK (0:3) These Output pins are the Clock Outputs that drive processor and other CPU related circuitry that requires clocks which are in tight skew tolerance with the CPU clock. The voltage swing of these Clocks is controlled by the Voltage level applied to the VDDL2 pin of the device. See the Functionality Table for a list of the specific frequencies that are available for these Clocks and the selection codes to produce them. 3 ICS9148-32 Technical Pin Function Descriptions PWR_DWN# This is an asynchronous active Low Input pin used to Power Down the device into a Low Power state by not removing the power supply. The internal Clocks are disabled and the VCO and Crystal are stopped. Powered Down will also place all the Outputs in a low state at the end of their current cycle. The latency of Power Down will not be greater than 3ms. CPU_STOP# This is a synchronous active Low Input pin used to stop the CPUCLK clocks in an active low state. All other Clocks including SDRAM clocks will continue to run while this function is enabled. The CPUCLKs will have a turn ON latency of at least 3 CPU clocks. This input pin is valid only when MODE=0 (Power Management Mode) PCI_STOP# This is a synchronous active Low Input pin used to stop the PCICLK clocks in an active low state. It will not affect PCICLK_F nor any other outputs. This input pin is valid only when MODE=0 (Power Management Mode) 4 ICS9148-32 Power Management Clock Enable Configuration CPU_STOP# PCI_STOP# PWR_DWN# CPUCLK PCICLK X 0 0 1 1 X 0 1 0 1 0 1 1 1 1 Low Low Low 100/66.6MHz 100/66.6MHz Low Low 33.3 MHz Low 33.3 MHz Other Clocks, REF, IOAPICs, 48 MHz 0 48 MHz 1 Stopped Running Running Running Running Crystal VCOs Off Running Running Running Running Off Running Running Running Running Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power up and power down operations using the PD# select pin will not cause clocks of a shorter or longer pulse than that of the running clock. The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging circuitry. Board routing and signal loading may have a large impact on the initial clock distortion also. ICS9148-32 Power Management Requirements SIGNAL SIGNAL STATE CPU_ STOP# 0 (Disabled) 2 1 (Enabled) 1 0 (Disabled) 2 1 (Enabled) 1 1 (Normal Operation) 3 0 (Power Down) 4 PCI_STOP# PD# Latency No. of rising edges of free running PCICLK 1 1 1 1 3ms 2max Notes. 1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device. 2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device. 3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device. 4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only. The REF and IOAPIC will be stopped independent of these. 5 ICS9148-32 Serial Bitmap Byte 3: Functionality & Frequency Select & Sperad Select Register Bit 7 6:4 3 2 10 Description 0: Center Spread ±0.255% 1: Down Spread 0 to -0.6% SEL 100/66.6# CPU Bits 5 4 or Bit 6 MHz 0 00 68.5 0 01 75 0 10 83.3 0 11 66.6 1 00 103 1 01 112 1 10 133.3 1 11 100 0 - Frequency is selected by hardware select SEL100166.6# 1 - Frequency is selected by 6:4 above (Reserved) 00 - Normal operation 01 - Test mode 10 - Spread sprectrum ON 11 - Tristate all outputs PWD 0 PCI MHz 34.25 37.5 41.6 33.3 34.3 37.3 44.43 33.3 000 0 00 Byte 4: Bit Pin# Pin Name PWD 7 6 5 4 - - - 3 35 CPUCLK3 1 2 36 CPUCLK2 1 1 39 CPUCLK1 1 0 40 CPUCLK0 1 Description Bit Value = 0 Bit Value = 1 (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) Disabled Enabled (low) Disabled Enabled (low) Disabled Enabled (low) (Disabled) Enabled (low) Notes: 1 = Enabled; 0 = Disabled, outputs held low Note: PWD = Power-Up Default 6 ICS9148-32 Byte 5: Bit Pin# Pin Name PWD 7 7 PCICLK_F 1 6 14 PCICLK6 1 5 16 PCICLK5 1 4 14 PCICLK4 1 3 13 PCICLK3 1 2 11 PCICLK2 1 1 6 PCICLK1 1 0 5 PCICLK0 1 Description Bit Value = 0 Bit Value = 1 Disabled Enabled (low) Disabled Enabled (low) Disabled Enabled (low) Disabled Enabled (low) Disabled Enabled (low) Disabled Enabled (low) Disabled Enabled (low) Disabled Enabled (low) Notes: 1 = Enabled; 0 = Disabled, outputs held low Byte 6: Bit Pin# Pin Name PWD 7 6 - - 0 0 5 44 IOAPIC1 1 4 45 IOAPIC1 0 3 - - 0 2 47 REF2 0 1 2 REF1 1 0 1 REF0 1 Description Bit Value = 0 Bit Value = 1 (Reserved) (Reserved) (Reserved) (Reserved) Disabled Enabled (low) Disabled Enabled (low) (Reserved) (Reserved) Disabled Enabled (low) (Disabled) Enabled (low) (Disabled) Enabled (low) Notes: 1 = Enabled; 0 = Disabled, outputs held low 7 ICS9148-32 CPU_STOP# Timing Diagram CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP# is synchronized by the ICS9148-32. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is 100 CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs. Notes: 1. All timing is referenced to the internal CPUCLK. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside the ICS9148-32. 3. All other clocks continue to run undisturbed. 4. PD# and PCI_STOP# are shown in a high (true) state. PCI_STOP# Timing Diagram PCI_STOP# is an asynchronous input to the ICS9148-32. It is used to turn off the PCICLK (0:6) clocks for low power operation. PCI_STOP# is synchronized by the ICS9148-32 internally. The minimum that the PCICLK (0:6) clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK (0:6) clocks. PCICLK (0:6) clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK (0:6) clock on latency cycles are only one rising PCICLK. Clock off latency is one PCICLK clock. Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9148-32. 3. All other clocks continue to run undisturbed. 4. PD# and CPU_STOP# are shown in a high (true) state. 8 ICS9148-32 PD# Timing Diagram The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal is synchronized internally by the ICS9148-32 prior to its control action of powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down state. When PD# is active (low) all clocks are driven to a low state and held prior to turning off the VCOs and the Crystal oscillator. The power on latency is guaranteed to be less than 3ms. The power down latency is less than three CPUCLK cycles. PCI_STOP# and CPU_STOP# are dont care signals during the power down operations. Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device). 2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9148. 3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated. 9 ICS9148-32 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Input Capacitance1 Transition Time1 Settling Time 1 Clk Stabilization 1 Skew1 1 SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP66 IDD3.3OP100 IDD3.3PD CONDITIONS MIN 2 VSS-0.3 VIN = VDD VIN = 0 V; Inputs with no pull-up resistors -5 VIN = 0 V; Inputs with pull-up resistors -200 CL = 0 pF; Select @ 66MHz CL = 0 pF; Select @ 100MHz CL = 0 pF; With input address to Vdd or GND Fi VDD = 3.3 V; CIN CINX Logic Inputs X1 & X2 pins Ttrans To 1st crossing of target Freq. TYP 0.1 2.0 -100 60 66 3 MAX UNITS VDD+0.3 V 0.8 V µA 5 µA µA 170 mA 170 µA 650 14.318 27 Ts From 1st crossing to 1% target Freq. TSTAB TAGP-PCI1 From VDD = 3.3 V to 1% target Freq. VT = 1.5 V; 36 MHz 5 45 pF pF 3 ms 5 1 ms 3.5 3 ms 4 ns Guaranteed by design, not 100% tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Operating Supply Current Power Down Supply Current 1 Skew 1 SYMBOL IDD2.5OP66 IDD2.5OP 100 IDD2.5PD tCPU-AGP tCPU-PCI2 CONDITIONS CL = 0 pF; Select @ 66.8 MHz CL = 0 pF; Select @ 100 MHz CL = 0 pF; With input address to Vdd or GND VT = 1.5 V; VTL = 1.25 V Guaranteed by design, not 100% tested in production. 10 MIN 0 1 TYP 16 23 MAX 72 100 UNITS mA mA 10 100 µA 0.5 2.6 1 4 ns ns ICS9148-32 Electrical Characteristics - CPUCLK TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current SYMBOL VOH2B VOL2B IOH2B IOL2B Rise Time tr2B1 VOL = 0.4 V, VOH = 2.0 V 1.25 1.6 ns Fall Time tf2B 1 VOH = 2.0 V, VOL = 0.4 V 1 1.6 ns Duty Cycle VT = 1.25 V 48 55 % Skew d t2B1 tsk2B1 VT = 1.25 V 30 175 ps Jitter, Cycle-to-cycle tjcyc-cyc2B1 VT = 1.25 V 150 250 ps VT = 1.25 V VT = 1.25 V 40 150 ps -250 140 +250 ps MIN 2 TYP 2.2 0.33 -41 37 MAX UNITS V 0.4 V -28 mA mA Jitter, One Sigma Jitter, Absolute 1 1 tj1s2B tjabs2B1 CONDITIONS IOH = -12.0 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V MIN 2 19 45 TYP 2.3 0.2 -41 37 MAX UNITS V 0.4 V -19 mA mA Guaranteed by design, not 100% tested in production. Electrical Characteristics - IOAPIC TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time 1 1 Duty Cycle 1 1 Skew Jitter, Absolute 1 1 CONDITIONS IOH = -18 mA IOL = 18 mA VOH = 1.7 V VOL = 0.7 V 29 Tr4B VOL = 0.4 V, VOH = 2.0 V 1.3 1.6 ns Tf4B VOH = 2.0 V, VOL = 0.4 V 1.1 1.6 ns Dt4B VT = 1.25 V 54 55 % VT = 1.25 V 60 250 ps Tj1s4B VT = 1.25 V 1 3 % Tjabs4B VT = 1.25 V 5 % tsk4B Jitter, One Sigma 1 SYMBOL VOH4B VOL4B IOH4B IOL4B 1 45 -5 Guaranteed by design, not 100% tested in production. 11 ICS9148-32 Electrical Characteristics - PCICLK TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time 1 1 Duty Cycle 1 1 Skew Jitter, One Sigma Jitter, Absolute 1 1 1 SYMBOL VOH1 VOL1 IOH1 IOL1 CONDITIONS IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V MIN 2.4 16 TYP 3.1 0.1 -62 57 MAX UNITS V 0.4 V -22 mA mA tr1 VOL = 0.4 V, VOH = 2.4 V 1.5 2 ns tf1 VOH = 2.4 V, VOL = 0.4 V 1.1 2 ns d t1 VT = 1.5 V 50 55 % tsk1 VT = 1.5 V 140 500 ps tj1s1 VT = 1.5 V 17 150 ps tjabs1 VT = 1.5 V -500 70 500 ps MIN 2.6 TYP 3.1 0.17 -44 42 45 Guaranteed by design, not 100% tested in production. Electrical Characteristics - REF TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time 1 1 Duty Cycle 1 Jitter, One Sigma Jitter, Absolute 1 1 1 SYMBOL VOH5 VOL5 IOH5 IOL5 CONDITIONS IOH = -12 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V 29 MAX UNITS V 0.4 V -22 mA mA tr5 VOL = 0.4 V, VOH = 2.4 V 1.4 2 ns tf5 VOH = 2.4 V, VOL = 0.4 V 1.1 2 ns d t5 VT = 1.5 V 54 57 % tj1s5 VT = 1.5 V 1 3 % tjabs5 VT = 1.5 V 3 5 % 47 Guaranteed by design, not 100% tested in production. 12 ICS9148-32 Electrical Characteristics - 48, 24 MHz TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time 1 1 Duty Cycle 1 Jitter, One Sigma Jitter, Absolute 1 1 1 SYMBOL VOH5 VOL5 IOH5 IOL5 CONDITIONS IOH = -12 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V MIN 2.6 16 TYP 3 0.14 -44 42 MAX UNITS V 0.4 V -22 mA mA tr5 VOL = 0.4 V, VOH = 2.4 V 1.2 4 ns tf5 VOH = 2.4 V, VOL = 0.4 V 1.2 4 ns d t5 VT = 1.5 V 52 55 % tj1s5 VT = 1.5 V 1 3 % tjabs5 VT = 1.5 V 3 5 % 45 Guaranteed by design, not 100% tested in production. 13 ICS9148-32 SSOP Package SYMBOL A A1 A2 B C D E e H h L N ∝ X COMMON DIMENSIONS MIN. NOM. MAX. .095 .101 .110 .008 .012 .016 .088 .090 .092 .008 .010 .0135 .005 .006 .0085 See Variations .292 .296 .299 0.025 BSC .400 .406 .410 .010 .013 .016 .024 .032 .040 See Variations 0° 5° 8° .085 .093 .100 VARIATIONS MIN. .620 .720 AC AD D NOM. .625 .725 N MAX. .630 .730 48 56 This table in inches Ordering Information ICS9148F-32 Example: ICS XXXX F - PPP Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 14 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.