Click to see this datasheet in Simplified Chinese! FIN324C 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays Features Description Ultra-Low Operating Power: ~4mA at 5.44MHz No External Timing Reference Needed Direct Support for Motorola -Style R/W Microcontroller Interface Direct Support for Intel -Style /WE, /RE Microcontroller Interface The FIN324C is a 24-bit serializer / deserializer with dual strobe inputs. The device can be configured as a master or slave device through the master/slave select pin (M/S). This allows for the same device to be used as either a serializer or deserializer, minimizing component types in the system. The dual strobe inputs allow implementation of dual-display systems with a single pair of µSerDes. The FIN324C can accommodate RGB, microcontroller, or SPI mode interfaces. Read and write transactions are supported when operating with a microcontroller interface for one or both displays. Unlike other SerDes solutions, no external timing reference is required for operation. Supports Dual-Display Implementations with RGB or Microcontroller Interface SPI Mode Support Single Device Operates as a Serializer or Deserializer ® ® 15MHz Maximum Strobe Frequency Available in BGA and MLP packages High ESD Protection: >15kV IEC 61000 Utilizes Fairchild’s Proprietary CTL Serial I/O Technology Wide Parallel Supply Voltage Range: 1.60 to 3.0V Low Power Core Operation: VDDS/A=2.5 to 3.0V Voltage Translation Capability Across Pair with No External Components Power-Saving Burst-Mode Operation The FIN324C is designed for ultra-low power operation. Reset (/RES) and standby (/STBY) signals put the device in an ultra-low power state. In standby mode, the outputs of the slave device maintain state, allowing the system to resume operation from the last-known state. The device utilizes Fairchild’s proprietary ultra-low power, low-EMI Current Transfer Logic™ (CTL) technology. The serial interface disables between transactions to minimize EMI at the serial interface and to conserve power. CMOS parallel output buffers have been implemented with slew rate control to adjust for capacitive loading and to minimize EMI. Related Application Notes Applications For additional Information, please visit: http://www.fairchildsemi.com/userdes Single or Dual 16/18-Bit RGB Cell Phone Displays AN-5058 µSerDes™ Frequently Asked Questions Single or Dual Mobile Display at QVGA or HVGA Resolution Single or Dual 16/18-Bit Cell Phone Displays with Microcontroller Interface © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 AN-5061 µSerDes™ Layout Guidelines AN-6047 FIN324C Reset and Standby www.fairchildsemi.com µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays July 2008 Order Number Operating Temperature Range FIN324CMLX -30 to 85°C 40-Terminal Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm Square Green Tape & Reel FIN324CGFX -30 to 85°C 42-Ball, Ultra Small Scale Ball Grid Array (USSBGA), JEDEC MO-195, 3.5 x 4.5mm Wide, 0.5mm Ball Pitch RoHS Tape & Reel Package Description Eco Status Packing Method For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. Typical Application Diagram LCD ‘A’ WE/PCLK WE/PCLK CKS Baseband / Microprocessor Data/Control 2 Data/Control FIN324 FIN324 DS 24 24 WE/PCLK LCD ‘B’ Supports optional seconda ry display Figure 1. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 Typical Application Diagram µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays Ordering Information www.fairchildsemi.com 2 Pin I/O Type # Pins Description of Signals M/S CMOS IN 1 Master/Slave Control Input: The master is tied to the processor. The slave is tied to the display(s). M/S=1 MASTER, M/S=0 SLAVE /RES CMOS IN 1 Reset and power-down signal /RES=0: Resets and powers down all circuitry /RES=1: Device enabled /STBY CMOS IN 1 Master standby signal /STBY=0: Device powered down /STBY=1: Device enabled SLEW CMOS IN 1 Slave output slew rate control SLEW=1: Fast edge rate SLEW=0: Slow edge rate PAR/SPI CMOS IN 1 Parallel / SPI display interface select PAR/SPI=1: Parallel Interface PAR/SPI=0: SPI Interface using STRB0 and WCLK0 CKSEL CMOS IN 1 Master clock source select input. CKSEL=1: STRB1 and WCLK1 Active CKSEL=0: STRB0 and WCLK0 Active DP[17:0] CMOS I/O 18 Parallel data I/O. I/O direction controlled by M/S pin and R/W internal state. DP[6] SPI mode SCLK signal pin when PAR/SPI=0 (Slave Only) DP[7] SPI mode SDAT signal pin when PAR/SPI=0(Slave Only) CNTL[5:0] CMOS I/O 6 Parallel data I/O. I/O direction controlled by M/S pin M/S=1: Inputs M/S=0: Outputs Read / Write input control or output signal. M/S=1: Input M/S=0: Output R/W CMOS I/O 1 STRB0 STRB1 CMOS IN 2 Word latch or pixel clock input. WCLK0 WCLK1 CMOS OUT 2 Word latch or pixel clock output. Functional operation: R/W=1: Read R/W=0: Write SCLK SDAT /CS CMOS I/O 2 SPI mode signal pins. The master SCLK input is shared with CNTL[5] when M/S=1 and PARI/SPI=0. The master SDAT input is shared with CNTL[4] when M/S=1 and PARI/SPI=0. The master /CS input is shared with STRB0 when M/S=1 and PAR/SPI=0. The slave SCLK output is shared with DP[6] and CNTL[5] when M/S=0 and PAR/SPI=0. The slave SDAT output is shared with DP[7] and CNTL[4] when M/S=0 and PAR/SPI=0. The slave /CS output is shared with WCLK0 when M/S=0 and PAR/SPI=0. CKS+ CKS- Differential Serial I/O 2 Serial clock differential signal(1) DS+ DS- Differential Serial I/O 2 Serial data differential signal(1) VDDP Supply 1 Power supply for parallel I/O and internal circuitry. VDDS Supply 1 Power supply for serial I/O. VDDA Supply 1 Power supply for internal bit clock generator. GND Supply 1-3 Ground Pins: BGA - C1 and D2; E3 is for supplier use only and must be tied to ground. MLP - center pad; Pin 12 is for supplier use only and must be tied to ground. µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays Pin Definitions Note: 1. Serial I/O signals are swapped on the slave so system traces do not have to cross between master and slave. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 www.fairchildsemi.com 3 24 DP[11] Figure 2. 31 DP[17] 32 WCLK1 33 WCLK0 35 CNTL[1] 36 CNTL[2] 37 CNTL[3] 38 CNTL[4] or SDAT 34 CNTL[0] 25 VDDP 24 DP[11] 8 23 DP[10] 9 22 DP[9] 10 21 DP[8] SLEW GND DP[0] DP[1] DP[2] DP[3] DP[4] DP[5] SCLK or DP[6] SDAT or DP[7] 11 20 19 18 26 DP[12] Ground Pad 7 /STBY GND DP[0] DP[1] DP[2] DP[3] DP[4] DP[5] DP[6] DP[7] 17 21 DP[8] 16 10 15 22 DP[9] 14 9 13 23 DP[10] 12 8 6 20 Ground Pad 7 27 DP[13] M/S=0 19 25 VDDP 6 5 18 26 DP[12] M/S=1 28 DP[14] Slave 4 17 5 27 DP[13] 29 DP[15] 3 16 Master 4 30 DP[16] 2 15 28 DP[14] 1 14 3 VDDP DS+ DSVDDS VDDA CKSCKS+ /RES PAR/SPI M/S 13 29 DP[15] 12 30 DP[16] 2 39 CNTL[5] or SCLK 40 R/W 31 DP[17] 32 STRB1 33 STRB0 34 CNTL[0] 35 CNTL[1] 36 CNTL[2] 37 CNTL[3] 38 CNTL[4] or SDAT 39 CNTL[5] or SCLK 40 R/W 1 11 CKSEL CKS+ CKSVDDS VDDA DSDS+ /RES PAR/SPI M/S MLP Pin Assignments (40 Pins, 6x6mm, .5mm Pitch, Top View) 42 FBGA Package 3.5mm x 4.5mm (.5mm Pitch) (Top View) 1 2 3 4 5 6 A B C D E F G Master (M/S=1) 1 2 CNTL[4] or SDAT CNTL[5] or SCLK Slave (M/S=0) 3 4 5 6 1 CNTL[2] STROB0 DP[17] DP[16] A R/W CNTL[3] STROB1 DP[15] DP[14] B VDDP 2 CNTL[4] or SDAT CNTL[5] or SCLK 3 4 5 6 CNTL[2] WCLK0 DP[17] DP[16] CNTL[3] WCLK1 DP[15] DP[14] A R/W B CKSEL C GND VDDP CNTL[1] CNTL[0] DP[13] DP[12] C GND VDDP CNTL[1] CNTL[0] DP[13] DP[12] D CKS+ GND M/S DP[11] DP[9] DP[10] D DS+ GND M/S DP[11] DP[9] DP[10] E CKS- VDDS GND DP[2] DP[7] DP[8] E DS- VDDS GND DP[2] DP[7] or SDAT DP[8] F DS- VDDA PAR/SPI DP[0] DP[4] DP[6] F CKS- VDDA PAR/SPI DP[0] DP[4] DP[6] or SCLK G DS+ /RES /STBY DP[1] DP[3] DP[5] G CKS+ /RES SLEW DP[1] DP[3] DP[5] Figure 3. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays Pin Assignments BGA Pin Assignments www.fairchildsemi.com 4 (M/S) Master / Slave Selection: A given device can be configured as a master or slave device based on the state of the M/S pin. (/RES, /STBY) Reset and Standby Mode Functionality: Reset and standby mode functionality is determined by the state of the /RES and /STBY signals for the master device and the /RES and internal standby-detect signal for the slave device. The /RES control signal has a filter that rejects spurious pulses on /RES. Table 1. Master/Slave M/S Configuration 0 Slave Mode 1 Master Mode Table 4. Reset and Standby Modes /RES (PAR/SPI) SPI Mode Selection: The PAR/SPI signal configures STRB0(WCLK0) for SPI mode write operation. STRB1(WCLK1) always operates in parallel mode. Control signals CNTL[5:0] all pass in SPI mode. In SPI mode, the SCLK signal is used to strobe the serializer. SPI mode supports SPI writes only. M/S=1 MASTER M/S=0 SLAVE 0 SPI Mode SDAT=CNTL[4] SCLK=CNTL[5] /CS=STRB0 SPI Mode SDAT=DP[7] & CNTL[4] SCLK=DP[6] & CNTL[5] /CS=WCLK0 Parallel Mode Parallel Mode 1 (2) Master Slave 0 X Reset Mode Reset Mode 1 0 Standby Mode Standby (2) Mode 1 1 Operating Mode Operating Mode Note: 2. The slave device is put into standby mode through control signals sent from the master device. Table 2. Channel 0 PAR/SPI Configuration PAR /SPI /STBY Table 5. Reset and Standby Mode States Master Reset / Standby Slave Reset Slave Standby DP[17:0] Disabled Low Last data CNTL[5:0] Disabled Low Last data STRB[0:1] (WCLK[0:1]) Disabled High High Pin (CKSEL) Strobe Selection Signal: The CKSEL signal exists only on the master device and determines which strobe signal is active. The active strobe signal is selected by CKSEL and PAR/SPI inputs. (SLEW) Slew Control: The slew control operates only when in slave mode. This signal changes the edge rate of the DP[17:0], CNTL[5:0], R/W, WCLK1, and WCLK0 signals to optimize edge rate for the load being driven. Master read mode outputs have “slow” edge rates. See the AC Deserializer Specifications table for “slow” and “fast” edge rates. Table 3. PAR/SPI PAR /SPI CKSEL Master Strobe Source Slave Strobe Source 0 0 CNTL[5] DP[6] & CNTL[5] 0 1 STRB1 WCLK1 /STBY (SLEW) Slave M/S=0 1 0 STRB0 WCLK0 0 “Slow” WCLK1 1 “Fast” 1 1 STRB1 © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 Table 6. Slew Rate Control µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays System Control Pins www.fairchildsemi.com 5 System Control Signals Parallel I/O Signals The system control signals consist of M/S, /RES, /STBY(SLEW), PAR/SPI, and CKSEL. For connectivity flexibility, these signals are over-voltage tolerant to the maximum supply voltage connected to the device. This allows these signals to be tied HIGH to either a VDDS or VDDP supply without static current consumption. These signals are all CMOS inputs and should never be allowed to float. The parallel data port signals consist of the DP[17:0], CNTL[5:0], R/W, and STRB1(0)(WCLK1(0)) signals. These signals have built-in voltage translation, allowing the signals of the master and slave to be connected to different VDDP supply voltages. Serial I/O Signals CTL I/O Technology Serial I/O Orientation Logic The serial I/O is implemented using Fairchild’s proprietary differential CTL I/O technology. During data transfers, the serial I/O are powered up to a normal operating mode around .5V. Upon completion of a data transfer, the serial I/O goes to a lower power mode around VDDS. The serial I/O signal traces should not cross between the master and the slave. The pin locations have been designed to eliminate the need to cross traces. See Table 7, Figure 4 and Figure 5. Table 7. Serial Pin Orientation Master (M/S=1) (Pad/Pin #) Slave (M/S=0) (Pad/Pin #) Package CKS+ CKS- DS- DS+ CKS+ CKS- DS- DS+ MLP 2 3 6 7 7 6 3 2 BGA D1 E1 F1 G1 G1 F1 E1 D1 (CKS-) <CKS+> 1 2 G 25 29 CKS+ 2 7 (CKS+) 24 30 CKSEL(H) 1 8 /RES 3 4 5 23 9 PAR/SPI 22 10 M/S 21 6 11 BGA Master A Figure 4. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 BGA Pair Figure 5. MLP Pair 29 28 20 CKS+ 31 6 32 3 33 26 CKS- 34 VDD A 28 19 D F 35 27 5 36 VDD S 4 37 4 VDD S 38 5 27 39 (DS-) 40 3 18 <CKS-> 11 6 VDDA 17 CKS- 12 DS- 26 16 E BGA Slave 13 25 30 MLP Slave 15 E 14 (DS+) 14 <DS-> 15 CKSEL(H) 2 13 DS- 16 1 7 12 F 17 8 DS+ 24 40 <DS+> 18 9 /RES 39 DS+ 19 10 38 G B M/S PAR/SPI MLP Master 22 23 D C 21 37 1 36 2 35 3 34 4 33 5 31 6 32 B C 20 A µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays CMOS I/O Signals www.fairchildsemi.com 6 Read transactions have two phases: The Read-Control Phase, where CNTL[5:0], R/W, CKSEL are transmitted to the deserializer; and the Read-Data Phase, where the DP[17:0] signals of the slave are read and transmitted back to the master device. The slave device generates its own strobe signal for latching in the data. Slave data must be valid prior to the WCLKn signal going HIGH. Slave Deserializer Operation (Read-Control Phase) 1. Captures data from serial transfer. 2. Internally decodes that this is a READ transaction. 3. Outputs control signals and prepares DP pins to accept data. 4. Outputs falling edge of WCLK pulse. Slave Serializer Read Operation (Read-Data Phase) The slave serializer is enabled on the tail end of the Read-Control Phase of operation. The operation of the serializer is identical to the master serialization except that the strobe signal is generated internally and only the data bits DP[17:0] are captured. Master Serializer Operation (Read Control Phase) When the R/W signal is asserted HIGH and the STROBE signal transitions LOW, the Read-Control Phase of the read cycle is initiated. The R/W signal must not transition until the READ cycle completes. For a READ transaction, only eight control signals are captured. The 18 DP bits are ignored during the READ operation. The following sequence must occur for data to be serialized properly: 1. Display device outputs data onto DP bus on falling edge of WCLK. 2. Captures parallel data on generated rising edge of WCLK signal. 3. Serializes data stream. 1. CPU selects input strobe source (CKSEL=0 or 1). 2. CPU sends signals (R/W=1, CKSEL, CNTL[5:0]). 3. CPU sends LOW STROBE signal. Master Deserializer Read Operation (Read-Data Phase): 1. Receives valid serial stream. 2. Outputs data DP[17:0]. 3. CPU asserts rising edge of strobe signal to capture data. SPI WRITE transaction On the rising edge of SCLK, all eight control signals (CNTL[5:0], R/W, CKSEL) are captured and serialized. The data signals are not sent. The deserializer captures the serial stream and outputs it to the parallel port. SPI mode is activated by asserting the PAR/SPI signal low on both the master and slave device. A SPI write is only performed when CKSEL=0. During a SPI transaction, SCLK must be connected to CNTL[5] and is the strobe source for serialization. SDAT is on CNTL[4] and all of the remaining control signals and STRB0 are serialized. STRB0 should be connected to the SPI mode chip select. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 As shown in Table 2, SDAT and SCLK are output on multiple pins. The DP[7] and DP[6] connections can be used for displays with dual-mode operation and the data pins are multiplexed with the SPI signals. CNTL[5] and CNTL[4] signals can be used when the signals are not multiplexed. µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays Master/Slave READ Transactions www.fairchildsemi.com 7 Master Baseband Processor VDDP1 C2 Slave VDDS/A VDDP2 E2 C2 F2 /CS PCLK B4 D4:G6 R,G,B[5:0] Hsync_D/C Vsync SD OE RESET C4 C3 A3 B3 A2 B2 A1 VDDP1 GPIO D3 F3 G3 /STBY G2 /RES CKSEL B1 Figure 6. WCLK0 A4 WCLK1 B4 STRB0 STRB1 DP[17:0] CNTL[0] CNTL[1] D1 CNTL[2] CKS+ E1 CKSCNTL[3] CNTL[4] G1 DS+ F1 CNTL[5] DSR/W M/S PAR/SPI /STBY /RES CKSEL Notes: 1. 2. 3. 4. 5. G1 F1 D1 E1 E3 D2 C1 GND E3 GND D2 GND C1 DP[17:0] CNTL[0] CNTL[1] CKS+ CNTL[2] CKS- CNTL[3] CNTL[4] DS+ CNTL[5] DSR/W M/S PAR/SPI GND SLEW GND /RES GND VDDP VDDP1 C2 A4 /WE PCLK B4 D4:G6 R,G,B[5:0] Hsync_ADDR Vsync SD OE RESET /CS C4 C3 A3 B3 A2 B2 A1 VDDP1 D3 F3 G3 G2 B1 Notes: 1. 2. 3. 4. 5. Figure 7. C3 A3 B3 OE A2 B2 NC A1 NC D3 F3 VDDP2 G3 Edge Rate Control Option SLEW must be connected to VDDP or GND for low power. G2 B1 Slave VDDS/A VDDP2 VDDS/A E2 C2 E2 F2 WCLK0 A4 WCLK1 B4 STRB0 STRB1 DP[17:0] CNTL[0] CNTL[1] D1 CNTL[2] CKS+ E1 CKSCNTL[3] CNTL[4] G1 DS+ F1 CNTL[5] DSR/W M/S PAR/SPI /STBY /RES CKSEL Sub-Display Data [7:0] ADDR /WE RESET P/S /CS F2 VDDP VDDS/A VDDP VDDS/A /RES CKSEL C4 Write-only Interface. Unused slave output pin must be NC (No Connection). /CS used to strobe sub-display data. PCLK used for RGB mode. Pin numbers for BGA package. Master /STBY Main Display PCLK R,G,B [5:0] Hsync Vsync SD D4:G6 Dual Display with Parallel RGB Main Display and 6800-Style Microcontroller Sub-Display Baseband Processor GPIO F2 VDDP VDDS/A VDDP VDDS/A A4 Sub-Display Data [7:0] D/C /CS RESET P/S VDDS/A E2 E3 GND D2 GND C1 GND G1 F1 D1 E1 E3 D2 C1 DP[17:0] CNTL[0] CNTL[1] CKS+ CNTL[2] CKS- CNTL[3] CNTL[4] DS+ CNTL[5] DSR/W M/S PAR/SPI GND SLEW GND /RES GND VDDP Main Display PCLK R,G,B [5:0] Hsync Vsync SD D4:G6 C4 C3 A3 B3 OE A2 B2 A1 NC D3 F3 G3 G2 B1 VDDP2 Edge Rate Control Option SLEW must be connected to VDDP or GND for low power. Write-only Interface. Unused slave output pin must be NC (No Connection). /WE used to strobe sub-display data. PCLK used for RGB mode. Pin numbers for BGA package. µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays Application Diagrams Dual Display with Parallel RGB Main Display and x86-Style Microcontroller Sub-Display © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 www.fairchildsemi.com 8 µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays Application Diagrams (Continued) Master Baseband Processor VDDP1 C2 Slave VDDS/A VDDP2 VDDS/A E2 C2 E2 F6 SCLK DP[6] F2 VDDP VDDS/A VDDP VDDS/A A4 /CS PCLK D4:G6 R,G,B[5:0] Hsync Vsync SD D/C SDAT SCLK DP[17:0] CNTL[0] CNTL[1] D1 CNTL[2] CKS+ E1 CKSCNTL[3] CNTL[4] DS+ G1 CNTL[5] DS- F1 R/W M/S C4 C3 A3 B3 A2 B2 A1 GPIO VDDP1 D3 F3 PAR/SPI /STBY G3 /STBY G2 /RES CKSEL WCLK0 A4 WCLK1 B4 STRB0 STRB1 B4 E3 GND D2 GND C1 GND /RES CKSEL B1 E5 SDAT DP[7] F2 DP[17:0] CNTL[0] CNTL[1] G1 CKS+ CNTL[2] F1 CKS- CNTL[3] CNTL[4] D1 DS+ E1 DSCNTL[5] R/W M/S PAR/SPI E3 GND SLEW D2 GND /RES C1 GND VDDP Sub-Display SCLK SDAT /CS D/C RESET P/S Main Display PCLK R,G,B [5:0] Hsync Vsync SD D4:G6 C4 C3 A3 B3 A2 NC B2 NC A1 NC D3 F3 VDDP2 G3 Edge Rate Control Option SLEW must be connected to VDDP or GND for low power. G2 B1 Module 1 Notes: 1. 2. 3. 4. 5. 6. Figure 8. Write-only interface (R/W hardwired LOW). SPI sub-display interface PAR/SPI=LOW for both . master and slave. SCLK connected to CNTL[5]; SDAT connected to CNTL[4]. Shared data pin SDAT; SCLK connections on sub-display. Unused slave output pin must be NC (No Connection). Pin numbers for BGA package. Dual Display with RGB Main Display and SPI Sub-Display Interface Master Baseband Processor VDDP1 C2 Slave VDDS/A VDDP2 E2 C2 F2 /CS0 /CS1 DATA[17:0] D/C RESET 0 RESET 1 B4 D4:G6 C4 C3 A3 B3 A2 B2 R/W A1 VDDP1 D3 GPIO /STBY /RES CKSEL F3 G3 G2 B1 WCLK0 A4 WCLK1 B4 STRB0 STRB1 DP[17:0] CNTL[0] CNTL[1] D1 CNTL[2] CKS+ E1 CKSCNTL[3] CNTL[4] G1 DS+ F1 CNTL[5] DSR/W M/S PAR/SPI /STBY /RES CKSEL F2 VDDP VDDS/A VDDP VDDS/A A4 Sub-Display DATA [17:0] D/C /CS0 RESET 0 P/S VDDS/A E2 GND E3 GND D2 GND C1 G1 F1 D1 E1 E3 D2 C1 DP[17:0] CNTL[0] CNTL[1] CKS+ CNTL[2] CKS- CNTL[3] CNTL[4] DS+ CNTL[5] DSR/W M/S PAR/SPI SLEW GND GND /RES GND VDDP Main Display /CS1 DATA[17:0] D/C D4:G6 C4 C3 A3 B3 A2 B2 RESET 1 R/W NC NC NC A1 D3 F3 G3 G2 B1 VDDP2 Edge Rate Control Option SLEW must be connected to VDDP or GND for low power. Module 1 Notes: 1. 2. 3. 4. Figure 9. R/W interface. R/W signal connected to baseband . microprocessor. Unused slave output pin must be NC (No Connection). PAR/SPI connected HIGH to indicate parallel operation. . Pin numbers for BGA package. R/W Dual Display with Parallel Microcontroller Main Display and Sub-Display © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 www.fairchildsemi.com 9 Master Baseband Processor VDDP1 C2 Slave VDDS/A VDDP2 VDDS/A E2 C2 E2 F2 VDDP VDDS/A VDDP VDDS/A A4 /RE /WE DATA[17:0] ADDR B4 D4:G6 C4 C3 A3 /CS0 /CS1 B3 A2 B2 A1 VDDP1 D3 GPIO F3 G3 /STBY G2 /RES CKSEL0 CKSEL1 B1 WCLK0 A4 WCLK1 B4 STRB0 STRB1 DP[17:0] CNTL[0] CNTL[1] D1 CNTL[2] CKS+ E1 CKSCNTL[3] CNTL[4] DS+ G1 CNTL[5] DS- F1 R/W M/S PAR/SPI /STBY /RES CKSEL Sub-Display /RE /WE DATA[7:0] ADDR /CS0 Main Display /RE /WE DATA[17:0] ADDR F2 E3 GND D2 GND C1 GND G1 F1 D1 E1 E3 D2 C1 DP[17:0] CNTL[0] CNTL[1] CKS+ CNTL[2] CKS- CNTL[3] CNTL[4] DS+ CNTL[5] DSR/W M/S PAR/SPI GND SLEW GND /RES GND VDDP D4:G6 C4 C3 A3 B3 /CS1 A2 NC B2 NC A1 D3 F3 G3 G2 B1 VDDP2 Edge Rate Control Option SLEW must be connected to VDDP or GND for low power. Module 1 Notes: 1. 2. 3. 4. 5. Dual display R/W Intel® interface. Unused slave output pin must be NC (No Connection). GPIO signal used to select READ or WRITE functionality. Connected to CKSEL and R/W. . selects. Displays selected via the chip Pin numbers for BGA package. Figure 10. Dual R/W x86-Style Microcontroller Display Interface Additional Application Information Flex Cabling: The serial I/O information is transmitted at a high serial rate. Care must be taken implementing this serial I/O flex cable. The following best practices should be used when developing the flex cabling or Flex PCB. Keep all four differential Serial Wires the same length. Use only one ground plane or wire over the differential serial wires. Do not run ground over top and bottom. Do not allow noisy signals over or near differential serial wires. Example: No CMOS traces over differential serial wires. Design goal of 100-ohms differential characteristic impedance. Do not place test points on differential serial wires. Use differential serial wires a minimum of 2cm away from the antenna. Visit Fairchild’s website at http://www.fairchildsemi.com/products/interface/userdes.html, contact your sales rep, or contact Fairchild directly at [email protected] for applications notes or flex guidelines. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays Application Diagrams (Continued) www.fairchildsemi.com 10 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit V VDD Supply Voltage -0.5 +3.6 All Input/Output Voltage -0.5 VDDP+0.5 V TSTG Storage Temperature Range -65 +150 °C Maximum Junction Temperature +150 °C Lead Temperature (Soldering, 4 Seconds) TJ TL ESD +260 °C IEC 61000 Board Level 15 kV Human Body Model, JESD22-A114, Serial I/0, /RES, PAR/SPI Pins 14 kV Human Body Model, JESD22-A114, All Other Pins 7.5 kV Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol (3) VDDA, VDDS VDDP TA Parameter Min. Max. Unit Supply Voltage 2.5 3.0 V Supply Voltage 1.6 VDDA/S V Operating Temperature -30 +85 °C Note: 3. VDDA and VDDS supplies must be hardwired together to the same power supply. VDDP must be less than or equal to VDDA/VDDS. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays Absolute Maximum Ratings www.fairchildsemi.com 11 Values valid for over supply voltage and operating temperature ranges unless otherwise specified. Symbol Parameter Test Conditions Min. Typ. Max. Unit DC Parallel I/O and Serial Characteristics VIH Input High Voltage 0.7 x VDDP VDDP V VIL Input Low Voltage GND 0.3 x VDDP V VOH Output High Voltage VOL Output Low Voltage IIN VGO Z SLEW=0 IOH=-250µA V 0.8 x VDDP SLEW=1 IOH=-1mA SLEW=0 IOL=250µA SLEW=1 IOL=1mA Input Current -5 Serial Input Voltage Ground Offset Slave Relative to Master Serial Transmission Line Impedance 0.2 x VDDP V 5 µA 0 70 100 V 120 Ω Power Characteristics 5.44MHz 4 12.00MHz 7 15.00MHz 8 5.44MHz 5 12.00MHz 8 15.00MHz 10 Burst Standby Current of Master VDDA/S=2.75V, VDDP=1.8V, M/S=1, /STBY=1, /RST=1, No STROBE Signal, CL=0pF 1.3 mA Burst Standby Current of Slave VDDA/S=2.75V, VDDP=1.8V, M/S=0, /STBY=1, /RST=1, No STROBE Signal, CL=0pF 1.8 mA ISTBY Standby Current Serializer or Deserializer VDDS/A=VDDP=3.0V, /STBY=0, /RST=1 10 µA IRES Reset Current Serializer or Deserializer VDDS/A=VDDP=3.0V, /RST=0 10 µA 0 8 MHz 0 15 MHz 0 2 MHz 40 ns Dynamic Current of Master Device VDDA/S=2.75V, M/S=1, VDDP=1.8V, /STBY=1, /RES=1 Dynamic Current of Slave Device VDDA/S=2.75V M/S=0 VDDP=1.8V, /STBY=1, /RES=1, CL=0pF IBRST_M IBRST_S IDYN_SER IDYN_DES mA mA AC Operating Characteristics fWSTRB0 Write Strobe Frequency CKSEL=0 STRB0 fWSTRB1 Write Strobe Frequency CKSEL=1 STRB1 fRSTRB Read Strobe Frequency tR, tF Input Edge Rates (5) tS1 Write Mode Setup Time DP before STRBn ↑, Figure 11 5 ns tH1 Write Mode Hold Time DP after STRBn ↑, Figure 11 15 ns tS2 READ Mode Setup Time R/W, CNTL before STRBn ↓ Figure 12 0 ns tH2 READ Mode Hold Time R/W, CNTL after STRBn ↓ Figure 12 16 ns tS-STRB CKSEL to STRBn Setup Time CKSEL before active edge (4) STRBn , CKSEL before SPI /CS, SPI /CS before CKSEL Figure 13, Figure 14 50 ns © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays Electrical Specifications www.fairchildsemi.com 12 Parameter Test Conditions Min. Typ. Max. Unit AC Deserializer Specifications SLEW=0, CL=5pF 20% to 80% tCS CNTL[5:0],R/W to Falling Edge of WCLKn (5) SLEW=1, CL=5pF 20% to 80% (5) SLEW=0, CL=5pF 20% to 80% (5) SLEW=1, CL=5pF 20% to 80% (5) (5) M/S=0 , CL=5pF 50% to 50% Figure 15 8 17 8 22 10 17 (5) 0 4 ns tPDV-WR0 DP, CNTL to WCLK0 ↑ PAR/SPI=1 , Figure 15 (5) 50 60 ns tPDV-WR1 DP, CNTL to WCLK1 ↑ (5) PAR/SPI=1 , Figure 15 18 24 ns (5) 200 224 ns 40 60 ns 50 56 ns 18 20 ns 200 220 ns 40 56 ns 147 ns 111 ns tPDV-RD tPDV-SPI CNTL to WCLKn ↑ Data, CNTL to SCLK ↑ PAR/SPI=1 , Figure 17 (5) PAR/SPI=0 , Figure 16 (5,7) tPWL-WR0 WCLK0 Pulse Width Low; Write Mode M/S=0, R/W=0, PAR/SPI=1 Figure 15 tPWL-WR1 WCLK1 Pulse Width Low; Write Mode M/S=0, R/W=0, PAR/SPI=1 Figure 15 tPWL-RD Pulse Width Low of WCLK; Read Mode M/S=0, R/W=1, PAR/SPI=1 Figure 17 tPWL-SPI Pulse Width Low of WCLK; SPI Mode M/S=0, R/W=0, PAR/SPI=0 Figure 16 (5,7) (5,7) (5,7) AC Data Latencies tPD-WR0 Write Latency WRITE Mode, CKSEL=0 Figure 15 (8,9,10) (8,9,10) tPD-WR1 Write Latency WRITE Mode, CKSEL=1 Figure 15 Total Read Latency READ Mode Figure 17 (8,10,11) tPD-RD Read Control Latency READ Mode Figure 17 (8,10,12) tPD-RDC Read Data Latency READ Mode Figure 17 (8,10,13) tPD-RDD tPD-SPI SPI Write Latency 340 SPI-WRITE Mode Figure 16 480 ns 276 ns 84 ns 115 ns (8,10,14) AC Oscillator Specifications fOSC Serial Operating Frequency 275 310 MHz tOSC-STBY Oscillator Stabilization Time After Standby VDDA=VDDS=2.75V /RES=1, /STBY ↑ Transition 240 15 30 µs tOSC-RES Oscillator Stabilization Time After Reset VDDA=VDDS=2.75V /STBY=1, /RES ↑ Transition 30 50 µs AC Reset and Standby Timing tVDD-OFF Power Down Relative to (15) /RES tSTRB-RES /RES after last STRBn ↑ tSTRB-STBY tRES-OFF Figure 19 M/S=1, /STBY=1, R/W=0 Figure 19 µs 0 ns 200 ns (16) (17) Standby time after last strobe M/S=1, /STBY=1 Figure 19 Master/Slave Reset Disable Time M/S=1 /STBY=1, /RES=↓ Figure 19 © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 20 µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays Symbol 15 20 µs www.fairchildsemi.com 13 tVDD-SKEW Parameter Test Conditions Allowed Skew between VDDP Figure 18 (18) and VDDA/S Min. -∞ (19) Typ. Max. Unit +∞ ms tVDD-RES Minimum Reset Low Time After VDD Stable M/S=0, /RES=↑ Figure 18 20 µs tRES-STBY /STBY Wait Time After /RES ↑ M/S=1 /RES=1, /STBY= ↑ Figure 18 20 µs /STBY to Active Edge of Strobe M/S=0 /RES=1 Figure 18 30 µs tDVALID (20) Notes: 4. Active edge of strobe is the rising edge for a write transaction and the falling edge for a read transaction. 5. Characterized, but not production tested. 6. Indirectly tested through serial clock frequency and serial data bit tests. 7. Pulse width low WCLKn measurements are measured at 30% of VDDP. Measurements apply when SLEW=0 or SLEW=1. 8. Minimum times occur with maximum oscillator frequency. Maximum times occur with minimum oscillator frequency. 9. Write latency is the sum of the delay through the master serializer and slave deserializer, plus the flight time across the flex cable and I/O propagation delays. 10. Assumes propagation delay across the flex cable and through the I/Os of 20ns. 11. Total read latency tPD-RD is the sum of the Read-Control Phase latency (tPD-RDC) and the Read-Data Phase latency (tPD-RDD). tPD-RD=tPD-RDC+ tPD-RDD. 12. Read-Control latency is the sum of the delay through the master serializer and slave deserializer, plus flex cable flight times and I/O propagation delays. 13. Read Data latency is the sum of the delay through the slave serializer and master deserializer, plus flex cable flight times and I/O propagation delays. 14. SPI-Write latency is the sum of the delay through the master serializer and slave deserializer, plus the flight time across the flex cable and I/O propagation delays. 15. Timing allows the device to completely reset prior to powering down. 16. Internal reset filter allows assertion prior to completion of read or write date transfer. 17. Timing ensures that last write transaction is complete prior to going into standby. 18. VDDA/S must power up together. VDDP may power-up relative to VDDA/S in any order without static power being consumed. Guaranteed by characterization. 19. /RES signal should be held low for minimum time specified after supplies go HIGH. It is recommended that /RES be held low during the power supply ramp. 20. STRBn must be held off until internal oscillator has stabilized. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays Symbol www.fairchildsemi.com 14 Setup Time Setup Time tS1 STROBE tS2 STRBn DP,CNTL Data Hold Time CNTL,R/W Control Hold Time tH1 STROBE tH2 STRBn DP,CNTL Data CNTL,R/W Setup: CKSEL=0 or 1, R/W=0 Figure 11. Setup: CKSEL=0 or 1, R/W=1 Master Write Setup and Hold Time tS-STRB tS-STRB Control Figure 12. tS-STRB Master Read Setup and Hold Time tS-STRB tS-STRB STRB0 STRB0 STRB1 STRB1 SPI /CS CKSEL CKSEL DP,CNTL Data CNTL Setup: CKSEL=0 or 1, R/W=0 Figure 13. Data Setup: CKSEL=0 or 1, R/W=1 CKSEL Write Setup Time Figure 14. CKSEL Read Setup Time Master SCLK STRBn CKS CKS DS DS tPD-WR tPD-SPI DP CNTL WCLKn Slave SDAT, CNTL, /CS tPWLn tCS Slave SCLK tPDV Setup: CKSEL=0, R/W=0, PAR/SPI=0, /CS=0 Slave Write Mode Timing © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 tPWL-SPI tPDV-SPI Setup: CKSEL=0 or 1, R/W=0, PAR/SPI=1 Figure 15. tCS Figure 16. µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays Typical Performance Characteristics Slave SPI Mode Timing www.fairchildsemi.com 15 tPD-RD STRBn CKS DS t PD-RD C tPD-RD D CNTLSLV tPW L-RD n tCSn WCLKn] t PDV-RD n DPSLV DPMSTR Setup: CKSEL=0 or 1, R/W=1, PAR/SPI=1 Figure 17. VDDP VDDS/A Slave Read Mode Timing tVDD-SKEW tVDD-RES /RES /STBY tRES-STBY Standby Mode Dynamic Mode Valid Data DP[23:0],R/W STRBn tDVALID CKS DS OFF Deserializer Figure 18. ON Power-Up Timing VDDP VDDS/A /RES /STBY tVDDOFF tSTRB-RES Dynamic Mode Standby Mode tSTRB-STBY STROBE tRES-OFF Deserializer ON Figure 19. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 OFF µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays Typical Performance Characteristics (Continued) Power-Down Timing www.fairchildsemi.com 16 0.15 C 6.00 B A (0.80) 6.00 PIN #1 IDENT 6.38MIN 4.37MAX 0.15 C 4.77MIN 0.80 MAX 0.10 C (0.20) 0.08 C 0.05 0.00 0.20MIN X4 C 0.28 MAX SEATING PLANE X40 4.20 4.00 0.50TYP E 0.50 0.30 0.50 4.20 4.00 (DATUM B) (DATUM A) PIN #1 ID 0.18-0.30 0.10 0.05 0.50 C A B C NOTES: A. CONFORMS TO JEDEC REGISTRATION MO-220, VARIATION WJJD-2 WITH EXCEPTION THAT THIS IS A SAWN VERSION.. B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994. D. LAND PATTERN PER IPC SM-782. E. WIDTH REDUCED TO AVOID SOLDER BRIDGING. F. DIMENSIONS ARE NOT INCLUSIVE OF BURRS, MOLD FLASH, OR TIE BAR PROTRUSIONS. G. DRAWING FILENAME: MKT-MLP40Arev3. Figure 20. 40-Lead, Molded Leadless Package (MLP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays Physical Dimensions Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 www.fairchildsemi.com 17 Figure 21. 42-Ball, Ball Grid Array (BGA) Package Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays Physical Dimensions (Continued) Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 www.fairchildsemi.com 18 µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays 19 www.fairchildsemi.com © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2