MCNIX MX25L12845EZNI10G 128m-bit [x 1/x 2/x 4] cmos mxsmioí (serial multi i/o) flash memory Datasheet

MX25L12845E
MX25L12845E
HIGH PERFORMANCE
SERIAL FLASH SPECIFICATION
P/N: PM1428
REV. 1.9, SEP. 06, 2013
1
MX25L12845E
Contents
FEATURES................................................................................................................................................................... 5
GENERAL DESCRIPTION.......................................................................................................................................... 7
Table 1. Additional Features ............................................................................................................................... 7
PIN CONFIGURATION................................................................................................................................................. 8
PIN DESCRIPTION....................................................................................................................................................... 8
BLOCK DIAGRAM........................................................................................................................................................ 9
DATA PROTECTION................................................................................................................................................... 10
Table 2. Protected Area Sizes........................................................................................................................... 11
Table 3. 4K-bit Secured OTP Definition............................................................................................................. 11
Memory Organization................................................................................................................................................ 12
Table 4. Memory Organization......................................................................................................................... 12
DEVICE OPERATION................................................................................................................................................. 13
Figure 1-1. Serial Modes Supported (for Normal Serial mode)......................................................................... 13
Figure 1-2. Serial Modes Supported (for Double Transfer Rate serial read mode)........................................... 13
COMMAND DESCRIPTION........................................................................................................................................ 14
Table 5. Command Sets.................................................................................................................................... 14
(1) Write Enable (WREN).................................................................................................................................. 16
(2) Write Disable (WRDI)................................................................................................................................... 16
(3) Read Identification (RDID)........................................................................................................................... 16
(4) Read Status Register (RDSR)..................................................................................................................... 17
(5) Write Status Register (WRSR)..................................................................................................................... 18
Protection Modes.............................................................................................................................................. 18
(6) Read Data Bytes (READ)............................................................................................................................ 19
(7) Read Data Bytes at Higher Speed (FAST_READ)...................................................................................... 19
(8) Fast Double Transfer Rate Read (FASTDTRD)........................................................................................... 19
(9) 2 x I/O Read Mode (2READ)....................................................................................................................... 19
(10) 2 x I/O Double Transfer Rate Read Mode (2DTRD).................................................................................. 20
(11) 4 x I/O Read Mode (4READ)...................................................................................................................... 20
(12) 4 x I/O Double Transfer Rate Read Mode (4DTRD).................................................................................. 21
(13) Sector Erase (SE)...................................................................................................................................... 21
(14) Block Erase (BE)....................................................................................................................................... 22
(15) Block Erase (BE32K)................................................................................................................................. 22
(16) Chip Erase (CE)......................................................................................................................................... 22
(17) Page Program (PP)................................................................................................................................... 23
(18) 4 x I/O Page Program (4PP)...................................................................................................................... 23
Program/Erase Flow(1) with read array data.................................................................................................... 24
Program/Erase Flow(2) without read array data............................................................................................... 25
(19) Continuously program mode (CP mode)................................................................................................... 26
(20) Parallel Mode (Highly recommended for production throughputs increasing)........................................... 26
(21) Deep Power-down (DP)............................................................................................................................. 27
(22) Release from Deep Power-down (RDP), Read Electronic Signature (RES)............................................. 27
(23) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4), (REMS4D)........................ 27
Table 6. ID Definitions ...................................................................................................................................... 28
(24) Enter Secured OTP (ENSO)...................................................................................................................... 28
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(25) Exit Secured OTP (EXSO)......................................................................................................................... 28
(26) Read Security Register (RDSCUR)........................................................................................................... 28
Security Register Definition............................................................................................................................... 29
(27) Write Security Register (WRSCUR)........................................................................................................... 29
(28) Write Protection Selection (WPSEL).......................................................................................................... 30
BP and SRWD if WPSEL=0.............................................................................................................................. 30
The individual block lock mode is effective after setting WPSEL=1.................................................................. 31
WPSEL Flow..................................................................................................................................................... 32
(29) Single Block Lock/Unlock Protection (SBLK/SBULK)................................................................................ 33
Block Lock Flow................................................................................................................................................ 33
Block Unlock Flow............................................................................................................................................. 34
(30) Read Block Lock Status (RDBLOCK)........................................................................................................ 35
(31) Gang Block Lock/Unlock (GBLK/GBULK)................................................................................................. 35
(32) Clear SR Fail Flags (CLSR)....................................................................................................................... 35
(33) Read SFDP Mode (RDSFDP).................................................................................................................... 36
Read Serial Flash Discoverable Parameter (RDSFDP) Sequence................................................................... 36
Table a. Signature and Parameter Identification Data Values .......................................................................... 37
Table b. Parameter Table (0): JEDEC Flash Parameter Tables........................................................................ 38
Table c. Parameter Table (1): Macronix Flash Parameter Tables...................................................................... 40
POWER-ON STATE.................................................................................................................................................... 42
ELECTRICAL SPECIFICATIONS............................................................................................................................... 43
ABSOLUTE MAXIMUM RATINGS.................................................................................................................... 43
Figure 2. Maximum Negative Overshoot Waveform......................................................................................... 43
CAPACITANCE TA = 25°C, f = 1.0 MHz............................................................................................................ 43
Figure 3. Maximum Positive Overshoot Waveform........................................................................................... 43
Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL............................................................. 44
Figure 5. OUTPUT LOADING.......................................................................................................................... 44
Table 7. DC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) .. 45
Table 8. AC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) .46
Timing Analysis......................................................................................................................................................... 48
Figure 6. Serial Input Timing............................................................................................................................. 48
Figure 7. Output Timing..................................................................................................................................... 48
Figure 8. Serial Input Timing for Double Transfer Rate Mode........................................................................... 49
Figure 9. Serial Output Timing for Double Transfer Rate Mode........................................................................ 49
Figure 10. WP# Setup Timing and Hold Timing during WRSR when SRWD=1................................................ 50
Figure 11. Write Enable (WREN) Sequence (Command 06)............................................................................ 50
Figure 12. Write Disable (WRDI) Sequence (Command 04)............................................................................. 50
Figure 13. Read Identification (RDID) Sequence (Command 9F)..................................................................... 51
Figure 14. Read Status Register (RDSR) Sequence (Command 05)............................................................... 51
Figure 15. Write Status Register (WRSR) Sequence (Command 01).............................................................. 51
Figure 16. Read Data Bytes (READ) Sequence (Command 03)..................................................................... 52
Figure 17. Read at Higher Speed (FAST_READ) Sequence (Command 0B)................................................. 52
Figure 18. Fast DT Read (FASTDTRD) Sequence (Command 0D).................................................................. 52
Figure 19. 2 x I/O Read Mode Sequence (Command BB)................................................................................ 53
Figure 20. Fast Dual I/O DT Read (2DTRD) Sequence (Command BD).......................................................... 53
Figure 21. 4 x I/O Read Mode Sequence (Command EB)................................................................................ 54
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Figure 22. 4 x I/O Read Enhance Performance Mode Sequence (Command EB)........................................... 54
Figure 23. Fast Quad I/O DT Read (4DTRD) Sequence (Command ED)......................................................... 55
Figure 24. Fast Quad I/O DT Read (4DTRD) Enhance Performance Sequence (Command ED).................... 55
Figure 25. Sector Erase (SE) Sequence (Command 20)................................................................................. 56
Figure 26. Block Erase (BE/BE32K) Sequence (Command D8/52)................................................................. 56
Figure 27. Chip Erase (CE) Sequence (Command 60 or C7).......................................................................... 56
Figure 28. Page Program (PP) Sequence (Command 02).............................................................................. 57
Figure 29. 4 x I/O Page Program (4PP) Sequence (Command 38)................................................................. 57
Figure 30. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD).................. 58
Figure 31-1. Enter Parallel Mode (ENPLM) Sequence (Command 55)........................................................... 59
Figure 31-2. Exit Parallel Mode (EXPLM) Sequence (Command 45).............................................................. 59
Figure 31-3. Parallel Mode Read Identification (Parallel RDID) Sequence (Command 9F)............................ 59
Figure 31-4. Parallel Mode Read Electronic Manufacturer & Device ID (Parallel REMS) Sequence (Command
90)..................................................................................................................................................................... 60
Figure 31-5. Parallel Mode Release from Deep Power-down (RDP) and Read Electronic Signature (RES)
Sequence.......................................................................................................................................................... 60
Figure 31-6. Parallel Mode Read Array (Parallel READ) Sequence (Command 03)....................................... 61
Figure 31-7. Parallel Mode Page Program (Parallel PP) Sequence (Command 02)....................................... 61
Figure 32. Deep Power-down (DP) Sequence (Command B9)....................................................................... 61
Figure 33. Read Electronic Signature (RES) Sequence (Command AB)......................................................... 62
Figure 34. Release from Deep Power-down (RDP) Sequence (Command AB).............................................. 62
Figure 35. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF or CF)...
63
Figure 36. Write Protection Selection (WPSEL) Sequence (Command 68)..................................................... 63
Figure 37. Single Block Lock/Unlock Protection (SBLK/SBULK) Sequence (Command 36/39)...................... 64
Figure 38. Read Block Protection Lock Status (RDBLOCK) Sequence (Command 3C)................................. 64
Figure 39. Gang Block Lock/Unlock (GBLK/GBULK) Sequence (Command 7E/98)....................................... 64
Figure 40. Power-up Timing.............................................................................................................................. 65
Table 9. Power-Up Timing ................................................................................................................................ 65
INITIAL DELIVERY STATE............................................................................................................................... 65
OPERATING CONDITIONS........................................................................................................................................ 66
Figure 41. AC Timing at Device Power-Up........................................................................................................ 66
Figure 42. Power-Down Sequence................................................................................................................... 67
ERASE AND PROGRAMMING PERFORMANCE..................................................................................................... 68
DATA RETENTION..................................................................................................................................................... 68
LATCH-UP CHARACTERISTICS............................................................................................................................... 68
ORDERING INFORMATION....................................................................................................................................... 69
PART NAME DESCRIPTION...................................................................................................................................... 70
PACKAGE INFORMATION......................................................................................................................................... 71
REVISION HISTORY .................................................................................................................................................. 73
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REV. 1.9, SEP. 06, 2013
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MX25L12845E
128M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY
FEATURES
GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 128Mb: 134,217,728 x 1 bit structure or 67,108,864 x 2 bits (two I/O mode) structure or 33,554,432 x 4 bits (four
I/O mode) structure
• 4096 Equal Sectors with 4K bytes each
- Any Sector can be erased individually
• 512 Equal Blocks with 32K bytes each
- Any Block can be erased individually
• 256 Equal Blocks with 64K bytes each
- Any Block can be erased individually
• Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
VCC = 2.7~3.6V
- Normal read
- 50MHz
- Fast read (Normal Serial Mode)
- 1 I/O: 104MHz with 8 dummy cycles
- 2 I/O: 70MHz with 4 dummy cycles
- 4 I/O: 70MHz with 6 dummy cycles
- Fast read (Double Transfer Rate Mode)
- 1 I/O: 50MHz with 6 dummy cycles
- 2 I/O: 50MHz with 6 dummy cycles
- 4 I/O: 50MHz with 8 dummy cycles
- Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)
- Byte program time: 9us (typical)
- Continuously Program mode (automatically increase address under word program mode)
- Fast erase time: 60ms (typ.)/sector (4K-byte per sector) ; 0.7s(typ.) /block (64K-byte per block); 80s(typ.) /chip
• Low Power Consumption
- Low active read current: 19mA(max.) at 104MHz, 15mA(max.) at 66MHz and 10mA(max.) at 33MHz
- Low active programming current: 25mA (max.)
- Low active erase current: 25mA (max.)
- Low standby current: 100uA (max.)
- Deep power down current: 40uA (max.)
• Typical 100,000 erase/program cycles
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
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MX25L12845E
• Advanced Security Features
- BP0-BP3 block group protect
- Flexible individual block protect when OTP WPSEL=1
- Additional 4K bits secured OTP for unique identifier
• Auto Erase and Auto Program Algorithms
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse width (Any page to be programed should have page in the erased state first.)
• Status Register Feature
• Electronic Identification
- JEDEC 1-byte Manufacturer ID and 2-byte Device ID
- RES command for 1-byte Device ID
- REMS, REMS2, REMS4 and REMS4D commands for 1-byte Manufacturer ID and 1-byte Device ID
• Support Serial Flash Discoverable Parameters (SFDP) mode
HARDWARE FEATURES
• SCLK Input
- Serial clock input
• SI/SIO0
- Serial Data Input or Serial Data Input/Output for 2 x I/O mode and 4 x I/O mode
• SO/SIO1/PO7
- Serial Data Output or Serial Data Input/Output for 2 x I/O mode and 4 x I/O mode or Parallel Data
• WP#/SIO2
- Hardware write protection or serial data Input/Output for 4 x I/O mode
• NC/SIO3
- NC pin or serial data Input/Output for 4 x I/O mode
• PO0~PO6
- For parallel mode data (only 128Mb provide parallel mode)
• PACKAGE
- 16-pin SOP (300mil)
- 8-WSON (8x6mm)
- All devices are RoHS Compliant and Halogen-free
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MX25L12845E
GENERAL DESCRIPTION
MX25L12845E is 134,217,728 bits serial Flash memory, which is configured as 16,777,216 x 8 internally. When it
is in two or four I/O mode, the structure becomes 67,108,864 bits x 2 or 33,554,432 bits x 4. The MX25L12845E
features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus
signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device
is enabled by CS# input.
MX25L12845E provides high performance read mode, which may latch address and data on both rising and falling
edge of clock. By using this high performance read mode, the data throughput may be doubling. Moreover, the performance may reach direct code execution, the RAM size of the system may be reduced and further saving system
cost.
MX25L12845E, MXSMIO (Serial Multi I/O) flash memory, provides sequential read operation on the whole chip
and multi-I/O features.
When it is in dual I/O mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and
data output. When it is in quad I/O mode, the SI pin, SO pin, WP# pin and NC pin become SIO0 pin, SIO1 pin, SIO2
pin and SIO3 pin for address/dummy bits input and data Input/Output. Parallel mode is also provided in this device.
It features 8 bit input/output for increasing throughputs. This feature is recommeded to be used for factory production purpose.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, or word basis. Continuously Program mode and erase command are executed on 4K-byte sector, 32Kbyte/64K-byte block, or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via the WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode and draws less than 100uA DC current.
The MX25L12845E utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
Table 1. Additional Features
Additional
Features
Part
Name
MX25L12845E
Protection and Security
Read Performance
Flexible or
1 I/O DT 2 I/O DT 4 I/O DT
Individual block
4K-bit
1 I/O Read 2 I/O Read 4 I/O Read
Read
Read
Read
(or sector)
secured OTP (104 MHz) (70 MHz) (70 MHz)
(50 MHz) (50 MHz) (50 MHz)
protection
V
V
V
V
Additional
Features
Part
Name
MX25L12845E
V
V
V
V
8 I/O
Parallel
Mode
(6 MHz)
V
(Note 1)
Identifier
RES
(command: AB
hex)
REMS
(command: 90
hex)
REMS2
(command: EF
hex)
REMS4
(command: DF
hex)
REMS4D
(command: CF
hex)
RDID
(command: 9F
hex)
17 (hex)
C2 17 (hex)
C2 17 (hex)
C2 17 (hex)
C2 17 (hex)
C2 20 18 (hex)
Note 1: Only MX25L12845E provide parallel mode.
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MX25L12845E
PIN DESCRIPTION
PIN CONFIGURATION
16-PIN SOP (300mil)
NC/SIO3
VCC
NC
PO2
PO1
PO0
CS#
SO/SIO1/PO7
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SYMBOL
DESCRIPTION
CS#
Chip Select
Serial Data Input (for 1xI/O)/ Serial Data
SI/SIO0
Input & Output (for 2xI/O or 4xI/O mode)
Serial Data Output (for 1xI/O)/Serial
SO/SIO1/
Data Input & Output (for 2xI/O or 4xI/O
PO7
mode) / Parallel Data Output/Input
SCLK
Clock Input
Write protection: connect to GND or
WP#/SIO2 Serial Data Input & Output (for 4xI/O
mode)
NC pin (Not connect) or Serial Data
NC/SIO3
Input & Output (for 4xI/O mode)
VCC
+ 3.3V Power Supply
GND
Ground
Parallel data output/input (PO0~PO6 can
PO0~PO6
be connected to NC in Serial Mode)
NC
No Connection
SCLK
SI/SIO0
PO6
PO5
PO4
PO3
GND
WP#/SIO2
8-WSON (8x6mm)
CS#
SO/SIO1
WP#/SIO2
GND
1
2
3
4
8
7
6
5
VCC
NC/SIO3
SCLK
SI/SIO0
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MX25L12845E
BLOCK DIAGRAM
X-Decoder
Address
Generator
Memory Array
Page Buffer
SI/SIO0
Data
Register
Y-Decoder
SRAM
Buffer
Sense
Amplifier
CS#
WP#/SIO2
NC/SIO3
SCLK
Mode
Logic
State
Machine
HV
Generator
Clock Generator
Output
Buffer
SO/SIO1
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MX25L12845E
DATA PROTECTION
During power transition, there may be some false system level signals which result in inadvertent erasure or
programming. The device is designed to protect itself from these accidental write cycles.
The state machine will be reset as standby mode automatically during power up. In addition, the control register
architecture of the device constrains that the memory contents can only be changed after specific command
sequences have completed successfully.
In the following, there are several features to protect the system from the accidental write cycles during VCC powerup and power-down or from system noise.
• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before issuing other commands to change data. The WEL bit will return to reset stage under following situations:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP, 4PP) command completion
- Continuously Program mode (CP) instruction completion
- Sector Erase (SE) command completion
- Block Erase (BE, BE32K) command completion
- Chip Erase (CE) command completion
- Single Block Lock/Unlock (SBLK/SBULK) instruction completion
- Gang Block Lock/Unlock (GBLK/GBULK) instruction completion
•
Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from
writing all commands except Release from Deep Power Down mode command (RDP) and Read Electronic Signature command (RES).
I. Block lock protection
- The Software Protected Mode (SPM) uses (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected
as read only. The protected area definition is shown as table of "Protected Area Sizes", the protected areas are
more flexible which may protect various area by setting value of BP0-BP3 bits. Please refer to table of "Protected Area Sizes".
- The Hardware Protected Mode (HPM) uses WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and SRWD
bit. If the system goes into four I/O mode, the feature of HPM will be disabled.
- MX25L12845E provides individual block (or sector) write protect & unprotect. User may enter the mode with
WPSEL command and conduct individual block (or sector) write protect with SBLK instruction, or SBULK for
individual block (or sector) unprotect. Under the mode, user may conduct whole chip (all blocks) protect with
GBLK instruction and unlock the whole chip with GBULK instruction.
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Table 2. Protected Area Sizes
Status bit
Protection Area
BP3
BP2
BP1
BP0
128Mb
0
0
0
0
0 (none)
0
0
0
1
1 (2 blocks, block 254th-255th)
0
0
1
0
2 (4 blocks, block 252nd-255th)
0
0
1
1
3 (8 blocks, block 248th-255th)
0
1
0
0
4 (16 blocks, block 240th-255th)
0
1
0
1
5 (32 blocks, block 224th-255th)
0
1
1
0
6 (64 blocks, block 192nd-255th)
0
1
1
1
7 (128 blocks, block 128th-255th)
1
0
0
0
8 (256 blocks, all)
1
0
0
1
9 (256 blocks, all)
1
0
1
0
10 (256 blocks, all)
1
0
1
1
11 (256 blocks, all)
1
1
0
0
12 (256 blocks, all)
1
1
0
1
13 (256 blocks, all)
1
1
1
0
14 (256 blocks, all)
1
1
1
1
15 (256 blocks, all)
Note: The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP3, BP2, BP1, BP0) are 0.
II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit One-Time Program area for setting device unique serial number - Which may be set by factory or system maker. Please refer to Table 3. 4K-bit Secured OTP Definition.
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with ENSO command), and going
through normal program procedure, and then exiting 4K-bit secured OTP mode by writing EXSO command.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register)
command to set customer lock-down bit1 as "1". Please refer to table of "Security Register Definition" for security register bit definition and table of "4K-bit Secured OTP Definition" for address range definition.
- Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit Secured OTP mode, array access is not allowed.
Table 3. 4K-bit Secured OTP Definition
Address range
Size
Standard Factory Lock
xxx000~xxx00F
128-bit
ESN (electrical serial number)
xxx010~xxx1FF
3968-bit
N/A
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Customer Lock
Determined by customer
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MX25L12845E
Memory Organization
Table 4. Memory Organization
Block(64K-byte)
Block(32K-byte)
Sector
254
508
individual block
lock/unlock unit:64K-byte
507
253
506
FF7FFFh
individual 16 sectors
lock/unlock unit:4K-byte
…
FF8FFFh
FF7000h
4080
FF0000h
FF0FFFh
4079
FEF000h
FEFFFFh
…
509
FF8000h
4087
4072
FE8000h
FE8FFFh
4071
FE7000h
FE7FFFh
4064
FE0000h
FE0FFFh
4063
FDF000h
FDFFFFh
…
510
4088
…
255
FFFFFFh
4056
FD8000h
FD8FFFh
4055
FD7000h
FD7FFFh
4048
FD0000h
FD0FFFh
47
02F000h
02FFFFh
…
511
Address Range
FFF000h
…
4095
1
2
1
0
0
027FFFh
…
028FFFh
027000h
32
020000h
020FFFh
31
01F000h
01FFFFh
…
3
028000h
39
24
018000h
018FFFh
23
017000h
017FFFh
…
4
individual block
lock/unlock unit:64K-byte
40
16
010000h
010FFFh
15
00F000h
00FFFFh
…
2
8
008000h
008FFFh
7
007000h
007FFFh
000000h
000FFFh
individual 16 sectors
lock/unlock unit:4K-byte
…
5
…
individual block
lock/unlock unit:64K-byte
0
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MX25L12845E
DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation.
2. When incorrect command is inputted to this device, it enters standby mode and remains in standby mode until
next CS# falling edge. In standby mode, SO pin of the device is High-Z.
3. When correct command is inputted to this device, it enters active mode and remains in active mode until next
CS# rising edge.
4. For standard single data rate serial mode, input data is latched on the rising edge of Serial Clock (SCLK) and
data is shifted out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as Figure
1-1. For high performance (Double Transfer Rate Read serial mode), data is latched on both rising and falling
edge of clock and data shifts out on both rising and falling edge of clock as Figure 1-2.
5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, RDSFDP, 2READ,
4READ,FASTDTRD, 2DTRD, 4DTRD, RDBLOCK, RES, REMS, REMS2, REMS4, and REMS4D the shifted-in
instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be
high. For the following instructions: WREN, WRDI, WRSR, SE, BE, BE32K, HPM, CE, PP, CP, 4PP, RDP, DP,
WPSEL, SBLK, SBULK, GBLK, GBULK, ENSO, EXSO, WRSCUR, ENPLM, EXPLM and CLSR the CS# must
go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
6. While a Write Status Register, Program, or Erase operation is in progress, access to the memory array is neglected and will not affect the current operation of Write Status Register, Program, Erase.
Figure 1-1. Serial Modes Supported (for Normal Serial mode)
CPOL
CPHA
shift in
(Serial mode 0)
0
0
SCLK
(Serial mode 3)
1
1
SCLK
SI
shift out
MSB
SO
MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
Figure 1-2. Serial Modes Supported (for Double Transfer Rate serial read mode)
CPOL
data
in
CPHA
(Serial mode 0)
0
0
SCLK
(Serial mode 3)
1
1
SCLK
SI
data
in
data
out
data
out
MSB
SO
P/N: PM1428
REV. 1.9, SEP. 06, 2013
13
MX25L12845E
COMMAND DESCRIPTION
Table 5. Command Sets
RDSR
WRSR
FASTDTRD
4DTRD
COMMAND WREN (write WRDI (write RDID (read
2DTRD (Dual
(read status (write status
(fast DT
(Quad I/O DT
(byte)
enable)
disable)
identification)
I/O DT Read)
register)
register)
read)
Read)
Command
06
04
9F
05
01
0D
BD
ED
(hex)
Input
Data(8)
ADD(12)
ADD(6)
ADD(3)
Cycles
Dummy
6
6
1+7
Cycles
sets the
resets the
outputs
to read out to write new n bytes read n bytes read n bytes read
JEDEC
the values
values to
out (Double out (Double out (Double
(WEL) write (WEL) write
Transfer
Transfer
Transfer
enable latch enable latch ID: 1-byte of the status the status
register
Rate)
until
Rate)
by
2xI/
Rate)
by 4xI/
bit
bit
Manufacturer
register
Action
O until CS# O until CS#
ID & 2-byte
CS# goes
goes high
high
goes high
Device ID
COMMAND READ (read
(byte)
data)
Command
(hex)
Input
Cycles
Dummy
Cycles
Action
Action
4READ (4
x I/O read
command)
4PP (quad
page
program)
SE (sector
erase)
BE (block
erase 64KB)
03
0B
5A
BB
EB
38
20
D8
ADD(24)
ADD(24)
ADD(24)
ADD(12)
ADD(6)
ADD(6)+
Data(512)
ADD(24)
ADD(24)
8
8
4
2+4
n bytes read n bytes read Read SFDP n bytes read n bytes read quad input to erase the
selected
mode
out by 2 x I/ out by 4 x I/ to program
out until CS# out until CS#
sector
goes high
goes high
O until CS# O until CS# the selected
goes high
goes high
page
COMMAND BE 32K (block
(byte)
erase 32KB)
Command
(hex)
Input
Cycles
Dummy
Cycles
2READ (2
FAST READ
RDSFDP
x I/O read
(fast read
(Read SFDP) command)
data)
Note1
52
CP
RDP
REMS (read
(Continuously DP (Deep
(Release
RES (read
electronic
program
power down) from deep electronic ID) manufacturer
mode)
power down)
& device ID)
CE (chip
erase)
PP (Page
program)
60 or C7
02
AD
ADD(24)+
Data(2048)
ADD(24)+
Data(16)
ADD(24)
to erase the
selected
64KB block
B9
AB
AB
90
ADD(24)
24
to erase the
selected
32KB block
to erase
whole chip
to program
the selected
page
output the
continously enters deep release from to read out
program
power down deep power 1-byte Device Manufacturer
ID & Device
whole chip,
mode
down mode
ID
the address is
ID
automatically
increase
P/N: PM1428
REV. 1.9, SEP. 06, 2013
14
MX25L12845E
COMMAND BE 32K (block
(byte)
erase 32KB)
Command
(hex)
Input
Cycles
Dummy
Cycles
REMS4 (read REMS4D (read
ENSO (enter
EXSO (exit
ID for 4x I/O
ID for 4x I/O
secured OTP) secured OTP)
mode)
DT mode)
52
DF
CF
ADD(24)
ADD(24)
ADD(24)
to erase the
selected 32KB
block
output the
Manufacturer ID &
device ID
output the
Manufacturer ID &
Device ID
Action
COMMAND ENPLM (Enter EXPLM (EXIT CLSR (Clear
(byte)
Parallel Mode) Parallel Mode) SR Fail Flags)
Command
(hex)
Input
Cycles
Dummy
Cycles
Action
COMMAND
(byte)
Command
(hex)
Input
Cycles
Dummy
Cycles
Action
55
45
clear security
register bit 6
and bit 5
RDBLOCK
(block protect
read)
GBLK (gang
block lock)
GBULK (gang
block unlock)
3C
7E
98
whole chip
write protect
whole
chip unprotect
C1
to enter the 4K- to exit the 4Kbit Secured
bit Secured
OTP mode
OTP mode
WRSCUR
(write security
register)
2B
2F
to read value
of security
register
to set the lockdown bit as
"1" (once lockdown, cannot
be updated)
HPM (High
Performance
Enable Mode)
WPSEL (write
protection
selection)
SBLK (single
block lock)
*Note 2
SBULK (single
block unlock)
A3
68
36
39
ADD(24)
ADD(24)
30
to exit 8xI/
O parallel
programming
mode
8xI/O parallel
programming
mode
B1
RDSCUR
(read security
register)
Quad I/O high to enter and individual block individual block
Performance enable individal (64K-byte) or (64K-byte) or
block protect sector (4K-byte) sector (4K-byte)
mode
unprotect
mode
write protect
ADD(24)
read individual
block or sector
write protect
status
Notes:
1. It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden
mode.
2: In individual block write protection mode, all blocks/sectors is locked as defualt.
P/N: PM1428
REV. 1.9, SEP. 06, 2013
15
MX25L12845E
(1) Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP,
CP, SE, BE, BE32K, CE, WRSR, SBLK, SBULK, GBLK and GBULK, which are intended to change the device content, should be set every time after the WREN instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes high.
(Please refer to Figure 11)
(2) Write Disable (WRDI)
The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes high. (Please
refer to Figure 12)
The WEL bit is reset by following situations:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP, 4PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE, BE32K) instruction completion
- Chip Erase (CE) instruction completion
- Continuously Program mode (CP) instruction completion
- Single Block Lock/Unlock (SBLK/SBULK) instruction completion
- Gang Block Lock/Unlock (GBLK/GBULK) instruction completion
(3) Read Identification (RDID)
The RDID instruction is for reading the Manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC
Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte Device ID, and the individual Device ID
of second-byte ID are listed as table of "ID Definitions". (Please refer to Table 6)
The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code → 24-bits ID data out
on SO→ to end RDID operation can use CS# to high at any time during data out. (Please refer to Figure 13)
While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.
P/N: PM1428
REV. 1.9, SEP. 06, 2013
16
MX25L12845E
(4) Read Status Register (RDSR)
The RDSR instruction is for reading Status Register. The Read Status Register can be read at any time (even in
program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP)
bit before sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register
data out on SO (Please refer to Figure 14).
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write
status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status
register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status
register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable
latch. When WEL bit sets to "1", which means the internal write enable latch is set, the device can accept program/
erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. The program/erase command will be ignored and
will reset WEL bit if it is applied to a protected memory area.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as
defined in Table 2) of the device to against the program/erase instruction without hardware protection mode being
set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to
be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE),
Block Erase (BE) and Chip Erase (CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be
executed).
QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0" (factory default), it performs non-Quad and WP# is
enable. While QE is "1", it performs Quad I/O mode and WP# is disabled. In the other word, if the system goes into
four I/O mode (QE=1), the feature of HPM will be disabled.
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, default value is "0". SRWD bit is operated together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The hardware protection
mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write
Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP3,
BP2, BP1, BP0) are read only.
Status Register
bit7
bit6
SRWD (status
register write
protect)
QE
(Quad
Enable)
1= Quad
1=status
Enable
register write
0=not Quad
disable
Enable
Non-volatile Non-volatile
bit
bit
bit5
BP3
(level of
protected
block)
bit4
BP2
(level of
protected
block)
bit3
BP1
(level of
protected
block)
bit2
BP0
(level of
protected
block)
(note 1)
(note 1)
(note 1)
(note 1)
Non-volatile
bit
Non-volatile
bit
Non-volatile
bit
Non-volatile
bit
bit1
bit0
WEL
WIP
(write enable
(write in
latch)
progress bit)
1=write
1=write
enable
operation
0=not write 0=not in write
enable
operation
volatile bit
volatile bit
Note: see the Table 2 "Protected Area Size" in page 11.
P/N: PM1428
REV. 1.9, SEP. 06, 2013
17
MX25L12845E
(5) Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the
Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the protected area of memory (as shown in Table 2). The WRSR also can set or reset the Quad enable (QE) bit and set or
reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/SIO2) pin signal, but
has no effect on bit1(WEL) and bit0 (WIP) of the status register. The WRSR instruction cannot be executed once the
Hardware Protected Mode (HPM) is entered.
The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register
data on SI→ CS# goes high. (Please refer to Figure 15)
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1
during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL)
bit is reset.
Protection Modes
Mode
Software protection
mode(SPM)
Hardware protection
mode (HPM)
Status register condition
WP# and SRWD bit status
Memory
Status register can be written
in (WEL bit is set to "1") and
the SRWD, BP0-BP3
bits can be changed
WP#=1 and SRWD bit=0, or
WP#=0 and SRWD bit=0, or
WP#=1 and SRWD=1
The protected area
cannot
be program or erase.
The SRWD, BP0-BP3 of
status register bits cannot be
changed
WP#=0, SRWD bit=1
The protected area
cannot
be program or erase.
Note: As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 2.
As the table above showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM):
Software Protected Mode (SPM):
- When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can
change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1,
BP0, is at software protected mode (SPM).
- When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values of
SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM)
Hardware Protected Mode (HPM):
- When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware
protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2,
BP1, BP0 and hardware protected mode by the WP#/SIO2 to against data modification.
Note:
To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered.
If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only
can use software protected mode via BP3, BP2, BP1, BP0.
If the system goes into four I/O mode, the feature of HPM will be disabled.
P/N: PM1428
REV. 1.9, SEP. 06, 2013
18
MX25L12845E
(6) Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on
the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can
be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been
reached.
The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→3-byte address on
SI →data out on SO→ to end READ operation can use CS# to high at any time during data out. (Please refer to Figure 16)
(7) Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at
any location. The address is automatically increased to the next higher address after each byte data is shifted out,
so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when
the highest address has been reached.
The sequence of issuing FAST_READ instruction is: CS# goes low→sending FAST_READ instruction code→3-byte
address on SI→ 1-dummy byte (default) address on SI→data out on SO→ to end FAST_READ operation can use
CS# to high at any time during data out. (Please refer to Figure 17)
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.
(8) Fast Double Transfer Rate Read (FASTDTRD)
The FASTDTRD instruction is for doubling reading data out, signals are triggered on both rising and falling edge of
clock. The address is latched on both rising and falling edge of SCLK, and data of each bit shifts out on both rising
and falling edge of SCLK at a maximum frequency fC2. The 2-bit address can be latched-in at one clock, and 2-bit
data can be read out at one clock, which means one bit at rising edge of clock, the other bit at falling edge of clock.
The first address byte can be at any location.
The address is automatically increased to the next higher address after each byte data is shifted out, so the whole
memory can be read out at a single FASTDTRD instruction. The address counter rolls over to 0 when the highest
address has been reached.
The sequence of issuing FASTDTRD instruction is: CS# goes low → sending FASTDTRD instruction code (1bit
per clock) → 3-byte address on SI (2-bit per clock) → 6-dummy clocks (default) on SI → data out on SO (2-bit per
clock) → to end FASTDTRD operation can use CS# to high at any time during data out. (Please refer to Figure 18)
While Program/Erase/Write Status Register cycle is in progress, FASTDTRD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.
(9) 2 x I/O Read Mode (2READ)
The 2READ instruction enables Double Transfer Rate of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maxiP/N: PM1428
REV. 1.9, SEP. 06, 2013
19
MX25L12845E
mum frequency fT. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 24-bit address interleave on SIO1 & SIO0→ 4-bit dummy cycle on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→ to end
2READ operation can use CS# to high at any time during data out (Please refer to Figure 19 for 2 x I/O Read Mode
Timing Waveform).
While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
(10) 2 x I/O Double Transfer Rate Read Mode (2DTRD)
The 2DTRD instruction enables Double Transfer Rate throughput on dual I/O of Serial Flash in read mode. The address (interleave on dual I/O pins) is latched on both rising and falling edge of SCLK, and data (interleave on dual
I/O pins) shift out on both rising and falling edge of SCLK at a maximum frequency fT2. The 4-bit address can be
latched-in at one clock, and 4-bit data can be read out at one clock, which means two bits at rising edge of clock,
the other two bits at falling edge of clock. The first address byte can be at any location.
The address is automatically increased to the next higher address after each byte data is shifted out, so the whole
memory can be read out at a single 2DTRD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 2DTRD instruction, the following address/dummy/ data out will perform as
4-bit instead of previous 1-bit.
The sequence of issuing 2DTRD instruction is: CS# goes low → sending 2DTRD instruction (1-bit per clock) → 24bit address interleave on SIO1 & SIO0 (4-bit per clock) → 6-bit dummy clocks on SIO1 & SIO0 → data out interleave on SIO1 & SIO0 (4-bit per clock) → to end 2DTRD operation can use CS# to high at any time during data
out (Please refer to Figure 20 for 2 x I/O Double Transfer Rate Read Mode Timing Waveform).
While Program/Erase/Write Status Register cycle is in progress, 2DTRD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
(11) 4 x I/O Read Mode (4READ)
The 4READ instruction enables quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status
Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK,
and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency
fQ. The first address byte can be at any location. The address is automatically increased to the next higher address
after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing 4READ instruction is: CS# goes low→ sending 4READ instruction→ 24-bit address interleave on SIO3, SIO2, SIO1 & SIO0→ 6 dummy cycles → data out interleave on SIO3, SIO2, SIO1 & SIO0→ to
end 4READ operation can use CS# to high at any time during data out (Please refer to Figure 21 for 4 x I/O Read
Mode Timing Waveform).
Another sequence of issuing 4READ instruction especially useful in random access is : CS# goes low→ sending 4
READ instruction→ 3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 →performance enhance toggling bit
P/N: PM1428
REV. 1.9, SEP. 06, 2013
20
MX25L12845E
P[7:0]→ 4 dummy cycles → data out still CS# goes high → CS# goes low (reduce 4 Read instruction) → 24-bit random access address (Please refer to Figure 22 for 4x I/O Read Enhance Performance Mode timing waveform).
In the performance-enhancing mode (Notes of Figure. 22), P[7:4] must be toggling with P[3:0]; likewise P[7:0]=A5h,
5Ah, F0h or 0Fh can make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer
toggling with P[3:0]; likewise P[7:0]=FFh, 00h, AAh or 55h. These commands will reset the performance enhance
mode. And afterwards CS# is raised and then lowered, the system then will return to normal operation.
While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
(12) 4 x I/O Double Transfer Rate Read Mode (4DTRD)
The 4DTRD instruction enables Double Transfer Rate throughput on quad I/O of Serial Flash in read mode. A Quad
Enable (QE) bit of status Register must be set to "1" before sending the 4DTRD instruction. The address (interleave
on 4 I/O pins) is latched on both rising and falling edge of SCLK, and data (interleave on 4 I/O pins) shift out on
both rising and falling edge of SCLK at a maximum frequency fQ2. The 8-bit address can be latched-in at one clock,
and 8-bit data can be read out at one clock, which means four bits at rising edge of clock, the other four bits at falling edge of clock. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single 4DTRD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 4DTRD instruction, the following address/dummy/data out will perform as 8-bit instead of previous 1-bit.
The sequence of issuing 4DTRD instruction is: CS# goes low → sending 4DTRD instruction (1-bit per clock) → 24bit address interleave on SIO3, SIO2, SIO1 & SIO0 (8-bit per clock) → 8 dummy clocks → data out interleave on
SIO3, SIO2, SIO1 & SIO0 (8-bit per clock) → to end 4DTRD operation can use CS# to high at any time during data
out (Please refer to Figure 23 for 4 x I/O Read Mode Double Transfer Rate Timing Waveform).
Another sequence of issuing enhanced mode of 4DTRD instruction especially useful in random access is: CS# goes
low → sending 4DTRD instruction (1-bit per clock) → 3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 (8-bit
per clock) → performance enhance toggling bit P[7:0] → 7 dummy clocks → data out(8-bit per clock) still CS#
goes high → CS# goes low (eliminate 4 Read instruction) → 24-bit random access address (Please refer to Figure
24 for 4x I/O Double Transfer Rate read enhance performance mode timing waveform).
While Program/Erase/Write Status Register cycle is in progress, 4DTRD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
(13) Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for
any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before
sending the Sector Erase (SE). Any address of the sector (see Table 4) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of the address been latchedin); otherwise, the instruction will be rejected and not executed.
The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 3-byte address on SI
→CS# goes high. (Please refer to Figure 25)
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets during the tSE
timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
sector is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no
change) and the WEL bit still be reset.
P/N: PM1428
REV. 1.9, SEP. 06, 2013
21
MX25L12845E
(14) Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
64K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch
(WEL) bit before sending the Block Erase (BE). Any address of the block (see Table 4) is a valid address for Block
Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of address byte
been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE instruction is: CS# goes low → sending BE instruction code → 3-byte address on SI
→ CS# goes high. (Please refer to Figure 26)
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets during the tBE
timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
block is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no
change) and the WEL bit still be reset.
(15) Block Erase (BE32K)
The Block Erase (BE32) instruction is for erasing the data of the chosen block to be "1". The instruction is used
for 32K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable
Latch (WEL) bit before sending the Block Erase (BE32). Any address of the block (see Table 4) is a valid address
for Block Erase (BE32) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of
address byte been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE32 instruction is: CS# goes low → sending BE32 instruction code → 3-byte address on
SI → CS# goes high. (Please refer to Figure 26)
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the tBE timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the block
is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no change)
and the WEL bit still be reset.
(16) Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must
go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low → sending CE instruction code → CS# goes high. (Please
refer to Figure 27)
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Chip Erase cycle is in progress. The WIP sets during the tCE timing, and clears when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the chip is
protected the Chip Erase (CE) instruction will not be executed, but WEL will be reset.
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MX25L12845E
(17) Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction
must be executed to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device
programs only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed,
A7-A0 (the eight least significant address bits) should be set to 0. The last address byte (the 8 least significant address bits, A7-A0) should be set to 0 for 256 bytes page program. If A7-A0 are not all zero, transmitted data that
exceed page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently
selected page. If the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page and previous data will be disregarded. If the data bytes sent to the device has not exceeded 256, the
data will be programmed at the request address of the page. There will be no effort on the other data bytes of the
same page.
The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→
at least 1-byte on data on SI→ CS# goes high. (Please refer to Figure 28)
The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte
boundary( the latest eighth bit of data being latched in), otherwise, the instruction will be rejected and will not be
executed.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Page Program cycle is in progress. The WIP sets during the tPP
timing, and clears when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If
the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no
change) and the WEL bit will still be reset.
(18) 4 x I/O Page Program (4PP)
The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN)
instruction must be executed to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1"
before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2,
and SIO3, which can raise programer performance and and the effectiveness of application of lower clock less
than 20MHz. For system with faster clock, the Quad page program cannot provide more performance, because
the required internal page program time is far more than the time data flows in. Therefore, we suggest that while
executing this command (especially during sending data), user can slow the clock speed down to 20MHz below.
The other function descriptions are as same as standard page program.
The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on
SIO[3:0]→ at least 1-byte on data on SIO[3:0]→ CS# goes high. (Please refer to Figure 29)
If the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no
change) and the WEL bit will still be reset.
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MX25L12845E
The Program/Erase function instruction function flow is as follows:
Program/Erase Flow(1) with read array data
Start
WREN command
RDSR command*
WREN=1?
No
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
No
WIP=0?
Yes
Read array data
(same address of PGM/ERS)
Verify OK?
No
Yes
Program/erase fail
Program/erase successfully
CLSR(30h) command
Program/erase
another block?
No
Yes
*
* Issue RDSR to check BP[3:0].
* If WPSEL=1, issue RDBLOCK to check the block status.
Program/erase completed
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MX25L12845E
Program/Erase Flow(2) without read array data
Start
WREN command
RDSR command*
WREN=1?
No
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
No
WIP=0?
Yes
RDSCUR command
P_FAIL/E_FAIL=1?
Yes
No
Program/erase fail
Program/erase successfully
CLSR(30h) command
Program/erase
another block?
No
Yes
* Issue RDSR to check BP[3:0].
* If WPSEL=1, issue RDBLOCK to check the block status.
Program/erase completed
P/N: PM1428
REV. 1.9, SEP. 06, 2013
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MX25L12845E
(19) Continuously program mode (CP mode)
The CP mode may enhance program performance by automatically increasing address to the next higher address
after each byte data has been programmed.
The Continuously program (CP) instruction is for multiple byte program to Flash. A write Enable (WREN) instruction
must execute to set the Write Enable Latch (WEL) bit before sending the Continuously program (CP) instruction.
CS# requires to go high before CP instruction is executing. After CP instruction and address input, two bytes of
data is input sequentially from MSB(bit7) to LSB(bit0). The first byte data will be programmed to the initial address
range with A0=0 and second byte data with A0=1. If only one byte data is input, the CP mode will not process. If
more than two bytes data are input, the additional data will be ignored and only two byte data are valid. Any byte to
be programmed should be in the erase state (FF) first. It will not roll over during the CP mode, once the last unprotected address has been reached, the chip will exit CP mode and reset write Enable Latch bit (WEL) as "0" and CP
mode bit as "0". Please check the WIP bit status if it is not in write progress before entering next valid instruction.
During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR command (05
hex), and RDSCUR command (2B hex). And the WRDI command is valid after completion of a CP programming cycle, which means the WIP bit=0.
The sequence of issuing CP instruction is : CS# goes low → sending CP instruction code → 3-byte address on SI
pin → two data bytes on SI → CS# goes high to low → sending CP instruction and then continue two data bytes
are programmed → CS# goes high to low → till last desired two data bytes are programmed → CS# goes high to
low →sending WRDI (Write Disable) instruction to end CP mode → send RDSR instruction to verify if CP mode
word program ends, or send RDSCUR to check bit4 to verify if CP mode ends. (Please refer to Figure 30 of CP
mode timing waveform)
Two methods to detect the completion of a program cycle during CP mode:
1) Software method-I: by checking WIP bit of Status Register to detect the completion of CP mode.
2) Software method-II: by waiting for a tBP time out to determine if it may load next valid command or not.
If the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no
change) and the WEL bit will still be reset.
(20) Parallel Mode (Highly recommended for production throughputs increasing)
The parallel mode provides 8 bit inputs/outputs for increasing throughputs of factory production purpose. The
parallel mode requires 55h command code, after writing the parallel mode command and then CS# going high,
after that, the Memory can be available to accept RDID/RES & REMS/READ/PP command as the normal writing
command procedure. To exit parallel mode, it requires 45h command code, or power-off/on sequence. The
sequence of issuing Paralle Mode instruction is : CS# goes low→sending Parallel Mode Code→CS# goes high (Please
refer to Figure 31-1, and refer to Figure 31-2~31-7 for other parallel mode).
a. For normal write command (by SI), No effect
b. Under parallel mode, the fastest access clock freq. will be changed to 6MHz (SCLK pin clock freq.)
c. For parallel mode, the tV will be changed to 70ns.
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MX25L12845E
(21) Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device to minimum power consumption (the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction
to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are
ignored. When CS# goes high, the device is only in standby mode, not deep power-down mode. It's different from
Standby mode.
The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→ CS# goes high. (Please
refer to Figure 32)
Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP)
and Read Electronic Signature (RES) instruction. (those instructions allow the ID being reading out). When Powerdown, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby
mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction
code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay
of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2.
(22) Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is completed by driving Chip Select (CS#) High. When Chip
Select (CS#) is driven High, the device is put in the standby Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the standby Power mode is immediate. If the device was previously in
the Deep Power-down mode, though, the transition to the standby Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2(max), as specified in Table 8. Once in the standby mode, the device
waits to be selected, so that it can receive, decode and execute instructions.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of
ID Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new
design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be
executed, only except the device is in progress of program/erase/write cycles; there's no effect on the current program/erase/write cycles in progress. The sequence is shown as Figure 33, 34.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously
in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in
Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at
least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and
execute instruction.
The RDP instruction is for releasing from Deep Power-down Mode.
(23) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4), (REMS4D)
The REMS, REMS2, REMS4 and REMS4D instruction provides both the JEDEC assigned Manufacturer ID and the
specific Device ID.
The instruction is initiated by driving the CS# pin low and shift the instruction code "90h", "CFh", "DFh" or "EFh" followed by two dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for MXIC (C2h) and
the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 34.
The Device ID values are listed in table of ID Definitions. If the one-byte address is initially set to 01h, then the Device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read
continuously, alternating from one to the other. The instruction is completed by driving CS# high.
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MX25L12845E
Table 6. ID Definitions
Command Type
RDID
MX25L12845E
memory type
20
electronic ID
17
device ID
17
manufacturer ID
C2
RES
REMS/REMS2/REMS4/REMS4D
manufacturer ID
C2
memory density
18
(24) Enter Secured OTP (ENSO)
The ENSO instruction is for entering the additional 4K-bit Secured OTP mode. While the device is in 4K-bit Secured OTP mode, array access is not available. The additional 4K-bit Secured OTP is independent from main array
and may be used to store unique serial number for system identifier. After entering the Secured OTP mode, follow
standard read or program procedure to read out the data or update data. The Secured OTP data cannot be updated again once it is lock-down.
The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP
mode→ CS# goes high.
Please note that WRSR/WRSCUR/WPSEL/SBLK/GBLK/SBULK/GBULK/CE/BE/SE/BE32K commands are not acceptable during the access of secure OTP region. Once Security OTP is lock down, only read related commands
are valid.
(25) Exit Secured OTP (EXSO)
The EXSO instruction is for exiting the additional 4K-bit Secured OTP mode.
The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP
mode→ CS# goes high.
(26) Read Security Register (RDSCUR)
The RDSCUR instruction is for reading the value of Security Register. The Read Security Register can be read at
any time (even in program/erase/write status register/write security register condition) and continuously.
The sequence of issuing RDSCUR instruction is : CS# goes low→ sending RDSCUR instruction → Security Register data out on SO→ CS# goes high.
The definition of the Security Register is as below:
Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory or not. When it is
"0", it indicates non-factory lock; "1" indicates factory- lock.
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured
OTP area cannot be updated any more.
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MX25L12845E
Continuously Program Mode( CP mode) bit. The Continuously Program Mode bit indicates the status of CP
mode, "0" indicates not in CP mode; "1" indicates in CP mode.
Program Fail Flag bit. While a program failure happened, the Program Fail Flag bit would be set. This bit will also
be set when the user attempts to program a protected main memory region or a locked OTP region. This bit can indicate whether one or more of program operations fail, and can be reset by command CLSR (30h)
Erase Fail Flag bit. While a erase failure happened, the Erase Fail Flag bit would be set. This bit will also be set
when the user attempts to erase a protected main memory region or a locked OTP region. This bit can indicate
whether one or more of erase operations fail, and can be reset by command CLSR (30h)
Write Protection Select bit. The Write Protection Select bit indicates that WPSEL has been executed successfully.
Once this bit has been set (WPSEL=1), all the blocks or sectors will be write-protected after the power-on every
time. Once WPSEL has been set, it cannot be changed again, which means it's only for individual WP mode.
Under the individual block protection mode (WPSEL=1), hardware protection is performed by driving WP#=0. Once
WP#=0 all array blocks/sectors are protected regardless of the contents of SRAM lock bits.
Security Register Definition
bit7
bit6
bit5
bit4
Continuously
Program
mode
(CP mode)
bit3
x
bit2
x
bit1
bit0
LDSO
(lock-down
4K-bit
4K-bit Se- Secured OTP
cured OTP)
WPSEL
E_FAIL
P_FAIL
0=normal
WP mode
1=individual
WP mode
(default=0)
0=normal
Erase
succeed
1=indicate
Erase failed
(default=0)
0=normal
Program
succeed
1=indicate
Program
failed
(default=0)
0=normal
Program
mode
1=CP mode
(default=0)
reserved
reserved
0 = not
lockdown
1 = lockdown
(cannot
program/
erase
OTP)
non-volatile
bit
volatile bit
volatile bit
volatile bit
volatile bit
volatile bit
non-volatile
bit
non-volatile
bit
OTP
Read Only
Read Only
Read Only
Read Only
Read Only
OTP
Read Only
0=
nonfactory
lock
1 = factory
lock
(27) Write Security Register (WRSCUR)
The WRSCUR instruction is for changing the values of Security Register Bits. Unlike write status register, the WREN
instruction is not required before sending WRSCUR instruction. The WRSCUR instruction may change the values
of bit1 (LDSO bit) for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area cannot be updated any more.
The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high.
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
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(28) Write Protection Selection (WPSEL)
There are two write protection methods, (1) BP protection mode (2) individual block protection mode. If WPSEL=0,
flash is under BP protection mode . If WPSEL=1, flash is under individual block protection mode. The default value
of WPSEL is “0”. WPSEL command can be used to set WPSEL=1. Please note that WPSEL is an OTP bit. Once
WPSEL is set to 1, there is no chance to recovery WPSEL back to “0”. If the flash is put on BP mode, the individual block protection mode is disabled. Contrarily, if flash is on the individual block protection mode, the BP mode
is disabled.
Every time after the system is powered-on, the Security Register bit 7 is checked. If WPSEL=1, all the
blocks and sectors will be write protected by default. User may only unlock the blocks or sectors via SBULK
and GBULK instructions. Program or erase functions can only be operated after the Unlock instruction is executed.
BP protection mode, WPSEL=0:
ARRAY is protected by BP3~BP0 and BP3~BP0 bits are protected by “SRWD=1 and WP#=0”, where SRWD is bit 7
of status register that can be set by WRSR command.
Individual block protection mode, WPSEL=1:
Blocks are individually protected by their own SRAM lock bits which are set to “1” after power up. SBULK and SBLK
command can set SRAM lock bit to “0” and “1”. When the system accepts and executes WPSEL instruction, the bit
7 in security register will be set. It will activate SBLK, SBULK, RDBLOCK, GBLK, GBULK etc instructions to conduct
block lock protection and replace the original Software Protect Mode (SPM) use (BP3~BP0) indicated block methods.Under the individual block protection mode (WPSEL=1), hardware protection is performed by driving WP#=0.
Once WP#=0 all array blocks/sectors are protected regardless of the contents of SRAM lock bits.
The sequence of issuing WPSEL instruction is: CS# goes low → sending WPSEL instruction to enter the individual
block protect mode → CS# goes high.
WPSEL instruction function flow is as follows:
BP and SRWD if WPSEL=0
WP# pin
BP3
BP2
BP1
BP0
SRWD
64KB
64KB
64KB
(1) BP3~BP0 is used to define the protection group region.
(The protected area size see Table 2)
(2) “SRWD=1 and WP#=0” is used to protect BP3~BP0. In this
case, SRWD and BP3~BP0 of status register bits can not
be changed by WRSR
.
.
.
64KB
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The individual block lock mode is effective after setting WPSEL=1
SRAM
SRAM
…
…
TOP 4KBx16
Sectors
4KB
4KB
4KB
SRAM
SRAM
…
64KB
SRAM
…
……
Uniform
64KB blocks
64KB
4KB
SRAM
…
…
Bottom
4KBx16
Sectors
4KB
SRAM
• Power-Up: All SRAM bits=1 (all blocks are default protected).
All array cannot be programmed/erased
• SBLK/SBULK(36h/39h):
- SBLK(36h) : Set SRAM bit=1 (protect) : array can not be
programmed/erased
- SBULK(39h): Set SRAM bit=0 (unprotect): array can be
programmed/erased
- All top 4KBx16 sectors and bottom 4KBx16 sectors and other 64KB uniform blocks can be protected and
unprotected with SRAM bits individually by SBLK/SBULK
command set.
• GBLK/ GBULK(7Eh/98h):
- GBLK(7Eh): Set all SRAM bits=1, the whole chip is protected and cannot be programmed/erased.
- GBULK(98h): Set all SRAM bits=0, the whole chip is unprotected and can be programmed/erased.
- All sectors and blocks SRAM bits of the whole chip can be
protected and unprotected at one time by GBLK/GBULK
command set.
• RDBLOCK(3Ch):
- use RDBLOCK mode to check the SRAM bits status after
SBULK /SBLK/GBULK/GBLK command set.
SBULK / SBLK / GBULK / GBLK / RDBLOCK
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WPSEL Flow
start
RDSCUR(2Bh) command
Yes
WPSEL=1?
No
WPSEL disable,
block protected by BP[3:0]
WPSEL(68h) command
RDSR command
WIP=0?
No
Yes
RDSCUR(2Bh) command
WPSEL=1?
No
Yes
WPSEL set successfully
WPSEL set fail
WPSEL enable.
Block protected by individual lock
(SBLK, SBULK, … etc).
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(29) Single Block Lock/Unlock Protection (SBLK/SBULK)
These instructions are only effective after WPSEL was executed. The SBLK instruction is for write protection a specified block(or sector) of memory, using A23-A16 or (A23-A12) address bits to assign a 64Kbyte block (or 4K bytes
sector) to be protected as read only. The SBULK instruction will cancel the block (or sector) write protection state.
This feature allows user to stop protecting the entire block (or sector) through the chip unprotect command (GBULK).
The WREN (Write Enable) instruction is required before issuing SBLK/SBULK instruction.
The sequence of issuing SBLK/SBULK instruction is: CS# goes low → send SBLK/SBULK (36h/39h) instruction →
send 3 address bytes assign one block (or sector) to be protected on SI pin → CS# goes high. (Please refer to Figure 37)
The CS# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not be executed.
SBLK/SBULK instruction function flow is as follows:
Block Lock Flow
Start
RDSCUR(2Bh) command
WPSEL=1?
No
WPSEL command
Yes
WREN command
SBLK command
( 36h + 24bit address )
RDSR command
WIP=0?
No
Yes
RDBLOCK command
( 3Ch + 24bit address )
Data = FFh ?
No
Yes
Block lock successfully
Lock another block?
Block lock fail
Yes
No
Block lock completed
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Block Unlock Flow
start
RDSCUR(2Bh) command
WPSEL=1?
No
WPSEL command
Yes
WREN command
SBULK command
( 39h + 24bit address )
RDSR command
No
WIP=0?
Yes
Unlock another block?
Yes
Unlock block completed?
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MX25L12845E
(30) Read Block Lock Status (RDBLOCK)
This instruction is only effective after WPSEL was executed. The RDBLOCK instruction is for reading the status of
protection lock of a specified block(or sector), using A23-A16 (or A23-A12) address bits to assign a 64K bytes block (4K
bytes sector) and read protection lock status bit which the first byte of Read-out cycle. The status bit is"1" to indicate
that this block has be protected, that user can read only but cannot write/program /erase this block. The status bit is
"0" to indicate that this block hasn't be protected, and user can read and write this block.
The sequence of issuing RDBLOCK instruction is: CS# goes low → send RDBLOCK (3Ch) instruction → send 3 address bytes to assign one block on SI pin → read block's protection lock status bit on SO pin → CS# goes high. (Please
refer to Figure 38)
(31) Gang Block Lock/Unlock (GBLK/GBULK)
These instructions are only effective after WPSEL was executed. The GBLK/GBULK instruction is for enable/disable
the lock protection block of the whole chip.
The WREN (Write Enable) instruction is required before issuing GBLK/GBULK instruction.
The sequence of issuing GBLK/GBULK instruction is: CS# goes low → send GBLK/GBULK (7Eh/98h) instruction →
CS# goes high. (Please refer to Figure 39)
The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed.
(32) Clear SR Fail Flags (CLSR)
The CLSR instruction is for resetting the Program/Erase Fail Flag bit of Security Register. It should be executed before program/erase another block during programming/erasing flow without read array data.
The sequence of issuing CLSR instruction is: CS# goes low → send CLSR instruction code → CS# goes high.
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
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(33) Read SFDP Mode (RDSFDP)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional
and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables
can be interrogated by host system software to enable adjustments needed to accommodate divergent features
from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on
CFI.
The sequence of issuing RDSFDP instruction is CS# goes low→send RDSFDP instruction (5Ah)→send 3 address
bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation can use CS#
to high at any time during data out.
SFDP is a standard of JEDEC. JESD216. v1.0.
Read Serial Flash Discoverable Parameter (RDSFDP) Sequence
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
SO
24 BIT ADDRESS
23 22 21
5Ah
3
2
1
0
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Cycle
SI
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
SO
7
6
5
4
3
2
1
0
7
MSB
MSB
P/N: PM1428
6
5
4
3
2
1
0
7
MSB
REV. 1.9, SEP. 06, 2013
36
MX25L12845E
Table a. Signature and Parameter Identification Data Values
Description
SFDP Signature
Comment
Fixed: 50444653h
Add (h) DW Add Data (h/b)
(Byte)
(Bit)
(Note1)
00h
07:00
53h
Data
(h)
53h
01h
15:08
46h
46h
02h
23:16
44h
44h
03h
31:24
50h
50h
SFDP Minor Revision Number
Start from 00h
04h
07:00
00h
00h
SFDP Major Revision Number
Start from 01h
05h
15:08
01h
01h
Number of Parameter Headers
Start from 01h
06h
23:16
01h
01h
07h
31:24
FFh
FFh
00h: it indicates a JEDEC specified
header.
08h
07:00
00h
00h
Start from 00h
09h
15:08
00h
00h
Start from 01h
0Ah
23:16
01h
01h
How many DWORDs in the
Parameter table
0Bh
31:24
09h
09h
0Ch
07:00
30h
30h
0Dh
15:08
00h
00h
0Eh
23:16
00h
00h
0Fh
31:24
FFh
FFh
it indicates Macronix manufacturer
ID
10h
07:00
C2h
C2h
Start from 00h
11h
15:08
00h
00h
Start from 01h
12h
23:16
01h
01h
How many DWORDs in the
Parameter table
13h
31:24
04h
04h
14h
07:00
60h
60h
15h
15:08
00h
00h
16h
23:16
00h
00h
17h
31:24
FFh
FFh
Unused
ID number (JEDEC)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
Parameter Table Pointer (PTP)
First address of JEDEC Flash
Parameter table
Unused
ID number
(Macronix manufacturer ID)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
Parameter Table Pointer (PTP)
First address of Macronix Flash
Parameter table
Unused
P/N: PM1428
REV. 1.9, SEP. 06, 2013
37
MX25L12845E
Table b. Parameter Table (0): JEDEC Flash Parameter Tables
Description
Comment
Block/Sector Erase sizes
00: Reserved, 01: 4KB erase,
10: Reserved,
11: not support 4KB erase
Write Granularity
Write Enable Instruction
Requested for Writing to Volatile
Status Registers
Add (h) DW Add Data (h/b)
(Byte)
(Bit)
(Note1)
01:00
01b
0: 1Byte, 1: 64Byte or larger
02
1b
0: Nonvolatitle status bit
1: Volatitle status bit
(BP status register bit)
03
0b
30h
0: use 50h opcode,
1: use 06h opcode
Write Enable Opcode Select for
Note: If target flash status register is
Writing to Volatile Status Registers
nonvolatile, then bits 3 and 4 must
be set to 00b.
Contains 111b and can never be
Unused
changed
4KB Erase Opcode
31h
Data
(h)
E5h
04
0b
07:05
111b
15:08
20h
16
0b
18:17
00b
19
1b
20
1b
20h
(1-1-2) Fast Read (Note2)
0=not support 1=support
Address Bytes Number used in
addressing flash array
Double Transfer Rate (DTR)
Clocking
00: 3Byte only, 01: 3 or 4Byte,
10: 4Byte only, 11: Reserved
(1-2-2) Fast Read
0=not support 1=support
(1-4-4) Fast Read
0=not support 1=support
21
1b
(1-1-4) Fast Read
0=not support 1=support
22
0b
23
1b
33h
31:24
FFh
37h:34h
31:00
07FFFFFFh
0=not support 1=support
32h
Unused
Unused
Flash Memory Density
(1-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
states (Note3)
Clocks) not support
(1-4-4) Fast Read Number of
000b: Mode Bits not support
Mode Bits (Note4)
38h
(1-4-4) Fast Read Opcode
39h
(1-1-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
states
Clocks) not support
(1-1-4) Fast Read Number of
000b: Mode Bits not support
Mode Bits
3Ah
(1-1-4) Fast Read Opcode
3Bh
P/N: PM1428
04:00
0 0100b
07:05
010b
15:08
EBh
20:16
0 0000b
23:21
000b
31:24
FFh
B8h
FFh
44h
EBh
00h
FFh
REV. 1.9, SEP. 06, 2013
38
MX25L12845E
Description
Comment
(1-1-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
states
Clocks) not support
(1-1-2) Fast Read Number of
000b: Mode Bits not support
Mode Bits
Add (h) DW Add Data (h/b)
(Byte)
(Bit)
(Note1)
3Ch
(1-1-2) Fast Read Opcode
3Dh
(1-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
states
Clocks) not support
(1-2-2) Fast Read Number of
000b: Mode Bits not support
Mode Bits
3Eh
(1-2-2) Fast Read Opcode
3Fh
(2-2-2) Fast Read
0=not support 1=support
Unused
(4-4-4) Fast Read
0=not support 1=support
40h
Unused
04:00
0 0000b
07:05
000b
15:08
0xFFh
20:16
0 0100b
23:21
000b
31:24
BBh
00
0b
03:01
111b
04
0b
07:05
111b
Data
(h)
00h
0xFFh
04h
BBh
EEh
Unused
43h:41h
31:08
0xFFh
0xFFh
Unused
45h:44h
15:00
0xFFh
0xFFh
20:16
0 000b
23:21
000b
(2-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
states
Clocks) not support
(2-2-2) Fast Read Number of
000b: Mode Bits not support
Mode Bits
46h
(2-2-2) Fast Read Opcode
47h
31:24
FFh
FFh
49h:48h
15:00
0xFFh
0xFFh
20:16
0 0000b
23:21
000b
Unused
00h
(4-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
states
Clocks) not support
(4-4-4) Fast Read Number of
000b: Mode Bits not support
Mode Bits
4Ah
(4-4-4) Fast Read Opcode
4Bh
31:24
FFh
FFh
4Ch
07:00
0Ch
0Ch
4Dh
15:08
20h
20h
4Eh
23:16
0Fh
0Fh
4Fh
31:24
52h
52h
50h
07:00
10h
10h
51h
15:08
D8h
D8h
52h
23:16
00h
00h
53h
31:24
FFh
FFh
Sector Type 1 Size
Sector/block size = 2^N bytes (Note5)
0x00b: this sector type doesn't exist
Sector Type 1 erase Opcode
Sector Type 2 Size
Sector/block size = 2^N bytes
0x00b: this sector type doesn't exist
Sector Type 2 erase Opcode
Sector Type 3 Size
Sector/block size = 2^N bytes
0x00b: this sector type doesn't exist
Sector Type 3 erase Opcode
Sector Type 4 Size
Sector/block size = 2^N bytes
0x00b: this sector type doesn't exist
Sector Type 4 erase Opcode
P/N: PM1428
00h
REV. 1.9, SEP. 06, 2013
39
MX25L12845E
Table c. Parameter Table (1): Macronix Flash Parameter Tables
Description
Comment
Add (h) DW Add Data (h/b)
(Byte)
(Bit)
(Note1)
Data
(h)
Vcc Supply Maximum Voltage
2000h=2.000V
2700h=2.700V
3600h=3.600V
61h:60h
07:00
15:08
00h
36h
00h
36h
Vcc Supply Minimum Voltage
1650h=1.650V
2250h=2.250V
2350h=2.350V
2700h=2.700V
63h:62h
23:16
31:24
00h
27h
00h
27h
HW Reset# pin
0=not support 1=support
00
0b
HW Hold# pin
0=not support 1=support
01
0b
Deep Power Down Mode
0=not support 1=support
02
1b
SW Reset
0=not support 1=support
03
0b
SW Reset Opcode
Reset Enable (66h) should be issued 65h:64h
before Reset command
11:04
1111 1111b
(FFh)
Program Suspend/Resume
0=not support 1=support
12
0b
Erase Suspend/Resume
0=not support 1=support
13
0b
14
1b
15
0b
66h
23:16
FFh
FFh
67h
31:24
FFh
FFh
Unused
Wrap-Around Read mode
0=not support 1=support
Wrap-Around Read mode Opcode
Wrap-Around Read data length
08h:support 8B wrap-around read
16h:8B&16B
32h:8B&16B&32B
64h:8B&16B&32B&64B
Individual block lock
0=not support 1=support
00
1b
Individual block lock bit
(Volatile/Nonvolatile)
0=Volatile 1=Nonvolatile
01
0b
09:02
0011 0110b
(36h)
10
0b
11
1b
Individual block lock Opcode
4FF4h
Individual block lock Volatile
protect bit default protect status
0=protect 1=unprotect
Secured OTP
0=not support 1=support
Read Lock
0=not support 1=support
12
0b
Permanent Lock
0=not support 1=support
13
0b
Unused
15:14
11b
Unused
31:16
0xFFh
0xFFh
31:00
0xFFh
0xFFh
Unused
6Bh:68h
6Fh:6Ch
P/N: PM1428
C8D9h
REV. 1.9, SEP. 06, 2013
40
MX25L12845E
Note 1: h/b is hexadecimal or binary.
Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x),
address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1), (2-2-2),
and (4-4-4)
Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits.
Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system controller
if they are specified. (eg,read performance enhance toggling bits)
Note 5: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h
Note 6: 0xFFh means all data is blank ("1b").
P/N: PM1428
REV. 1.9, SEP. 06, 2013
41
MX25L12845E
POWER-ON STATE
The device is at the following states after power-up:
- Standby mode ( please note it is not Deep Power-down mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage until the VCC reaches the following levels:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal Power-on Reset (POR) circuit may protect the device from data corruption and inadvertent data change
during power up state.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not
guaranteed. The read, write, erase, and program command should be sent after the time delay:
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.
Please refer to the figure of "Power-up Timing".
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended.
(generally around 0.1uF)
P/N: PM1428
REV. 1.9, SEP. 06, 2013
42
MX25L12845E
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
RATING
VALUE
Ambient Operating Temperature
Industrial grade
-40°C to 85°C
Storage Temperature
-65°C to 150°C
Applied Input Voltage
-0.5V to VCC+0.5V
Applied Output Voltage
-0.5V to VCC+0.5V
VCC to Ground Potential
-0.5V to 4.0V
NOTICE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is stress rating only and functional operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see Figure 2, 3.
Figure 3. Maximum Positive Overshoot Waveform
Figure 2. Maximum Negative Overshoot Waveform
20ns
20ns
20ns
Vss
Vcc + 2.0V
Vss-2.0V
Vcc
20ns
20ns
20ns
CAPACITANCE TA = 25°C, f = 1.0 MHz
Symbol Parameter
CIN
COUT
Min.
Typ.
Max.
Unit
Input Capacitance
20
pF
VIN = 0V
Output Capacitance
20
pF
VOUT = 0V
P/N: PM1428
Conditions
REV. 1.9, SEP. 06, 2013
43
MX25L12845E
Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL
Input timing reference level
0.8VCC
0.2VCC
0.7VCC
0.3VCC
Output timing reference level
AC
Measurement
Level
0.5VCC
Note: Input pulse rise and fall time are <5ns
Figure 5. OUTPUT LOADING
DEVICE UNDER
TEST
2.7K ohm
CL
6.2K ohm
+3.3V
DIODES=IN3064
OR EQUIVALENT
CL=30/15pF Including jig capacitance
P/N: PM1428
REV. 1.9, SEP. 06, 2013
44
MX25L12845E
Table 7. DC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V)
Symbol Parameter
Notes
Min.
Max.
Units Test Conditions
ILI
Input Load Current
1
±2
uA
VCC = VCC Max, VIN = VCC or GND
ILO
Output Leakage Current
1
±2
uA
VCC = VCC Max, VOUT=VCC or GND
ISB1
VCC Standby Current
1
100
uA
VIN = VCC or GND, CS# = VCC
ISB2
Deep Power-down
Current
40
uA
VIN = VCC or GND, CS# = VCC
22
mA
fQ=70MHz (4 x I/O read)
SCLK=0.1VCC/0.9VCC, SO=Open
19
mA
f=104MHz
SCLK=0.1VCC/0.9VCC, SO=Open
17
mA
fT=70MHz (2 x I/O read)
SCLK=0.1VCC/0.9VCC, SO=Open
15
mA
f=66MHz
SCLK=0.1VCC/0.9VCC, SO=Open
10
mA
f=33MHz,
SCLK=0.1VCC/0.9VCC, SO=Open
25
mA
Program in Progress, CS# = VCC
20
mA
Program status register in progress,
CS#=VCC
1
25
mA
Erase in Progress, CS#=VCC
1
20
mA
Erase in Progress, CS#=VCC
0.8
V
ICC1
VCC Read
VIL
VCC Program Current
(PP)
VCC Write Status
Register (WRSR) Current
VCC Sector Erase
Current (SE)
VCC Chip Erase Current
(CE)
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
ICC2
ICC3
ICC4
ICC5
1
1
-0.5
0.7VCC VCC+0.4
0.4
VCC-0.2
V
V
V
IOL = 1.6mA;
IOL = 140uA for parallel mode
IOH = -100uA;
IOH = 65uA for parallel mode
Notes :
1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds).
2. Typical value is calculated by simulation.
P/N: PM1428
REV. 1.9, SEP. 06, 2013
45
MX25L12845E
Table 8. AC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V)
Symbol
fSCLK
fRSCLK
fTSCLK
f4PP
Alt. Parameter
fC
Clock Frequency for the following
Serial
instructions: FAST_READ, RDSFDP, PP,
SE, BE, CE, DP, RES, RDP, WREN,
Parallel
WRDI, RDID, RDSR, WRSR
fR
fT
Clock Frequency for READ instructions
Clock Frequency for 2READ instructions
fQ
Clock Frequency for 4READ instructions
VCC=2.7V-3.6V
VCC=3.0V-3.6V
fC2 Clock Frequency for FASTDTRD instructions
fT2 Clock Frequency for 2DTRD instructions
fQ2 Clock Frequency for 4DTRD instructions
Clock Frequency for 4PP (Quad page program)
tCH(1)
tCLH Clock High Time
tCL(1)
tCLL Clock Low Time
tCLCH(2)
Clock Rise Time (3) (peak to peak)
tCHCL(2)
Clock Fall Time (3) (peak to peak)
tSLCH
tCHSL
tDVCH
tCHDX
tCHSH
tSHCH
tSHSL(3)
(2)
tSHQZ
tCLQV
Serial
Serial
Parallel
Serial
Serial
Parallel
Serial
Parallel
Serial
Parallel
tCSS CS# Active Setup Time (relative to SCLK)
CS# Not Active Hold Time (relative to SCLK)
Serial
tDSU Data In Setup Time
Parallel
Serial
tDH Data In Hold Time
Parallel
Serial
CS# Active Hold Time (relative to SCLK)
Parallel
CS# Not Active Setup Time (relative to SCLK)
Read
tCSH CS# Deselect Time
Write/Erase/
Program
2.7V-3.6V
Serial
tDIS Output Disable Time
3.0V-3.6V
Serial
Parallel
1 I/O
Loading: 15pF
Clock Low to Output Valid
2 I/O & 4 I/O
tV
VCC=2.7V~3.6V
2 I/O & 4 I/O
Loading: 30pF
Parallel
P/N: PM1428
Min.
Max.
Unit
D.C.
104
MHz
6
MHz
50
70
70
85
50
50
50
20
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
4.5
(Fast_Read)
9 (Read)
30
4.5
(Fast_Read)
9 (Read)
30
0.1
0.25
0.1
0.25
5
5
2
10
5
10
5
30
5
15
ns
ns
ns
ns
ns
ns
V/ns
V/ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
ns
10
ns
8
ns
20
9
9.5
12
70
ns
ns
ns
ns
ns
REV. 1.9, SEP. 06, 2013
46
MX25L12845E
Symbol
tCLQV2
tCLQX
tWHSL
tSHWL
tDP(2)
tRES1
(2)
tRES2(2)
tW
tBP
tPP
tSE
tBE
tBE
tCE
tWPS
tWSR
Alt. Parameter
Clock Low to Output Valid (DTR mode) 1 I/O, 2 I/O
tV2
VCC=2.7V~3.6V, Loading: 15pF
& 4 I/O
tHO Output Hold Time
Write Protect Setup Time
Write Protect Hold Time
CS# High to Deep Power-down Mode
CS# High to Standby Mode without Electronic
Signature Read
CS# High to Standby Mode with Electronic Signature
Read
Write Status Register Cycle Time
Byte-Program
Page Program Cycle Time
Sector Erase Cycle Time (4KB)
Block Erase Cycle Time (32KB)
Block Erase Cycle Time (64KB)
Chip Erase Cycle Time
Write Protection Selection Time
Write Security Register Time
Min.
Typ.
2
20
100
40
9
1.4
60
0.5
0.7
80
Max.
Unit
9.5
ns
10
ns
ns
ns
us
100
us
100
us
100
300
5
300
2
2
200
1
1
ms
us
ms
ms
s
s
s
ms
ms
Notes:
1. tCH + tCL must be greater than or equal to 1/ fC.
2. Value guaranteed by characterization, not 100% tested in production.
3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
P/N: PM1428
REV. 1.9, SEP. 06, 2013
47
MX25L12845E
Timing Analysis
Figure 6. Serial Input Timing
tSHSL
CS#
tCHSL
tSLCH
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
tCLCH
LSB
MSB
SI
High-Z
SO
Figure 7. Output Timing
CS#
tCH
SCLK
tCLQV
tCLQX
tCL
tCLQV
tCLQX
LSB
SO
SI
tSHQZ
ADDR.LSB IN
P/N: PM1428
REV. 1.9, SEP. 06, 2013
48
MX25L12845E
Figure 8. Serial Input Timing for Double Transfer Rate Mode
tSHSL
CS#
tSLCH
tCHSL
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tDVCH
tCHDX
tCHDX
tCLCH
LSB
MSB
SI
High-Z
SO
Figure 9. Serial Output Timing for Double Transfer Rate Mode
CS#
tCH
SCLK
tCLQV2
tCLQX
tCLQV2
tCLQV2
tCL
LSB
SO
SI
tSHQZ
tCLQX
ADDR.LSB IN
P/N: PM1428
REV. 1.9, SEP. 06, 2013
49
MX25L12845E
Figure 10. WP# Setup Timing and Hold Timing during WRSR when SRWD=1
WP#
tSHWL
tWHSL
CS#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCLK
01
SI
SO
High-Z
Figure 11. Write Enable (WREN) Sequence (Command 06)
CS#
0
1
2
3
4
5
6
6
7
7
SCLK
Command
SI
06
High-Z
SO
Figure 12. Write Disable (WRDI) Sequence (Command 04)
CS#
0
1
2
3
4
5
SCLK
Command
SI
SO
04
High-Z
P/N: PM1428
REV. 1.9, SEP. 06, 2013
50
MX25L12845E
Figure 13. Read Identification (RDID) Sequence (Command 9F)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
28 29 30 31
SCLK
Command
SI
9F
Manufacturer Identification
High-Z
SO
Device Identification
D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13
MSB
D3 D2 D1 D0
MSB
Figure 14. Read Status Register (RDSR) Sequence (Command 05)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
command
05
SI
SO
Status Register Out
High-Z
D7 D6 D5 D4 D3 D2 D1 D0
MSB
Figure 15. Write Status Register (WRSR) Sequence (Command 01)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI
SO
command
Status
Register In
01
D7 D6 D5 D4 D3 D2 D1 D0
MSB
High-Z
P/N: PM1428
REV. 1.9, SEP. 06, 2013
51
MX25L12845E
Figure 16. Read Data Bytes (READ) Sequence (Command 03)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
24 ADD Cycles
03
SI
A23 A22 A21
A3 A2 A1 A0
MSB
SO
Data Out 2
Data Out 1
High-Z
D7 D6 D5 D4 D3 D2 D1 D0 D7
MSB
MSB
Figure 17. Read at Higher Speed (FAST_READ) Sequence (Command 0B)
CS#
0
1
2
3
4
5
6
7
8
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
9 10
SCLK
Command
SI
SO
8 Dummy Cycles
24 ADD Cycles
0B
A23 A22 A21
A3 A2 A1 A0
Data Out 1
High-Z
Data Out 2
D7 D6 D5 D4 D3 D2 D1 D0 D7
MSB
Figure 18. Fast DT Read (FASTDTRD) Sequence (Command 0D)
CS#
7
0
SCLK
…
Command
SI/SIO0
8
0D
25
19
…
…
27
28
29
…
6 Dummy
Cycles
12 ADD Cycles
A23 A22
26
Data Out
1
Data Out
2
A1 A0
D7 D6 D5 D4 D3 D2 D1 D0 D7
SO/SIO1
P/N: PM1428
REV. 1.9, SEP. 06, 2013
52
MX25L12845E
Figure 19. 2 x I/O Read Mode Sequence (Command BB)
CS#
0
1
2
3
4
5
6
7
8
SCLK
…
Command
High Impedance
Data Out
2
Data Out
1
4 dummy
cycle
12 ADD Cycle
BB(hex)
SI/SIO0
SO/SIO1
18 19 20 21 22 23 24 25 26 27 28 29
9
A22 A20
…
A2 A0 P2 P0
D6 D4 D2 D0 D6 D4
A23 A21
…
A3 A1 P3 P1
D7 D5 D3 D1 D7 D5
Note: SI/SIO0 or SO/SIO1 should be kept "0h" or "Fh" in the first two dummy cycles. In other words, P2=P0 or
P3=P1 is necessary.
Figure 20. Fast Dual I/O DT Read (2DTRD) Sequence (Command BD)
CS#
0
SCLK
SI/SIO0
SO/SIO1
7
8
13
14
19
…
…
…
Command
6 ADD Cycles
6 Dummy
Cycles
BD
20
Data Out
1
21
22
Data Out
2
23
…
A22 A20
…
A2 A0 P2 P0
D6 D4 D2 D0 D6 D4 D2 D0 D6
A23 A21
…
A3 A1 P3 P1
D7 D5 D3 D1 D7 D5 D3 D1 D7
Note: SI/SIO0 or SO/SIO1 should be kept "0h" or "Fh" in the first two dummy cycles. In other words, P2=P0 or
P3=P1 is necessary.
P/N: PM1428
REV. 1.9, SEP. 06, 2013
53
MX25L12845E
Figure 21. 4 x I/O Read Mode Sequence (Command EB)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
SCLK
Command
EB
SI/SIO0
High Impedance
SO/SIO1
High Impedance
WP#/SIO2
High Impedance
NC/SIO3
6 ADD Cycles
4 dummy
cycles
Performance
Enhance
Indicator
(Note1, 2)
Data Data
Out 1 Out 2
Data
Out 3
A20 A16 A12 A8 A4 A0
P4 P0
D4 D0 D4 D0 D4
A21 A17 A13 A9 A5 A1
P5 P1
D5 D1 D5 D1 D5
A22 A18 A14 A10 A6 A2
P6 P2
D6 D2 D6 D2 D6
A23 A19 A15 A11 A7 A3
P7 P3
D7 D3 D7 D3 D7
Notes:
1. Hi-impedance is inhibited for the two clock cycles.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) will result in entering the performance enhance mode.
Figure 22. 4 x I/O Read Enhance Performance Mode Sequence (Command EB)
CS#
0 1
SCLK
SI/SIO0
SO/SIO1
WP#/SIO2
NC/SIO3
6
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
n+1
…
…
… n+9 …
n+7
n+13
…
…
4 dummy
cycles
Command
6 ADD Cycles
EB
A20 A16 A12 A8 A4 A0
P4 P0
D4 D0 D4 D0
A20
…
A0
P4 P0
D4 D0 D4 D0 D4
A21 A17 A13 A9 A5 A1
P5 P1
D5 D1 D5 D1
A21
…
A1
P5 P1
D5 D1 D5 D1 D5
A22 A18 A14 A10 A6 A2
P6 P2
D6 D2 D6 D2
A22
…
A2
P6 P2
D6 D2 D6 D2 D6
A23 A19 A15 A11 A7 A3
P7 P3
D7 D3 D7 D3
A23
…
A3
P7 P3
D7 D3 D7 D3 D7
High Impedance
High Impedance
High Impedance
Performance
enhance
indicator (Note)
Data Data
Out 1 Out 2
6 ADD
Cycles
Performance
enhance
indicator (Note)
4 dummy
cycles
Data Data
Out 1 Out 2
Data
Out 3
Notes:
1. Performance enhance mode: if P7≠P3 & P6≠P2 & P5≠P1 & P4≠P0 (Toggling), ex: A5, 5A, F0, 0F.
2. Reset the performance enhance mode: if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 55, 00, FF.
P/N: PM1428
REV. 1.9, SEP. 06, 2013
54
MX25L12845E
Figure 23. Fast Quad I/O DT Read (4DTRD) Sequence (Command ED)
CS#
0
7
SCLK
8
9
10
11
18
…
19
20
…
Command
1 cycle
3 ADD Cycles
Performance
Enhance Indicator
(Note1,2)
7 Dummy
cycles
A20 A16
…
A4 A0
P4 P0
D4 D0 D4 D0 D4
SO/SIO1
A21 A17
…
A5 A1 P5 P1
D5 D1 D5 D1 D5
WP#/SIO2
A22 A18
…
A6 A2
P6 P2
D6 D2 D6 D2 D6
NC/SIO3
A23 A19
…
A7 A3 P7
P3
D7 D3 D7 D3 D7
SI/SIO0
ED
Notes:
1. Hi-impedance is inhibited for this clock cycle.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) will result in entering the performance enhance mode.
Figure 24. Fast Quad I/O DT Read (4DTRD) Enhance Performance Sequence (Command ED)
CS#
0
SCLK
7
9
10
11
18
ED (hex)
19
20
…
…
Command
SI/SIO0
8
3 ADD Cycles
A20 A16
…
…
1 cycle
Performance
enhance
indicator (Note)
…
7 Dummy Data Out Data Out
cycles
1
2
…
3 ADD Cycles
A4 A0 P4 P0
D4 D0 D4 D0
A20 A16
A5 A1 P5 P1
D5 D1 D5 D1
A21 A17
…
…
1 cycle
Performance
enhance
indicator (Note)
7 Dummy Data Out Data Out
cycles
1
2
…
A4 A0 P4 P0
D4 D0 D4 D0 D4
A5 A1 P5 P1
D5 D1 D5 D1 D5
SO/SIO1
A21 A17
WP#/SIO2
A22 A18
…
A6 A2 P6 P2
D6 D2 D6 D2
A22 A18
…
A6 A2 P6 P2
D6 D2 D6 D2 D6
NC/SIO3
A23 A19
…
A7 A3 P7 P3
D7 D3 D7 D3
A23 A19
…
A7 A3 P7 P3
D7 D3 D7 D3 D7
Note: Performance enhance, if P7≠P3 & P6≠P2 & P5≠P1 & P4≠P0 (Toggle)
P/N: PM1428
REV. 1.9, SEP. 06, 2013
55
MX25L12845E
Figure 25. Sector Erase (SE) Sequence (Command 20)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
…
24 ADD Cycles
Command
SI
…
A23 A22
20
A2 A1 A0
MSB
Figure 26. Block Erase (BE/BE32K) Sequence (Command D8/52)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
24 ADD Cycles
Command
SI
D8/52
A23 A22
A2 A1 A0
MSB
Figure 27. Chip Erase (CE) Sequence (Command 60 or C7)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
60 or C7
P/N: PM1428
REV. 1.9, SEP. 06, 2013
56
MX25L12845E
Figure 28. Page Program (PP) Sequence (Command 02)
2079
2078
2077
2076
2075
2074
28 29 30 31 32 33 34 35 36 37 38 39
2073
0 1 2 3 4 5 6 7 8 9 10
2072
CS#
SCLK
Command
24 ADD Cycles
A23 A22 A21
02
SI
A3 A2 A1 A0
Data Byte 1
Data Byte 256
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
MSB
MSB
Figure 29. 4 x I/O Page Program (4PP) Sequence (Command 38)
CS#
0
1
2
3
4
5
6
7
8
524 525
9 10 11 12 13 14 15 16 17
SCLK
…
Command
6 ADD cycles
Data
Byte 256
Data Data
Byte 1 Byte 2
A20 A16 A12 A8 A4 A0 D4 D0 D4 D0
…
D4 D0
SO/SIO1
A21 A17 A13 A9 A5 A1 D5 D1 D5 D1
…
D5 D1
WP#/SIO2
A22 A18 A14 A10 A6 A2 D6 D2 D6 D2
…
D6 D2
NC/SIO3
A23 A19 A15 A11 A7 A3 D7 D3 D7 D3
…
D7 D3
SI/SIO0
38
P/N: PM1428
REV. 1.9, SEP. 06, 2013
57
MX25L12845E
Figure 30. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD)
CS#
0 1
6 7 8 9
30 31 31 32
47 48
0 1
6 7 8
20 21 22 23 24
0
7
0
7 8
SCLK
Command
SI
S0
AD (hex)
24-bit address
data in
Byte 0, Byte1
Valid
Command (1)
high impedance
data in
Byte n-1, Byte n
04 (hex)
05 (hex)
status (2)
Notes:
(1) During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR command
(05 hex), and RDSCUR command (2B hex).
(2) Once an internal programming operation begins, CS# goes low will drive the status on the SO pin and CS#
goes high will return the SO pin to tri-state.
(3) To end the CP mode, either reaching the highest unprotected address or sending Write Disable (WRDI) command (04 hex) may achieve it and then it is recommended to send RDSR command (05 hex) to verify if CP
mode is ended.
P/N: PM1428
REV. 1.9, SEP. 06, 2013
58
MX25L12845E
Figure 31-1. Enter Parallel Mode (ENPLM) Sequence (Command 55)
CS#
1
0
2
3
4
5
6
7
SCLK
Command
SI
55
High-Z
SO
Figure 31-2. Exit Parallel Mode (EXPLM) Sequence (Command 45)
CS#
1
0
2
3
4
5
6
7
SCLK
Command
SI
45
High-Z
SO
Figure 31-3. Parallel Mode Read Identification (Parallel RDID) Sequence (Command 9F)
CS#
0
1
2
3
4
5
6
7
8
9
10
SCLK
Command
SI
9F
Device Identification
PO7~0
High-Z
Manufacturer Identification
Note: There are 3 data bytes which would be output sequentially for Manufacturer and Device ID 1'st byte (Memory
Type) and Device ID 2'nd byte (Memory Density).
P/N: PM1428
REV. 1.9, SEP. 06, 2013
59
MX25L12845E
Figure 31-4. Parallel Mode Read Electronic Manufacturer & Device ID (Parallel REMS) Sequence (Command
90)
CS#
0
1
2
3
4
5
6
7
8
9 10
SCLK
Command
SI
90
28 29 30 31 32 33
24 ADD Cycles
A23 A22 A21
A3 A2 A1 A0
Device Identification
High-Z
PO7~0
Manufacturer Identification
Note: A0=0 will output the Manufacturer ID first and A0=1 will output Device ID first. A1~A23 don't care.
Figure 31-5. Parallel Mode Release from Deep Power-down (RDP) and Read Electronic Signature (RES) Sequence
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38
SCLK
Instruction
SI
PO7~0
AB
tRES2
24 ADD Cycles
A23 A22 A21
A3 A2 A1 A0
Electronic Signature Out
High Impedance
Byte Output
Deep Power-down Mode
Stand-by Mode
Note: Under parallel mode, the fastest access clock freg. will be changed to 6MHz(SCLK pin clock freg.)
To release from Deep Power-down mode and read ID in parallel mode, which requires a parallel mode command (55h) before the read status register command.
To exit parallel mode, it requires a (45h) command or power-off/on sequence.
P/N: PM1428
REV. 1.9, SEP. 06, 2013
60
MX25L12845E
Figure 31-6. Parallel Mode Read Array (Parallel READ) Sequence (Command 03)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33
SCLK
n-1 n
…
Command
SI
24 ADD Cycles
03
A23 A22 A21
… A3
A2 A1 A0
MSB
High-Z
PO7~0
…
D0~D7 D0~D7
Byte 1 Byte 2
D0~D7 D0~D7
Byte n-1 Byte n
Figure 31-7. Parallel Mode Page Program (Parallel PP) Sequence (Command 02)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34
SCLK
286 287
…
Command
24 ADD Cycles
02
SI
A23 A22 A21
A3 A2 A1 A0
MSB
High-Z
PO7~0
…
MSB
Data Byte1 Data Byte3
Data Byte255
Data Byte2
Data Byte256
Figure 32. Deep Power-down (DP) Sequence (Command B9)
CS#
0
1
2
3
4
5
6
tDP
7
SCLK
Command
SI
B9
Stand-by Mode
P/N: PM1428
Deep Power-down Mode
REV. 1.9, SEP. 06, 2013
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MX25L12845E
Figure 33. Read Electronic Signature (RES) Sequence (Command AB)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
SI
tRES2
24 ADD Cycles
AB
A23 A22 A21
… A3
A2 A1 A0
MSB
Electronic Signature Out
High-Z
SO
D7 D6 D5 D4 D3 D2 D1 D0
MSB
Deep Power-down Mode
Stand-by Mode
Figure 34. Release from Deep Power-down (RDP) Sequence (Command AB)
CS#
0
1
2
3
4
5
6
tRES1
7
SCLK
Command
SI
SO
AB
High-Z
Deep Power-down Mode
P/N: PM1428
Stand-by Mode
REV. 1.9, SEP. 06, 2013
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MX25L12845E
Figure 35. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF or CF)
CS#
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Command
SI
SO
90
24 ADD Cycles
A3 A2 A1 A0
A23 A22 A21
Manufacturer ID
High-Z
Device ID
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
MSB
MSB
MSB
Notes:
1. A0=0 will output the Manufacturer ID first and A0=1 will output Device ID first. A1~A23 is don't care.
2. Instruction is either 90(hex) or EF(hex) or DF(hex) or CF(hex).
Figure 36. Write Protection Selection (WPSEL) Sequence (Command 68)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
68
P/N: PM1428
REV. 1.9, SEP. 06, 2013
63
MX25L12845E
Figure 37. Single Block Lock/Unlock Protection (SBLK/SBULK) Sequence (Command 36/39)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
24 Bit Address
Cycles
Command
SI
36/39
A23 A22
A2 A1 A0
MSB
Figure 38. Read Block Protection Lock Status (RDBLOCK) Sequence (Command 3C)
CS#
0
1
2
3
4
5
6
7
8
28 29 30 31 32 33 34 35 36 37 38 39
9 10
SCLK
Command
SI
3C
24 ADD Cycles
A23 A22 A21
A3 A2 A1 A0
MSB
SO
Block Protection Lock status out
High-Z
D7 D6 D5 D4 D3 D2 D1 D0
MSB
Figure 39. Gang Block Lock/Unlock (GBLK/GBULK) Sequence (Command 7E/98)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
7E/98
P/N: PM1428
REV. 1.9, SEP. 06, 2013
64
MX25L12845E
Figure 40. Power-up Timing
VCC
VCC(max)
Chip Selection is Not Allowed
VCC(min)
tVSL
Device is fully accessible
time
Note: VCC (max.) is 3.6V and VCC (min.) is 2.7V.
Table 9. Power-Up Timing
Symbol
tVSL(1)
Parameter
VCC(min) to CS# low
Min.
300
Max.
Unit
us
Note: The parameter is characterized only.
INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 00h (all Status Register bits are 0).
P/N: PM1428
REV. 1.9, SEP. 06, 2013
65
MX25L12845E
OPERATING CONDITIONS
At Device Power-Up and Power-Down
AC timing illustrated in Figure 41 and Figure 42 are for the supply voltages and the control signals at device powerup and power-down. If the timing in the figures is ignored, the device will not operate correctly.
During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be
selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.
Figure 41. AC Timing at Device Power-Up
VCC
VCC(min)
GND
tVR
tSHSL
CS#
tSLCH
tCHSL
tSHCH
tCHSH
SCLK
tDVCH
tCHCL
tCHDX
LSB IN
MSB IN
SI
High Impedance
SO
Symbol
tVR
tCLCH
Parameter
VCC Rise Time
Notes
1
Min.
20
Max.
500000
Unit
us/V
Notes :
1. Sampled, not 100% tested.
2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to
"AC CHARACTERISTICS" table.
P/N: PM1428
REV. 1.9, SEP. 06, 2013
66
MX25L12845E
Figure 42. Power-Down Sequence
During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.
VCC
CS#
SCLK
P/N: PM1428
REV. 1.9, SEP. 06, 2013
67
MX25L12845E
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Write Status Register Cycle Time
Sector Erase Time (4KB)
Block Erase Time (64KB)
Block Erase Time (32KB)
Chip Erase Time
Byte Program Time (via page program command)
Page Program Time
Erase/Program Cycle
Typ. (1)
40
60
0.7
0.5
80
9
1.4
100,000
Max. (2)
100
300
2
2
200
300
5
Unit
ms
ms
s
s
s
us
ms
cycles
Notes:
1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and checkerboard pattern.
2. Under worst conditions of 85°C and 2.7V.
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command.
DATA RETENTION
Parameter
Condition
Min.
Data retention
55˚C
20
Max.
Unit
years
LATCH-UP CHARACTERISTICS
Input Voltage with respect to GND on all power pins, SI, CS#
Input Voltage with respect to GND on SO
Current
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
P/N: PM1428
Min.
-1.0V
-1.0V
-100mA
Max.
2 VCCmax
VCC + 1.0V
+100mA
REV. 1.9, SEP. 06, 2013
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MX25L12845E
ORDERING INFORMATION
CLOCK
(MHz)
TEMPERATURE
MX25L12845EMI-10G
104
-40°C~85°C
MX25L12845EZNI-10G
104
-40°C~85°C
PART NO.
P/N: PM1428
PACKAGE
Remark
16-SOP
(300mil)
8-WSON
(8x6mm)
RoHS
Compliant
RoHS
Compliant
REV. 1.9, SEP. 06, 2013
69
MX25L12845E
PART NAME DESCRIPTION
MX 25
L 12845E
M
I
10 G
OPTION:
G: RoHS Compliant & Halogen-free
SPEED:
10: 104MHz
TEMPERATURE RANGE:
I: Industrial (-40° C to 85° C)
PACKAGE:
M: 300mil 16-SOP
ZN: 8x6mm 8-WSON
DENSITY & MODE:
12845E: 128Mb standard type
TYPE:
L: 3V
DEVICE:
25: Serial Flash
P/N: PM1428
REV. 1.9, SEP. 06, 2013
70
MX25L12845E
PACKAGE INFORMATION
P/N: PM1428
REV. 1.9, SEP. 06, 2013
71
MX25L12845E
P/N: PM1428
REV. 1.9, SEP. 06, 2013
72
MX25L12845E
REVISION HISTORY
Revision No. Description
Page
Date
1.0
1. Removed "Preliminary"
P5
MAY/19/2009
2. Merge MX25L6445E and MX25L12845E together
All
3. Add CFI mode content
P37
4. Align waveform format
All
5. Modify tCH/tCL value, from rev0.06 tCH/tCL=5.5ns
P43,45
to rev1.0 tCH/tCL(FAST_READ/READ)=4.5/9ns
6. Change command table format
P15,16
7. Added "DATA RETENTION" Condition
P66
8. Modified sector erase time from 90ms to 60ms
P5,43,46,
P66
9. Modified 128Mb chip erase time (max) from 512s to 200s
P46,66
1.1
1. Added 128M 8-WSON EPN
P67
JUL/16/2009
2. Change RDCFI command from A5 to 5A
P16,37
1.2
1. Added DMC Code content table
P37~39
OCT/21/2009
2. Removed MX25L12845EZNI-10G advanced information remark
P69
3. Changed the naming "CFI mode" as "DMC mode"
All
1.3
1. Corrected error
P8,43,44,54 APR/01/2010
P68
2. Added wording "e.g. Vcc and CS# ramp up simultaneously"
P67
3. Modified low active read and standby current consumption
P5,43~44,69
and deep power down current consumption
4. Deleted parallel mode condition
P43
5. Modified table of "Read DMC mode (RDDMC)"
P37~39
6. Added "Input Test Waveforms And Measurement Level"
P42
7. Modified tSLCH, tSHCH from 8ns to 5ns
P45,47
1.4
1. Removed DMC sequence description & content table
P6,14,16,37 JUL/14/2010
2. Revised low active read current spec
P5
3. Revised Table 7-1 and Table 7-2
P40~41
1.5
1. Removed MX25L6445E information from the previous combined
All
AUG/15/2011
version of MX25L6445E/MX25L12845E
2. Modified description for RoHS compliance
P6,63,64
3. Revised Figure 18. Fast DT Read (FASTDTRD) Sequence
P46,47,49
Figure 20. Fast Dual I/O DT Read (2DTRD) Sequence;
Figure 23. Fast Quad I/O DT Read (4DTRD) Sequence; and
Figure 24. Fast Quad I/O DT Read (4DTRD) Enhance Performance.
4. Corrected ILO TEST CONDITIONS in Table 7
P39
5. Revised Storage Temperature
P37
6. Revised CP mode completion method descriptions
P26
7. Revised DEVICE OPERATION descriptions
P13
1.6
1. Added Quad I/O Read Frequency: 85MHz@VCC=3.0V~3.6V
P40
SEP/13/2011
1.7
1. Revised the description in The individual block lock mode
P31
OCT/05/2011
1.8
1. Modified Input Capacitance & Output Capacitance
P43
FEB/10/2012
2. Modified Figure 42. Power-Down Sequence
P67
3. Changed ordering information format
P69
4. Added Read SFDP (RDSFDP) Mode
P6,13,14,
P36~41,46
1.9
1. Modified ABSOLUTE MAXIMUM RATINGS table
P43
SEP/06/2013
P/N: PM1428
REV. 1.9, SEP. 06, 2013
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MX25L12845E
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