Holtek HT36A0 8-bit music synthesizer mcu Datasheet

HT36A0
8-Bit Music Synthesizer MCU
Features
· Operating voltage: 3.6V~5.0V
· Polyphonic up to 16 notes
· Operating frequency: 3.58MHz~12MHz
· Independent pan and volume mix can be assigned to
(typ. 11.059MHz)
each sound component
· 28 bidirectional I/O lines
· Sampling rate of 44.1kHz as 11.059MHz for system
frequency
· Two 16-bit programmable timer/event counters with
· Eight-level subroutine nesting
overflow interrupts
· Watchdog Timer
· HALT function and wake-up feature to reduce power
consumption
· Built-in 8-bit MCU with 208´8 bits RAM
· Bit manipulation instructions
· Built-in 64K´16-bit ROM for program/data shared
· 16-bit table read instructions
· Digital output pins for external DAC
· 63 powerful instructions
· Single data format with 16 bits digital stereo audio
· All instructions in 1 or 2 machine cycles
output
· 48-pin SSOP package
· Two High D/A converter resolution: 16 bits
General Description
The HT36A0 has a built-in 8-bit microprocessor which
programs the synthesizer to generate the melody by
setting the special register from 20H~2AH. A HALT feature is provided to reduce power consumption.
The HT36A0 is an 8-bit high performance RISC-like
microcontroller specifically designed for music applications. It provides an 8-bit MCU and a 16 channel
wavetable synthesizer. The program ROM is composed
of both program control codes and wavetable voice
codes, and can be easily programmed.
Block Diagram
P A
P B
P C
P D
0 ~
0 ~
0 ~
0 ~
P A
P B
P C
P D
3
7
7
7
O S C 1
O S C 2
R E S
P F 0 ~ 2
8 - B it
M C U
2 0 8 ´ 8
R A M
M u ltip lie r /P h a s e
G e n e ra l
1
D
S
D A
S A
1 6 - B it
D A C
R C H
1 6 - B it
D A C
L C H
P D 3 /D C L K
P D 2 /L O A D
P D 1 /D O U T
Rev. 1.20
V D
V S
V D
V S
6 4 K ´ 1 6 - b it
R O M
June 18, 2003
HT36A0
Pin Assignment
N C
1
4 8
N C
O S C 1
2
4 7
O S C 2
V S S
3
4 6
V D D A
V S S
4
4 5
L C H
V D D
5
4 4
R C H
N C
6
4 3
V S S A
N C
7
4 2
N C
P A 0
8
4 1
R E S
P A 1
9
4 0
P D 3
P A 2
1 0
3 9
P D 2
P A 3
1 1
3 8
P D 1
P A 4
1 2
3 7
P D 0
P A 5
1 3
3 6
P C 7
P A 6
1 4
3 5
P C 6
P A 7
1 5
3 4
P C 5
P B 0
1 6
3 3
P C 4
P B 1
1 7
3 2
N C
N C
1 8
3 1
N C
P B 2
1 9
3 0
P C 3
P B 3
2 0
2 9
P C 2
P B 4
2 1
2 8
P C 1
P B 5
2 2
2 7
P C 0
P B 6
2 3
2 6
P B 7
N C
2 4
2 5
N C
H T 3 6 A 0
4 8 S S O P -A
Pad Assignment
V S S
V S S
V D D
O S C 1
O S C 2
V D D A
L C H
R C H
V S S A
3 8
3 5
3 4
3 3
3 2
3 1
3 0
3 7 3 6
P A 0
1
2 9
R E S
P A 1
2
2 8
P D 3
2 7
P D 2
2 6
P D 1
2 5
P D 0
2 4
P C 7
2 3
P C 6
2 2
P C 5
2 1
P C 4
P A 2
3
P A 3
4
P A 4
P A 5
(0 , 0 )
5
6
P A 6
7
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
P C 1
P C 2
P C 3
1 2
P C 0
1 1
P B 7
1 0
P B 6
P B 1
P B 5
9
P B 4
P B 0
P B 3
8
P B 2
P A 7
Chip size: 120.5 ´ 124.4 (mil)
* The IC substrate should be connected to VSS in the PCB layout artwork.
Rev. 1.20
2
June 18, 2003
HT36A0
Pad Coordinates
Unit: mm
Pad No.
X
Y
Pad No.
X
Y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
-1365.58
-1365.58
-1365.58
-1365.58
-1365.58
-1365.58
-1365.58
-1365.58
-1365.58
-1365.58
-1062.50
-802.90
-543.30
-283.70
-24.10
235.50
495.10
754.70
1014.30
1008.20
748.60
489.00
229.40
-30.2
-289.80
-549.40
-809.00
-1068.60
-1328.20
-1415.28
-1415.28
-1415.28
-1415.28
-1415.28
-1415.28
-1415.28
-1415.28
-1415.28
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
1273.90
1367.30
1367.30
1367.30
1367.30
1367.30
1367.30
1367.30
1367.30
1367.30
1172.575
965.075
705.475
497.925
349.436
-328.416
-481.370
-611.375
-741.385
-1415.28
-1106.75
-847.15
-587.55
-327.95
-68.35
191.25
450.85
710.45
970.05
1414.78
1414.78
1414.78
1414.78
1396.935
1396.935
1368.13
1368.13
1368.13
Pad Description
Pad No.
Pad Name
I/O
Internal
Connection
Function
1~8
PA0~PA7
I/O
Pull-High
or None
Bidirectional 8-bit Input/Output port, wake-up by mask option
9~16
PB0~PB7
I/O
Pull-High
or None
Bidirectional 8-bit Input/Output port
17~24
PC0~PC7
I/O
Pull-High
or None
Bidirectional 8-bit Input/Output port
25
PD0
I/O
Pull-High
or None
Bidirectional 8-bit Input/Output port
26
PD1/DOUT
I/O
Pull-High
or None
Bidirectional 8-bit Input/Output port DAC data out
27
PD2/LOAD
I/O
Pull-High
or None
Bidirectional 8-bit Input/Output port DAC word clock
28
PD3/DCLK
I/O
Pull-High
or None
Bidirectional 8-bit Input/Output port DAC bit clock
29
RES
I
¾
Reset input, active low
30
VSSA
¾
¾
Negative power supply of DAC, ground
31
RCH
O
CMOS
R channel audio output
32
LCH
O
CMOS
L channel audio output
33
VDDA
¾
¾
DAC power supply
35
34
OSC1
OSC2
I
O
¾
OSC1 and OSC2 are connected to an RC network or a crystal (by
mask option) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/8 system clock. The system
clock may come from the crystal, the two pins cannot be floating.
36, 37
VSS
¾
¾
Negative power supply, ground
38
VDD
¾
¾
Positive power supply
Rev. 1.20
3
June 18, 2003
HT36A0
Absolute Maximum Ratings
Supply Voltage ...........................................-0.3V to 6V
Storage Temperature ...........................-50°C to 125°C
Input Voltage .............................VSS-0.3V to VDD+0.3V
Operating Temperature ..........................-25°C to 70°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol
Ta=25°C
Test Conditions
Parameter
VDD
Conditions
Min.
Typ.
Max.
Unit
VDD
Operating Voltage
¾
¾
3.6
5
6
V
IDD
Operating Current
5V
No load
fOSC=11.0592MHz
¾
8
16
mA
ISTB
Standby Current (WDT Disabled)
5V
No load
System HALT
¾
0
¾
mA
IOL
I/O Ports Sink Current
5V
VOL=0.5V
9.7
16.2
¾
mA
IOH
I/O Ports Source Current
5V
VOH=4.5V
-5.2
-8.7
¾
mA
RPH
Pull-High Resistance of I/O Ports
5V
VIL=0V
11
22
44
kW
VIH1
Input High Voltage for I/O Ports
5V
¾
3.5
¾
5
V
VIL1
Input Low Voltage for I/O Ports
5V
¾
0
¾
1.5
V
VIH2
Input High Voltage (RES)
5V
¾
¾
4
¾
V
VIL2
Input Low Voltage (RES)
5V
¾
¾
2.5
¾
V
Min.
Typ.
Max.
Unit
¾
12
¾
MHz
A.C. Characteristics
Symbol
Parameter
Test Conditions
Conditions
VDD
MCU interface
fOSC
System Frequency
5V
fSYS
System Clock
5V
¾
4
¾
16
MHz
tWDT
Watchdog Time-Out Period (RC)
¾
Without WDT prescaler
9
17
35
ms
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
Symbol
Parameter
12MHz crystal
Figure
Min.
Typ.
Max.
Unit
DAC interface
fBC
DCK Bit Clock Frequency
Fig 1
¾
fSYS/16
¾
MHz
tCH
DCK Bit Clock H Level Time
Fig 1
600
¾
¾
ns
tDOS
Data Output Setup Time
Fig 1
200
¾
¾
ns
tDOH
Data Output Hold Time
Fig 1
200
¾
¾
ns
tLCS
Load Clock Setup Time
Fig 1
200
¾
¾
ns
tLCH
Load Clock Hold Time
Fig 1
200
¾
¾
ns
Rev. 1.20
4
June 18, 2003
HT36A0
1 /fB
C
D C K
tC
V
O H
V
O L
H
tD
O S
tD
IIS
O H
V
O H
V
O L
V
O H
V
O L
L S B
tL
tL
C H
C S
L O A D
Fig 1. Audio output timing
Characteristics Curves
V vs F Characteristics Curve
H T 3 6 A 0 V v s F C h a rt
1 3 .0
1 2 .5
F re q u e n c y (M H z )
1 2 .0
R = 4 9 k W
1 1 .5
R = 5 1 k W
1 1 .0
R = 5 3 k W
1 0 .5
1 0 .0
9 .5
9 .0
3 .1
3 .4
3 .7
4
4 .3
H T 3 6 A 0 R
4 .6
4 .9
5 .2
5 .5
V o lta g e ( V )
v s F C h a rt
1 5
1 4
1 3
F re q u e n c y (M H z )
1 2
1 1
1 0
9
8
V 3 = 5 .0 V
7
V 2 = 4 .5 V
6
5
4
Rev. 1.20
4 3
6 8
5 6
5
7 5
k W
June 18, 2003
HT36A0
Function Description
When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from
subroutine, the PC manipulates the program transfer by
loading the address corresponding to each instruction.
Execution Flow
The system clock for the HT36A0 is derived from either
a crystal or an RC oscillator. The oscillator frequency divided by 2 is the system clock for the MCU and it is internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
The conditional skip is activated by instruction. Once the
condition is met, the next instruction, fetched during the
current instruction execution, is discarded and a dummy
cycle replaces it to retrieve the proper instruction. Otherwise proceed with the next instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruction to effectively execute in one cycle. If an instruction
changes the program counter, two cycles are required
to complete the instruction.
The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.
Program Counter - PC
Once a control transfer takes place, an additional
dummy cycle is required.
The 13-bit program counter (PC) controls the sequence
in which the instructions stored in program ROM are executed and its contents specify a maximum of 8192 addresses for each bank.
Program ROM
HT36A0 provides 16 address lines WA[15:0] to read the
Program ROM which is up to 1M bits, and is commonly
used for the wavetable voice codes and the program
memory. It provides two address types, one type is for
program ROM, which is addressed by a bank pointer
PF2~0 and a 13-bit program counter PC 12~0; and the
After accessing a program memory word to fetch an instruction code, the contents of the program counter are
incremented by one. The program counter then points
to the memory word containing the next instruction
code.
S y s te m C lo c k o f M C U
( S y s te m C lo c k /2 )
T 1
T 2
T 3
T 4
T 1
T 2
P C
P C
T 3
T 4
T 1
T 2
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
T 3
T 4
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution flow
Mode
Program Counter
*12
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Timer/Event Counter 0 Overflow
0
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter 1 Overflow
0
0
0
0
0
0
0
0
0
1
1
0
0
Loading PCL
*12
*11
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#12
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return From Subroutine
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Skip
PC+2
Program counter
Note:
*12~*0: Bits of Program Counter
S12~S0: Bits of Stack Register
@7~@0: Bits of PCL
@7~@0: Bits of PCL
#12~#0: Bits of Instruction Code
Rev. 1.20
6
June 18, 2003
HT36A0
0 0 0 0 H
other type is for wavetable code, which is addressed by
the start address ST15~0. On the program type,
WA15~0= PF2~0 ´ 213+ PC12~0. On the wave table
ROM type, WA15~0=ST15~0 ´ 25.
0 0 0 8 H
0 0 0 C H
Program Memory - ROM
D e v ic e in itia liz a tio n p r o g r a m
T im e r /e v e n t C o u n te r 0 in te r r u p t s u b r o u tin e
T im e r /e v e n t C o u n te r 1 in te r r u p t s u b r o u tin e
n 0 0 H
The program memory is used to store the program instructions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
8192´16 bits, addressed by the bank pointer, program
counter and table pointer.
n F F H
L o o k - u p ta b le ( 2 5 6 w o r d s )
1 F F F H
Certain locations in the program memory of each bank
are reserved for special usage:
1 6 b its
N o te : n ra n g e s fro m
· Location 000H on bank0
0 0 to 1 F .
Program memory for each bank
This area is reserved for the initialization program. After chip reset, the program always begins execution at
location 000H on bank0.
be placed in TBLP. The TBLH is read only and cannot
be restored. If the main routine and the ISR (Interrupt
Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are
likely to be changed by the table read instruction used
in the ISR. Errors can occur. In this case, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table
read instruction has to be applied in both the main routine and the ISR, the interrupt should be disabled prior
to the table read instruction. It will not be enabled until
the TBLH has been backed up. All table related instructions need 2 cycles to complete the operation.
These areas may function as normal program memory depending upon user requirements.
· Location 008H
This area is reserved for the Timer/Event Counter 0 interrupt service program on each bank. If timer interrupt
results from a timer/event counter 0 overflow, and if the
interrupt is enabled and the stack is not full, the program
begins execution at location 008H corresponding to its
bank.
· Location 00CH
This area is reserved for the Timer/Event Counter 1
interrupt service program on each bank. If a timer interrupt results from a Timer/Event Counter 1 overflow,
and if the interrupt is enabled and the stack is not full,
the program begins execution at location 00CH corresponding to its bank.
· Bank pointer
· Table location
The program memory is organized into 8 banks and
each bank into 8192 ´ 16 of bits program ROM.
PF[2~0] is used as the bank pointer only when PFC is
configured as output mode. PFC is the control register
for PF and is used to control the input/output configuration. To function as an output, the corresponding bit
of the control register must be ²0². After an instruction
has been executed to write data to the PF register to
select a different bank, note that the new bank will not
be selected immediately. It is not until the following instruction has completed execution that the bank will
be actually selected. It should be note that the PF register has to be cleared before setting to output mode.
Any location in the ROM space can be used as
look-up tables. The instructions TABRDC [m] (the current page, 1 page=256 words) and TABRDL [m] (the
last page) transfer the contents of the lower-order
byte to the specified data memory, and the
higher-order byte to TBLH (08H). Only the destination
of the lower-order byte in the table is well-defined, the
higher-order byte of the table word are transferred to
the TBLH. The Table Higher-order byte register
(TBLH) is read only. The Table Pointer (TBLP) is a
read/write register (07H), which indicates the table location. Before accessing the table, the location must
Instruction(s)
P ro g ra m
R O M
L o o k - u p ta b le ( 2 5 6 w o r d s )
Table Location
*12
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P12
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table location
Note:
*12~*0: Bits of table location
P12~P8: Bits of current Program Counter
@7~@0: Bits of table pointer
Rev. 1.20
7
June 18, 2003
HT36A0
Wavetable ROM
0 0 H
The ST[15~0] is used to defined the start address of
each sample on the wavetable and read the waveform
data from the location. HT36A0 provides 21 output address lines from WA[16~0], the ST[15~0] is used to locate the major 16 bits i.e. WA[16:5] and the undefined
data from WA[4~0] is always set to 00000b. So the start
address of each sample have to be located at a multiple
of 32. Otherwise, the sample will not be read out correctly because it has a wrong starting code.
0 1 H
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
0 4 H
0 5 H
Stack Register - Stack
This is a special part of the memory which is used to
save the contents of the program counter (PC) only. The
stack is organized into 8 levels and is neither part of the
data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledgment, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the
stack. After a chip reset, the SP will point to the top of the
stack.
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
W D T S
0 A H
S T A T U S
0 B H
IN T C
0 C H
T M R 0 H
0 D H
T M R 0 L
0 E H
T M R 0 C
0 F H
T M R 1 H
1 0 H
T M R 1 L
1 1 H
T M R 1 C
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
P C
P C C
1 6 H
1 7 H
1 8 H
1 9 H
S p e c ia l P u r p o s e
D A T A M E M O R Y
P D
P D C
1 A H
1 B H
1 C H
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a CALL is subsequently executed, a stack overflow occurs and the first
entry will be lost (only the most recent eight return address are stored).
1 D H
P F
P F C
1 E H
1 F H
2 0 H
C h a n n e l n u m b e r s e le c t
2 1 H
F r e q u e n c y n u m b e r h ig h b y te
2 2 H
F r e q u e n c y n u m b e r lo w b y te
2 3 H
S ta r t a d d r e s s h ig h b y te
2 4 H
The data memory is designed with 256 ´ 8 bits. The data
memory is divided into three functional groups: special
function registers, wavetable function register, and general purpose data memory (208´8). Most of them are
read/write, but some are read only.
S ta r t a d d r e s s lo w
b y te
2 5 H
R e p e a t n u m b e r h ig h b y te
2 6 H
R e p e a t n u m b e r lo w
2 7 H
2 8 H
Data Memory - RAM
b y te
W a v e ta b le F u n c tio n
R e g is te r
C o n tr o l r e g is te r
2 9 H
L e ft v o lu m n c o n tr o l
2 A H
2 B H
R ig h t v o lu m
c o n tro l
2 F H
3 0 H
The special function registers include the Indirect Addressing register 0 (00H), the Memory Pointer register 0
(MP0;01H), the Indirect Addressing register 1 (02H), the
Memory Pointer register 1 (MP1;03H), the Accumulator
(ACC;05H), the Program Counter Lower-byte register
(PCL;06H), the Table Pointer (TBLP;07H), the Table
Higher-order byte register (TBLH;08H), the Watchdog
Timer option Setting register (WDTS;09H), the Status
register (STATUS;0AH), the Interrupt Control register
(INTC;0BH), the Timer/event Counter 0 Higher-order
byte register (TMR0H;0CH), the Timer/event Counter 0
Lower-order byte register (TMR0L;0DH), the
Timer/event Counter 0 Control register (TMR0C;0EH),
the Timer/ event Counter 1 Higher-order byte register
Rev. 1.20
In d ir e c t A d d r e s s in g R e g is te r 0
G e n e ra l P u rp o s e
D A T A M E M O R Y
(2 0 8 B y te s )
: U n u s e d .
R e a d a s "0 0 "
F F H
RAM mapping
(TMR1H;0FH), the Timer/event Counter 1 Lower-order
byte register (TMR1L;10H), the Timer/event Counter 1
Control register (TMR1C;11H), the I/O registers
(PA;12H, PB;14H, PC;16H, PD;18H), the program ROM
bank select (PF;1CH)) and the I/O Control registers
(PAC;13H, PBC;15H, PCC;17H, PDC;19H), and the
8
June 18, 2003
HT36A0
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
program ROM bank control register (PFC;1DH). The
wavetable function registers is defined between
20H~2AH. The remaining space before the 30H is reserved for future expanded usage and reading these locations will return the result 00H. The general purpose
data memory, addressed from 30H to FFH, is used for
data and control information under instruction command.
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment & Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation but
can also change the status register.
All data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data
memory can be set and reset by the SET [m].i and CLR
[m].i instructions, respectively. They are also indirectly
accessible through Memory pointer registers
(MP0;01H, MP1;03H).
Status Register - STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PD) and Watchdog time-out flag (TO).
It also records the status information and controls the operation sequence.
With the exception of the TO and PD flags, bits in the
status register can be altered by instructions like any
other register. Any data written into the status register
will not change the TO or PD flags. In addition it should
be noted that operations related to the status register
may give different results from those intended. The TO
and PD flags can only be changed by system power up,
Watchdog Timer overflow, executing the HALT instruction and clearing the Watchdog Timer.
Indirect Addressing Register
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write operation of [00H] and [02H] access data memory pointed
to by MP0 (01H) and MP1 (03H) respectively. Reading
location 00H or 02H directly will return the result 00H.
And writing directly results in no operation.
The function of data movement between two indirect addressing registers, is not supported. The memory
pointer registers, MP0 and MP1, are 8-bit register which
can be used to access the data memory by combining
corresponding indirect addressing registers.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, on entering the interrupt sequence or executing a subroutine call, the status register will not be
automatically pushed onto the stack. If the contents of
status are important and the subroutine can corrupt the
status register, the programmer must take precautions
to save it properly.
Accumulator
The accumulator closely relates to ALU operations. It is
mapped to location 05H of the data memory and it can
operate with immediate data. The data movement between two data memory locations must pass through
the accumulator.
Interrupt
The HT36A0 provides two internal timer/event counter
interrupts on each bank. The Interrupt Control register
(INTC;0BH) contains the interrupt control bits that sets
the enable/disable and the interrupt request flags.
Arithmetic and Logic Unit - ALU
This circuit performs 8-bit arithmetic and logic operation.
The ALU provides the following functions:
Labels
Bits
Function
C
0
C is set if an operation results in a carry during an addition operation or if a borrow does not take
place during a subtraction operation; otherwise C is cleared. Also it is affected by a rotate
through carry instruction.
AC
1
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the
high nibble into the low nibble in subtraction; otherwise AC is cleared.
Z
2
Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
OV
3
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
PD
4
PD is cleared by either a system power-up or executing the CLR WDT instruction. PD is set by
executing the HALT instruction.
TO
5
TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by
a WDT time-out.
¾
6~7
Unused bit, read as ²0²
STATUS register
Rev. 1.20
9
June 18, 2003
HT36A0
During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the RETI instruction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, the RET or RETI instruction may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not.
Once an interrupt subroutine is serviced, all other interrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain interrupt needs servicing within the service routine, the programmer may set the EMI bit and the corresponding bit
of the INTC to allow interrupt nesting. If the stack is full,
the interrupt request will not be acknowledged, even if
the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must
be prevented from becoming full.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests
the priorities in the following table apply. These can be
masked by resetting the EMI bit.
All these kinds of interrupt have a wake-up capability. As
an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack and then
branching to subroutines at specified locations in the
program memory. Only the program counter is pushed
onto the stack. If the contents of the register and Status
register (STATUS) are altered by the interrupt service
program which may corrupt the desired control sequence, then the programmer must save the contents
first.
Vector
Timer/event Counter 0 overflow
1
08H
Timer/event Counter 1 overflow
2
0CH
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine. Because interrupts often occur in an unpredictable manner
or need to be serviced immediately in some applications, if only one stack is left and enabling the interrupt is
not well controlled, once the ²CALL subroutine² operates
in the interrupt subroutine, it may damage the original
control sequence.
The Timer/Event Counter 1 interrupt is operated in the
same manner as Timer/Event Counter 0. The related interrupt control bits ET1I and T1F of the Timer/Event
Counter 1 are bit 3 and bit 6 of the INTC respectively.
INTC
(0BH)
Priority
The Timer/Event Counter 0/1 interrupt request flag
(T0F/T1F), Enable Timer/Event Counter 0/1 bit
(ET0I/ET1I), Enable Master Interrupt bit (EMI) constitute
an interrupt control register (INTC) which is located at
0BH in the data memory. EMI, ET0I, ET1I are used to
control the enabling/disabling of interrupts. These bits
prevent the requested interrupt from being serviced.
Once the interrupt request flags (T0F, T1F) are set, they
will remain in the INTC register until the interrupts are
serviced or cleared by a software instruction.
The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (T0F; bit 5 of INTC), caused by a Timer/Event
Counter 0 overflow. When the interrupt is enabled, and
the stack is not full and the T0F bit is set, a subroutine
call to location 08H will occur. The related interrupt request flag (T0F) will be reset and the EMI bit cleared to
disable further interrupts.
Register
Interrupt Source
Bit No.
Label
Function
0
EMI
1
¾
2
ET0I
Controls the Timer/Event Counter 0 interrupt
(1=enabled; 0=disabled)
3
ET1I
Controls the Timer/Event Counter 1 interrupt
(1=enabled; 0=disabled)
4
¾
5
T0F
Internal Timer/Event Counter 0 request flag
(1=active; 0=inactive)
6
T1F
Internal Timer/Event Counter 1 request flag
(1=active; 0=inactive)
7
¾
Controls the Master (Global) interrupt
(1=enabled; 0=disabled)
Unused bit, read as ²0²
Unused bit, read as ²0²
Unused bit, read as ²0²
INTC register
Rev. 1.20
10
June 18, 2003
HT36A0
Oscillator Configuration
O S C 1
The HT36A0 provides two types of oscillator circuit for
the system clock, i.e., RC oscillator and crystal oscillator. No matter what type of oscillator, the signal divided
by 2 is used for the system clock. The HALT mode stops
the system oscillator and ignores external signal to conserve power. If the RC oscillator is used, an external resistor between OSC1 and VSS is required, and the
range of the resistance should be from 30kW to 680kW.
The system clock, divided by 4, is available on OSC2
with pull-high resistor, which can be used to synchronize
external logic. The RC oscillator provides the most cost
effective solution. However, the frequency of the oscillation may vary with VDD, temperature, and the chip itself
due to process variations. It is therefore, not suitable for
timing sensitive operations where accurate oscillator
frequency is desired.
V
fS
O S C 2
Y S
O S C 1
D D
/8
O S C 2
C r y s ta l O s c illa to r
R C
O s c illa to r
System oscillator
temperature, VDD and process variations. By invoking
the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the
WDTS) can give different time-out periods. If WS2,
WS1, WS0 all equal to 1, the division ratio is up to 1:128,
and the maximum time-out period is 2.6 seconds.
If the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operate in the same
manner except that in the HALT state the WDT may stop
counting and lose its protecting purpose. In this situation
the logic can only be restarted by external logic. The
high nibble and bit 3 of the WDTS are reserved for user
defined flags, and the programmer may use these flags
to indicate some specified status.
On the other hand, if the crystal oscillator is selected, a
crystal across OSC1 and OSC2 is needed to provide the
feedback and phase shift required for the oscillator, and
no other external components are required. A resonator
may be connected between OSC1 and OSC2 to replace
the crystal and to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required.
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDT oscillator still works with a
period of approximately 78ms. The WDT oscillator can
be disabled by mask option to conserve power.
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
Watchdog Timer - WDT
1
1
0
1:64
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (system clock of the MCU divided by 4), determined by mask
options. This timer is designed to prevent a software
malfunction or sequence jumping to an unknown location with unpredictable results. The Watchdog Timer can
be disabled by mask option. If the Watchdog Timer is
disabled, all the executions related to the WDT result in
no operation.
1
1
1
1:128
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock.
The WDT overflow under normal operation will initialize
a ²chip reset² and set the status bit TO. Whereas in the
HALT mode, the overflow will initialize a ²warm reset²
only the PC and SP are reset to zero. To clear the WDT
contents (including the WDT prescaler ), 3 methods are
implemented; external reset (a low level to RES), software instructions, or a HALT instruction. The software
instructions include CLR WDT and the other set - CLR
Once the internal WDT oscillator (RC oscillator with a
period of 78ms normally) is selected, it is first divided by
256 (8-stages) to get the nominal time-out period of approximately 20ms. This time-out period may vary with
S y s te m
C lo c k /8
W D T
O S C
M a s k
O p tio n
S e le c t
W D T P r e s c a le r
8 - b it C o u n te r
7 - b it C o u n te r
8 -to -1 M U X
W S 0 ~ W S 2
W D T T im e - o u t
Watchdog timer
Rev. 1.20
11
June 18, 2003
HT36A0
WDT1 and CLR WDT2. Of these two types of instructions, only one can be active depending on the mask option - ²CLR WDT times selection option². If the ²CLR
WDT² is selected (i.e. CLRWDT times equal one), any
execution of the CLR WDT instruction will clear the
WDT. In case ²CLR WDT1² and ²CLR WDT2² are chosen (i.e. CLRWDT times equal two), these two instructions must be executed to clear the WDT; otherwise, the
WDT may reset the chip because of time-out.
is set to ²1² before entering the HALT mode, the
wake-up function of the related interrupt will be disabled.
Power Down Operation - HALT
· WDT time-out reset during normal operation
The HALT mode is initialized by a HALT instruction and
results in the following...
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re set² that just resets the PC and SP, leaving the other circuits to maintain their state. Some registers remain unchanged during any other reset conditions. Most
registers are reset to the ²initial condition² when the reset conditions are met. By examining the PD and TO
flags, the program can distinguish between different
²chip resets².
To minimize power consumption, all I/O pins should be
carefully managed before entering the HALT status.
Reset
There are 3 ways in which a reset can occur:
· RES reset during normal operation
· RES reset during HALT
· The system oscillator will turn off but the WDT oscilla-
tor keeps running (If the WDT oscillator is selected).
Watchdog Timer - WDT
· The contents of the on-chip RAM and registers remain
unchanged
· The WDT and WDT prescaler will be cleared and
starts to count again (if the clock comes from the WDT
oscillator).
· All I/O ports maintain their original status.
V D D
· The PD flag is set and the TO flag is cleared.
R E S
· The HALT pin will output a high level signal to disable
S T
S S T T im e - o u t
the external ROM.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow performs a ²warm reset². By examining the TO and PD flags,
the cause for a chip reset can be determined. The PD flag
is cleared when there is a system power-up or by executing the CLR WDT instruction and it is set when a HALT instruction is executed. The TO flag is set if the WDT
time-out occurs, and causes a wake-up that only resets
the PC and SP, the others remain in their original status.
C h ip R e s e t
Reset timing chart
V
D D
R E S
The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit
in port A can be independently selected to wake-up the
device by mask option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If awakening from an interrupt, two sequences
may occur. If the related interrupts is disabled or the interrupts is enabled but the stack is full, the program will
resume execution at the next instruction. If the interrupt
is enabled and the stack is not full, a regular interrupt response takes place.
Reset circuit
H A L T
W D T
W D T
W a rm
R e s e t
T im e - o u t
R e s e t
R E S
O S C I
Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume to normal operation. In
other words, a dummy cycle period will be inserted after
the wake-up. If the wake-up results from an interrupt acknowledge, the actual interrupt subroutine will be delayed by one more cycle. If the wake-up results in next
instruction execution, this will execute immediately after
a dummy period has finished. If an interrupt request flag
Rev. 1.20
tS
S S T
1 0 -s ta g e
R ip p le C o u n te r
C o ld
R e s e t
P o w e r - o n D e te c tin g
Reset configuration
12
June 18, 2003
HT36A0
The registers status is summarized in the following table:
Register
Reset
(Power On)
WDT Time-out
(Normal Operation)
RES Reset
(Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
Program Counter
0000H
0000H
0000H
0000H
0000H
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMR0H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR0L
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR0C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u 1uuu
TMR1H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1L
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u 1uuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PCC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PD
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
PDC
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
PF
---- -111
---- -111
---- -111
---- -111
---- -uuu
PFC
---- -111
---- -111
---- -111
---- -111
---- -uuu
CHAN
00-- 0000
uu-- uuuu
uu-- uuuu
uu-- uuuu
uu-- uuuu
FreqNH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
FreqNL
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
AddrH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
AddrL
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ReH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ReL
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ENV
x-xx xxxx
u-uu uuuu
u-uu uuuu
u-uu uuuu
u-uu uuuu
LVC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
RVC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
Note:
²*² stands for warm reset
²u² stands for unchanged
²x² stands for unknown
Rev. 1.20
13
June 18, 2003
HT36A0
TO
PD
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
buffer, and writing TMR0H will write the data and the
contents of the low byte buffer into the Timer/Event
Counter 0 Preload register (16-bit) simultaneously. The
Timer/Event Counter 0 Preload register is changed by
writing TMR0H operations and writing TMR0L will keep
the Timer/Event Counter 0 Preload register unchanged.
RESET Conditions
Reading TMR0H will also latch the TMR0L into the low
byte buffer to avoid a false timing problem. Reading
TMR0L returns the contents of the low byte buffer. In
other words, the low byte of the Timer/Event Counter 0
cannot be read directly. It must read the TMR0H first to
make the low byte contents of the Timer/Event Counter
0 latched into the buffer.
Note: ²u² stands for ²unchanged²
To guarantee that the system oscillator has started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses during system
power up or when the system awakes from a HALT
state.
There are three registers related to the Timer/Event
Counter 1; TMR1H (0FH), TMR1L (10H), TMR1C (11H).
The Timer/Event Counter 1 operates in the same manner as Timer/Event Counter 0.
When a system power-up occurs, the SST delay is
added during the reset period. But when the reset comes from the RES pin, the SST delay is disabled. Any
wake-up from HALT will enable the SST delay.
The TMR0C is the Timer/Event Counter 0 control register, which defines the Timer/Event Counter 0 options.
The Timer/Event Counter 1 has the same options with
Timer/Event Counter 0 and is defined by TMR1C.
The functional units chip reset status are shown below.
Program counter
000H
Interrupt
Disable
Prescaler
Clear
WDT
Clear. After master reset,
WDT begins counting
The Timer/event Counter control registers define the operating mode, counting enable or disable and active
edge.
The TM0, TM1 bits define the operating mode. The
Event count mode is used to count external events,
which means the clock source comes from an external
(TMR) pin. The Timer mode functions as a normal timer
with the clock source coming from the instruction clock.
The pulse width measurement mode can be used to
count the high or low level duration of the external signal
(TMR). The counting is based on the instruction clock.
Timer/Event Counter (0/1) Off
Input/output ports
Input mode
SP
Points to the top of stack
Timer/Event Counter
Two timer/event counters are implemented in the
HT36A0. The Timer/Event Counter 0 and Timer/Event
Counter 1 contain 16-bit programmable count-up counters and the clock comes from the system clock divided
by 4.
In the Event count or Timer mode, once the timer/event
counter starts counting, it will count from the current
contents in the timer/event counter to FFFFH. Once
overflow occurs, the counter is reloaded from the
Timer/Event Counter Preload register and simultaneously generates the corresponding interrupt request
flag (T0F/T1F; bit 5/6 of INTC).
There are three registers related to Timer/Event Counter 0; TMR0H (0CH), TMR0L (0DH), TMR0C (0EH).
Writing TMR0L only writes the data into a low byte
Label
Bits
Function
¾
0~2
TE
3
Define the TMR active edge of Timer/Event Counter 0
(0=active on low to high; 1=active on high to low)
TON
4
Enable/disable timer counting
(0=disable; 1=enable)
¾
5
Unused bit, read as ²0²
TM0
TM1
6
7
Defines the operating mode
01=Event count mode (External clock)
10=Timer mode (Internal clock)
11=Pulse width measurement mode
00=Unused
Unused bit, read as ²0²
TMR0C/TMR1C register
Rev. 1.20
14
June 18, 2003
HT36A0
Input/Output Ports
In pulse width measurement mode with the TON and TE
bits equal to one, once the TMR has received a transient
from low to high (or high to low; if the TE bit is 0) it will
start counting until the TMR returns to the original level
and resets the TON. The measured result will remain in
the even if the activated transient occurs again. In other
words, only one cycle measurements can be done. Until
setting the TON, the cycle measurement will function
again as long as it receives further transient pulse. Note
that, in this operating mode, the timer/event counter
starts counting not according to the logic level but according to the transient edges. In the case of counter
overflows, the counter is reloaded from the timer/event
counter preload register and issues the interrupt request
just like the other two modes.
There are 28 bidirectional input/output lines labeled
from PA to PD, which are mapped to the data memory of
[12H], [14H], [16H], [18H] respectively. All these I/O
ports can be used for input and output operations. For
input operation, these ports are non-latching, that is, the
inputs must be ready at the T2 rising edge of instruction
MOV A,[m] (m=12H, 14H, 16H or 18H). For output operation, all data is latched and remains unchanged until
the output latch is rewritten.
Each I/O line has its own control register (PAC, PBC,
PCC, PDC) to control the input/output configuration.
With this control register, CMOS output or Schmitt Trigger input with or without pull-high resistor (mask option)
structures can be reconfigured dynamically under software control. To function as an input, the corresponding
latch of the control register must write a ²1². The
pull-high resistance will exhibit automatically if the
pull-high option is selected. The input source also depends on the control register. If the control register bit is
²1², input will read the pad state. If the control register bit
is ²0², the contents of the latches will move to the internal
bus. The latter is possible in ²read-modify-write² instruction. For output function, CMOS is the only configuration. These control registers are mapped to locations
13H, 15H, 17H and 19H).
To enable the counting operation, the Timer ON bit
(TON; bit 4 of TMR0C/TMR1C) should be set to 1. In the
pulse width measurement mode, the TON will be
cleared automatically after the measurement cycle is
completed. But in the other two modes the TON can only
be reset by instruction. The overflow of the timer/event
counter is one of the wake-up sources. No matter what
the operation mode is, writing a 0 to ET0I/ET1I can disable the corresponding interrupt service.
In the case of timer/event counter OFF condition, writing
data to the Timer/event Counter Preload register will
also reload that data to the timer/event counter. But if
the timer/event counter is turned on, data written to the
timer/event counter will only be kept in the timer/event
counter preload register. The timer/event counter will
still operate until overflow occurs.
After a chip reset, these input/output lines remain at high
levels or floating (mask option). Each bit of these input/output latches can be set or cleared by the SET [m].i
or CLR [m].i (m=12H, 14H, 16H or 18H) instruction.
Some instructions first input data and then follow the
output operations. For example, the SET [m].i, CLR
[m].i, CPL [m] and CPLA [m] instructions read the entire
port states into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
When the timer/event counter (reading
TMR0H/TMR1H) is read, the clock will be blocked to
avoid errors. As this may results in a counting error,
this must be taken into consideration by the programmer.
The two timer counters of HT36A0 are internal clock
mode only, so only Timer mode can be selected. Therefore the (TM1, TM0) bits can only be set to (TM1,TM0) =
(1,0), and the other clock modes are invalid.
S y s te m
C lo c k /8
G N D
Each line of port A has the capability to wake-up the device.
D a ta B u s
T M 1
T M 0
T im e r /e v e n t C o u n te r 0
P r e lo a d R e g is te r
R e lo a d
T E
T M 1
T M 0
T O N
T im e r /e v e n t
C o u n te r 0
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
O v e r flo w
T o In te rru p t
L o w B y te
B u ffe r
Timer/Event Counter 0/1
Rev. 1.20
15
June 18, 2003
HT36A0
D a ta B u s
W r ite C o n tr o l R e g is te r
V
Q
D
C K
Q
S
V
W e a k
P u ll- u p
D D
C h ip R e s e t
M a s k O p tio n
R e a d C o n tr o l R e g is te r
D
W r ite I/O
P A
P B
P C
P D
Q
C K
Q
S
M
R e a d I/O
S y s te m
D D
U
0 ~
0 ~
0 ~
0 ~
P A
P B
P C
P D
7
7
3
7
X
W a k e - U p ( P A o n ly )
M a s k O p tio n
Input/output ports
16 Channel Wavetable Synthesizer
Wavetable Function Memory Mapping
Special Register for Wavetable Synthesizer
RAM
B7
B6
B5
B4
B3
B2
B1
B0
20H
VM
FR
¾
¾
CH3
CH2
CH1
CH0
21H
BL3
BL2
BL1
BL0
FR11
FR10
FR9
FR8
22H
FR7
FR6
FR5
FR4
FR3
FR2
FR1
FR0
23H
ST15
ST14
ST13
ST12
ST11
ST10
ST9
ST8
24H
ST7
ST6
ST5
ST4
ST3
ST2
ST1
ST0
25H
WBS
RE14
RE13
RE12
RE11
RE10
RE9
RE8
26H
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
27H
A_R
¾
VL9
VL8
ENV1
ENV0
VR9
VR8
29H
VL7
VL6
VL5
VL4
VL3
VL2
VL1
VL0
2AH
VR7
VR6
VR5
VR4
VR3
VR2
VR1
VR0
Wavetable Function Register Table
Register Name
Register Function
B7
B6
B5
B4
B3
B2
B1
B0
CH3
CH2
CH1
CH0
20H
Channel Number Selection
20H
Change Parameter Selection
VM
FR
21H
Block Number Selection
BL3
BL2
BL1
BL0
FR11
FR10
FR9
FR8
FR7
FR6
FR5
FR4
FR3
FR2
FR1
FR0
ST15
ST14
ST13
ST12
ST11
ST10
ST9
ST8
ST7
ST6
ST5
ST4
ST3
ST2
ST1
ST0
RE14
RE13
RE12
RE11
RE10
RE9
RE8
RE6
RE5
RE4
RE3
RE2
RE1
RE0
21H
22H
23H
24H
25H
25H
26H
Frequency Number Selection
Start Address Selection
Waveform Format Selection
Repeat Number Selection
27H
Envelope Type Selection
27H
Attach and Release Selection
27H
29H
27H
2AH
Rev. 1.20
Left Volume Controller
Right Volume Controller
WBS
RE7
ENV1 ENV0
A_R
VL7
VL6
VR7
VR6
16
VL9
VL8
VL5
VL4
VR5
VR4
VL3
VR3
VL2
VR2
VL1
VL0
VR9
VR8
VR1
VR0
June 18, 2003
HT36A0
· CH[3~0] channel number selection
· Waveform format definition
The HT36A0 has a built-in 16 output channels and
CH[3~0] is used to define which channel is selected.
When this register is written to, the wavetable synthesizer will automatically output the dedicated PCM
code. So this register is also used as a start playing
key and it has to be written to after all the other
wavetable function registers are already defined.
The HT36A0 accepts two waveform formats to ensure
a more economical data space. WBS is used to define
the sample format of each PCM code.
These two bits, VM and FR, are used to define which
register will be updated on this selected channel.
There are two modes that can be selected to reduce
the process of setting the register. Please refer to the
statements of the following table:
FR
0
0
Update all the parameter
0
1
Only update the frequency number
1
0
Only update the volume
WBS=1 means the sample format is 12-bit
8 - B it
1 B
2 B
3 B
4 B
5 B
6 B
7 B
8 B
A s a m p lin g d a ta c o d e ; B m e a n s o n e d a ta b y te .
1 2 - B it
Function
1 H
1 M
1 L
2 L
2 H
2 M
3 H
3 M
3 L
A s a m p lin g d a ta c o d e
N o te : " 1 H " H ig h N ib b le
" 1 M " M id d le N ib b le
" 1 L " L o w N ib b le
Waveform format
· Output frequency definition
The data on BL3~0] and FR[11~0] are used to define
the output speed of the PCM file, i.e. it can be used to
generate the tone scale. When the FR[11:0] is 800H
and BL[3:0] is 6H, each sample data of the PCM code
will be sent out sequentially.
When the fOSC is 12.8MHz, the formula of a tone frequency is:
50kHz FR [11 ~ 0]
fOUT= fRECORD ´
´ (17 - BL [3~0])
SR
2
where fOUT is the output signal frequency, fRECORD and
SR is the frequency and sampling rate on the sample
code, respectively.
So if a voice code of C3 has been recorded which has
the fRECORD of 261Hz and the SR of 11025Hz, the tone
frequency (fOUT) of G3: fOUT=196Hz.
Can be obtained by using the fomula:
50kHz
FR[11 ~ 0]
196Hz= 261Hz ´
´
11025Hz 2 (17 - BL [3~0])
A pair of the values FR[11~0] and BL[3~0] can be determined when the fOSC is 12.8MHz.
· Repeat number definition
The repeat number is used to define the address
which is the repeat point of the sample. When the repeat number is defined, it will be output from the start
code to the end code once and always output the
range between the repeat address to the end code
(80H) until the volume become close.
The RE[14~0] is used to calculate the repeat address
of the PCM code. The process for setting the
RE[14~0] is to write the 2¢s complement of the repeat
length to RE[14~0], with the highest carry ignored.
The HT36A0 will get the repeat address by adding the
RE[14~0] to the address of the end code, then jump to
the address to repeat this range.
· Left and Right volume control
The HT36A0 provides the left and right volume control
independently. The left and right volume are controlled by VL[9~0] and VR[9~0] respectively. The chip
provides 1024 levels of controllable volume, the 000H
is the maximum and 3FFH is the minimum output volume.
· Start address definition
The HT36A0 provides two address types for extended
use, one is the program ROM address which is program counter corresponding with PF value, the other
is the start address of the PCM code.
The ST[15~0] is used to define the start address of
each PCM code and reads the waveform data from
this location. The HT36A0 provides 16 input data lines
from WA[15~0], the ST[15~0] is used to locate the
major 16 bits i.e. WA[15~5] and the undefined data
from WA[4~0] is always set as 00000b. In other
words, the WA[15~0]=ST[15~0]´25. So each PCM
code has to be located at a multiple of 32. Otherwise,
the PCM code will not be read out correctly because it
has a wrong start code.
Rev. 1.20
WBS=0 means the sample format is 8-bit
¨
The 12-bit sample format allocates location to each
sample data. Please refer to the waveform format
statement as shown below.
· Change parameter selection
VM
¨
· Envelope type definition
The HT36A0 provides a function to easily program the
envelope by setting the data of ENV[1~0] and A_R. It
forms a vibrato effect by a change of the volume to attach and release alternately.
The A_R signal is used to define the volume change in
attach mode or release mode and ENV[1~0] is used to
define which volume control bit will be changeable.
On the attach mode, the control bits will be sequentially signaled down to 0. On the release mode, the
control bits will be sequentially signaled up to 1. The
relationship is shown in the following table.
17
June 18, 2003
HT36A0
A_R
ENV1
ENV0
Volume Control Bit
Control Bit Final Value
0
0
0
VL2~0, VR2~0
111b
0
0
1
VL1~0, VR1~0
11b
0
1
0
VL0, VR0
1b
x
1
1
No Bit
unchanged
1
0
0
VL2~0, VR2~0
000b
1
0
1
VL1~0, VR1~0
00b
1
1
0
VL0, VR0
0b
Mode
Release mode
No change mode
Attach mode
Envelope type definition
· The PCM code definition
Stereo Serial Data Format
The HT36A0 can only solve the voice format of the
signed 8-bit raw PCM. And the MCU will take the voice
code 80H as the end code.
So each PCM code section must be ended with the end
code 80H.
The audio output data is in serial mode with 16 bit digital signal and LSB first output. There is a high sampling rate of 50kHz when the system clock is 12.8MHz
and with two channel outputs for Right/Left channel.
HT36A0 provides only one serial data format as IIS
mode. The user could directly connect a D/A converter
which can accept the IIS serial data format, like
HT82V731.
D/A Converter Interface
HT36A0 provides the IIS serial data format to support the
multiple D/A converters, one bit clock output and a word
clock signal for left/right stereo serial data transmission.
Mask Option
No. Mask Option
Clock Signal
Function
The bit clock output signals DCK are used to synchronize
the IIS serial data.
1
WDT source
On-chip RC/Instruction clock/
disable WDT
The word clock signal LOAD divides the serial data into
left channel and right channel data for two-way audio output.
2
CLRWDT
times
One time, two times
(CLR WDT1/WDT2)
3
Wake-up
PA only
· LOAD
4
Pull-High
PA, PB, PC, PD input
5
OSC mode
Crystal or Resistor type
6
I/O DAC pin
PD1~3 DAC pin selection
The word clock signal LOAD is used for IIS serial data.
The stereo serial data consists of 16-channel sound
generator.
¨
On IIS format, a ²H² state on LOAD is used for the
right channel, and a ²L² state is used for the left
channel.
· DCK
DCK bit clock is the clock source for the signal.
W S
R ig h t
L e ft
B C K
D A T A
L S B
M S B
S a m p le O u t
D/A converter timing
R vs F Characteristics curve
Rev. 1.20
18
June 18, 2003
HT36A0
Application Circuit
V
D D
1 0 W
O S C I
O S C O
V D D
4 7 m F
V D D A
0 .1 m F
P A 0 ~ P A 7
P B 0 ~ P B 7
P C 0 ~ P C 7
V
D D
V
D D
P D 0 ~ P D 3
L C H
4 7 m F
R C H
1 0 0 k W
0 .1 m F
2 0 k W
R E S
V S S A
0 .1 m F
IN
V re f
3
1 0 m F
V S S
H T 3 6 A 0
V
2
8
V D D
O U T N
1
H T 8 2 V 7 3 3
5
V S S
4
S P K
8 W
7
O U T P
C E
D D
1 0 W
V D D
4 7 m F
V D D A
O S C I
0 .1 m F
P A 0 ~ P A 7
1 2 M H z
P B 0 ~ P B 7
O S C O
V
P C 0 ~ P C 7
D D
P D 0
P D 1 /D O U T
P D 2 /L O A D
P D 3 /D C L K
1 0 0 k W
R E S
V S S A
0 .1 m F
D A C
O P
H T 8 2 V 7 3 1
V S S
H T 3 6 A 0
Rev. 1.20
19
June 18, 2003
HT36A0
Package Information
48-pin SSOP (300mil) Outline Dimensions
4 8
2 5
A
B
2 4
1
C
C '
G
H
D
F
E
Symbol
Rev. 1.20
a
Dimensions in mil
Min.
Nom.
Max.
A
395
¾
420
B
291
¾
299
C
8
¾
12
C¢
613
¾
637
D
85
¾
99
E
¾
25
¾
F
4
¾
10
G
25
¾
35
H
4
¾
12
a
0°
¾
8°
20
June 18, 2003
HT36A0
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SSOP 48W
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330±1.0
B
Reel Inner Diameter
100±0.1
C
Spindle Hole Diameter
13.0+0.5
-0.2
D
Key Slit Width
2.0±0.5
T1
Space Between Flange
32.2+0.3
-0.2
T2
Reel Thickness
38.2±0.2
Rev. 1.20
21
June 18, 2003
HT36A0
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
D 1
C
B 0
K 1
P
K 2
A 0
SSOP 48W
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
32.0±0.3
P
Cavity Pitch
16.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
14.2±0.1
D
Perforation Diameter
2.0 Min.
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
12.0±0.1
B0
Cavity Width
16.20±0.1
K1
Cavity Depth
2.4±0.1
K2
Cavity Depth
3.2±0.1
t
Carrier Tape Thickness
C
Cover Tape Width
Rev. 1.20
0.35±0.05
25.5
22
June 18, 2003
HT36A0
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
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Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
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7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 021-6485-5560
Fax: 021-6485-0313
http://www.holtek.com.cn
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ISDN: 0755-8346-5591
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Tel: 010-6641-0030, 6641-7751, 6641-7752
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46712 Fremont Blvd., Fremont, CA 94538
Tel: 510-252-9880
Fax: 510-252-9885
http://www.holmate.com
Copyright Ó 2003 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.20
23
June 18, 2003