Anpec APA0715QBI-TRL 3w mono fully differential audio power amplifier Datasheet

APA0715
3W Mono Fully Differential Audio Power Amplifier
Features
•
•
•
•
•
•
•
•
General Description
The APA0715 is a Mono, fully differential Class-AB audio
amplifier which can operate with supply voltage from 2.4V
Operating Voltage: 2.4V~5.5V
Fully Differential Class-AB Amplifier
to 5V and is available in a MSOP8, MSOP8P, or TDFN3x38 package.
High PSRR and Excellent RF Rectification
Immunity
High PSRR and fully differential architecture increase immunity to noise and RF rectification. In addition to these
Low Crosstalk
3W Output Power into 3Ω Load at VDD=5V
features, a short startup time and small package size
make the APA0715 an ideal choice for Mobil Phones and
Thermal and Over-Current Protections
Low Supply Current :1.5mA Typical
Portable Devices.
The APA0715 also integrates the de-pop circuitry that re-
Space Saving Package
duces the pops and click noises during power on/off and
shutdown mode operation. Both Thermal and over-cur-
-MSOP-8
-MSOP-8P
•
rent protections are integrated to avoid the IC being destroyed by over temperature and short-circuit.
-TDFN3x3-8
Lead Free and Green Devices Available
The APA0715 is capable of driving 3W at 5V into 3Ω
speaker.
(RoHS Compliant)
Applications
•
•
Pin Configuration
Mobil Phones
SD 1
Portable Devices
BYPASS 2
INP 3
Simplified Application Circuit
8 OUTN
MSOP-8
Top View
INN 4
INP 3
8 OUTN
MSOP-8P
Top View
INN 4
LINN
LINP
7 GND
6 VDD
5 OUTP
LOUTP
APA0715
Input
6 VDD
5 OUTP
SD 1
BYPASS 2
7 GND
Speaker
8 OUTN
SD 1
7 GND
BYPASS 2
LOUTN
INP 3
INN 4
TDFN3x3-8
TOP View
6 VDD
5 OUTP
=Thermal Pad (connected the Thermal Pad to
GND plane for better heat dissipation)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2008
1
www.anpec.com.tw
APA0715
Ordering and Marking Information
APA0715
Package Code
X : MSOP-8 XA : MSOP-8P QB : TDFN3x3-8
Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
L : Lead Free Device G : Halogen and Lead Free Device
Assembly Material
Handling Code
Temperature Range
Package Code
APA0715
X:
A0715
XXX
XX
XXXXX - Date Code
APA0715
XA :
A0715
XXX
XX
XXXXX - Date Code
APA0715
QB :
APA
0715
XXXXX
XXXXX - Date Code
Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish;
which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and
halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed
1500ppm by weight).
Absolute Maximum Ratings
Symbol
VDD
(Note 1)
Parameter
Rating
Unit
Supply Voltage
-0.3 to 6
V
Input Voltage (INN, INP, SD to GND)
-0.3 to 6
V
Input Voltage (OUTN, OUTP to GND)
-0.3 to VDD +0.3
V
VIN
TJ
Maximum Junction Temperature
TSTG
Storage Temperature Range
TSDR
Maximum Soldering Temperature Range, 10 Seconds
PD
Power Dissipation
150
ο
-65 to +150
ο
260
ο
C
C
C
Internally Limited
W
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2008
2
www.anpec.com.tw
APA0715
Thermal Characteristics (Note 2,3)
Symbol
Parameter
Thermal Resistance -Junction to Ambient
Typical Value
θJC
200
52
54
MSOP-8
MSOP-8P
TDFN3x3-8
θJA
Unit
ο
C /W
Thermal Resistance -Junction to Case
ο
MSOP-8P
10
C /W
TDFN3x3-8
11
Note 2: Please refer to “ Layout Recommendation”, the Thermal Pad on the bottom of the IC should soldered directly to the PCB’s
ThermalPad area that with several thermal vias connect to the ground plan, and the PCB is a 2-layer, 5-inch square area with
2oz copper thickness.
Note 3: The case temperature is measured at the center of the Thermal Pad on the underside of the MSOP-8P and TDFN3x3-8
package.
Recommended Operating Conditions
Symbol
VDD
Parameter
Range
Supply Voltage
Unit
2.4
~ 5.5
V
SD
1.8
~ VDD
V
SD
0
~ 0.35
V
VIH
High Level Threshold Voltage
VIL
Low Level Threshold Voltage
VIC
Common Mode Input Voltage
0.5
~ VDD-0.5
Operating Ambient Temperature Range
-40
~ 85
ο
Operating Junction Temperature Range
-40
~ 125
ο
~
Ω
Speaker Resistance
3
C
C
Electrical Characteristics
VDD=5V, GND=0V, AV=1V/V, TA= 25oC (unless otherwise noted)
Symbol
IDD
ISD
II
TSTART-UP
RSD
Min.
APA0715
Typ.
Max.
-
1.5
3
SD = 0V
SD
-
0.1
5
-
mA
µA
µA
Cb=0.22µF
-
50
-
ms
90
100
110
kΩ
1
-
2.4
2.1
1.3
3
2.6
1.6
-
W
-
0.035
-
%
-
75
-
dB
Parameter
Test Conditions
Supply Current
Shutdown Current
Input Current
Start-Up Time from End of
Shutdown
Resistance from Shutdown to
GND
Unit
VDD=5V, TA=25°
C
RL = 3Ω
RL = 4Ω
RL = 8Ω
RL = 3Ω
THD+N = 10%
RL = 4Ω
fin = 1kHz
RL = 8Ω
RL = 8Ω
fin = 1kHz
PO= 0.9W
Cb= 0.22µF, RL = 8Ω, VRR=0.2VPP,
fin = 217Hz
THD+N = 1%
PO
Output Power
THD+N
Total Harmonic Distortion
Pulse Noise
PSRR
Power Supply Rejection Ratio
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2008
3
www.anpec.com.tw
APA0715
Electrical Characteristics (Cont.)
o
VDD=5V, GND=0V, TA= 25 C (unless otherwise noted)
Symbol
Parameter
Test Conditions
Min.
APA0715
Typ.
Max.
-
85
-
dB
-
112
-
dB
Unit
VDD=5V, TA=25°
C (CONT.)
CMRR
Common-Mode Rejection
Ratio
Cb= 0.22µF, RL = 8Ω, VIC=0.2VPP,
fin = 217Hz
With A-weighting Filter
PO = 1.3W, RL = 8Ω
S/N
Signal to Noise Ratio
VOS
Output Offset Voltage
RL = 8Ω
-
5
20
mV
Vn
Noise Output Voltage
Cb= 0.22µF, With A-weighting Filter
-
8
-
µV
(rms)
RL = 3Ω
-
1.2
-
RL = 4Ω
-
1
-
RL = 8Ω
-
0.65
-
RL = 3Ω
-
1.5
-
RL = 4Ω
-
1.3
-
RL = 8Ω
-
0.8
-
-
0.05
-
-
85
-
-
75
-
-
110
-
VDD=3.6V, TA=25°
C
THD+N = 1%
PO
Output Power
THD+N = 10%
fin = 1kHz
THD+N
Total Harmonic Distortion
Pulse Noise
PSRR
Power Supply Rejection Ratio
CMRR
Common-Mode Rejection
Ratio
RL = 8Ω
fin = 1kHz
PO= 0.45W
Cb= 0.22µF, RL = 8Ω, VRR=0.2VPP,
fin = 217Hz
Cb= 0.22µF, RL = 8Ω, VIC=0.2VPP,
fin = 217Hz
With A-weighting Filter
PO = 0.65W, RL = 8Ω
W
%
dB
S/N
Signal to Noise Ratio
VOS
Output Offset Voltage
RL = 8Ω
-
5
20
mV
Vn
Noise Output Voltage
Cb= 0.22µF, With A-weighting Filter
-
7
-
µV
(rms)
RL = 3Ω
-
0. 5
-
RL = 4Ω
-
0.45
-
RL = 8Ω
-
0.3
-
RL = 3Ω
-
0.7
-
RL = 4Ω
-
0.6
-
-
0.35
-
-
0.08
-
-
80
-
-
65
-
-
106
-
VDD=2.4V, TA=25°
C
THD+N = 1%
PO
Output Power
THD+N = 10%
fin = 1kHz
THD+N
Total Harmonic Distortion
Pulse Noise
PSRR
Power Supply Rejection Ratio
CMRR
Common-Mode Rejection
Ratio
RL = 8Ω
PO = 0.2W,
fin = 1kHz
RL = 8Ω
Cb= 0.22µF, RL = 8Ω, VRR=0.2VPP,
fin = 217Hz
Cb= 0.22µF, RL = 8Ω, VIC=0.2VPP,
fin = 217Hz
With A-weighting Filter
PO = 0.3W, RL = 8Ω
W
%
dB
S/N
Signal to Noise Ratio
VOS
Output Offset Voltage
RL = 8Ω
-
5
20
mV
Vn
Noise Output Voltage
Cb= 0.22µF, With A-weighting Filter
-
7
-
µV
(rms)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2008
4
www.anpec.com.tw
APA0715
Typical Operating Characteristics
THD+N vs. Output Power
THD+N vs. Output Power
10
10
VDD=2.4V
0.1
VDD=3.6V
0.01
10m
RL=4Ω
fin=1kHz
Ci=0.22µF
AV=1V/V
BW<80kHz
1
THD+N (%)
THD+N (%)
RL=3Ω
fin=1kHz
Ci=0.22µF
AV=1V/V
1 BW<80kHz
VDD=2.4V
0.1
VDD=3.6V
VDD=5.0V
100m
1
0.01
10m
5
100m
Output Power (W)
THD+N vs. Frequency
THD+N (%)
THD+N (%)
VDD=5.0V
RL=8Ω
Ci=0.22µF
AV=1V/V
BW<80kHz
1
VDD=2.4V
0.1
PO=250mW
0.1
PO=25mW
PO=0.9W
VDD=3.6V
VDD=5.0V
0.01
10m
100m
1
0.01
3
20
100
1k
Frequency (Hz)
Output Power (W)
THD+N vs. Frequency
10
VDD=3.6V
RL=8Ω
Ci=0.22µF
AV=1V/V
BW<80kHz
THD+N (%)
THD+N (%)
10k 20k
THD+N vs. Frequency
10
1
5
10
RL=8Ω
fin=1kHz
Ci=0.22µF
AV=1V/V
BW<80kHz
1
1
Output Power (W)
THD+N vs. Output Power
10
VDD=5.0V
PO=250mW
PO=25mW
0.1
1
VDD=2.4V
RL=8Ω
Ci=0.22µF
AV=12dB
BW<80kHz
PO=75mW
0.1
PO=15mW
PO=450mW
0.01
20
100
1k
PO=350mW
0.01
10k 20k
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2008
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
5
www.anpec.com.tw
APA0715
Typical Operating Characteristics (Cont.)
Output Power vs. Load Resistance
Output Power vs. Supply Voltage
3.5
3.5
fin=1kHz
AV=1V/V
3.0
Output Power (W)
RL=4Ω,THD+N=10%
2.5
RL=3Ω,THD+N=1%
2.0
RL=4Ω,THD+N=1%
1.5
1.0
0.5
4.5
VDD=2.4V,THD+N=1%
1.0
RL=4Ω
0.5
VDD=5V
fin=1kHz
AV=1V/V
RL=8Ω
0.0
0.5
1.0
1.5
2.0
Output Power (W)
2.5
3
8
13
18
23
Load Resistance (Ω)
RL=3Ω
0.6
RL=4Ω
0.4
0.2
RL=8Ω
0.0
3.0
0.0
0.3
0.6
0.9
VDD=3.6V
fin=1kHz
AV=1V/V
1.2
1.5
1.8
Output Power (W)
Supply Current vs. Output Power
Supply Current vs. Output Power
0.8
RL=3Ω
RL=3Ω
0.8
0.6
0.6
Supply Current (A)
Supply Current (A)
32
0.8
1.0
RL=4Ω
0.4
RL=8Ω
VDD=5V
fin=1kHz
AV=1V/V
0.2
0.0
0.0
28
Power Dissipation vs. Output
Power
1.0
RL=3Ω
0.0
VDD=2.4V,THD+N=10%
5.0
1.5
1.0
VDD=3.6V,THD+N=1%
1.5
Power Dissipation vs. Output
Power
2.0
VDD=3.6V,THD+N=10%
2.0
0.0
3.5
4.0
Supply Volume (V)
VDD=5V,THD+N=10%
2.5
RL=8Ω,THD+N=1%
3.0
fin=1kHz
AV=1V/V
0.5
RL=8Ω,THD+N=10%
0.0
2.4
Power Dissipation (W)
VDD=5V,THD+N=1%
RL=3Ω,THD+N=10%
Power Dissipation (W)
Output Power (W)
3.0
0.5
1.0
1.5
2.0
2.5
Output Power (W)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2008
RL=8Ω
0.2
0.0
3.0
RL=4Ω
0.4
VDD=3.6V
fin=1kHz
AV=1V/V
0.0
0.3
0.6
0.9
1.2
1.5
1.8
Output Power (W)
6
www.anpec.com.tw
APA0715
Typical Operating Characteristics (Cont.)
Output Noise Voltage vs.
Frequency
10u
7u
5u
4u
3u
2u
1u
Output Noise Voltage (Vrms)
Output Noise Voltage (Vrms)
20u
VDD=5.0V
RL=8Ω
AV=1V/V
Ci=0.22µF
A-Weighting
20
100
1k
Frequency (Hz)
Output Noise Voltage vs.
Frequency
50u
40u
30u
7u
1u
VDD=2.4V
RL=8Ω
AV=1V/V
Ci=0.22µF
A-Weighting
20
100
1k
10u
7u
5u
4u
3u
2u
VDD=3.6V
RL=8Ω
AV=1V/V
Ci=0.22µF
A-Weighting
20
100
-20
-30
-40
-50
-60
10k 20k
VDD=5.0V
-70
VDD=2.4V
-80
-90
-100
VDD=3.6V
20
100
Power Supply Rejection Ratio (dB)
Power Supply Rejection Ratio (dB)
+0
RL=8Ω
AV=1V/V
Cb=0.47µF
Ci=2.2µF
Inputs Floating
-30
-40
-50
-60
-70
VDD=5.0V
-80
VDD=3.6V
-90
-100
20
100
VDD=2.4V
1k
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2008
10k 20k
PSRR vs. Frequency
PSRR vs. Frequency
-20
1k
Frequency (Hz)
T
-10
10k 20k
RL=8Ω
AV=1V/V
Cb=0.47µF
Ci=2.2µF
Inputs ac-Grounded
-10
Frequency (Hz)
+0
1k
Frequency (Hz)
PSRR vs. Frequency
10u
2u
20u
+0
20u
5u
4u
3u
50u
40u
30u
1u
10k 20k
Power Supply Rejection Ratio (dB)
Output Noise Voltage (Vrms)
50u
40u
30u
Output Noise Voltage vs.
Frequency
-10
-20
-30
-40
-50
-60
7
Cb=0.01µF
-70
Cb=0.1µF
-80
-90
-100
20
10k 20k
R
VDD=3.6V
RL=8Ω
AV=1V/V
Ci=2.2µF
Inputs ac-Grounded
Cb=0.47µF
100
Cb=1µF
1k
Frequency (Hz)
10k 20k
www.anpec.com.tw
APA0715
Typical Operating Characteristics (Cont.)
CMRR vs. Common Mode Input
Voltage
+0
RL=8Ω
AV=1V/V
Vin=0.2VPP
Ci=0.22µF
VDD=3.6V
-80
-90
-100
VDD=2.4V
VDD=5.0V
-110
-120
20
100
1k
Frequency (Hz)
-20
-30
-40
-50
-60
VDD=3.6V
VDD=2.4V
500m 1 1.5
2 2.5
-70
-80
10k 20k
RL=8Ω
AV=1V/V
Vin=0.2VPP
Ci=0.22µF
-10
+1
+220
+0
+180
Phase
-2
+140
VDD=5.0V
AV=1V/V
RL=8Ω
Ci=0.22µF
10
100
1k
10k
Frequency (Hz)
200k
Gain (dB)
Gain (dB)
+260
Phase (deg)
Gain
-1
-4
+260
Gain
+180
Phase
-2
+100
-3
+60
-4
+140
VDD=3.6V
AV=1V/V
RL=8Ω
Ci=0.22µF
10
-2
+140
VDD=2.4V
AV=1V/V
RL=8Ω
Ci=0.22µF
1k
10k
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2008
200k
Supply Current (mA)
Phase
Phase (deg)
Gain (dB)
2.5
+220
+180
100
1k
10k
+60
200k
Supply Current vs. Supply Voltage
Gain
10
100
+100
3.0
+260
-1
-4
+220
-1
Frequency Response
-3
5
Frequency (Hz)
+1
+0
4 4.5
Frequency Response
Frequency Response
-3
3 3.5
Common Mode Input Voltage
+1
+0
VDD=5.0V
Phase (deg)
-50
-60
-70
Common Mode Rejection Ratio (dB)
Common Mode Rejection Ratio (dB)
CMRR vs. Frequency
+0
-10
-20
-30
-40
+100
AV=1V/V
No Load
2.0
1.5
1.0
0.5
0.0
2.4
+60
8
3.0
3.5
4.5
4.0
Supply Voltage (V)
5.0
5.5
www.anpec.com.tw
APA0715
150
GSM Power Supply Rejection vs.
Frequency
VDD=5.0V
AV=1V/V
No Load
-80
-120
90
60
30
0
0.0
+0
-40
Output Voltage (dBV)
Start-up Time (ms)
120
Start-up Time vs. Bypass
Capacitor
0.2
0.4
0.6
0.8
1.0
-40
-80
-120
-160
0
400
800
1.2k
1.6k
2k
Frequency (Hz)
Bypass Capacitor (µF)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2008
-160
+0
Supply Voltage (dBV)
Typical Operating Characteristics (Cont.)
9
www.anpec.com.tw
APA0715
Operating Waveforms
GSM Power Supply Rejection vs. Time
Power On
VDD
1
V DD
1
2
VROUT
VROUT
2
CH1: VDD, 100mV/Div, DC, VDD Offset =5.0V
CH1: VDD, 2V/Div, DC
CH2: VROUT, 20mV/Div, DC
CH2: VROUT, 50mV/Div, DC
TIME: 2ms/Div
TIME: 20ms/Div
Shutdown Release
Power Off
VDD
VR S D
1
1
VROUT
2
V ROUTN
2
CH1: VDD, 2V/Div, DC
CH1: VRSD, 2V/Div, DC
CH2: VROUTN, 2V/Div, DC
CH2: VROUT, 50mV/Div, DC
TIME: 20ms/Div
TIME: 50ms/Div
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2008
10
www.anpec.com.tw
APA0715
Operating Waveforms (Cont.)
Shutdown
V RSD
1
VROUTN
2
CH1: VRSD, 2V/Div, DC
CH2: VROUTN, 2V/Div, DC
TIME: 20ms/Div
Pin Description
PIN
I/O/P
FUNCTION
NO.
NAME
1
SD
I
Shutdown mode control signal input, place left channel speaker amplifier in
shutdown mode when held low.
2
BYPASS
P
Bypass voltage input pin
3
INP
I
The non-inverting input of amplifier. INP is via a capacitor to Gnd for single-end
(SE) input signal.
4
INN
I
The inverting input of amplifier. INN is used as audio input terminal, typically.
5
ROUTP
O
The positive output terminal of speaker amplifier.
6
VDD
P
Supply voltage input pin
7
GND
P
Ground connection for circuitry.
8
LOUTN
O
The negative output terminal of speaker amplifier.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2008
11
www.anpec.com.tw
APA0715
Block Diagram
LINN
OUTP
OUTN
LINP
BYPASS
SD
Bias and Control Circuitrys
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2008
12
www.anpec.com.tw
APA0715
Typical Application Circuits
Single-ended input mode
VDD
Rf1 10kΩ
Cs2
0.1µF
Cs1
10µF
6 VDD
Ci1
Ri1
Input
0.22µF
Ci2
0.22µF
SHUTDOWN
Control
INN 4
5 OUTP
10kΩ
Ri2
8 OUTN
INP 3
4Ω
10kΩ
SD 1
Bias and Control
Circuitrys
2 BYPASS
0.22µF
Cb
RSD
100kΩ
7 GND
Rf2 10kΩ
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2008
13
www.anpec.com.tw
APA0715
Typical Application Circuits (Cont.)
Differential input mode
VDD
Rf1 10kΩ
Cs2
0.1µF
Cs1
10µF
6 VDD
Ci1
0.22µF
Ri1
INN 4
5 OUTP
10kΩ
Input
Ci2
0.22µF
SHUTDOWN
Control
Ri2
8 OUTN
INP 3
4Ω
10kΩ
SD 1
Bias and Control
Circuitrys
2 BYPASS
0.22µF
Cb
RSD
100kΩ
7 GND
Rf2 10kΩ
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2008
14
www.anpec.com.tw
APA0715
Function Description
Fully Differential Amplifier
The power amplifiers are fully differential amplifiers with
vide maximum device performance. By switching the SD
pin to a low level, the amplifier enters a low-consump-
differential inputs and outputs. The fully differential amplifier has some advantages versus traditional amplifiers.
tion-current state, IDD for APA0715 is in shutdown mode.
Under normal operating, APA0715’s SD pin should pull
First, don’t need the input coupling capacitors because
the common-mode feedback compensates the input bias.
to a high level to keep the IC out of the shutdown mode.
The SD pin should be tied to a definite voltage to avoid
The inputs can be biased from 0.5V to VDD-0.5V, and the
outputs are still biased at mid-supply of the power
unwanted state changing.
amplifier. If the inputs are biased out of the input range,
the coupling capacitors are required. Second, the fully
differential amplifier has outstanding immunity against
supply voltage ripple (217Hz) cuased by the GSM RF transmitters’ signal which is better than the typical audio
amplifier.
Thermal Protection
The over-temperature circuit limits the junction temperature of the APA0715. When the junction temperature exceeds T J = +150 oC, a thermal sensor turns off the
amplifiers, allowing the device to cool. The thermal sensor allows the amplifiers to start-up after the junction temperature cools down to about 125 oC. The thermal protection is designed with a 25 oC hysteresis to lower the average TJ during continuous thermal overload conditions,
increasing lifetime of the IC.
Over-Current Protection
The APA0715 monitors the output buffers’current. When
the over-current occurs, the output buffers’current will be
reduced and limited to a fold-back current level.
The power amplifier will go back to normal operation until
the over-current situation has been removed. In addition,
if the over-current period is long enough and the IC’s
junction temperature reaches the thermal protection
threshold, the IC enters thermal protection mode.
Shutdown Function
In order to reduce power consumption while not in use,
the APA0715 contains a shutdown function to externally
turn off the amplifier bias circuitry. This shutdown feature
turns the amplifier off when logic low is placed on the SD
pin for APA0715. The trigger point between a logic high
and logic low level is typically 1.8V. It is best to switch
between the ground and the supply voltage VDD to pro-
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2008
15
www.anpec.com.tw
APA0715
Application Information
Input Resistance (Ri) and Feedback Resistance (Rf)
input in most applications because the DC level of the
The gain for the APA0715 is set by the external input resistors (Ri) and external feedback resistors (Rf).
amplifiers’ inputs are held at VDD/2. Please note that it is
important to confirm the capacitor polarity in the application.
Rf
Ri
AV =
Effective Bypass Capacitor (CBYPASS)
(1)
The BYPASS pin sets the VDD/2 for internal reference by
Ri and Rf should range from 1kΩ to 100kΩ. Ri is 10kΩ
recommended. For the performance of a fully differential
voltage divider. Adding capacitors at this pin to filter the
noise and regulator the mid-supply rail will increase the
amplifier, it’s better to select matching input resistors Ri1
and R i2 . Therefore, 1% tolerance resistors are
PSRR and noise performance.
The capacitors should be as close to the device as
recommended. If the input resistors are not matched, the
CMRR and PSRR performance are worse than using
possible. The effect of a larger bypass capacitor will improve PSRR due to increased supply stability.
matching devices.
The bypass capacitance also affects to the start time. The
large capacitors will increase the start time when device
Input Capacitor (Ci)
in shutdown.
When the APA0715 is driven by a differential input source,
the input capacitor may not be required.
Optimizing Depop Circuitry
In the single-ended input application, an input capacitor,
Ci, is required to allow the amplifier to bias the input sig-
Circuitry has been included in the APA0715 to minimize
the amount of popping noise at power-up and when com-
nal to the proper DC level for optimum operation. In this
case, Ci and the input resistance Ri form a high-pass filter
ing out of shutdown mode. Popping occurs whenever a
voltage step is applied to the speaker. In order to elimi-
with the corner frequency determined in the following
nate clicks and pops, all capacitors must be fully discharged before turn-on. Rapid on/off switching of the de-
equation:
FC(highpass) =
1
2πR iCi
vice or the shutdown function will cause the click and pop
circuitry.
(2)
The value of Ci must be considered carefully because it
directly affects the low frequency performance of the circuit.
The value of Ci will also affect turn-on pops. The bypass
Consider the example where Ri is 10kΩ and the specification that calls for a flat bass response down to 100Hz.
Although the BYPASS pin current source cannot be
voltage ramp up should be slower than input bias voltage.
modified, the size of CBYPASS can be changed to alter the
device turn-on time and the amount of clicks and pops.
The equation is reconfigured as below:
Ci =
1
2πRiFc
By increasing the value of CBYPASS, turn-on pop can be
reduced. However, the tradeoff for using a larger bypass
(3)
When the input resistance variation is considered, the Ci
capacitor is to increase the turn-on time for this device.
There is a linear relationship between the size of CBYPASS
is 0.16µF. Therefore, a value in the range of 0.22µF to
0.47µF would be chosen. A further consideration for this
and the turn-on time.
A high gain amplifier intensifies the problem as the small
capacitor is the leakage path from the input source through
the input network (Ri + Rf, Ci) to the load.
delta in voltage is multiplied by the gain. Hence, it is advantageous to use low-gain configurations.
This leakage current creates a DC offset voltage at the
input of the amplifier. The offset reduces useful
Power Supply Decoupling Capacitor (Cs)
headroom, especially in high gain applications. For this
reason, a low-leakage tantalum or ceramic capacitor is
The APA0715 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to
the best choice. When polarized capacitors are used, the
positive side of the capacitor should face the amplifier
ensure the output total harmonic distortion (THD+N) is
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2008
16
www.anpec.com.tw
APA0715
Application Information (Cont.)
Power Supply Decoupling Capacitor (Cs) (Cont.)
as low as possible. Power supply decoupling also prevents the oscillations being caused by long lead length
less than the dissipation in the half power range. Calculating the efficiency for a specific system is the key to
between the amplifier and the speaker.
The optimum decoupling is achieved by using two differ-
proper power supply design. For a Mono 1W audio system with 8Ω loads and a 5V supply, the maximum draw
on the power supply is almost 1.63W.
ent types of capacitors that target on different types of
noises on the power supply leads. For higher frequency
R L (Ω)
transients, spikes, or digital hash on the line, a good low
equivalent-series- resistance (ESR) ceramic capacitor,
typically 0.1µF, is placed as close as possible to the device VDD lead works best. For filtering lower frequency
8
noise signals, a large aluminum electrolytic capacitor of
10µF or greater placed near the audio power amplifier is
4
recommended.
Fully Differential Amplifier Efficiency
3
The traditional class AB power amplifier efficiency can be
calculated starts out as being equal to the ratio of power
from the power supply to the power delivered to the load.
The following equations are the basis for calculating the
2
(4)
IDD(AVG)
0.17
0.23
0.33
0.43
0.29
0.51
0.66
0.70
0.37
0.52
0.74
0.92
0.58
0.66
0.63
0.46
1.06
1.30
1.21
0.91
1.32
1.58
1.63
1.49
0.83
1.16
1.63
2.06
1.46
2.50
3.21
3.51
1.82
2.58
3.63
4.49
cates that as VDD goes down, efficiency goes up. In other
words, use the efficiency analysis to choose the correct
supply voltage and speaker impedance for the application.
VP
2
Layout Recommendation
1. All components should be placed close to the APA0715.
(5)
For example, the input capacitor (Ci) should be close
to APA0715’s input pins to avoid causing noise cou-
2VP
=
πRL
pling to APA0715’s high impedance inputs; the
decoupling capacitor (Cs ) should be placed by the
So the Efficiency (η) is:
πVP π 2PORL
Efficiency (η) =
=
4VDD
4VDD
30.1
43.1
61.5
77.7
27.5
48.1
62.4
74.1
27.5
38.7
55.1
66.8
efficiency equation to an utmost advantage when possible.
Note that in equation, VDD is in the denominator. This indi-
2
2V V
PSUP = VDD XIDD(AVG)= DD PP
πRL
0.25
0.50
1
1.6
0.4
1.2
2
2.6
0.5
1
2
3
P D (W) P SUP (W)
A final point to remember about linear amplifiers (either
SE or Differential) is how to manipulate the terms in the
VOrms
V
= P
RL
2RL
VOrms =
IDD(A)
Amplifier Syetems
where:
PO =
Efficiency
(%)
Table 1: Efficiency vs. Output Power in 5-V Differential
amplifier efficiency.
P
Efficiency (η) = O
PSUP
P O (W)
APA0715’s power pin to decouple the power rail noise.
2. The output traces should be short, wide ( >50mil), and
(6)
Table 1 calculates efficiencies for four different output
symmetric.
3. The input trace should be short and symmetric.
power levels. Note that the efficiency of the amplifier is
quite low for lower power levels and rises sharply as
4. The power trace width should greater than 50mil.
5. The MSOP-8P and DFN3x3-8 Thermal PAD should be
power to the load is increased resulting in nearly flat internal power dissipation over the normal operating range.
soldered on PCB, and the ground plane needs soldered mask (to avoid short circuit) except the Thermal
Note that the internal dissipation at full output power is
PAD area.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2008
17
www.anpec.com.tw
APA0715
Application Information (Cont.)
Layout Recommendation (Cont.)
1.85mm
0.38mm
1.95mm
3.3mm
1.4mm
0.65mm
0.7mm
ThermalVia
diameter
0.3mm X 5
Ground plane
for Thermal
PAD
Solder Mask
to Prevent
Short Circuit
Figure 1:TDFN3X3-8 Land Pattern Recommendation
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2008
18
www.anpec.com.tw
APA0715
Package Information
MSOP-8
D
b
0.25
A
A1
A2
c
L
GAUGE PLANE
SEATING PLANE
0
e
E
E1
SEE VIEW A
VIEW A
S
Y
M
B
O
L
MSOP-8
MILLIMETERS
MIN.
INCHES
MIN.
MAX.
A
MAX.
0.043
1.10
0.15
0.000
0.006
0.75
0.95
0.030
0.037
b
0.22
0.38
0.009
0.015
A1
A2
0.00
c
0.08
0.23
0.003
0.009
D
2.90
3.10
0.114
0.122
E
4.70
5.10
0.185
0.201
E1
2.90
3.10
0.114
0.122
e
0.65 BSC
0.026 BSC
L
0.40
0.80
0.016
0.031
0
0°
8°
0°
8°
Note: 1. Follow JEDEC MO-187 AA.
2. Dimension “D”does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil
per side.
3. Dimension “E1”does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 5 mil per side.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2008
19
www.anpec.com.tw
APA0715
Package Information
MSOP-8P
D
SEE VIEW A
E
c
A
0.25
b
GAUGE PLANE
SEATING PLANE
A1
L
0
A2
e
E1
EXPOSED
PAD
E2
D1
VIEW A
S
Y
M
B
O
L
A
MSOP-8P
INCHES
MILLIMETERS
MIN.
MAX.
MIN.
MAX.
1.10
0.043
0.000
0.006
A1
0.00
0.15
A2
0.75
0.95
0.030
0.037
0.015
b
0.22
0.38
0.009
c
0.08
0.23
0.003
0.009
D
2.90
3.10
0.114
0.122
D1
1.50
2.50
0.059
0.098
E
4.70
5.10
0.185
0.201
E1
2.90
3.10
0.114
0.122
E2
1.50
2.50
0.059
0.098
e
0.65 BSC
0.026 BSC
L
0.40
0.80
0.016
0.031
0
0°
8°
0°
8°
Note: 1. Follow JEDEC MO-187 AA-T
2. Dimension “D”does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not flash or protrusions.
3. Dimension “E1” does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 6 mil per side.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2008
20
www.anpec.com.tw
APA0715
Package Information
TDFN3x3-8
A
b
E
D
Pin 1
A1
A3
D2
L K
E2
Pin 1
Corner
e
S
Y
M
B
O
L
A
A1
TDFN3*3-8
INCHES
MILLIMETERS
MAX.
MIN.
MAX.
0.70
0.80
0.028
0.031
0.00
0.05
0.000
0.002
MIN.
A3
0.20 REF
0.008 REF
b
0.25
0.35
0.010
0.014
D
2.90
3.10
0.114
0.122
D2
1.90
2.40
0.075
0.094
E
2.90
3.10
0.114
0.122
1.75
0.055
0.069
0.50
0.012
E2
1.40
e
0.65 BSC
L
0.30
K
0.20
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2008
0.026 BSC
0.020
0.008
21
www.anpec.com.tw
APA0715
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
MSOP-8(P)
Application
A
H
330.0±2.00
50 MIN.
P0
P1
4.00±0.10
8.00±0.10
A
H
178.0±2.00 50 MIN.
TDFN3x3-8
P0
4.0±0.10
T1
d
D
1.5 MIN.
20.2 MIN.
W
E1
12.0±0.30 1.75±0.10
F
5.5±0.05
P2
D0
D1
T
A0
B0
K0
2.00±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
5.30±0.20
3.30±0.20
1.40±0.20
T1
C
d
D
W
E1
F
12.4+2.00 13.0+0.50
-0.00
-0.20 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10
P1
8.0±0.10
C
12.4+2.00 13.0+0.50
-0.00
-0.20
P2
D0
2.0±0.05
1.5+0.10
-0.00
D1
1.5 MIN.
T
A0
B0
5.5±0.05
K0
0.6+0.00
-0.40 3.30±0.20 3.30±0.20 1.30±0.20
(mm)
Devices Per Unit
Package Type
MOSP-8(P)
Unit
Tape & Reel
Quantity
3000
TDFN3x3-8
Tape & Reel
3000
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2008
22
www.anpec.com.tw
APA0715
Taping Dircetion Information
MSOP-8(P)
USER DIRECTION OF FEED
TDFN3x3-8
USER DIRECTION OF FEED
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2008
23
www.anpec.com.tw
APA0715
Reflow Condition
(IR/Convection or VPR Reflow)
tp
TP
Critical Zone
TL to TP
Ramp-up
Temperature
TL
tL
Tsmax
Tsmin
Ramp-down
ts
Preheat
25
t 25°C to Peak
Time
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TST
ESD
Latch-Up
Method
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B,A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
Description
245°C, 5 sec
1000 Hrs Bias @125°C
168 Hrs, 100%RH, 121°C
-65°C~150°C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms, 1tr > 100mA
Classification Reflow Profiles
Profile Feature
Average ramp-up rate
(TL to TP)
Preheat
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
Time maintained above:
- Temperature (TL)
- Time (tL)
Peak/Classification Temperature (Tp)
Time within 5°C of actual
Peak Temperature (tp)
Ramp-down Rate
Time 25°C to Peak Temperature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
3°C/second max.
3°C/second max.
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
183°C
60-150 seconds
217°C
60-150 seconds
See table 1
See table 2
10-30 seconds
20-40 seconds
6°C/second max.
6°C/second max.
6 minutes max.
8 minutes max.
Note: All temperatures refer to topside of the package. Measured on the body surface.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2008
24
www.anpec.com.tw
APA0715
Classification Reflow Profiles (Cont.)
Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures
3
3
Package Thickness
<2.5 mm
≥2.5 mm
Volume mm
≥350
225 +0/-5°C
225 +0/-5°C
Volume mm
<350
240 +0/-5°C
225 +0/-5°C
Table 2. Pb-free Process – Package Classification Reflow Temperatures
3
3
3
Volume mm
Volume mm
Volume mm
<350
350-2000
>2000
<1.6 mm
260 +0°C*
260 +0°C*
260 +0°C*
1.6 mm – 2.5 mm
260 +0°C*
250 +0°C*
245 +0°C*
≥2.5 mm
250 +0°C*
245 +0°C*
245 +0°C*
* Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated
classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL
level.
Package Thickness
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2008
25
www.anpec.com.tw
Similar pages