ICST ICS844004AGIT Femtoclocksâ ¢ crystal-to-lvds frequency synthesizer Datasheet

PRELIMINARY
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS844004I is a 4 output LVDS Synthesizer
optimized to generate Fibre Channel reference
HiPerClockS™ clock frequencies and is a member of the
HiPerClocksTM family of high performance clock
solutions from ICS. Using a 26.5625MHz 18pF
parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL[1:0]):
212.5MHz, 187.5MHz, 159.375MHz, 156.25MHz, 106.25MHz
and 53.125MHz. The ICS844004I uses ICS’ 3rd generation
low phase noise VCO technology and can achieve <1ps
typical rms phase jitter, easily meeting Fibre Channel jitter
requirements. The ICS844004I is packaged in a small 24-pin
TSSOP package.
• Four LVDS outputs
ICS
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following output frequencies: 212.5MHz,
187.5MHz, 159.375MHz, 156.25MHz, 106.25MHz, 53.125MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal
(637KHz - 10MHz): 0.65ps (typical)
• Full 3.3V or 2.5V supply modes
• -40°C to 85°C ambient operating temperature
FREQUENCY SELECT FUNCTION TABLE
Inputs
Input
Frequency
(MHz)
26.5625
ICS844004I
F_SEL1 F_SEL0
M Divider
Value
N Divider
Value
M/N Divider
Value
Output
Frequency
(MHz)
0
0
24
3
8
212.5
26.5625
0
1
24
4
6
159.375
26.5625
1
0
24
6
4
106.25
26.5625
1
1
24
12
2
53.125
26.04166
0
1
24
4
6
156.25
23.4375
0
0
24
3
8
187.5
PIN ASSIGNMENT
nQ1
Q1
VDD o
Q0
nQ0
MR
nPLL_SEL
nc
VDDA
F_SEL0
VDD
F_SEL1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
nQ2
Q2
VDDO
Q3
nQ3
GND
nc
nXTAL_SEL
TEST_CLK
GND
XTAL_IN
XTAL_OUT
ICS844004I
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
Q0
BLOCK DIAGRAM
F_SEL[1:0] Pulldown
nPLL_SEL
2
Pulldown
TEST_CLK Pulldown
1
1
26.5625MHz
XTAL_IN
OSC
XTAL_OUT
nXTAL_SEL
0
Phase
Detector
F_SEL[1:0]
0 0 ÷3
0 1 ÷4
10
11
VCO
637.5MHz
÷6
÷12
nQ0
Q1
nQ1
0
(w/26.5625MHz
Reference)
Q2
Pulldown
nQ2
M = 24 (fixed)
MR
Q3
nQ3
Pulldown
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
844004AGI
www.icst.com/products/hiperclocks.html
REV. A JUNE 15, 2005
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844004I
FEMTOCLOCKS™CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
1, 2
nQ1, Q1
Output
Differential output pair. LVDS interface levels.
3, 22
VDDO
Power
Output supply pins.
4, 5
Q0, nQ0
Ouput
6
MR
Input
7
nPLL_SEL
Input
8, 18
nc
Unused
9
Power
15, 19
VDDA
F_SEL0,
F_SEL1
VDD
XTAL_OUT,
XTAL_IN
GND
Power
16
TEST_CLK
Input
17
nXTAL_SEL
Input
20, 21
nQ3, Q3
Output
23, 24
Q2, nQ2
Output
10, 12
11
13, 14
Type
Input
Power
Input
Description
Differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inver ted outputs nQx
Pulldown
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
Selects between the PLL and TEST_CLK as input to the dividers. When
Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock
(PLL Bypass). LVCMOS/LVTTL interface levels.
No connect.
Analog supply pin.
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
Core supply pin.
Parallel resonant cr ystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Power supply ground.
Pulldown LVCMOS/LVTTL clock input.
Selects between cr ystal or TEST_CLK inputs as the the PLL Reference
Pulldown source. Selects XTAL inputs when LOW. Selects TEST_CLK when HIGH.
LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLDOWN
Input Pulldown Resistor
51
kΩ
844004AGI
Test Conditions
Minimum
www.icst.com/products/hiperclocks.html
2
Typical
Maximum
Units
REV. A JUNE 15, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844004I
FEMTOCLOCKS™CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA
70°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VDD
Core Supply Voltage
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
VDDA
Analog Supply Voltage
3.135
3.3
3.465
V
VDDO
Output Supply Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
TBD
mA
IDDA
Analog Supply Current
TBD
mA
IDDO
Output Supply Current
TBD
mA
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
Test Conditions
2.375
2.5
2.625
V
VDDA
Analog Supply Voltage
2.375
2.5
2.625
V
VDDO
Output Supply Voltage
2.375
2.5
2.625
IDD
Power Supply Current
TBD
mA
IDDA
Analog Supply Current
TBD
mA
IDDO
Output Supply Current
TBD
mA
V
TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input
High Current
IIL
Input
Low Current
844004AGI
Test Conditions
VDD = 3.3V
TEST_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL
TEST_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL
Minimum Typical
2
Maximum
VDD + 0.3
Units
V
VDD = 2.5V
1.7
VDD + 0.3
V
VDD = 3.3V
-0.3
0.8
V
VDD = 2.5V
-0.3
0.7
V
150
µA
VDD = VIN = 3.465 or 2.625V
VDD = 3.465V or 2.625V,
VIN = 0V
www.icst.com/products/hiperclocks.html
3
-150
µA
REV. A JUNE 15, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844004I
FEMTOCLOCKS™CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER
TABLE 3D. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VOD
Differential Output Voltage
Δ VOD
VOD Magnitude Change
VOS
Offset Voltage
Δ VOS
VOS Magnitude Change
Test Conditions
Minimum
Typical
Maximum
Units
350
mV
40
mV
1.45
V
50
mV
TABLE 3E. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VOD
Differential Output Voltage
Test Conditions
Minimum
Typical
350
Maximum
Units
mV
Δ VOD
VOD Magnitude Change
40
mV
VOS
Offset Voltage
1.2
V
Δ VOS
VOS Magnitude Change
50
mV
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Maximum
Units
28.33
MHz
Fundamental
Frequency
23.33
26.5625
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
NOTE: Characterized using an 18pF parallel resonant crystal.
844004AGI
www.icst.com/products/hiperclocks.html
4
REV. A JUNE 15, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844004I
FEMTOCLOCKS™CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
Output Frequency
tsk(o)
Output Skew; NOTE 1, 2
tjit(Ø)
tR / tF
RMS Phase Jitter (Random);
NOTE 3
Output Rise/Fall Time
Test Conditions
Minimum
F_SEL[1:0] = 00
186.67
Typical
Maximum
Units
226.66
MHz
F_SEL[1:0] = 01
140
170
MHz
F_SEL[1:0] = 10
93.33
113.33
MHz
F_SEL[1:0] = 11
46.67
56.66
MHz
TBD
ps
212.5MHz, (637kHz - 10MHz)
0.65
ps
159.375MHz, (637kHz - 10MHz)
0.61
ps
156.25MHz, (637kHz - 10MHz))
0.74
ps
106.25MHz, (637kHz -10MHz)
0.64
ps
53.125MHz, (637kHz - 10MHz)
0.80
ps
20% to 80%
400
ps
odc
Output Duty Cycle
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
%
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol
fOUT
tsk(o)
Parameter
Output Frequency
Test Conditions
Minimum
F_SEL[1:0] = 00
186.67
226.66
MHz
F_SEL[1:0] = 01
140
170
MHz
F_SEL[1:0] = 10
93.33
113.33
MHz
F_SEL[1:0] = 11
46.67
56.66
MHz
Output Skew; NOTE 1, 2
tR / tF
RMS Phase Jitter (Random);
NOTE 3
Output Rise/Fall Time
Units
ps
0.65
ps
159.375MHz, (637kHz - 10MHz)
0.61
ps
156.25MHz, (637kHz - 10MHz))
0.74
ps
106.25MHz, (637kHz -10MHz)
0.64
ps
53.125MHz, (637kHz - 10MHz)
0.80
ps
20% to 80%
430
ps
odc
Output Duty Cycle
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
844004AGI
Maximum
TBD
212.5MHz, (637kHz - 10MHz)
tjit(Ø)
Typical
www.icst.com/products/hiperclocks.html
5
%
REV. A JUNE 15, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844004I
FEMTOCLOCKS™CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
Qx
3.3V±5%
POWER SUPPLY
+ Float GND -
SCOPE
Qx
2.5V±5%
POWER SUPPLY
+ Float GND -
LVDS
SCOPE
LVDS
nQx
nQx
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
nQx
TEST_CLK
Qx
nQy
nQ0:nQ3
Qy
Q0:Q3
tPD
tsk(o)
OUTPUT SKEW
PROPAGATION DELAY
Phase Noise Plot
nQ0:nQ3
Noise Power
Q0:Q3
t PW
t
Phase Noise Mask
odc =
f1
Offset Frequency
PERIOD
t PW
x 100%
t PERIOD
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
844004AGI
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
www.icst.com/products/hiperclocks.html
6
REV. A JUNE 15, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844004I
FEMTOCLOCKS™CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER
VDD
out
80%
DC Input
VSW I N G
Clock
Outputs
LVDS
➤
80%
20%
20%
tR
out
tF
➤
VOS/Δ VOS
➤
OUTPUT RISE/FALL TIME
OFFSET VOLTAGE SETUP
VDD
LVDS
100
➤
VOD/Δ VOD
out
➤
DC Input
➤
out
DIFFERENTIAL OUTPUT VOLTAGE SETUP
844004AGI
www.icst.com/products/hiperclocks.html
7
REV. A JUNE 15, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844004I
FEMTOCLOCKS™CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS844004I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
capacitor should be connected to each VDDA.
3.3V or 2.5V
VDD
.01μF
10 Ω
V DDA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
below were determined using a 26.5625MHz 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
The ICS844004I has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in Figure 2
XTAL_OUT
C1
33p
X1
18pF Parallel Crystal
XTAL_IN
C2
27p
ICS844004I
Figure 2. CRYSTAL INPUt INTERFACE
844004AGI
www.icst.com/products/hiperclocks.html
8
REV. A JUNE 15, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844004I
FEMTOCLOCKS™CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER
3.3V, 2.5V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 3. In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near
the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the
un-used outputs.
2.5V or 3.3V
VDD
LVDS_Driv er
+
R1
100
-
100 Ohm Differential Transmission Line
FIGURE 3. TYPICAL LVDS DRIVER TERMINATION
844004AGI
www.icst.com/products/hiperclocks.html
9
REV. A JUNE 15, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844004I
FEMTOCLOCKS™CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 6.
θJAVS. AIR FLOW TABLE
FOR
24 LEAD TSSOP
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
70°C/W
65°C/W
62°C/W
TRANSISTOR COUNT
The transistor count for ICS844004I is: 2914
844004AGI
www.icst.com/products/hiperclocks.html
10
REV. A JUNE 15, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX
FOR
ICS844004I
FEMTOCLOCKS™CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER
24 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
SYMBOL
Millimeters
Minimum
N
A
Maximum
24
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
7.70
7.90
E
E1
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
844004AGI
www.icst.com/products/hiperclocks.html
11
REV. A JUNE 15, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844004I
FEMTOCLOCKS™CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS844004AGI
ICS844004AGI
24 Lead TSSOP
tube
-40°C to 85°C
ICS844004AGIT
ICS844004AGI
24 Lead TSSOP
2500 tape & reel
-40°C to 85°C
The aforementioned trademarks, HiPerClockS™ and FEMTOCLOCKS™ are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended
without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in
life support devices or critical medical instruments.
844004AGI
www.icst.com/products/hiperclocks.html
12
REV. A JUNE 15, 2005
Similar pages