FDS7082N3 30V N-Channel PowerTrench MOSFET General Description Features This N-Channel MOSFET in the thermally enhanced SO8 FLMP package has been designed specifically to improve the overall efficiency of DC/DC converters. Providing a balance of low RDS(ON) and Qg it is ideal for synchronous rectifier applications in both isolated and non-isolated topologies. It is also well suited for both high and low side switch applications in Point of Load converters. • 17.5 A, 30 V RDS(ON) = 6 mΩ @ VGS = 10 V RDS(ON) = 8 mΩ @ VGS = 4.5 V • High performance trench technology for extremely low RDS(ON) • Low Qg and Rg for fast switching Applications • FLMP SO-8 package for enhanced thermal performance in an industry-standard package outline. • Secondary side Synchronous rectifier • Synchronous Buck VRM and POL Converters 5 Absolute Maximum Ratings Symbol Bottom-side Drain Contact 4 6 3 7 2 8 1 TA=25oC unless otherwise noted Ratings Units VDSS Drain-Source Voltage Parameter 30 V VGSS Gate-Source Voltage ±20 V ID Drain Current (Note 1a) 17.5 A PD Power Dissipation for Single Operation (Note 1a) 3.0 (Note 1b) 1.5 – Continuous – Pulsed TJ, TSTG 60 W –55 to +150 °C (Note 1a) 40 °C/W (Note 1) 0.5 °C/W Operating and Storage Junction Temperature Range Thermal Characteristics RθJA Thermal Resistance, Junction-to-Ambient RθJC Thermal Resistance, Junction-to-Case Package Marking and Ordering Information Device Marking Device Reel Size Tape width Quantity FDS7082N3 FDS7082N3 13’’ 12mm 2500 units 2004 Fairchild Semiconductor Corporation FDS7082N3 Rev D1 (W) FDS7082N3 February 2004 Symbol Parameter TA = 25°C unless otherwise noted Test Conditions Min Typ Max Units Off Characteristics BVDSS ∆BVDSS ∆TJ IDSS IGSS VGS = 0 V, ID = 250 µA 30 V Drain–Source Breakdown Voltage Breakdown Voltage Temperature Coefficient ID = 250 µA, Referenced to 25°C Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V 10 µA Gate–Body Leakage VGS = ± 20 V, VDS = 0 V ± 100 nA 3 V On Characteristics 24 mV/°C (Note 2) VGS(th) ∆VGS(th) ∆TJ RDS(on) Gate Threshold Voltage Gate Threshold Voltage Temperature Coefficient Static Drain–Source On–Resistance gFS Forward Transconductance VDS = VGS, ID = 250 µA ID = 250 µA, Referenced to 25°C 1 2 –4.3 mV/°C VGS = 10 V, ID = 17.5 A VGS = 4.5 V, ID = 15.5 A VGS = 10 V, ID = 17.5 A,TJ = 125°C VDS = 10 V, ID = 17.5 A 4.9 6.5 5.0 116 VDS = 15 V, V GS = 0 V, f = 1.0 MHz 2271 pF 554 pF 213 pF 1.4 Ω 6.0 8.0 8.0 mΩ S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance RG Gate Resistance Switching Characteristics td(on) Turn–On Delay Time VGS = 15 mV, f = 1.0 MHz (Note 2) VDD = 15 V, ID = 1 A, VGS = 10 V, RGEN = 6 Ω 14 20 ns ns tr Turn–On Rise Time 12 37 td(off) Turn–Off Delay Time 38 64 ns tf Turn–Off Fall Time 18 32 ns Qg Total Gate Charge VDS = 15 V, ID = 17.5 A, VGS =10 V 43 53 nC Qg Total Gate Charge VDS = 15 V, ID = 17.5 A, VGS = 5 V 22 31 nC Qgs Gate–Source Charge 6.8 nC Qgd Gate–Drain Charge 6.9 nC Drain–Source Diode Characteristics and Maximum Ratings IS VSD trr Qrr Maximum Continuous Drain–Source Diode Forward Current Drain–Source Diode Forward VGS = 0 V, IS = 2.5 A Voltage IF = 17.5 A, Diode Reverse Recovery Time diF/dt = 100 A/µs Diode Reverse Recovery Charge (Note 2) 0.7 2.5 A 1.2 V 31 nS 21 nC FDS7082N3 Rev D1 (W) FDS7082N3 Electrical Characteristics Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. a) 40°C/W when mounted on a 1in2 pad of 2 oz copper b) 85°C/W when mounted on a minimum pad of 2 oz copper Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0% FDS7082N3 Rev D1 (W) FDS7082N3 Electrical Characteristics FDS7082N3 Typical Characteristics 60 3 4.0V RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE ID, DRAIN CURRENT (A) VGS = 10V 4.5V 6.0V 40 3.5V 20 3.0V 0 0 0.5 1 VDS, DRAIN-SOURCE VOLTAGE (V) 2.6 2.4 2.2 2 1.8 4.0V 1.6 4.5V 1.4 5.0V 1.2 6.0V 1 10V 0.8 0 1.5 Figure 1. On-Region Characteristics. 10 20 30 40 ID, DRAIN CURRENT (A) 50 60 Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 0.022 1.6 ID = 8.75A ID = 17.5A VGS = 10V 1.4 RDS(ON), ON-RESISTANCE (OHM) RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE VGS = 3.5V 2.8 1.2 1 0.8 0.6 0.018 0.014 TA = 125oC 0.01 TA = 25oC 0.006 0.002 -50 -25 0 25 50 75 100 o TJ, JUNCTION TEMPERATURE ( C) 125 150 2 Figure 3. On-Resistance Variation withTemperature. 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 10 Figure 4. On-Resistance Variation with Gate-to-Source Voltage. 60 100 IS, REVERSE DRAIN CURRENT (A) VDS = 5V ID, DRAIN CURRENT (A) 50 40 30 TA =125oC 25oC 20 -55oC 10 10 TA = 125oC 1 25oC 0.1 -55oC 0.01 0.001 0.0001 0 2 2.5 3 3.5 VGS, GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics. 4 0 0.2 0.4 0.6 0.8 1 VSD, BODY DIODE FORWARD VOLTAGE (V) 1.2 Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. FDS7082N3 Rev D1 (W) FDS7082N3 Typical Characteristics 10 3000 f = 1MHz VGS = 0 V 2500 8 VDS = 5V CAPACITANCE (pF) VGS, GATE-SOURCE VOLTAGE (V) ID = 17.5A 10V 6 15V 4 Ciss 2000 1500 1000 2 Coss 500 Crss 0 0 0 10 20 30 Qg, GATE CHARGE (nC) 40 50 0 Figure 7. Gate Charge Characteristics. 20 Figure 8. Capacitance Characteristics. 50 1000 100 P(pk), PEAK TRANSIENT POWER (W) RDS(ON) LIMIT ID , D R A IN C U R R E N T (A ) 5 10 15 VDS, DRAIN TO SOURCE VOLTAGE (V) 100µs 1ms 10ms 100ms 1s 10 1 10s DC VGS = 10V SINGLE PULSE o RθJA = 85 C/W 0.1 o TA = 25 C 0.01 0.01 0.1 1 10 VDS, DRAIN-SOURCE VOLTAGE (V) 100 SINGLE PULSE RθJA = 85°C/W TA = 25°C 40 30 20 10 0 0.01 Figure 9. Maximum Safe Operating Area. 0.1 1 10 t1, TIME (sec) 100 1000 Figure 10. Single Pulse Maximum Power Dissipation. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1.00 D = 0.5 RθJA(t) = r(t) * RθJA RθJA = 85 °C/W 0.2 0.10 0.1 0.05 P(pk) 0.02 0.01 t1 0.01 t2 TJ - TA = P * RθJA(t) Duty Cycle, D = t1 / t2 SINGLE PULSE 0.00 0.0001 0.001 0.01 0.1 1 10 100 1000 t1, TIME (sec) Figure 11. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in Note 1b. Transient thermal response will change depending on the circuit board design. FDS7082N3 Rev D1 (W) FDS7082N3 Dimensional Outline and Pad Layout FDS7082N3 Rev D1 (W) TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ FACT Quiet Series™ ActiveArray™ FAST Bottomless™ FASTr™ CoolFET™ FPS™ CROSSVOLT™ FRFET™ DOME™ GlobalOptoisolator™ EcoSPARK™ GTO™ E2CMOSTM HiSeC™ EnSignaTM I2C™ FACT™ ImpliedDisconnect™ Across the board. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I8