SN54/74LS569A FOUR-BIT UP/DOWN COUNTER WITH THREE-STATE OUTPUTS The SN54 / 74LS569A is designed as programmable up/down BCD and Binary counters respectively. These devices have 3-state outputs for use in bus organized systems. With the exception of output enable (OE) and asynchronous clear (ACLR), all functions occur on the positive edge of the clock pulse (CP). When the LOAD input is LOW, the outputs will be programmed by the parallel data inputs (A, B, C, D) on the next clock edge. Enabling of the counters occurs only when CEP and CET are LOW and LOAD is HIGH. Direction of the count is controlled by the up-down input (U/D), HIGH counts up and LOW counts down. High-speed counting and cascading is implemented by internal look-ahead carry logic and an active LOW ripple carry output (RCO). On the LS569A, the RCO is LOW at binary 15 during up-count and during down-count it is also LOW at binary 0. During normal cascading operation RCO connected to the succeeding block at CET is the only requisite. When counting and when RCO is LOW, the clocked carry output (CCO) provides a HIGH-LOW-HIGH pulse for a duration equal to the LOW time of the clock pulse. Two active LOW reset lines are provided, a master reset asynchronous clear (ACLR) and a synchronous clear (SCLR). When in a HIGH state, the output control (OE) input forces the counter output into a HIGH impedance state and when LOW, the counter outputs are enabled. FOUR-BIT UP/ DOWN COUNTER WITH THREE-STATE OUTPUTS LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 732-03 20 1 N SUFFIX PLASTIC CASE 738-03 20 • ESD > 3500 Volts 1 DW SUFFIX SOIC CASE 751D-03 CONNECTION DIAGRAM (TOP VIEW) 20 1 ORDERING INFORMATION SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXDW SOIC Note: Pin 1 is marked for orientation. GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 74 4.5 4.75 5.0 5.0 5.5 5.25 V TA Operating Ambient Temperature Range 54 74 – 55 0 25 25 125 70 °C IOH Output Current — High Except RCO, CCO 54 74 – 1.0 – 2.6 mA IOH Output Current — High RCO, CCO 54, 74 – 0.44 mA IOL Output Current — Low Except RCO, CCO 54 74 12 24 mA IOL Output Current — Low, RCO, CCO 54 74 4.0 8.0 mA FAST AND LS TTL DATA 5-573 SN54/74LS569A FUNCTION TABLE INPUTS CP D C B A OUTPUTS LOAD CET CEP U/D ACLR SCLR OE RCO CCO YD A/R A/R H H (QT – CP) + 1 (QT – CP) – 1 NC NC NC NC NC NC NC NC ↑ ↑ ↑ ↑ X X X X X X X X X X X X X X X X H H H H L L H L L L X H H L X X H H H H H H H H L L L L A/R A/R H A/R Ω ↑ ↑ X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X L L H L L H L H X L H X H H H L L L H H H H H H H H H H H H L L L L L L L L H L L H L H L H X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X L X X X X X X X X X X H L L H X L L H X X X L H X X L H X X X H L L L H L L L X H H H H H L L L L X H L L L L X X X X X L L L L L L L L L H H H L L H H L L H X ↑ ↑ ↑ ↑ ↑ ↑ X X X X (QT — CP) = Output state prior to clock edge NC = No change H H H H H H H H H H H X YC YB H H H L L L H H H L L L H H H L L L Overflow Overflow Overflow Inhibit Underflow Underflow Underflow Inhibit L L L L L L L L L H L L L L L L L L L L L L L L L L L H L L L L L L L L Load Example Clear (Synchronous) Clear (Synchronous) Clear (Synchronous) Clear (Synchronous) Asynchronous Clear Asynchronous Clear Asynchronous Clear Asynchronous Clear Output Disabled Hi-Z A/R = Assumes required output state; High except during Overflow and Underflow X = Don’t care OE ACLR Q D R CP Q A * B * C * D * SCLR Y A Y B Y C Y D LOAD CEP CET CP RCO U/D CCO FAST AND LS TTL DATA 5-574 Count Up Count Down Count Inhibit Count Inhibit H H H L L L LOGIC DIAGRAM * YA SN54/74LS569A DEFINITION OF FUNCTIONAL TERMS A, B, C, D The four programmable data inputs. CEP Count Enable Parallel. Can be used to enable and inhibit counting in high speed cascaded operation. CEP must be LOW to count. CET Count Enable Trickle. Enables the ripple carry output for cascaded operation. Must be LOW to count. CP Clock Pulse. All synchronous functions occur on the LOW-to-HIGH transition of the clock. LOAD Enables parallel load of counter outputs from data inputs on the next clock edge. Must be HIGH to count. U/D Up/Down Count Control. HIGH counts up and LOW counts down. ACLR Asynchronous Clear. Master reset of counters to zero when ACLR is LOW, independent of the clock. SCLR Synchronous clear of counters to zero on the next clock edge when SCLR is LOW. OE A HIGH on the output control sets the four counter outputs in the high impedance, and a LOW, enables the output. YA, YB, YC, YD The four counter outputs. RCO Ripple Carry Output. Output will be LOW on the maximum count on up-count. Upon down-count, RCO is LOW at 0000. CCO Clock Carry Output. While counting and RCO is LOW, CCO will follow the clock HIGH-LOW-HIGH transition. LOW-POWER SCHOTTKY INPUT/OUTPUT CURRENT INTERFACE CONDITIONS Note: Actual current flow direction shown FAST AND LS TTL DATA 5-575 SN54/74LS569A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Min Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage Output HIGH Voltage 54 0.7 74 0.8 – 0.65 IOZH Unit – 1.5 Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = – 18 mA 54 2.4 3.4 V 74 2.4 3.1 V RCO, CCO 54 2.5 3.5 V 74 2.7 3.5 V 0.25 74 0.4 0.35 Test Conditions V YA– YD 54, 74 Output LOW Voltage Max 2.0 VOH VOL Typ VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table V IOL = IOL MAX VCC = VCC MIN, VIN = VIL or VIH per Truth Table 0.5 V Output Off Current HIGH 20 µA VCC = MAX, VO = 2.7 V IOZL Output Off Current LOW – 20 µA VCC = MAX, VO = 0.4 V 20 IIH Input HIGH Current µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V Others – 0.4 mA IIL Input LOW Current CET – 0.8 mA IOS Short Circuit Current (Note 1) ICC Power Supply Current, 3-State RCO, CCO – 20 –100 mA Others – 30 – 130 mA 43 mA Max Unit VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C) Limits Symbol Parameter Min Typ FAST AND LS TTL DATA 5-576 Test Conditions fMAX Maximum Toggle Frequency tPLH tPHL Propagation Delay Clock to Q 35 15 20 MHz ns tPLH tPHL Propagation Delay CET to RCO 14 15 ns tPLH tPHL Propagation Delay U/D to RCO 20 24 ns tPLH tPHL Propagation Delay Clock to RCO 20 25 ns tPLH tPHL Propagation Delay CET to CCO 16 28 ns tPLH tPHL Propagation Delay CEP to CCO 16 26 ns tPLH tPHL Propagation Delay Clock to CCO 15 17 ns tPLH tPHL Propagation Delay ACLR to Q 22 32 ns tPZH tPZL Output Enable Time 15 20 ns tPHZ tPLZ Output Disable Time 20 27 ns FAST AND LS TTL DATA 5-577 VCC = 5.0 V CL = 45 pF RL = 667 Ω CL = 5.0 pF SN54/74LS569A AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Limits Symbol Parameter Min Typ Max Unit tW Clock Pulse Width (Low) 20 ns ts Setup Time, A, B, C, D 20 ns ts Setup Time, SCLR 20 ns ts Setup Time, LOAD 25 ns ts Setup Time, U/D 30 ns ts Setup Time, CET, CEP 20 ns th Hold Time, Any Inputs 0 ns trec ACLR 15 ns Test Conditions VCC = 5.0 V MICROPROGRAMMABLE DUAL-EVENT 8-BIT COUNTERS LS569A LS569A LS569A LS569A FAST AND LS TTL DATA 5-578 Case 751D-03 DW Suffix 20-Pin Plastic SO-20 (WIDE) "! ! " -A11 1 10 ! " # P C -T- " #! D J F K ! #! * * !" $ !" M * R X 45° " " %# G ! " ! -B- ! " 20 & ! ! ° ° ° ° ) ) ) ! Case 732-03 J Suffix 20-Pin Ceramic Dual In-Line "! ! $" '' " # !" " !" " %# 20 " 11 1 10 B L C F N H G D J M K Case 738-03 N Suffix 20-Pin Plastic ! ! ° ° ° ° ! " " ! ( " " B ! ! $ ! ( ! " # ! C -T- L K G ! & 11 E ! 10 1 #! !#! "! -A20 ! $ A " " " N M F J D " " FAST AND LS TTL DATA 5-579 * !" $ !" * ! ! ! ! ! ° ° ! ° ° Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. SYMBOL SW1 SW2 tPLZ Closed Closed tPHZ Closed Closed Literature Distribution Centers: USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. tPZH Open Closed EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. tPZL Closed Open ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. ◊ FAST AND LS TTL DATA 5-580