Cypress CY7C1231H-133AXI 2-mbit (128k x 18) flow-through sram with noblâ ¢ architecture Datasheet

CY7C1231H
2-Mbit (128K x 18) Flow-Through SRAM
with NoBL™ Architecture
Features
Functional Description[1]
• Can support up to 133-MHz bus operations with zero
wait states
— Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for flow-through operation
The CY7C1231H is a 3.3V/2.5V, 128K x 18 Synchronous
Flow-through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1231H is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to
enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
• Byte Write capability
• 128K x 18 common I/O architecture
• 3.3V core power supply
• 3.3V/2.5V I/O operation
• Fast clock-to-output times
Write operations are controlled by the two Byte Write Select
(BW[A:B]) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
— 6.5 ns (133-MHz device)
• Clock Enable (CEN) pin to suspend operation
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
• Synchronous self-timed write
• Asynchronous Output Enable
• Offered in JEDEC-standard lead-free 100-pin TQFP
package
• Burst Capability—linear or interleaved burst order
• Low standby power
Logic Block Diagram
ADDRESS
REGISTER
A0, A1, A
A1
D1
A0
D0
MODE
CLK
CEN
C
CE
ADV/LD
C
BURST
LOGIC
Q1 A1'
A0'
Q0
WRITE ADDRESS
REGISTER
ADV/LD
BWA
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BWB
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
WE
OE
CE1
CE2
CE3
ZZ
INPUT
REGISTER
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQPA
DQPB
E
E
READ LOGIC
SLEEP
CONTROL
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 001-00207 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 26, 2006
[+] Feedback
CY7C1231H
Selection Guide
133 MHz
Unit
Maximum Access Time
6.5
ns
Maximum Operating Current
225
mA
Maximum CMOS Standby Current
40
mA
Pin Configuration
A
A
OE
86
81
CEN
87
82
WE
88
NC(9M)
CLK
89
83
VSS
90
ADV/LD
VDD
91
NC(18M)
CE3
92
84
BWA
93
85
NC
NC
96
BWB
CE2
97
94
A
CE1
98
A
99
95
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
A
A
A
A1
A0
NC/288M
NC/144M
VSS
VDD
NC(72M)
NC(36M)
A
A
A
A
A
A
NC/4M
CY7C1231H
A
BYTE B
VDDQ
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
NC
NC
NC
100
100-pin TQFP Pinout
Document #: 001-00207 Rev. *B
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
BYTE A
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
NC
NC
Page 2 of 12
[+] Feedback
CY7C1231H
Pin Definitions
Name
I/O
Description
A0, A1, A
InputAddress Inputs used to select one of the 128K address locations. Sampled at the rising edge of
Synchronous the CLK. A[1:0] are fed to the two-bit burst counter.
BW[A:B]
InputByte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the
Synchronous rising edge of CLK.
WE
InputWrite Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
Synchronous signal must be asserted LOW to initiate a write sequence.
ADV/LD
InputAdvance/Load Input. Used to advance the on-chip address counter or load a new address. When
Synchronous HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address
can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW
in order to load a new address.
CLK
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK
is only recognized if CEN is active LOW.
CE1
InputChip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE2, and CE3 to select/deselect the device.
CE2
InputChip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE3 to select/deselect the device.
CE3
InputChip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE2 to select/deselect the device.
OE
InputOutput Enable, asynchronous input, active LOW. Combined with the synchronous logic block
Asynchronous inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave
as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked
during the data portion of a write sequence, during the first clock when emerging from a deselected
state, when the device has been deselected.
CEN
InputClock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the SRAM.
Synchronous When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not deselect the
device, CEN can be used to extend the previous cycle when required.
ZZ
InputZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
Asynchronous with data integrity preserved. During normal operation, this pin has to be low or left floating. ZZ pin has
an internal pull-down.
DQs
I/OBidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by
Synchronous the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by address during the clock rise of the read cycle. The direction of the pins is controlled by OE and
the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH,
DQs and DQP[A:B] are placed in a tri-state condition. The outputs are automatically tri-stated during
the data portion of a write sequence, during the first clock when emerging from a deselected state,
and when the device is deselected, regardless of the state of OE.
DQP[A:B]
I/OBidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write
Synchronous sequences, DQP[A:B] is controlled by BWx correspondingly.
Mode
VDD
VDDQ
Input
Strap Pin
Mode Input. Selects the burst order of the device. When tied to Gnd selects linear burst sequence. When
tied to VDD or left floating selects interleaved burst sequence.
Power Supply Power supply inputs to the core of the device.
I/O Power
Supply
VSS
Ground
NC
–
Power supply for the I/O circuitry.
Ground for the device.
No Connects. Not Internally connected to the die. 4M, 9M, 18M, 36M, 72M, 144M, 288M, 576M, and
1G are address expansion pins and are not internally connected to the die.
Document #: 001-00207 Rev. *B
Page 3 of 12
[+] Feedback
CY7C1231H
Functional Overview
The CY7C1231H is a synchronous flow-through burst SRAM
designed specifically to eliminate wait states during
Write-Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. Maximum access delay from the clock
rise (tCDV) is 6.5 ns (133-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE). BW[A:B] can be used to
conduct Byte Write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and 4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory array
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within 6.5
ns (133-MHz device) provided OE is active LOW. After the first
clock of the read access, the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output will be tri-stated
immediately.
Burst Read Accesses
The CY7C1231H has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap around when incremented sufficiently. A HIGH input on
ADV/LD will increment the internal burst counter regardless of
the state of Chip Enable inputs or WE. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.
Document #: 001-00207 Rev. *B
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the Write signal WE
is asserted LOW. The address presented to the address bus
is loaded into the Address Register. The write signals are
latched into the Control Logic block. The data lines are
automatically tri-stated regardless of the state of the OE input
signal. This allows the external logic to present the data on
DQs and DQP[A:B].
On the next clock rise the data presented to DQs and DQP[A:B]
(or a subset for Byte Write operations, see Truth Table for
details) inputs is latched into the device and the write is
complete. Additional accesses (Read/Write/Deselect) can be
initiated on this cycle.
The data written during the Write operation is controlled by
BW[A:B] signals. The CY7C1231H provides Byte Write
capability that is described in the Truth Table. Asserting the
Write Enable input (WE) with the selected Byte Write Select
input will selectively write to only the desired bytes. Bytes not
selected during a Byte Write operation will remain unaltered.
A synchronous self-timed write mechanism has been provided
to simplify the Write operations. Byte Write capability has been
included in order to greatly simplify Read/Modify/Write
sequences, which can be reduced to simple byte write operations.
Because the CY7C1231H is a common I/O device, data
should not be driven into the device while the outputs are
active. The Output Enable (OE) can be deasserted HIGH
before presenting data to the DQs and DQP[A:B] inputs. Doing
so will tri-state the output drivers. As a safety precaution, DQs
and DQP[A:B].are automatically tri-stated during the data
portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1231H has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs are
ignored and the burst counter is incremented. The correct
BW[A:B] inputs must be driven in each cycle of the burst write,
in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive for
the duration of tZZREC after the ZZ input returns LOW.
Page 4 of 12
[+] Feedback
CY7C1231H
Interleaved Burst Sequence
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
00
01
10
11
Second
Address
A1, A0
01
10
11
00
Third
Address
A1, A0
10
11
00
01
Fourth
Address
A1, A0
11
00
01
10
First
Address
Second
Address
Third
Address
Fourth
Address
A1, A0
A1, A0
A1, A0
A1, A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to sleep current
ZZ inactive to exit sleep current
Test Conditions
ZZ > VDD − 0.2V
ZZ > VDD − 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
Max.
40
2tCYC
Unit
mA
ns
ns
ns
ns
2tCYC
2tCYC
0
Truth Table[2, 3, 4, 5, 6, 7, 8]
Address
Used CE1 CE2 CE3 ZZ ADV/LD WE BWX OE CEN CLK
None
H
X
X
L
L
X
X
X
L L->H
Operation
Deselect Cycle
Deselect Cycle
None
X
Deselect Cycle
None
Continue Deselect Cycle
None
READ Cycle (Begin Burst)
X
H
L
X
L
X
X
X
X
External
L
H
L
Next
X
X
X
External
L
H
L
Next
X
X
X
READ Cycle (Continue Burst)
NOP/DUMMY READ (Begin Burst)
DUMMY READ (Continue Burst)
WRITE Cycle (Begin Burst)
DQ
Tri-State
L
X
X
X
L
L->H
Tri-State
L
L
X
X
X
L
L->H
Tri-State
L
H
X
X
X
L
L->H
Tri-State
L
L
H
X
L
L
L->H Data Out (Q)
L
H
X
X
L
L
L->H Data Out (Q)
L
L
H
X
H
L
L->H
Tri-State
L
H
X
X
H
L
L->H
Tri-State
External
L
H
L
L
L
L
L
X
L
L->H
Data In (D)
WRITE Cycle (Continue Burst)
Next
X
X
X
L
H
X
L
X
L
L->H
Data In (D)
NOP/WRITE ABORT (Begin Burst)
None
L
H
L
L
L
L
H
X
L
L->H
Tri-State
WRITE ABORT (Continue Burst)
Next
X
X
X
L
H
X
H
X
L
L->H
Tri-State
Current
X
X
X
L
X
X
X
X
H
L->H
–
None
X
X
X
H
X
X
X
X
X
X
Tri-State
IGNORE CLOCK EDGE (Stall)
Sleep MODE
Truth Table for Read/Write [2, 3]
Function
WE
BWA
BWB
Read
H
X
X
Write – No bytes written
L
H
H
Write Byte A – (DQA and DQPA)
L
H
H
Write Byte B – (DQB and DQPB)
L
H
H
Write All Bytes
L
L
L
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write
selects are asserted, see Truth Table for details.
3. Write is defined by BW[A:B], and WE. See Truth Table for Read/Write.
4. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
5. The DQs and DQP[A:B] pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP[A:B] = Tri-state when
OE is inactive or when the device is deselected, and DQs and DQP[A:B] = data when OE is active.
Document #: 001-00207 Rev. *B
Page 5 of 12
[+] Feedback
CY7C1231H
Maximum Ratings
DC Input Voltage ................................... –0.5V to VDD + 0.5V
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
Supply Voltage on VDDQ Relative to GND ...... –0.5V to +VDD
Range
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to VDDQ + 0.5V
Commercial
Industrial
Ambient
Temperature (TA)
0°C to +70°C
-40°C to +85°C
VDD
VDDQ
3.3V –
5%/+10%
2.5V – 5% to
VDD
Electrical Characteristics Over the Operating Range [9,10]
Parameter
Description
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
VOH
Output HIGH Voltage
VOL
VIH
Output LOW Voltage
Input HIGH Voltage
Test Conditions
Min.
Max.
Unit
3.135
3.6
V
for 3.3V I/O
3.135
VDD
V
for 2.5V I/O
2.375
2.625
for 3.3V I/O, IOH = –4.0 mA
2.4
for 2.5V I/O, IOH = –1.0 mA
2.0
for 3.3V I/O, IOL = 8.0 mA
0.4
for 2.5V I/O, IOL = 1.0 mA
0.4
for 3.3V I/O
2.0
VDD + 0.3V
for 2.5V I/O
1.7
VDD + 0.3V
VIL
Input LOW Voltage[9]
for 3.3V I/O
–0.3
0.8
for 2.5V I/O
–0.3
0.7
IX
Input Leakage Current
except ZZ and MODE
GND ≤ VI ≤ VDDQ
–5
5
Input Current of MODE
Input = VSS
–30
Input = VDD
Input Current of ZZ
V
V
µA
µA
µA
–5
Input = VDD
V
µA
5
Input = VSS
V
V
30
µA
5
µA
IOZ
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
IDD
VDD Operating Supply
Current
VDD = Max., IOUT = 0 mA,
f = fMAX= 1/tCYC
7.5-ns cycle, 133 MHz
225
mA
ISB1
Automatic CE
Power-down
Current—TTL Inputs
VDD = Max, Device Deselected, 7.5-ns cycle, 133 MHz
VIN ≥ VIH or VIN ≤ VIL, f = fMAX,
inputs switching
90
mA
ISB2
Automatic CE
Power-down
Current—CMOS Inputs
VDD = Max, Device Deselected, 7.5-ns cycle, 133 MHz
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
40
mA
ISB3
Automatic CE
Power-down
Current—CMOS Inputs
VDD = Max, Device Deselected, 7.5-ns cycle, 133 MHz
VIN ≥ VDDQ – 0.3V or VIN ≤ 0.3V,
f = fMAX, inputs switching
75
mA
ISB4
Automatic CE
Power-down
Current—TTL Inputs
VDD = Max, Device Deselected, 7.5-ns cycle, 133 MHz
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
45
mA
–5
Notes:
9. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> –2V (Pulse width less than tCYC/2).
10. TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document #: 001-00207 Rev. *B
Page 6 of 12
[+] Feedback
CY7C1231H
Capacitance[11]
Parameter
Test Conditions
100 TQFP
Max.
TA = 25°C, f = 1 MHz,
VDD = 3.3V
VDDQ = 2.5V
5
pF
5
pF
5
pF
100 TQFP
Package
Unit
30.32
°C/W
6.85
°C/W
Description
CIN
Input Capacitance
CCLOCK
Clock Input Capacitance
CI/O
I/O Capacitance
Unit
Thermal Resistance[11]
Parameters
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance,
per EIA/JESD51
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
Z0 = 50Ω
10%
(a)
INCLUDING
JIG AND
SCOPE
2.5V I/O Test Load
R = 351Ω
(b)
(c)
10%
(a)
90%
10%
90%
GND
5 pF
VT = 1.25V
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50Ω
Z0 = 50Ω
≤ 1 ns
≤ 1 ns
R = 1667Ω
2.5V
OUTPUT
90%
10%
90%
GND
5 pF
VL = 1.5V
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50Ω
R =1538Ω
INCLUDING
JIG AND
SCOPE
(b)
≤ 1 ns
≤ 1 ns
(c)
Note:
11. Tested initially and after any design or process change that may affect these parameters.
Document #: 001-00207 Rev. *B
Page 7 of 12
[+] Feedback
CY7C1231H
Switching Characteristics Over the Operating Range [12, 13]
-133
Parameter
tPOWER
Description
[14]
VDD(Typical) to the first Access
Min.
Max.
Unit
1
ms
Clock
tCYC
Clock Cycle Time
7.5
ns
tCH
Clock HIGH
2.5
ns
tCL
Clock LOW
2.5
ns
Output Times
tCDV
Data Output Valid after CLK Rise
tDOH
Data Output Hold after CLK Rise
2.0
6.5
ns
tCLZ
Clock to
Low-Z[15, 16, 17]
0
ns
tCHZ
Clock to
High-Z[15, 16, 17]
3.5
ns
tOEV
OE LOW to Output Valid
3.5
ns
tOELZ
OE LOW to Output Low-Z[15, 16, 17]
tOEHZ
OE HIGH to Output High-Z[15, 16, 17]
0
ns
ns
3.5
ns
Set-up Times
tAS
Address Set-up before CLK Rise
1.5
ns
tALS
ADV/LD Set-up before CLK Rise
1.5
ns
tWES
WE, BW[A:B] Set-up before CLK Rise
1.5
ns
tCENS
CEN Set-up before CLK Rise
1.5
ns
tDS
Data Input Set-up before CLK Rise
1.5
ns
tCES
Chip Enable Set-up before CLK Rise
1.5
ns
tAH
Address Hold after CLK Rise
0.5
ns
tALH
ADV/LD Hold after CLK Rise
0.5
ns
tWEH
WE, BW[A:B] Hold after CLK Rise
0.5
ns
tCENH
CEN Hold after CLK Rise
0.5
ns
tDH
Data Input Hold after CLK Rise
0.5
ns
tCEH
Chip Enable Hold after CLK Rise
0.5
ns
Hold Times
Notes:
12. Timing reference level is 1.5V when VDDQ = 3.3V and 1.25V when VDDQ = 2.5V.
13. Test conditions shown in (a) of AC Test Loads, unless otherwise noted.
14. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a read or write operation
can be initiated.
15. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
16. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve tri-state prior to Low-Z under the same system conditions.
17. This parameter is sampled and not 100% tested.
Document #: 001-00207 Rev. *B
Page 8 of 12
[+] Feedback
CY7C1231H
Switching Waveforms
Read/Write Waveforms[18, 19, 20]
1
2
3
tCYC
4
5
6
7
8
9
A5
A6
A7
10
CLK
tCENS
tCENH
tCES
tCEH
tCH
tCL
CEN
CE
ADV/LD
WE
BW[A:B]
A1
ADDRESS
tAS
A2
A4
A3
tCDV
tAH
tDOH
tCLZ
DQ
D(A1)
tDS
D(A2)
Q(A3)
D(A2+1)
tOEV
Q(A4+1)
Q(A4)
tOELZ
WRITE
D(A1)
WRITE
D(A2)
D(A5)
Q(A6)
D(A7)
WRITE
D(A7)
DESELECT
tOEHZ
tDH
OE
COMMAND
tCHZ
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
tDOH
WRITE
D(A5)
READ
Q(A6)
UNDEFINED
Notes:
18. For this waveform ZZ is tied LOW.
19. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
20. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document #: 001-00207 Rev. *B
Page 9 of 12
[+] Feedback
CY7C1231H
Switching Waveforms (continued)
NOP, STALL and Deselect Cycles[18, 19, 21]
1
2
3
A1
A2
4
5
A3
A4
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BW[A:B]
ADDRESS
A5
tCHZ
D(A1)
DQ
Q(A2)
Q(A3)
D(A4)
Q(A5)
tDOH
COMMAND
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
DON’T CARE
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
UNDEFINED
ZZ Mode Timing[22, 23]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes:
21. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
22. Device must be deselected when entering ZZ mode. See Truth Table for all possible signal conditions to deselect the device.
23. I/Os are in tri-state when exiting ZZ sleep mode.
Document #: 001-00207 Rev. *B
Page 10 of 12
[+] Feedback
CY7C1231H
Ordering Information
“Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered”.
Speed
(MHz)
133
Package
Diagram
Ordering Code
Operating
Range
Package Type
CY7C1231H-133AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
CY7C1231H-133AXI
Commercial
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Industrial
Package Diagram
100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)
16.00±0.20
1.40±0.05
14.00±0.10
100
81
80
1
20.00±0.10
22.00±0.20
0.30±0.08
0.65
TYP.
30
12°±1°
(8X)
SEE DETAIL
A
51
31
50
0.20 MAX.
R 0.08 MIN.
0.20 MAX.
0.10
1.60 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
0.25
NOTE:
1. JEDEC STD REF MS-026
GAUGE PLANE
0°-7°
R 0.08 MIN.
0.20 MAX.
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0.60±0.15
0.20 MIN.
51-85050-*B
1.00 REF.
DETAIL
A
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device
Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 001-00207 Rev. *B
Page 11 of 12
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback
CY7C1231H
Document History Page
Document Title: CY7C1231H 2-Mbit (128K x 18) Flow-Through SRAM with NoBL™ Architecture
Document Number: 001-00207
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
347377
See ECN
PCI
New Data Sheet
*A
428408
See ECN
NXR
Converted from Preliminary to Final.
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Removed 100 MHz Speed-bin
Changed Three-State to Tri-State.
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table.
Modified test condition from VDDQ < VDD to VDDQ < VDD
Replaced Package Name column with Package Diagram in the Ordering
Information table.
Updated the Ordering Information Table.
Replaced Package Diagram of 51-85050 from *A to *B
*B
459347
See ECN
NXR
Included 2.5V I/O option
Updated the Ordering Information table.
Document #: 001-00207 Rev. *B
Page 12 of 12
[+] Feedback