Freescale MPC5604PEF0VLQ7R Microcontroller units (mcus) Datasheet

Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MPC5604P
Rev. 5, 11/2009
MPC5604P
144 LQFP
20 mm x 20 mm
MPC5604P Microcontroller
Data Sheet
• High performance 64 MHz e200z0h CPU
– 32-bit Power Architecture Book E CPU
– Variable Length Encoding (VLE)
• Available memory
– As much as 512 KB on-chip code flash memory with
additional 64 KB for EEPROM emulation (data flash),
with ECC, with erase/program controller
– As much as 40 KB on-chip RAM with ECC
• Fail safe protection
– Programmable watchdog timer
– Junction temperature sensor
– Non-maskable interrupt
– Fault collection unit
• Nexus L2+ interface
• Interrupts
– 16 priority level controller
• 16-channel eDMA controller
• General purpose I/Os
– Individually programmable as input, output or special
function
• Two general purpose eTimer units
– Six timers each with up/down count capabilities
– 16-bit resolution, cascadable counters
– Quadrature decode with rotation direction flag
– Double buffer input capture and output compare
• Communications interfaces
– Two LINFlex channels (LIN 2.1)
– Four DSPI channels with automatic chip select
generation
– FlexCAN interface (2.0B Active) with 32 message
objects
– Safety port based on FlexCAN with 32 message objects
and up to 7.5 Mbit/s capability; usable as second CAN
when not used as safety port
– FlexRay™ module (V2.1) with dual or single channel,
32 message objects and up to 10 Mbit/s
100 LQFP
14 mm_x_14 mm
• Two 10-bit A/D converters
– Two × 15 input channels, four channels shared among
the two A/D converters
– Conversion time < 1 µs including sampling time at full
precision
– Programmable Cross Triggering Unit (CTU)
– Four analog watchdogs with interrupt capability
• On-chip CAN/UART/FlexRay Bootstrap loader with Boot
Assist Module (BAM)
• FlexPWM unit
– Eight complementary or independent outputs with ADC
synchronization signals
– Polarity control, reload unit
– Integrated configurable dead time unit and inverter fault
input pins
– 16-bit resolution, up to 2 × fCPU
– Lockable configuration
– Clock generation
– 4–40 MHz main oscillator
– 16 MHz internal RC oscillator
– Software controlled FMPLL capable of speeds as fast as
64 MHz
• Voltage supply
– 3.3 V or 5 V supply for I/Os and ADC
– On-chip single supply voltage regulator with external
ballast transistor
– Operating temperature ranges: –40 to 125 °C or
–40 to 105 °C
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2008, 2009. All rights reserved.
Preliminary—Subject to Change Without Notice
Table of Contents
1
2
3
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Package pinouts and signal descriptions . . . . . . . . . . . . . . . . .6
2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.2 Pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.2.1 Power supply and reference voltage pins . . . . . .8
2.2.2 System Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.2.3 Pin Muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .23
3.2 Recommended operating conditions . . . . . . . . . . . . . .26
3.3 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .29
3.3.1 General notes for specifications at maximum
junction temperature . . . . . . . . . . . . . . . . . . . . .30
3.4 Electromagnetic interference (EMI) characteristics. . . .32
3.5 Electrostatic discharge (ESD) characteristics . . . . . . . .32
3.6 Power management electrical characteristics. . . . . . . .33
3.6.1 Voltage regulator electrical characteristics . . . .33
3.6.2 Voltage monitor electrical characteristics. . . . . .35
3.7 Power up/down sequencing . . . . . . . . . . . . . . . . . . . . .36
3.8 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . .39
3.8.1 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . .39
3.8.2 DC electrical characteristics (5 V) . . . . . . . . . . .39
3.8.3 DC Electrical characteristics (3.3 V) . . . . . . . . .41
3.8.4 I/O pad current specification . . . . . . . . . . . . . . 44
Temperature sensor electrical characteristics . . . . . . . 48
Main oscillator electrical characteristics . . . . . . . . . . . 48
FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 49
16 MHz RC oscillator electrical characteristics . . . . . . 50
Analog-to-digital converter (ADC) electrical characteristics
51
3.13.1 Input impedance and ADC accuracy . . . . . . . . 51
3.13.2 ADC conversion characteristics . . . . . . . . . . . . 56
3.14 Flash memory electrical characteristics . . . . . . . . . . . 57
3.15 AC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.15.1 Pad AC Specifications . . . . . . . . . . . . . . . . . . . 58
3.16 AC Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . 59
3.16.1 RESET Pin Characteristics . . . . . . . . . . . . . . . 59
3.16.2 IEEE 1149.1 interface timing . . . . . . . . . . . . . . 61
3.16.3 Nexus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.16.4 External interrupt timing (IRQ pin) . . . . . . . . . . 66
3.16.5 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Package characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . 73
4.1.1 144 LQFP mechanical outline drawing. . . . . . . 73
4.1.2 100 LQFP Mechanical Outline Drawing . . . . . . 75
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.9
3.10
3.11
3.12
3.13
4
5
6
MPC5604P Microcontroller Data Sheet, Rev. 5
2
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
1
Overview
This document provides electrical specifications, pin assignments, and package diagrams for the MPC5604P series of
microcontroller units (MCUs). For functional characteristics, refer to the MPC5604P Microcontroller Reference Manual.
MPC5604P microcontrollers are members of a new family of next generation microcontrollers built on the Power
Architecture™. This document describes the features of the family and options available within the family members, and
highlights important electrical and physical characteristics of the devices.
The MPC5604P family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. It
belongs to an expanding range of automotive-focused products designed to address electrical hydraulic power steering (EHPS),
electric power steering (EPS) and airbag applications. The advanced and cost-efficient host processor core of the MPC5604P
automotive controller family complies with the Power Architecture embedded category, which is 100 percent user-mode
compatible with the original PowerPC user instruction set architecture (UISA). It operates at speeds of up to 64 MHz and offers
high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure
of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist
with users implementations.
1.1
Device comparison
Table 1 provides a summary of different members of the MPC5604P family and their features to enable a comparison among
the family members and an understanding of the range of functionality offered within this family.
Table 1. MPC5604P device comparison
Feature
MPC5603P
MPC5604P
Code Flash memory (with ECC)
384 KB
512 KB
Data Flash / EE (with ECC)
64 KB
64 KB
RAM (with ECC)
36 KB
40 KB
Processor core
32-bit e200z0h
Instruction set
VLE
CPU performance
0–64 MHz
FMPLL (frequency-modulated phase-locked loop) modules
2
INTC (interrupt controller) channels
PIT (periodic interrupt timer)
147
1 (includes four 32-bit timers)
Enhanced DMA (direct memory access) channels
16
FlexRay
Yes1
FlexCAN (controller area network)
22,3
Safety port
Yes (via second FlexCAN module)
FCU (fault collection unit)
Yes
CTU (cross triggering unit)
Yes
eTimer channels
2×6
FlexPWM (pulse-width modulation) channels
Analog-to-digital converters (ADC)
8
Two (10-bit, 16-channel)
LINFlex modules
2
DSPI (deserial serial peripheral interface) modules
4
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
3
Table 1. MPC5604P device comparison (continued)
Feature
MPC5603P
MPC5604P
CRC (cyclic redundancy check) unit
Yes
Junction temperature sensor
Yes
JTAG interface
Yes
Nexus port controller (NPC)
Supply
Yes (Level 2+)
4
Digital power supply
3.3 V or 5 V single supply with external transistor
Analog power supply
3.3 V or 5 V
Internal RC oscillator
16 MHz
External crystal oscillator
4–40 MHz
Packages
Temperature
100 LQFP
144 LQFP
Standard ambient temperature
Extended ambient temperature
–40 to 125 °C
5
–40 to 145 °C
1
32 message buffers, dual-channel.
Each FlexCAN module has 32 message buffers.
3 One FlexCAN module can act as a Safety Port with a bit rate as high as 7.5 Mbit/s.
4 3.3 V range and 5 V range correspond to different orderable parts.
5 Thermally enhanced 100-pin and 144-pin LQFP packages are under analysis to support an extended ambient
temperature range of –40 to 145 °C. The packages are not yet available.
2
MPC5604P Microcontroller Data Sheet, Rev. 5
4
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
1.2
Block diagram
Figure 1 shows a top-level block diagram of the MPC5604P MCU.
1.2 V Regulator
Control
e200z0 Core
32-bit
General
Purpose
Registers
Integer
Execution
Unit
Special
Purpose
Registers
Exception
Handler
Instruction
Unit
Variable
Length
Encoded
Instructions
Branch
Prediction
Unit
Load/Store
Unit
XOSC
16 MHz
RC Oscillator
FMPLL_0
(System)
FMPLL_1
(FlexRay, MotCtrl)
JTAG
Interrupt
Controller
Nexus Port
Controller
eDMA2 ¥
16 channels
Master
FlexRay
Data (32-bit)
Instruction (32-bit)
Master
Master
Master
Crossbar Switch (XBAR, AMBA 2.0 v6 AHB)
SWT
SRAM
(with ECC)
STM
Flash memory
(with ECC)
Slave
PIT
Slave
ECSM
Slave
Boot
Assist
Module
System
Integration
Unit-Lite
11
Safety Port
FlexCAN
2¥
LINFlex
4¥
DSPI
Fault Collection
Unit
4 ch.
2¥
eTimer (6 ch)
Junc. Temp. Sensor
2¥
ADC
1.2 V Rail Vreg
CTU
FlexPWM
Peripheral Bridge
4 11
CTUCross Triggering Unit
DSPIDeserial Serial Peripheral Interface
ECSMError Correction Status Module
eTimerEnhanced Timer
FlexCANFlexible Controller Area Network
FlexPWMFlexible Pulse Width Modulation
FMPLLFrequency-Modulated Phase-Locked Loop
LINFlexSerial Communication Interface (LIN support)
PITPeriodic Interrupt Timer
SRAMStatic Random-Access Memory
STMSystem Timer Module
SWTSoftware Watchdog Timer
Figure 1. MPC5604P block diagram
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
5
2
Package pinouts and signal descriptions
2.1
Package pinouts
NMI
IRQ6/dspi1 SCK/A[6]
flexray0 CA RX/etimer1 ETC[2]/ctu0 EXT TRG/D[1]
nexus0 MDO[3]/F[4]
nexus0 MDO[2]/F[5]
VDD_HV_IO0
VSS_HV_IO0
nexus0 MDO[1]/F[6]
nexus0 MDO 0
IRQ7/dspi1 SOUT/A[7]
IRQ22/sscm DEBUG[4]/dspi0 CS0/flexpwm0 X[1]/C[4]
IRQ8/dspi1 SIN/A[8]
IRQ23/sscm DEBUG[5]/dspi0 SCK/flexpwm0 FAULT[3]/C[5]
IRQ5/dspi1 CS0/etimer1 ETC[5]/dspi0 CS7/A[5]
sscm DEBUG[7]/dspi0 SIN/flexpwm0 A[1]/C[7]
IRQ21/dspi0 CS1/etimer1 ETC[4]/lin1 TXD/C[3]
VSS_LV_COR0
VDD_LV_COR0
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
144 LQFP
A[4]/etimer1 ETC[0]/dspi2 CS1/etimer0 ETC[4]/FAB/IRQ4
VPP TEST
F[12]/etimer1 ETC[3]
D[14]/flexpwm0 B[1]/dspi3 CS3/dspi3 SIN
G[3]/flexpwm0 A[2]
C[14]/etimer1 ETC[2]/ctu0 EXT TGR
G[2]/flexpwm0 X[2]
C[13]/etimer1 ETC[1]/ctu0 EXT IN/flexpwm0 ext. sync
G[4]/flexpwm0 B[2]
D[12]/flexpwm0 X[1]/lin1 RXD
G[6]/flexpwm0 A[3]
VDD_HV_FL
VSS_HV_FL
D[13]/flexpwm0 A[1]/dspi3 CS2/dspi3 SOUT
VSS_LV_COR1
VDD_LV_COR1
A[3]/etimer0 ETC[3]/dspi2 CS0/flexpwm0 B[3]/ABS1/IRQ3
VDD_HV_IO2
VSS_HV_IO2
jtag0 TDO
jtag0 TCK
jtag0 TMS
jtag0 TDI
G[5]/flexpwm0 X[3]
A[2]/etimer0 ETC[2]/dspi2 SIN/flexpwm0 A[3]/ABS0/IQR2
G[7]/flexpwm0 B[3]
C[12]/etimer0 ETC[5]/dspi2 CS3/dspi3 CS1
G[8]/flexpwm0 FAULT[0]
C[11]/etimer0 ETC[4]/dspi2 CS2/dspi3 CS0
G[9]/flexpwm0 FAULT[1]
D[11]/flexpwm0 B[0]/dspi3 CS1/dspi3 SCK
G[10]/flexpwm0 FAULT[2]
D[10]/flexpwm0 A[0]/dspi3 CS0
G[11]/flexpwm0 FAULT[3]
A[1]/etimer0 ETC[1]/dspi2 SOUT/fcu0 F[1]/IRQ1
A[0]/etimer0 ETC[0]/dspi2 SCK/fcu0 F[0]/IRQ0
VDD_HV_REG
adc1 AN[4]/D[15]
adc1 AN[6]/E[8]
adc1 AN[0]/lin1 RXD/B[13]
adc1 AN[7]/E[9]
IRQ20/adc1 AN[2]/B[15]
adc1 AN[8]/E[10]
IRQ19/adc1 AN[1]/etimer0 ETC[4]/B[14]
adc1 AN[9]/E[11]
adc1 AN[3]/C[0]
adc1 AN[10]/E[12]
adc1 AN[5]/E[0]
BCTRL
VDD_LV_REGCOR
VSS_LV_REGCOR
dspi1 CS3/fcu0 F[1]/dspi3 SIN/dspi0 CS4/D[7]
IRQ30/fcu0 F[0]/G[0]
adc0 AN[4]/E[1]
adc0 AN[6]/E[3]
adc0 AN[2]/C[1]
adc0 AN[7]/E[4]
adc0 AN[0]/lin0 RXD/B[7]
adc0 AN[8]/E[5]
adc0 AN[3]/C[2]
adc0 AN[9]/E[6]
adc0 AN[1]/etimer0 ETC[5]/B[8]
adc0 AN[10]/E[7]
adc0 AN[5]/E[2]
VDD_HV_AD0
VSS_HV_AD0
adc0-adc1 AN[11]/B[9]
adc0-adc1 AN[12]/B[10]
adc0-adc1 AN[13]/B[11]
adc0-adc1 AN[14]/B[12]
VDD_HV_AD1
VSS_HV_AD1
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
nexus0 MCKO/F[7]
nexus0 MSEO1/F[8]
VDD_HV_IO1
VSS_HV_IO1
nexus0 MSEO0/F[9]
nexus0 EVTO/F[10]
nexus0 EVTI/F[11]
flexpwm0 X[0]/lin1 TXD/D[9]
VDD_HV_OSC
VSS_HV_OSC
XTAL
EXTAL
RESET
dspi1 CS2/flexpwm0 FAULT[3]/dspi0 CS5/D[8]
dspi0 CS3/fcu0 F[0]/dspi3 SOUT/D[5]
dspi0 CS2/dspi3 SCK/flexpwm0 FAULT[1]/D[6]
VSS_LV_PLL
VDD_LV_PLL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
A[15]/safetyport0 RXD/etimer1 ETC[5]/IRQ14
A[14]/safetyport0 TXD/etimer1 ETC[4]/IRQ13
C[6]/dspi0 SOUT/flexpwm0 B[1]/sscm DEBUG[6]/IRQ24
G[1]/fcu0 F[1]/IRQ31
D[2]/flexray0 CB RX/etimer1 ETC[3]/flexpwm0 X[3]
F[3]/flexray0 DBG3/dspi3 CS0
B[6]/CLKOUT/dspi2 CS2/IRQ18
F[2]/flexray0 DBG2/dspi3 CS1
A[13]/dspi2 SIN/flexpwm0 B[2]/flexpwm0 FAULT[0]/IRQ12
F[1]/flexray0 DBG1/dspi3 CS2/IRQ29
A[9]/dspi2 CS1/flexpwm0 FAULT[0]/flexpwm0 B[3]
F[0]/flexray0 DBG0/dspi3 CS3/IRQ28
VSS_LV_COR2
VDD_LV_COR2
C[8]/dspi1 CS1/flexpwm0 FAULT[2]/dspi0 CS6
D[4]/flexray0 CB TR EN/etimer1 ETC[5]/flexpwm0 B[3]
D[3]/flexray0 CB TX/etimer1 ETC[4]/flexpwm0 A[3]
VSS_HV_IO3
VDD_HV_IO3
D[0]/flexray0 CA TX/etimer1 ETC[1]/flexpwm0 B[1]
C[15]/flexray0 CA TR EN/etimer1 ETC[0]/flexpwm0 A[1]/ctu0 EXT IN/flexpwm0 ext. sync
C[9]/dspi2 CS3/flexpwm0 FAULT[2]/flexpwm0 X[3]
A[12]/dspi2 SOUT/flexpwm0 A[2]/flexpwm0 B[2]/IRQ11
E[15]/dspi3 SIN/IRQ27
A[11]/dspi2 SCK/flexpwm0 A[0]/flexpwm0 A[2]/IRQ10
E[14]/dspi3 SOUT/IRQ26
A[10]/dspi2 CS0/flexpwm0 B[0]/flexpwm0 X[2]/IRQ9
E[13]/dspi3 SCK/IRQ25
B[3]/lin0 RXD/sscm DEBUG[3]
F[14]/lin1 TXD
B[2]/lin0 TXD/sscm DEBUG[2]/IRQ17
F[15]/lin1 RXD
F[13]/etimer1 ETC[4]
C[10]/dspi2 CS2/flexpwm0 FAULT[1]/flexpwm0 A[3]
B[1]/can0 RXD/etimer1 ETC[3]/sscm DEBUG[1]/IRQ16
B[0]/can0 TXD/etimer1 ETC[2]/sscm DEBUG[0]/IRQ15
The LQFP pinouts are shown in the following figures.
Figure 2. 144-pin LQFP pinout (top view)1
1. Availability of port pin alternate functions depends on product selection
MPC5604P Microcontroller Data Sheet, Rev. 5
6
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
A[15]/safetyport0 RXD/etimer1 ETC[5]/IRQ14
A[14]/safetyport0 TXD/etimer1 ETC[4]/IRQ13
C[6]/dspi0 SOUT/flexpwm0 B[1]/sscm DEBUG[6]/IRQ24
D[2]/flexray0 CB RX/etimer1 ETC[3]/flexpwm0 X[3]
B[6]/CLKOUT/dspi2 CS2/IRQ18
A[13]/dspi2 SIN/flexpwm0 B[2]/flexpwm0 FAULT[0]/IRQ12
A[9]/dspi2 CS1/flexpwm0 FAULT[0]/flexpwm0 B[3]
VSS_LV_COR2
VDD_LV_COR2
C[8]/dspi1 CS1/flexpwm0 FAULT[2]/dspi0 CS6
D[4]/flexray0 CB TR EN/etimer1 ETC[5]/flexpwm0 B[3]
D[3]/flexray0 CB TX/etimer1 ETC[4]/flexpwm0 A[3]
VSS_HV_IO3
VDD_HV_IO3
D[0]/flexray0 CA TX/etimer1 ETC[1]/flexpwm0 B[1]
C[15]/flexray0 CA TR EN/etimer1 ETC[0]/flexpwm0 A[1]/ctu0 EXT IN/flexpwm0 ext. sync
C[9]/dspi2 CS3/flexpwm0 FAULT[2]/flexpwm0 X[3]
A[12]/dspi2 SOUT/flexpwm0 A[2]/flexpwm0 B[2]/IRQ11
A[11]/dspi2 SCK/flexpwm0 A[0]/flexpwm0 A[2]/IRQ10
A[10]/dspi2 CS0/flexpwm0 B[0]/flexpwm0 X[2]/IRQ9
B[3]/lin0 RXD/sscm DEBUG[3]
B[2]/lin0 TXD/sscm DEBUG[2]/IRQ17
C[10]/dspi2 CS2/flexpwm0 FAULT[1]/flexpwm0 A[3]
B[1]/can0 RXD/etimer1 ETC[3]/sscm DEBUG[1]/IRQ16
B[0]/can0 TXD/etimer1 ETC[2]/sscm DEBUG[0]/IRQ15
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
100 LQFP
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A[4]/etimer1 ETC[0]/dspi2 CS1/etimer0 ETC[4]/FAB/IRQ4
VPP TEST
D[14]/flexpwm0 B[1]/dspi3 CS3/dspi3 SIN
C[14]/etimer1 ETC[2]/ctu0 EXT TGR
C[13]/etimer1 ETC[1]/ctu0 EXT IN/flexpwm0 ext. sync
D[12]/flexpwm0 X[1]/lin1 RXD
VDD_HV_FL
VSS_HV_FL
D[13]/flexpwm0 A[1]/dspi3 CS2/dspi3 SOUT
VSS_LV_COR1
VDD_LV_COR1
A[3]/etimer0 ETC[3]/dspi2 CS0/flexpwm0 B[3]/ABS[1]/IRQ3
VDD_HV_IO2
VSS_HV_IO2
jtag0 TDO
jtag0 TCK
jtag0 TMS
jtag0 TDI
A[2]/etimer0 ETC[2]/dspi2 SIN/flexpwm0 A[3]/ABS[0]/IRQ2
C[12]/etimer0 ETC[5]/dspi2 CS3/dspi3 CS1
C[11]/etimer0 ETC[4]/dspi2 CS2/dspi3 CS0
D[11]/flexpwm0 B[0]/dspi3 CS1/dspi3 SCK
D[10]/flexpwm0 A[0]/dspi3 CS0
A[1]/etimer0 ETC[1]/dspi2 SOUT/fcu0 F[1]/sscm /IRQ1
A[0]/etimer0 ETC[0]/dspi2 SCK/fcu0 F[0]/IRQ0
dspi1 CS3/fcu0 F[1]/dspi3 SIN/dspi0 CS4/D[7]
adc0 AN[4]/E[1]
adc0 AN[2]/C[1]
adc0 AN[0]/lin0 RXD/B[7]
adc0 AN[3]/C[2]
adc0 AN[1]/etimer0 ETC[5]/B[8]
adc0 AN[5]/E[2]
VDD_HV_AD0
VSS_HV_AD0
adc0-adc1 AN[11]/B[9]
adc0-adc1 AN[12]/B[10]
adc0-adc1 AN[13]/B[11]
adc0-adc1 AN[14]/B[12]
VDD_HV_AD1
VSS_HV_AD1
adc1 AN[4]/D[15]
adc1 AN[0]/lin1 RXD/B[13]
IRQ20/adc1 AN[2]/B[15]
adc1 AN[1]/etimer0 ETC[4]/B[14]
adc1 AN[3]/C[0]
adc1 AN[5]/E[0]
BCTRL
VDD_LV_REGCOR
VSS_LV_REGCOR
VDD_HV_REG
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NMI
IRQ6/dspi1 SCK/A[6]
flexray0 CA RX/etimer1 ETC[2]/ctu0 EXT TRG/D[1]
IRQ7/dspi1 SOUT/A[7]
IRQ22/sscm DEBUG[4]/dspi0 CS0/flexpwm0 X[1]/C[4]
IRQ8/dspi1 SIN/A[8]
IRQ23/sscm DEBUG[5]/dspi0 SCK/flexpwm0 FAULT[3]/C[5]
IRQ5/dspi1 CS0/etimer1 ETC[5]/dspi0 CS7/A[5]
sscm DEBUG[7]/dspi0 SIN/flexpwm0 A[1]/C[7]
IRQ21/dspi0 CS1/etimer1 ETC[4]/lin1 TXD/C[3]
VSS_LV_COR0
VDD_LV_COR0
VDD_HV_IO1
VSS_HV_IO1
flexpwm0 X[0]/lin1 TXD/D[9]
VDD_HV_OSC
VSS_HV_OSC
XTAL
EXTAL
RESET
dspi1 CS2/flexpwm0 FAULT[3]/dspi0 CS5/D[8]
dspi0 CS3/fcu0 F[0]/dspi3 SOUT/D[5]
dspi0 CS2/dspi3 SCK/flexpwm0 FAULT[1]/D[6]
VSS_LV_PLL
VDD_LV_PLL
Figure 3. 100-pin LQFP pinout (top view)1
1. Availability of port pin alternate functions depends on product selection
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
7
2.2
Pin descriptions
The following sections provide signal descriptions and related information about the functionality and configuration of the
MPC5604P devices.
2.2.1
Power supply and reference voltage pins
Table 2 lists the power supply and reference voltage for the MPC5604P devices.
Table 2. Supply pins
Supply
Symbol
Pin
Description
100-pin
144-pin
VREG control and power supply pins. Pins available on 100-pin and 144-pin package.
BCTRL
Voltage regulator external NPN Ballast base control pin
VDD_HV_REG (3.3 V Voltage regulator supply voltage
or 5.0 V)
47
69
50
72
VDD_LV_REGCOR
1.2 V decoupling1 pins for core logic supply and voltage
regulator feedback. Decoupling capacitor must be connected
between this pins and VSS_LV_REGCOR.
48
70
VSS_LV_REGCOR
1.2 V decoupling1 pins for core logic GND and voltage
regulator feedback. Decoupling capacitor must be connected
between this pins and VDD_LV_REGCOR.
49
71
ADC0/ADC1 reference and supply voltage. Pins available on 100-pin and 144-pin package.
VDD_HV_AD02
ADC0 supply and high reference voltage
33
50
VSS_HV_AD0
ADC0 ground and low reference voltage
34
51
VDD_HV_AD1
ADC1 supply and high reference voltage
39
56
VSS_HV_AD1
ADC1 ground and low reference voltage
40
57
Power supply pins (3.3 V or 5.0 V). All pins available on 144-pin package.
Five pairs (VDD; VSS) available on 100-pin package.
VDD_HV_IO03
Input/Output supply voltage
—
6
Input/Output ground
—
7
VDD_HV_IO1
Input/Output supply voltage
13
21
VSS_HV_IO1
Input/Output ground
14
22
VDD_HV_IO2
Input/Output supply voltage
63
91
VSS_HV_IO2
Input/Output ground
62
90
VDD_HV_IO3
Input/Output supply voltage
87
126
VSS_HV_IO3
Input/Output ground
88
127
VDD_HV_FL
Code and data flash supply voltage
69
97
VSS_HV_FL
Code and data flash supply ground
68
96
VDD_HV_OSC
Crystal oscillator amplifier supply voltage
16
27
VSS_HV_OSC
Crystal oscillator amplifier ground
17
28
VSS_HV_IO0
3
MPC5604P Microcontroller Data Sheet, Rev. 5
8
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Table 2. Supply pins (continued)
Supply
Symbol
Pin
Description
100-pin
144-pin
Power supply pins (1.2 V). All pins available on 100-pin and 144-pin package.
VDD_LV_COR0
1.2 V Decoupling pins for core logic supply. Decoupling
capacitor must be connected between these pins and the
nearest VSS_LV_COR0 pin.
12
18
VSS_LV_COR0
1.2 V Decoupling pins for core logic GND. Decoupling
capacitor must be connected between these pins and the
nearest VDD_LV_COR0 pin.
11
17
VDD_LV_COR1
1.2 V Decoupling pins for core logic supply. Decoupling
capacitor must be connected between these pins and the
nearest VSS_LV_COR1 pin.
65
93
VSS_LV_COR1
1.2 V Decoupling pins for core logic GND. Decoupling
capacitor must be connected between these pins and the
nearest VDD_LV_COR1 pin.
66
94
VDD_LV_COR2
1.2 V Decoupling pins for core logic supply. Decoupling
capacitor must be connected between these pins and the
nearest VSS_LV_COR2 pin.
92
131
VSS_LV_COR2
1.2 V Decoupling pins for core logic GND. Decoupling
capacitor must be connected between these pins and the
nearest VDD_LV_COR 2pin.
93
132
VDD_LV_COR3
1.2 V Decoupling pins for core logic supply. Decoupling
capacitor must be connected between these pins and the
nearest VSS_LV_COR3 pin.
25
36
VSS_LV_COR3
1.2 V Decoupling pins for core logic GND. Decoupling
capacitor must be connected between these pins and the
nearest VDD_LV_COR 3 pin.
24
35
1
See Section 3.6.1, “Voltage regulator electrical characteristics for more details
Analog supply/ground and high/low reference lines are internally physically separate, but are shorted via a
double-bonding connection on VDD_HV_ADx/VSS_HV_ADx pins.
3 Not available on 100-pin package
2
2.2.2
System Pins
Table 3 and Table 4 contain information on pin functions for the MPC5604P devices. The pins listed in Table 3 are
single-function pins. The pins shown in Table 4 are multi-function pins, programmable via their respective Pad Configuration
Register (PCR) values.
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
9
Table 3. System Pins
Pad Speed1
Symbol
Description
Pin
Direction
SRC=0
SRC=1
100-pin
144-pin
Dedicated pins. All pins available on 144-pin package. MDO 0 not available on 100-pin package.
MDO 0
Nexus Message Data Output—line 0
NMI
Non Maskable Interrupt
XTAL
Output Only
Fast
—
9
Input Only
—
—
1
1
Analog input of the oscillator amplifier circuit.
Needs to be grounded if oscillator is used in
bypass mode.
—
—
—
18
29
EXTAL
Analog output of the oscillator amplifier
circuit, when the oscillator is not in bypass
mode.
Analog input for the clock generator when
the oscillator is in bypass mode.
—
—
—
19
30
TMS2
JTAG state machine control
Input Only
—
—
59
87
TCK2
JTAG clock
Input Only
—
—
60
88
JTAG data input
Input Only
—
—
58
86
Output Only
Slow
Fast
61
89
—
20
31
—
74
107
2
TDI
2
JTAG data output
TDO
Reset pin, available on 100-pin and 144-pin package.
Bidirectional reset with Schmitt trigger
characteristics and
noise filter
RESET
Bidirectional
Medium
Test pin, available on 100-pin and 144-pin package.
VPP TEST
1
2
Pin for testing purpose only. To be tied to
ground in normal operating mode.
—
—
SRC values refer to the value assigned to the Slew Rate Control bits of the pad configuration register
In this pin there is an internal pull, refer to JTAGC chapter on MPC5604P Reference Manual for pull direction.
2.2.3
Pin Muxing
Table 4 defines the pin list and muxing for the MPC5604P devices.
Each row of Table 4 shows all the possible ways of configuring each pin, via “alternate functions”. The default function
assigned to each pin after reset is the ALT0 function.
Pins marked as external interrupt capable can also be used to resume from STOP and HALT mode.
MPC5604P devices provide four main I/O pad types depending of the associated functions:
•
•
•
•
Slow pads are the most common, providing a compromise between transition time and low electromagnetic emission.
Medium pads provide fast enough transition for serial communication channels with controlled current to reduce
electromagnetic emission.
Fast pads provide maximum speed. They are used for improved NEXUS debugging capability.
Symmetric pads are designed to meet FlexRay requirements.
Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at the cost of reducing AC performance.
MPC5604P Microcontroller Data Sheet, Rev. 5
10
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Table 4. Pin muxing
Port
pin
PCR
register
Alternate
function1,2
Functions
Peripheral3
I/O
direction4
Pad speed5
SRC = 0
SRC = 1
Pin
100-pin 144-pin
Port A (16-bit). Fully available on 100-pin and 144-pin package.
A[0]
PCR[0]
ALT0
ALT1
ALT2
ALT3
—
GPIO[0]
ETC[0]
SCK
F[0]
EIRQ[0]
SIU Lite
eTimer0
DSPI2
FCU0
SIU Lite
I/O
I/O
I/O
O
I
Slow
Medium
51
73
A[1]
PCR[1]
ALT0
ALT1
ALT2
ALT3
—
GPIO[1]
ETC[1]
SOUT
F[1]
EIRQ[1]
SIU Lite
eTimer0
DSPI2
FCU0
SIU Lite
I/O
I/O
O
O
I
Slow
Medium
52
74
A[2]6
PCR[2]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[2]
ETC[2]
—
A[3]
SIN
ABS[0]
EIRQ[2]
SIU Lite
eTimer0
—
FlexPWM0
DSPI2
mc_rgm
SIU Lite
I/O
I/O
—
O
I
I
I
Slow
Medium
57
84
A[3]6
PCR[3]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[3]
ETC[3]
CS0
B[3]
ABS[1]
EIRQ[3]
SIU Lite
eTimer0
DSPI2
FlexPWM0
mc_rgm
SIU Lite
I/O
I/O
I/O
O
I
I
Slow
Medium
64
92
A[4]6
PCR[4]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[4]
ETC[0]
CS1
ETC[4]
FAB
EIRQ[4]
SIU Lite
eTimer1
DSPI2
eTimer0
mc_rgm
SIU Lite
I/O
I/O
O
I/O
I
I
Slow
Medium
75
108
A[5]
PCR[5]
ALT0
ALT1
ALT2
ALT3
—
GPIO[5]
CS0
ETC[5]
CS7
EIRQ[5]
SIU Lite
DSPI1
eTimer1
DSPI0
SIU Lite
I/O
I/O
I/O
O
I
Slow
Medium
8
14
A[6]
PCR[6]
ALT0
ALT1
ALT2
ALT3
—
GPIO[6]
SCK
—
—
EIRQ[6]
SIU Lite
DSPI1
—
—
SIU Lite
I/O
I/O
—
—
I
Slow
Medium
2
2
A[7]
PCR[7]
ALT0
ALT1
ALT2
ALT3
—
GPIO[7]
SOUT
—
—
EIRQ[7]
SIU Lite
DSPI1
—
—
SIU Lite
I/O
O
—
—
I
Slow
Medium
4
10
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
11
Table 4. Pin muxing (continued)
Port
pin
PCR
register
Alternate
function1,2
Functions
A[8]
PCR[8]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[8]
—
—
—
SIN
EIRQ[8]
SIU Lite
—
—
—
DSPI1
SIU Lite
A[9]
PCR[9]
ALT0
ALT1
ALT2
ALT3
—
GPIO[9]
CS1
—
B[3]
FAULT[0]
A[10]
PCR[10]
ALT0
ALT1
ALT2
ALT3
—
A[11]
PCR[11]
A[12]
Peripheral
3
I/O
direction4
Pad speed5
Pin
SRC = 0
SRC = 1
100-pin 144-pin
I/O
—
—
—
I
I
Slow
Medium
6
12
SIU Lite
DSPI2
—
FlexPWM0
FlexPWM0
I/O
O
—
O
I
Slow
Medium
94
134
GPIO[10]
CS0
B[0]
X[2]
EIRQ[9]
SIU Lite
DSPI2
FlexPWM0
FlexPWM0
SIU Lite
I/O
I/O
O
I/O
I
Slow
Medium
81
118
ALT0
ALT1
ALT2
ALT3
—
GPIO[11]
SCK
A[0]
A[2]
EIRQ[10]
SIU Lite
DSPI2
FlexPWM0
FlexPWM0
SIU Lite
I/O
I/O
O
O
I
Slow
Medium
82
120
PCR[12]
ALT0
ALT1
ALT2
ALT3
—
GPIO[12]
SOUT
A[2]
B[2]
EIRQ[11]
SIU Lite
DSPI2
FlexPWM0
FlexPWM0
SIU Lite
I/O
O
O
O
I
Slow
Medium
83
122
A[13]
PCR[13]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[13]
—
B[2]
—
SIN
FAULT[0]
EIRQ[12]
SIU Lite
—
FlexPWM0
—
DSPI2
FlexPWM0
SIU Lite
I/O
—
O
—
I
I
I
Slow
Medium
95
136
A[14]
PCR[14]
ALT0
ALT1
ALT2
ALT3
—
GPIO[14]
TXD
ETC[4]
—
EIRQ[13]
SIU Lite
Safety Port0
eTimer1
—
SIU Lite
I/O
O
I/O
—
I
Slow
Medium
99
143
A[15]
PCR[15]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[15]
—
ETC[5]
—
RXD
EIRQ[14]
SIU Lite
—
eTimer1
—
Safety Port0
SIU Lite
I/O
—
I/O
—
I
I
Slow
Medium
100
144
MPC5604P Microcontroller Data Sheet, Rev. 5
12
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Table 4. Pin muxing (continued)
Port
pin
PCR
register
Alternate
function1,2
Functions
Peripheral
3
I/O
direction4
Pad speed5
SRC = 0
SRC = 1
Pin
100-pin 144-pin
Port B (16-bit). Fully available on 100-pin and 144-pin package.
B[0]
PCR[16]
ALT0
ALT1
ALT2
ALT3
—
GPIO[16]
TXD
ETC[2]
DEBUG[0]
EIRQ[15]
SIU Lite
CAN0
eTimer1
SSCM
SIU Lite
I/O
O
I/O
—
I
Slow
Medium
76
109
B[1]
PCR[17]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[17]
—
ETC[3]
DEBUG[1]
RXD
EIRQ[16]
SIU Lite
—
eTimer1
SSCM
CAN0
SIU Lite
I/O
—
I/O
—
I
I
Slow
Medium
77
110
B[2]
PCR[18]
ALT0
ALT1
ALT2
ALT3
—
GPIO[18]
TXD
—
DEBUG[2]
EIRQ[17]
SIU Lite
LIN0
—
SSCM
SIU Lite
I/O
O
—
—
I
Slow
Medium
79
114
B[3]
PCR[19]
ALT0
ALT1
ALT2
ALT3
—
GPIO[19]
—
—
DEBUG[3]
RXD
SIU Lite
—
—
SSCM
LIN0
I/O
—
—
—
I
Slow
Medium
80
116
B[6]
PCR[22]
ALT0
ALT1
ALT2
ALT3
—
GPIO[22]
CLKOUT
CS2
—
EIRQ[18]
SIU Lite
Control
DSPI2
—
SIU Lite
I/O
O
O
—
I
Slow
Medium
96
138
B[7]
PCR[23]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[23]
—
—
—
AN[0]
RXD
SIU Lite
—
—
—
ADC0
LIN0
Input Only
—
—
29
43
B[8]
PCR[24]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[24]
—
—
—
AN[1]
ETC[5]
SIU Lite
—
—
—
ADC0
eTimer0
Input Only
—
—
31
47
B[9]
PCR[25]
ALT0
ALT1
ALT2
ALT3
—
GPIO[25]
—
—
—
AN[11]
SIU Lite
Input Only
—
—
—
ADC0 – ADC1
—
—
35
52
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
13
Table 4. Pin muxing (continued)
Port
pin
PCR
register
Alternate
function1,2
Functions
B[10]
PCR[26]
ALT0
ALT1
ALT2
ALT3
—
GPIO[26]
—
—
—
AN[12]
B[11]
PCR[27]
ALT0
ALT1
ALT2
ALT3
—
B[12]
PCR[28]
B[13]
Peripheral
3
I/O
direction4
Pad speed5
Pin
SRC = 0
SRC = 1
100-pin 144-pin
SIU Lite
Input Only
—
—
—
ADC0 – ADC1
—
—
36
53
GPIO[27]
—
—
—
AN[13]
SIU Lite
Input Only
—
—
—
ADC0 – ADC1
—
—
37
54
ALT0
ALT1
ALT2
ALT3
—
GPIO[28]
—
—
—
AN[14]
SIU Lite
Input Only
—
—
—
ADC0 – ADC1
—
—
38
55
PCR[29]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[29]
—
—
—
AN[0]
RXD
SIU Lite
—
—
—
ADC1
LIN1
Input Only
—
—
42
60
B[14]
PCR[30]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[30]
—
—
—
AN[1]
ETC[4]
EIRQ[19]
SIU Lite
—
—
—
ADC1
eTimer0
SIU Lite
Input Only
—
—
44
64
B[15]
PCR[31]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[31]
—
—
—
AN[2]
EIRQ[20]
SIU Lite
—
—
—
ADC1
SIU Lite
Input Only
—
—
43
62
Port C (16-bit). Fully available on 100-pin and 144-pin package.
C[0]
PCR[32]
ALT0
ALT1
ALT2
ALT3
—
GPIO[32]
—
—
—
AN[3]
SIU Lite
—
—
—
ADC1
Input Only
—
—
45
66
C[1]
PCR[33]
ALT0
ALT1
ALT2
ALT3
—
GPIO[33]
—
—
—
AN[2]
SIU Lite
—
—
—
ADC0
Input Only
—
—
28
41
MPC5604P Microcontroller Data Sheet, Rev. 5
14
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Table 4. Pin muxing (continued)
Port
pin
PCR
register
Alternate
function1,2
Functions
C[2]
PCR[34]
ALT0
ALT1
ALT2
ALT3
—
GPIO[34]
—
—
—
AN[3]
SIU Lite
—
—
—
ADC0
C[3]
PCR[35]
ALT0
ALT1
ALT2
ALT3
—
GPIO[35]
CS1
ETC[4]
TXD
EIRQ[21]
C[4]
PCR[36]
ALT0
ALT1
ALT2
ALT3
—
C[5]
PCR[37]
C[6]
Peripheral
3
I/O
direction4
Pad speed5
Pin
SRC = 0
SRC = 1
100-pin 144-pin
Input Only
—
—
30
45
SIU Lite
DSPI0
eTimer1
LIN1
SIU Lite
I/O
O
I/O
O
I
Slow
Medium
10
16
GPIO[36]
CS0
X[1]
DEBUG[4]
EIRQ[22]
SIU Lite
DSPI0
FlexPWM0
SSCM
SIU Lite
I/O
I/O
I/O
—
I
Slow
Medium
5
11
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[37]
SCK
—
DEBUG[5]
FAULT[3]
EIRQ[23]
SIU Lite
DSPI0
—
SSCM
FlexPWM0
SIU Lite
I/O
I/O
—
—
I
I
Slow
Medium
7
13
PCR[38]
ALT0
ALT1
ALT2
ALT3
—
GPIO[38]
SOUT
B[1]
DEBUG[6]
EIRQ[24]
SIU Lite
DSPI0
FlexPWM0
SSCM
SIU Lite
I/O
O
O
—
I
Slow
Medium
98
142
C[7]
PCR[39]
ALT0
ALT1
ALT2
ALT3
—
GPIO[39]
—
A[1]
DEBUG[7]
SIN
SIU Lite
—
FlexPWM0
SSCM
DSPI0
I/O
—
O
—
I
Slow
Medium
9
15
C[8]
PCR[40]
ALT0
ALT1
ALT2
ALT3
—
GPIO[40]
CS1
—
CS6
FAULT[2]
SIU Lite
DSPI1
—
DSPI0
FlexPWM0
I/O
O
—
O
I
Slow
Medium
91
130
C[9]
PCR[41]
ALT0
ALT1
ALT2
ALT3
—
GPIO[41]
CS3
—
X[3]
FAULT[2]
SIU Lite
DSPI2
—
FlexPWM0
FlexPWM0
I/O
O
—
I/O
I
Slow
Medium
84
123
C[10] PCR[42]
ALT0
ALT1
ALT2
ALT3
—
GPIO[42]
CS2
—
A[3]
FAULT[1]
SIU Lite
DSPI2
—
FlexPWM0
FlexPWM0
I/O
O
—
O
I
Slow
Medium
78
111
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
15
Table 4. Pin muxing (continued)
Port
pin
PCR
register
Alternate
function1,2
Functions
C[11] PCR[43]
ALT0
ALT1
ALT2
ALT3
GPIO[43]
ETC[4]
CS2
CS0
SIU Lite
eTimer0
DSPI2
DSPI3
C[12] PCR[44]
ALT0
ALT1
ALT2
ALT3
GPIO[44]
ETC[5]
CS3
CS1
C[13] PCR[45]
ALT0
ALT1
ALT2
ALT3
—
—
C[14] PCR[46]
C[15] PCR[47]
Peripheral
3
I/O
direction4
Pad speed5
Pin
SRC = 0
SRC = 1
100-pin 144-pin
I/O
I/O
O
I/O
Slow
Medium
55
80
SIU Lite
eTimer0
DSPI2
DSPI3
I/O
I/O
O
O
Slow
Medium
56
82
GPIO[45]
ETC[1]
—
—
EXT IN
EXT. SYNC
SIU Lite
eTimer1
—
—
ctu0
FlexPWM0
I/O
I/O
—
—
I
I
Slow
Medium
71
101
ALT0
ALT1
ALT2
ALT3
GPIO[46]
ETC[2]
EXT TGR
—
SIU Lite
eTimer1
ctu0
—
I/O
I/O
O
—
Slow
Medium
72
103
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[47]
CA TR EN
ETC[0]
A[1]
EXT IN
EXT. SYNC
SIU Lite
FlexRay0
eTimer1
FlexPWM0
ctu0
FlexPWM0
I/O
O
I/O
O
I
I
Slow
Symmetric
85
124
Port D (16-bit). Fully available on 100-pin and 144-pin package.
D[0]
PCR[48]
ALT0
ALT1
ALT2
ALT3
GPIO[48]
CA TX
ETC[1]
B[1]
SIU Lite
FlexRay0
eTimer1
FlexPWM0
I/O
O
I/O
O
Slow
Symmetric
86
125
D[1]
PCR[49]
ALT0
ALT1
ALT2
ALT3
—
GPIO[49]
—
ETC[2]
EXT TRG
CA RX
SIU Lite
—
eTimer1
ctu0
FlexRay0
I/O
—
I/O
O
I
Slow
Medium
3
3
D[2]
PCR[50]
ALT0
ALT1
ALT2
ALT3
—
GPIO[50]
—
ETC[3]
X[3]
CB RX
SIU Lite
—
eTimer1
FlexPWM0
FlexRay0
I/O
—
I/O
I/O
I
Slow
Medium
97
140
D[3]
PCR[51]
ALT0
ALT1
ALT2
ALT3
GPIO[51]
CB TX
ETC[4]
A[3]
SIU Lite
FlexRay0
eTimer1
FlexPWM0
I/O
O
I/O
I/O
Slow
Symmetric
89
128
D[4]
PCR[52]
ALT0
ALT1
ALT2
ALT3
GPIO[52]
CB TR EN
ETC[5]
B[3]
SIU Lite
FlexRay0
eTimer1
FlexPWM0
I/O
O
I/O
O
Slow
Symmetric
90
129
MPC5604P Microcontroller Data Sheet, Rev. 5
16
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Table 4. Pin muxing (continued)
Port
pin
PCR
register
Alternate
function1,2
Functions
D[5]
PCR[53]
ALT0
ALT1
ALT2
ALT3
GPIO[53]
CS3
F[0]
SOUT
SIU Lite
DSPI0
FCU0
DSPI3
D[6]
PCR[54]
ALT0
ALT1
ALT2
ALT3
—
GPIO[54]
CS2
SCK
—
FAULT[1]
D[7]
PCR[55]
ALT0
ALT1
ALT2
ALT3
—
D[8]
PCR[56]
D[9]
Peripheral
3
I/O
direction4
Pad speed5
Pin
SRC = 0
SRC = 1
100-pin 144-pin
I/O
O
O
O
Slow
Medium
22
33
SIU Lite
DSPI0
DSPI3
—
FlexPWM0
I/O
O
I/O
—
I
Slow
Medium
23
34
GPIO[55]
CS3
F[1]
CS4
SIN
SIU Lite
DSPI1
FCU0
DSPI0
DSPI3
I/O
O
O
O
I
Slow
Medium
26
37
ALT0
ALT1
ALT2
ALT3
—
GPIO[56]
CS2
—
CS5
FAULT[3]
SIU Lite
DSPI1
—
DSPI0
FlexPWM0
I/O
O
—
O
I
Slow
Medium
21
32
PCR[57]
ALT0
ALT1
ALT2
ALT3
GPIO[57]
X[0]
TXD
—
SIU Lite
FlexPWM0
LIN1
—
I/O
I/O
O
—
Slow
Medium
15
26
D[10] PCR[58]
ALT0
ALT1
ALT2
ALT3
GPIO[58]
A[0]
CS0
—
SIU Lite
FlexPWM0
DSPI3
—
I/O
O
I/O
—
Slow
Medium
53
76
D[11] PCR[59]
ALT0
ALT1
ALT2
ALT3
GPIO[59]
B[0]
CS1
SCK
SIU Lite
FlexPWM0
DSPI3
DSPI3
I/O
O
O
I/O
Slow
Medium
54
78
D[12] PCR[60]
ALT0
ALT1
ALT2
ALT3
—
GPIO[60]
X[1]
—
—
RXD
SIU Lite
FlexPWM0
—
—
LIN1
I/O
I/O
—
—
I
Slow
Medium
70
99
D[13] PCR[61]
ALT0
ALT1
ALT2
ALT3
GPIO[61]
A[1]
CS2
SOUT
SIU Lite
FlexPWM0
DSPI3
DSPI3
I/O
O
O
O
Slow
Medium
67
95
D[14] PCR[62]
ALT0
ALT1
ALT2
ALT3
—
GPIO[62]
B[1]
CS3
—
SIN
SIU Lite
FlexPWM0
DSPI3
—
DSPI3
I/O
O
O
—
I
Slow
Medium
73
105
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
17
Table 4. Pin muxing (continued)
Port
pin
PCR
register
D[15] PCR[63]
Alternate
function1,2
Functions
ALT0
ALT1
ALT2
ALT3
—
GPIO[63]
—
—
—
AN[4]
Peripheral
SIU Lite
—
—
—
ADC1
3
I/O
direction4
Input Only
Pad speed5
SRC = 0
SRC = 1
—
—
Pin
100-pin 144-pin
41
58
Port E(16-bit). Fully available on 144-pin package. E[0], E[1] and E[2] available on 100-pin package.
E[0]
PCR[64]
ALT0
ALT1
ALT2
ALT3
—
GPIO[64]
—
—
—
AN[5]
SIU Lite
—
—
—
ADC1
Input Only
—
—
46
68
E[1]
PCR[65]
ALT0
ALT1
ALT2
ALT3
—
GPIO[65]
—
—
—
AN[4]
SIU Lite
—
—
—
ADC0
Input Only
—
—
27
39
E[2]
PCR[66]
ALT0
ALT1
ALT2
ALT3
—
GPIO[66]
—
—
—
AN[5]
SIU Lite
—
—
—
ADC0
Input Only
—
—
32
49
E[3]
PCR[67]
ALT0
ALT1
ALT2
ALT3
—
GPIO[67]
—
—
—
AN[6]
SIU Lite
—
—
—
ADC0
Input Only
—
—
—
40
E[4]
PCR[68]
ALT0
ALT1
ALT2
ALT3
—
GPIO[68]
—
—
—
AN[7]
SIU Lite
—
—
—
ADC0
Input Only
—
—
—
42
E[5]
PCR[69]
ALT0
ALT1
ALT2
ALT3
—
GPIO[69]
—
—
—
AN[8]
SIU Lite
—
—
—
ADC0
Input Only
—
—
—
44
E[6]
PCR[70]
ALT0
ALT1
ALT2
ALT3
—
GPIO[70]
—
—
—
AN[9]
SIU Lite
—
—
—
ADC0
Input Only
—
—
—
46
E[7]
PCR[71]
ALT0
ALT1
ALT2
ALT3
—
GPIO[71]
—
—
—
AN[10]
SIU Lite
—
—
—
ADC0
Input Only
—
—
—
48
MPC5604P Microcontroller Data Sheet, Rev. 5
18
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Table 4. Pin muxing (continued)
Port
pin
PCR
register
Alternate
function1,2
Functions
E[8]
PCR[72]
ALT0
ALT1
ALT2
ALT3
—
GPIO[72]
—
—
—
AN[6]
SIU Lite
—
—
—
ADC1
E[9]
PCR[73]
ALT0
ALT1
ALT2
ALT3
—
GPIO[73]
—
—
—
AN[7]
E[10]
PCR[74]
ALT0
ALT1
ALT2
ALT3
—
E[11]
PCR[75]
E[12]
Peripheral
3
I/O
direction4
Pad speed5
Pin
SRC = 0
SRC = 1
100-pin 144-pin
Input Only
—
—
—
59
SIU Lite
—
—
—
ADC1
Input Only
—
—
—
61
GPIO[74]
—
—
—
AN[8]
SIU Lite
—
—
—
ADC1
Input Only
—
—
—
63
ALT0
ALT1
ALT2
ALT3
—
GPIO[75]
—
—
—
AN[9]
SIU Lite
—
—
—
ADC1
Input Only
—
—
—
65
PCR[76]
ALT0
ALT1
ALT2
ALT3
—
GPIO[76]
—
—
—
AN[10]
SIU Lite
—
—
—
ADC1
Input Only
—
—
—
67
E[13]
PCR[77]
ALT0
ALT1
ALT2
ALT3
—
GPIO[77]
SCK
—
—
EIRQ[25]
SIU Lite
DSPI3
—
—
SIU Lite
I/O
I/O
—
—
I
Slow
Medium
—
117
E[14]
PCR[78]
ALT0
ALT1
ALT2
ALT3
—
GPIO[78]
SOUT
—
—
EIRQ[26]
SIU Lite
DSPI3
—
—
SIU Lite
I/O
O
—
—
I
Slow
Medium
—
119
E[15]
PCR[79]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[79]
—
—
—
SIN
EIRQ[27]
SIU Lite
—
—
—
DSPI3
SIU Lite
I/O
—
—
—
I
I
Slow
Medium
—
121
Medium
—
133
Port F (16-bit). Fully available on 144-pin package
F[0]
PCR[80]
ALT0
ALT1
ALT2
ALT3
—
GPIO[80]
DBG0
CS3
—
EIRQ[28]
SIU Lite
FlexRay0
DSPI3
—
SIU Lite
I/O
O
O
—
I
Slow
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
19
Table 4. Pin muxing (continued)
Port
pin
PCR
register
Alternate
function1,2
Functions
F[1]
PCR[81]
ALT0
ALT1
ALT2
ALT3
—
GPIO[81]
DBG1
CS2
—
EIRQ[29]
SIU Lite
FlexRay0
DSPI3
—
SIU Lite
F[2]
PCR[82]
ALT0
ALT1
ALT2
ALT3
GPIO[82]
DBG2
CS1
—
F[3]
PCR[83]
ALT0
ALT1
ALT2
ALT3
F[4]
PCR[84]
F[5]
Peripheral
3
I/O
direction4
Pad speed5
Pin
SRC = 0
SRC = 1
100-pin 144-pin
I/O
O
O
—
I
Slow
Medium
—
135
SIU Lite
FlexRay0
DSPI3
—
I/O
O
O
—
Slow
Medium
—
137
GPIO[83]
DBG3
CS0
—
SIU Lite
FlexRay0
DSPI3
—
I/O
O
I/O
—
Slow
Medium
—
139
ALT0
ALT1
ALT2
ALT3
GPIO[84]
MDO[3]
—
—
SIU Lite
nexus0
—
—
I/O
O
—
—
Slow
Fast
—
4
PCR[85]
ALT0
ALT1
ALT2
ALT3
GPIO[85]
MDO[2]
—
—
SIU Lite
nexus0
—
—
I/O
O
—
—
Slow
Fast
—
5
F[6]
PCR[86]
ALT0
ALT1
ALT2
ALT3
GPIO[86]
MDO[1]
—
—
SIU Lite
nexus0
—
—
I/O
O
—
—
Slow
Fast
—
8
F[7]
PCR[87]
ALT0
ALT1
ALT2
ALT3
GPIO[87]
MCKO
—
—
SIU Lite
nexus0
—
—
I/O
O
—
—
Slow
Fast
—
19
F[8]
PCR[88]
ALT0
ALT1
ALT2
ALT3
GPIO[88]
MSEO1
—
—
SIU Lite
nexus0
—
—
I/O
O
—
—
Slow
Fast
—
20
F[9]
PCR[89]
ALT0
ALT1
ALT2
ALT3
GPIO[89]
MSEO0
—
—
SIU Lite
nexus0
—
—
I/O
O
—
—
Slow
Fast
—
23
F[10]
PCR[90]
ALT0
ALT1
ALT2
ALT3
GPIO[90]
EVTO
—
—
SIU Lite
nexus0
—
—
I/O
O
—
—
Slow
Fast
—
24
F[11]
PCR[91]
ALT0
ALT1
ALT2
ALT3
—
GPIO[91]
—
—
—
EVTI
SIU Lite
—
—
—
nexus0
I/O
—
—
—
I
Slow
Medium
—
25
MPC5604P Microcontroller Data Sheet, Rev. 5
20
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Table 4. Pin muxing (continued)
Port
pin
PCR
register
Alternate
function1,2
Functions
F[12]
PCR[92]
ALT0
ALT1
ALT2
ALT3
GPIO[92]
ETC[3]
—
—
SIU Lite
eTimer1
—
—
F[13]
PCR[93]
ALT0
ALT1
ALT2
ALT3
—
GPIO[93]
—
—
—
ETC[4]
F[14]
PCR[94]
ALT0
ALT1
ALT2
ALT3
F[15]
PCR[95]
ALT0
ALT1
ALT2
ALT3
—
Peripheral
3
I/O
direction4
Pad speed5
Pin
SRC = 0
SRC = 1
100-pin 144-pin
I/O
I/O
—
—
Slow
Medium
—
106
SIU Lite
—
—
—
eTimer1
I/O
—
—
—
I
Slow
Medium
—
112
GPIO[94]
TXD
—
—
SIU Lite
LIN1
—
—
I/O
O
—
—
Slow
Medium
—
115
GPIO[95]
—
—
—
RXD
SIU Lite
—
—
—
LIN1
I/O
—
—
—
I
Slow
Medium
—
113
Port G (12-bit). Fully available on 144-pin package.
G[0]
PCR[96]
ALT0
ALT1
ALT2
ALT3
—
GPIO[96]
F[0]
—
—
EIRQ[30]
SIU Lite
FCU0
—
—
SIU Lite
I/O
O
—
—
I
Slow
Medium
—
38
G[1]
PCR[97]
ALT0
ALT1
ALT2
ALT3
—
GPIO[97]
F[1]
—
—
EIRQ[31]
SIU Lite
FCU0
—
—
SIU Lite
I/O
O
—
—
I
Slow
Medium
—
141
G[2]
PCR[98]
ALT0
ALT1
ALT2
ALT3
GPIO[98]
X[2]
—
—
SIU Lite
FlexPWM0
—
—
I/O
I/O
—
—
Slow
Medium
—
102
G[3]
PCR[99]
ALT0
ALT1
ALT2
ALT3
GPIO[99]
A[2]
—
—
SIU Lite
FlexPWM0
—
—
I/O
O
—
—
Slow
Medium
—
104
G[4] PCR[100]
ALT0
ALT1
ALT2
ALT3
GPIO[100]
B[2]
—
—
SIU Lite
FlexPWM0
—
—
I/O
O
—
—
Slow
Medium
—
100
G[5] PCR[101]
ALT0
ALT1
ALT2
ALT3
GPIO[101]
X[3]
—
—
SIU Lite
FlexPWM0
—
—
I/O
I/O
—
—
Slow
Medium
—
85
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
21
Table 4. Pin muxing (continued)
Port
pin
PCR
register
Alternate
function1,2
Functions
G[6] PCR[102]
ALT0
ALT1
ALT2
ALT3
GPIO[102]
A[3]
—
—
SIU Lite
FlexPWM0
—
—
G[7] PCR[103]
ALT0
ALT1
ALT2
ALT3
GPIO[103]
B[3]
—
—
G[8] PCR[104]
ALT0
ALT1
ALT2
ALT3
—
G[9] PCR[105]
Peripheral
3
I/O
direction4
Pad speed5
Pin
SRC = 0
SRC = 1
I/O
O
—
—
Slow
Medium
—
98
SIU Lite
FlexPWM0
—
—
I/O
O
—
—
Slow
Medium
—
83
GPIO[104]
—
—
—
FAULT[0]
SIU Lite
—
—
—
FlexPWM0
I/O
—
—
—
I
Slow
Medium
—
81
ALT0
ALT1
ALT2
ALT3
—
GPIO[105]
—
—
—
FAULT[1]
SIU Lite
—
—
—
FlexPWM0
I/O
—
—
—
I
Slow
Medium
—
79
G[10] PCR[106]
ALT0
ALT1
ALT2
ALT3
—
GPIO[106]
—
—
—
FAULT[2]
SIU Lite
—
—
—
FlexPWM0
I/O
—
—
—
I
Slow
Medium
—
77
G[11] PCR[107]
ALT0
ALT1
ALT2
ALT3
—
GPIO[107]
—
—
—
FAULT[3]
SIU Lite
—
—
—
FlexPWM0
I/O
—
—
—
I
Slow
Medium
—
75
1
2
3
4
5
6
100-pin 144-pin
ALT0 is the primary (default) function for each port after reset.
Alternate functions are chosen by setting the values of the PCR[PA] bitfields inside the SIU module.
PCR[PA] = 00 → ALT0; PCR[PA] = 01 → ALT1; PCR[PA] = 10 → ALT2; PCR[PA] = 11 → ALT3. This is intended to
select the output functions; to use one of the input-only functions, the PCR[IBE] bit must be written to ‘1’, regardless
of the values selected in the PCR[PA] bitfields. For this reason, the value corresponding to an input only function is
reported as “—”.
Module included on the MCU.
Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by
setting the values of the PSMI[PADSELx] bitfields inside the SIUL module.
Programmable via the SRC (Slew Rate Control) bits in the respective Pad Configuration Register.
Weak pull down during reset.
MPC5604P Microcontroller Data Sheet, Rev. 5
22
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
3
Electrical characteristics
This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing
specifications for the MPC5604P MCU.
The “Symbol” column of the electrical parameter and timings tables contains an additional column containing “SR”, “P”, “C”,
“T” or “D”.
•
•
“SR” identifies system requirements—conditions that must be provided to ensure normal device operation. An
example is the input voltage of a voltage regulator.
“P”, “C”, “T” or “D” apply only to controller characteristics—specifications that define normal device operation. They
specify how each characteristic is guaranteed.
— P: parameter is guaranteed by production testing of each individual device.
— C: parameter is guaranteed by design characterization. Measurements are taken from a statistically relevant
sample size across process variations.
— T: parameter is guaranteed by design characterization on a small sample size from typical devices under typical
conditions unless otherwise noted. All values are shown in the typical (“typ”) column are within this category.
— D: parameters are derived mainly from simulations.
NOTE
All values are preliminary and subject to change during characterization.
3.1
Absolute maximum ratings
Table 5. Absolute maximum ratings1
Conditions
Min
Max2
Unit
SR Digital ground
—
0
0
V
VDD_HV_IOx3
SR 3.3 V / 5.0 V input/output supply
voltage with respect to ground
(VSS_HV)
—
–0.3
6.0
V
VSS_HV_IOx
SR Input/output ground voltage with
respect to ground (VSS_HV)
—
–0.1
0.1
V
VDD_HV_FL
—
SR 3.3 V / 5.0 V code and data flash
supply voltage with respect to ground
Relative to
(VSS_HV)
VDD_HV_IOx
–0.3
6.0
V
–0.3
VDD_HV_IOx + 0.3
–0.1
0.1
V
–0.3
6.0
V
–0.3
VDD_HV_IOx + 0.3
–0.1
0.1
V
– 0.3
6.0
V
– 0.3
VDD_HV_IOx + 0.3
Symbol
VSS_HV
VSS_HV_FL
VDD_HV_OSC
Parameter
SR Code and data flash ground with
respect to ground (VSS_HV)
—
—
SR 3.3 V / 5.0 V crystal oscillator amplifier
supply voltage with respect to ground
Relative to
(VSS_HV)
VDD_HV_IOx
VSS_HV_OSC
SR 3.3 V / 5.0 V crystal oscillator amplifier
reference voltage with respect to
ground (VSS_HV)
—
VDD_HV_REG
—
SR 3.3 V / 5.0 V voltage regulator supply
voltage with respect to ground
Relative to
(VSS_HV)
VDD_HV_IOx
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
23
Table 5. Absolute maximum ratings1 (continued)
Symbol
VDD_HV_AD04
5
VDD_HV_REG <
2.7 V
– 0.3
VDD_HV_REG + 0.3
V
VDD_HV_REG >
2.7 V
– 0.3
6.0
—
–0.1
0.1
V
VDD_HV_REG <
2.7 V
– 0.3
VDD_HV_REG + 0.3
V
VDD_HV_REG >
2.7 V
– 0.3
6.0
SR ADC1 ground and low reference
voltage with respect to ground
(VSS_HV)
—
–0.1
0.1
V
SR Slope characteristics on all VDD during
power up5 with respect to ground
(VSS_HV)
—
0.5 V/µs
3 V/S
—
SR Voltage on any pin with respect to
ground (VSS_HV_IOx) with respect to
ground (VSS_HV)
—
–0.3
6.0
V
–0.3
VDD_HV_IOx + 0.3
SR 3.3 V / 5.0 V ADC0 supply and high
reference voltage with respect to
ground (VSS_HV)
SR 3.3 V / 5.0 V ADC0 supply and high
reference voltage with respect to
ground (VSS_HV)
Relative to
VDD_HV_IOx
IINJPAD
SR Injected input current on any pin
during overload condition
—
–10
10
mA
IINJSUM
SR Absolute sum of all injected input
currents during overload condition
—
–50
50
mA
IVDD_LV
SR Low voltage static current sink through
VDD_LV
—
—
155
mA
SR Storage temperature
—
–55
150
°C
TSTG
4
Unit
VDD_HV_AD14
VIN
3
Max2
SR ADC0 ground and low reference
voltage with respect to ground
(VSS_HV)
TVDD
2
Min
VSS_HV_AD0
VSS_HV_AD1
1
Conditions
Parameter
Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress
ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect
device reliability or cause permanent damage to the device.
Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device
stress have not yet been determined.
The difference between each couple of voltage supplies must be less that 300 mV, |VDD_HV_IOy – VDD_HV_IOx | <
300 mV.
The difference between ADC voltage supplies must be less that 300 mV, |VDD_HV_ADC1 - VDD_HV_ADC0| < 300 mV.
Guaranteed by device validation
MPC5604P Microcontroller Data Sheet, Rev. 5
24
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Figure 4 shows the constraints of the different power supplies.
VDD_HV_xxx
6.0V
-0.3V
VDD_HV_IOx
-0.3V
6.0V
Figure 4. Power supplies constraints
The MPC5604P supply architecture allows of having ADC supply managed independently from standard VDD_HV supply.
Figure 5 shows the constraints of the ADC power supply.
VDD_HV_ADCx
6.0V
-0.3V
VDD_HV_REG
-0.3V
2.7V
6.0V
Figure 5. Independent ADC supply
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
25
3.2
Recommended operating conditions
Table 6. Recommended operating conditions (5.0 V)
Symbol
Parameter
VSS_HV
Conditions
Min
Max1
Unit
SR Digital ground
—
0
0
V
VDD_HV_IOx2
SR 5.0 V input/output supply voltage
—
4.5
5.5
V
VSS_HV_IOx
SR Input/output ground voltage
—
0
0
V
VDD_HV_FL
SR 5.0 V code and data flash supply voltage
—
4.5
5.5
V
Relative to
VDD_HV_IOx
VSS_HV_FL
VDD_HV_OSC
VDD_HV_IO VDD_HV_IO
x – 0.1
x + 0.1
SR Code and data flash ground
—
0
0
V
SR 5.0 V crystal oscillator amplifier supply
voltage
—
4.5
5.5
V
Relative to
VDD_HV_IOx
VDD_HV_IO VDD_HV_IO
x – 0.1
x + 0.1
VSS_HV_OSC
SR 5.0 V crystal oscillator amplifier reference
voltage
—
0
0
V
VDD_HV_REG
SR 5.0 V voltage regulator supply voltage
—
4.5
5.5
V
Relative to
VDD_HV_IOx
VDD_HV_AD03
SR 5.0 V ADC0 supply and high reference
voltage
—
Relative to
VDD_HV_REG
VDD_HV_IO VDD_HV_IO
x – 0.1
x + 0.1
4.5
5.5
VDD_HV_R
EG – 0.1
—
V
VSS_HV_AD0
SR ADC0 ground and low reference voltage
—
0
0
V
VDD_HV_AD13
SR 5.0 V ADC1 supply and high reference
voltage
—
4.5
5.5
V
VDD_HV_R
EG – 0.1
—
VSS_HV_AD1
VDD_LV_REGCOR4,5
VSS_LV_REGCOR
4
VDD_LV_CORx4,5
VSS_LV_CORx4
TA
TJ
Relative to
VDD_HV_REG
SR ADC1 ground and low reference voltage
—
0
0
V
SR Internal supply voltage
—
—
—
V
SR Internal reference voltage
—
0
0
V
SR Internal supply voltage
—
—
—
V
SR Internal reference voltage
—
0
0
V
fCPU = 64 MHz
–40
105
°C
fCPU = 60 MHz
–40
125
–40
150
SR Ambient temperature under bias
SR Junction temperature under bias
—
°C
1
Full functionality cannot be guaranteed when voltage drops below 4.5 V. In particular, ADC electrical characteristics
and I/Os DC electrical specification may not be guaranteed.
2
The difference between each couple of voltage supplies must be less that 300 mV, |VDD_HV_IOy – VDD_HV_IOx | <
100 mV.
3 The power supply voltage must be identical for ADC0 and ADC1
MPC5604P Microcontroller Data Sheet, Rev. 5
26
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
4
To be connected to emitter of external NPN. Low voltage supplies are not under user control—they are produced
by an on-chip voltage regulator—but for the device to function properly the low voltage grounds (VSS_LV_xxx) must
be shorted to high voltage grounds (VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected
to the external ballast emitter.
5
The low voltage supplies (VDD_LV_xxx) are not all independent.
VDD_LV_COR1 and VDD_LV_COR2 are shorted internally via double bonding connections with lines that provide
the low voltage supply to the data flash module. Similarly, VSS_LV_COR1 and VSS_LV_COR2 are internally
shorted.
VDD_LV_REGCOR and VDD_LV_RECORx are physically shorted internally, as are VSS_LV_REGCOR and
VSS_LV_CORx.
Table 7. Recommended operating conditions (3.3 V)
Conditions
Min
Max1
Unit
SR Digital ground
—
0
0
V
VDD_HV_IOx2
SR 3.3 V input/output supply voltage
—
3.0
3.6
V
VSS_HV_IOx
SR Input/output ground voltage
—
0
0
V
VDD_HV_FL
SR 3.3 V code and data flash supply voltage
—
3.0
3.6
V
Symbol
Parameter
VSS_HV
Relative to
VDD_HV_IOx
VSS_HV_FL
VDD_HV_OSC
VDD_HV_IO VDD_HV_IO
x – 0.1
x + 0.1
SR Code and data flash ground
—
0
0
V
SR 3.3 V crystal oscillator amplifier supply
voltage
—
3.0
3.6
V
Relative to
VDD_HV_IOx
VDD_HV_IO VDD_HV_IO
x – 0.1
x + 0.1
VSS_HV_OSC
SR 3.3 V crystal oscillator amplifier reference
voltage
—
0
0
V
VDD_HV_REG
SR 3.3 V voltage regulator supply voltage
—
3.0
3.6
V
Relative to
VDD_HV_IOx
VDD_HV_AD03
SR 3.3 V ADC0 supply and high reference
voltage
VSS_HV_AD0
VDD_HV_AD1
3
VSS_HV_AD1
VDD_LV_REGCOR4,5
VSS_LV_REGCOR
4
VDD_LV_CORx4,5
—
Relative to
VDD_HV_REG
VDD_HV_IO VDD_HV_IO
x – 0.1
x + 0.1
3.0
5.5
VDD_HV_R
EG – 0.1
5.5
V
SR ADC0 ground and low reference voltage
—
0
0
V
SR 3.3 V ADC1 supply and high reference
voltage
—
3.0
5.5
V
VDD_HV_R
EG – 0.1
5.5
Relative to
VDD_HV_REG
SR ADC1 ground and low reference voltage
—
0
0
V
SR Internal supply voltage
—
—
—
V
SR Internal reference voltage
—
0
0
V
SR Internal supply voltage
—
—
—
V
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
27
Table 7. Recommended operating conditions (3.3 V) (continued)
Symbol
VSS_LV_CORx4
TA
TJ
1
2
3
4
5
Parameter
SR Internal reference voltage
SR Ambient temperature under bias
SR Junction temperature under bias
Conditions
Min
Max1
Unit
—
0
0
V
fCPU = 64 MHz
–40
105
°C
fCPU = 60 MHz
–40
125
–40
150
—
°C
Full functionality cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics
and I/Os DC electrical specification may not be guaranteed.
The difference between each couple of voltage supplies must be less that 300 mV, |VDD_HV_IOy – VDD_HV_IOx | <
100 mV.
The power supply voltage must be identical for ADC0 and ADC1
To be connected to emitter of external NPN. Low voltage supplies are not under user control—they are produced
by an on-chip voltage regulator—but for the device to function properly the low voltage grounds (VSS_LV_xxx) must
be shorted to high voltage grounds (VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected
to the external ballast emitter.
The low voltage supplies (VDD_LV_xxx) are not all independent.
VDD_LV_COR1 and VDD_LV_COR2 are shorted internally via double bonding connections with lines that provide
the low voltage supply to the data flash module. Similarly, VSS_LV_COR1 and VSS_LV_COR2 are internally
shorted.
VDD_LV_REGCOR and VDD_LV_RECORx are physically shorted internally, as are VSS_LV_REGCOR and
VSS_LV_CORx.
Figure 6 shows the constraints of the different power supplies:
VDD_HV_xxx
5.5V
3.0V
VDD_HV_IOx
3.0V
5.5V
Figure 6. Power supplies constraints
The MPC5604P supply architecture allows of having ADC supply managed independently from standard VDD_HV supply.
Figure 7 shows the constraints of the ADC power supply.
MPC5604P Microcontroller Data Sheet, Rev. 5
28
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
5.5V
3.0V
VDD_HV_REG
3.0V
5.5V
Figure 7. Independent ADC supply
3.3
Thermal characteristics
Table 8. Thermal characteristics for 144-pin LQFP1
No. Symbol
3
4
5
6
Typical
Unit
Value
RθJA
Thermal resistance junction-to-ambient,
natural convection2
Single layer board—1s
52
°C/W
2
RθJA
Thermal resistance junction-to-ambient,
natural convection2
Four layer board—2s2p
43
°C/W
3
RθJMA
Thermal resistance junction-to-ambient2
@ 200 ft./min.3, single layer
board—1s
43
°C/W
4
RθJMA
Thermal resistance junction-to-ambient2
@ 200 ft./min.3, four layer
board—2s2p
37
°C/W
5
RθJB
—
31
°C/W
—
12
°C/W
—
2
°C/W
7
2
Conditions
1
6
1
Parameter
Thermal resistance junction to board4
RθJCtop Thermal resistance junction to case (top)
ΨJT
Junction to package top natural
5
convection6
Thermal characteristics are targets based on simulation that are subject to change per device characterization.
Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board
meets JEDEC specification for this package.
Flow rate of forced air flow.
Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package.
Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
Thermal characterization parameter indicating the temperature difference between the package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JT.
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
29
Table 9. Thermal characteristics for 100-pin LQFP1
Symbol
1
RθJA
Thermal resistance junction-to-ambient
natural convection2
Single layer board—1s
56,3
°C/W
2
RθJA
Thermal resistance junction-to-ambient
natural convection2
Four layer board—2s2p
43,4
°C/W
3
RθJMA
Thermal resistance junction-to-ambient2
@ 200 ft./min.3, single layer
board—1s
43
°C/W
4
RθJMA
Thermal resistance junction-to-ambient2
@ 200 ft./min.3, four layer
board—2s2p
35
°C/W
5
RθJB
—
27
°C/W
—
14
°C/W
—
3
°C/W
6
7
1
2
3
4
5
6
3.3.1
Parameter
Conditions
Typical
Unit
Value
No.
Thermal resistance junction to board4
RθJCtop Thermal resistance junction to case (Top)5
ΨJT
Junction to package top natural convection6
Thermal characteristics are targets based on simulation that are subject to change per device characterization.
Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board
meets JEDEC specification for this package.
Flow rate of forced air flow.
Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package.
Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
Thermal characterization parameter indicating the temperature difference between the package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JT.
General notes for specifications at maximum junction temperature
An estimation of the chip junction temperature, TJ, can be obtained from Equation 1:
TJ = TA + (RθJA * PD)
Eqn. 1
where:
TA = ambient temperature for the package (oC)
RθJA= junction to ambient thermal resistance (oC/W)
PD = power dissipation in the package (W)
The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal
performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value
obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which
value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a
single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal
planes is usually appropriate if the board has low power dissipation and the components are well separated.
When a heat sink is used, the thermal resistance is expressed in Equation 2 as the sum of a junction to case thermal resistance
and a case to ambient thermal resistance:
RθJA = RθJC + RθCA
Eqn. 2
MPC5604P Microcontroller Data Sheet, Rev. 5
30
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
where:
RθJA = junction to ambient thermal resistance (°C/W)
RθJC= junction to case thermal resistance (°C/W)
RθCA= case to ambient thermal resistance (°C/W)
RθJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to
ambient thermal resistance, RθCA. For instance, the user can change the size of the heat sink, the air flow around the device, the
interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit
board surrounding the device.
To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal
Characterization Parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at
the top center of the package case using Equation 3:
TJ = TT + (ΨJT x PD)
Eqn. 3
where:
TT = thermocouple temperature on top of the package (°C)
ΨJT = thermal characterization parameter (°C/W)
PD = power dissipation in the package (W)
The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied
to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the
junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects
of the thermocouple wire.
References:
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134U.S.A.
(408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or
303-397-7956.
JEDEC specifications are available on the WEB at http://www.jedec.org.
1. C.E. Triplett and B. Joiner, An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller
Module, Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.
2. G. Kromann, S. Shidore, and S. Addison, Thermal Modeling of a PBGA for Air-Cooled Applications, Electronic Packaging
and Production, pp. 53-58, March 1998.
3. B. Joiner and V. Adams, Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in
Thermal Modeling, Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
31
3.4
Electromagnetic interference (EMI) characteristics
Table 10. EMI Testing Specifications1
Symbol
Radiated
emissions,
electric field
Parameter
VRE_TEM
Conditions
VDD = 5.5 V;
TA = +25 °C
150 kHz–30 MHz
RBW 9 kHz, Step
Size 5 kHz
30 MHz–1 GHz
RBW 120 kHz, Step
Size 80 kHz
1
3.5
fOSC/fBUS
Frequency
16 MHz crystal 150 kHz–50 MHz
40 MHz bus
50–150 MHz
No PLL frequency
modulation
150–500 MHz
16 MHz crystal
40 MHz bus
±2% PLL
frequency
modulation
Level
(Max)
Unit
20
dBμV
20
26
500–1000 MHz
26
IEC Level
K
—
SAE Level
3
—
150 kHz–50 MHz
18
dBμV
50–150 MHz
18
15–500 MHz
15
500–1000 MHz
15
IEC Level
M
—
SAE Level
2
—
EMI testing and I/O port waveforms per SAE J1752/3 issued 1995-03.
Electrostatic discharge (ESD) characteristics
Table 11. ESD ratings1,2
Symbol
Parameter
Conditions
Value
Unit
VESD(HBM)
SR Electrostatic discharge (Human Body Model)
—
2000
V
VESD(CDM)
SR Electrostatic discharge (Charged Device Model)
—
750 (corners)
V
500 (other)
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated
Circuits.
2
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification
MPC5604P Microcontroller Data Sheet, Rev. 5
32
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
3.6
3.6.1
Power management electrical characteristics
Voltage regulator electrical characteristics
The internal voltage regulator requires an external NPN (BCP56, BCP68, BCX68 or BC817) ballast to be connected as shown
in Figure 8 and Figure 9. Capacitances should be placed on the board as near as possible to the associated pins. Care should also
be taken to limit the serial inductance of the board to less than 5 nH.
NOTE
The voltage regulator output cannot be used to drive external circuits. Output pins are to be
used only for decoupling capacitance.
VDD_LV_COR must be generated using internal regulator and external NPN transistor. It
is not possible to provide VDD_LV_COR through external regulator.
For the MPC5604P microcontroller, 10 µF should be placed between each of the three VDD_LV_CORx/VSS_LV_CORx supply pairs
and also between the VDD_LV_REGCOR/VSS_LV_REGCOR pair. Additionally, 40 μF should be placed between the
VDD_HV_REG/VSS_HV_REG pins.
VDD = 3.0 V to 3.6 V / 4.5 V to 5.5 V, TA = –40 to 125 °C, unless otherwise specified.
VDD_HV_REG
CDEC3
BCP56,
BCP68,
BCX68,
BC817
BCTRL
MPC5604P
VDD_LV_COR
CDEC2
CDEC1
Figure 8. Configuration without resistor on base
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
33
Table 12. Voltage regulator electrical characteristics
Symbol
Parameter
Conditions
VDD_LV_REGCOR
P Output voltage under maximum load Post-trimming
run supply current configuration
CDEC1
SR External decoupling/stability ceramic 4 capacitances
capacitor
RREG
SR Resulting ESR of all four CDEC1
Min
1.145
absolute maximum
value between 100 kHz
and 10 MHz
Typ
—
Max
Unit
1.4
V
40
56
—
—
—
45
mΩ
CDEC2
SR External decoupling/stability ceramic 4 capacitances of
capacitor
100 nF each
400
—
—
CDEC3
SR External decoupling/stability ceramic
capacitor on VDD_HV_REG
40
—
—
—
µF
nF
µF
VDD_HV_REG
CDEC3
BCP68,
BCX68,
BC817su
BCTRL
MPC5604P
RB
VDD_LV_COR
CDEC2
CDEC1
Figure 9. Configuration without resistor on base
MPC5604P Microcontroller Data Sheet, Rev. 5
34
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Table 13. Voltage regulator electrical characteristics
Symbol
VDD_LV_REGCOR
RB
CDEC1
Parameter
Conditions
P Output voltage under maximum load Post-trimming
run supply current configuration
SR External Resistance on BJT base
SR External decoupling/stability ceramic Bipolar BCP68 or
capacitor
BCX68 or BC817.
Three capacitances of
10uF
SR Resulting ESR of all four CDEC1
1.145
—
Bipolar BC817.
One capacitance of
22uF
RREG
Min
18
Typ
—
—
Max
Unit
1.4
V
22
kΩ
µF
19.5
30
—
14.3
22
—
—
—
45
1760
1200
—
—
—
Typ
Max
Unit
1.4
V
22
kΩ
µF
absolute maximum
value between 100 kHz
and 10 MHz
mΩ
CDEC2
SR External decoupling/stability ceramic 4 capacitances of
capacitor
440 nF each
CDEC3
SR External decoupling/stability ceramic 2 capacitances of 10 µF
2 × 10
capacitor on VDD_HV_REG
each
nF
µF
Table 14. Voltage regulator electrical characteristics
Symbol
VDD_LV_REGCOR
RB
CDEC1
Parameter
Conditions
P Output voltage under maximum load Post-trimming
run supply current configuration
SR External Resistance on BJT base
—
SR External decoupling/stability ceramic Bipolar BCP68 or
capacitor
BCX68 or BC817.
Three capacitances of
10uF
Bipolar BC817.
One capacitance of
22uF
RREG
3.6.2
SR Resulting ESR of all four CDEC1
absolute maximum
value between 100 kHz
and 10 MHz
Min
1.145
18
—
—
µF
19.5
30
—
14.3
22
—
—
—
45
1760
1200
—
—
—
µF
mΩ
CDEC2
SR External decoupling/stability ceramic 4 capacitances of
capacitor
440 nF each
CDEC3
SR External decoupling/stability ceramic 2 capacitances of 10 µF
2 × 10
capacitor on VDD_HV_REG
each
nF
µF
Voltage monitor electrical characteristics
The device implements a Power On Reset module to ensure correct power-up initialization, as well as three low voltage
detectors to monitor the VDD and the VDD_LV voltage while device is supplied:
•
POR monitors VDD during the power-up phase to ensure device is maintained in a safe reset state
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
35
•
•
•
LVDHV3 monitors VDD to ensure device reset below minimum functional supply
LVDHV5 monitors VDD when application uses device in the 5.0V ± 10% range
LVDLVCOR monitors low voltage digital power domain
Table 15. Low voltage monitor electrical characteristics
Symbol
1
3.7
Parameter
VPORH
T Power-on reset threshold
VPORUP
P Supply for functional POR module
Conditions1
Value
Unit
Min
Max
—
1.5
2.7
V
TA = 25°C
1.0
—
V
VREGLVDMOK_H
P Regulator low voltage detector high threshold
—
—
2.95
V
VREGLVDMOK_L
P Regulator low voltage detector low threshold
—
2.6
—
V
VFLLVDMOK_H
P Flash low voltage detector high threshold
—
—
2.95
V
VFLLVDMOK_L
P Flash low voltage detector low threshold
—
2.6
—
V
VIOLVDMOK_H
P I/O low voltage detector high threshold
—
—
2.95
V
VIOLVDMOK_L
P I/O low voltage detector low threshold
—
2.6
—
V
VIOLVDM5OK_H
P I/O 5V low voltage detector high threshold
—
—
4.4
V
VIOLVDM5OK_L
P I/O 5V low voltage detector low threshold
—
3.8
—
V
VMLVDDOK_H
P Digital supply low voltage detector high
—
—
1.14
V
VMLVDDOK_L
P Digital supply low voltage detector low
—
1.08
—
V
VDD = 3.3V ± 10% / 5.0V ± 10%, TA = –40 to 125°C, unless otherwise specified
Power up/down sequencing
The MPC5604P implements a precise sequence to ensure each module is started only when all conditions for switching it ON
are available. This prevents overstress event or miss-functionality within and outside the device:
•
•
•
a POWER_ON module working on voltage regulator supply is controlling the correct start-up of the regulator. This is
a key module ensuring safe configuration for all Voltage regulator functionality when supply is below 1.5V. Associated
POWER_ON (or POR) signal is active low.
Several Low Voltage Detectors, working on voltage regulator supply are monitoring the voltage of the critical modules
(Voltage regulator, I/Os, Flash and Low voltage domain). LVDs are gated low when POWER_ON is active.
a POWER_OK signal is generated when all critical supplies monitored by the LVD are available. This signal is active
high and released to all modules including I/Os, Flash and RC16 oscillator needed during power-up phase and reset
phase. When POWER_OK is low the associated module are set into a safe state.
MPC5604P Microcontroller Data Sheet, Rev. 5
36
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
VPORH
VDD_HV_REG
VLVDHV3H
3.3V
VPOR_UP
0V
3.3V
POWER_ON
0V
3.3V
LVDM (HV)
0V
VMLVDOK_H
VDD_LV_REGCOR
1.2V
0V
3.3V
LVDD (LV)
0V
3.3V
POWER_OK
0V
RC16MHz Oscillator
1.2V
0V
~1us
Internal Reset Generation Module
FSM
P0
P1
1.2V
0V
Figure 10. Power-up typical sequence
VLVDHV3L
VDD_HV_REG
VPORH
3.3V
0V
3.3V
LVDM (HV)
0V
3.3V
POWER_ON
0V
1.2V
0V
VDD_LV_REGCOR
3.3V
LVDD (LV)
0V
3.3V
POWER_OK
0V
RC16MHz Oscillator
1.2V
0V
Internal Reset Generation Module
FSM
IDLE
P0
1.2V
0V
Figure 11. Power-down typical sequence
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
37
VLVDHV3L
VLVDHV3H
3.3V
VDD_HV_REG
0V
3.3V
LVDM (HV)
0V
3.3V
POWER_ON
0V
1.2V
0V
VDD_LV_REGCOR
3.3V
LVDD (LV)
0V
3.3V
POWER_OK
0V
RC16MHz Oscillator
1.2V
0V
~1us
Internal Reset Generation Module
FSM
IDLE
P0
P1
1.2V
0V
Figure 12. Brown-out typical sequence
MPC5604P Microcontroller Data Sheet, Rev. 5
38
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
3.8
3.8.1
DC electrical characteristics
NVUSRO register
Portions of the MPC5604P device configuration (that is, high voltage supply, oscillator margin, and watchdog enable/disable
after reset) are controlled via bit values in the NVUSRO register. NVUSRO[PAD3V5V] controls the device configuration as
follows:
Table 16. NVUSRO[PAD3V5V] field description1
Value2
1
2
Description
0
High Voltage supply is 5.0 V
1
High Voltage supply is 3.3 V
See the MPC5604P Reference Manual for more information on the NVUSRO register.
Default manufacturing value before flash initialization is '1' (3.3 V).
The DC electrical characteristics in the following sections are dependent on the PAD3V5V value as described above.
3.8.2
DC electrical characteristics (5 V)
Table 17 gives the DC electrical characteristics at 5 V (4.5 V < VDD_HV_IOx < 5.5 V, NVUSRO[PAD3V5V]=0) as described in
Figure 13.
VIN
VDD
VIH
VHYS
VIL
PDIx = ‘1’
(GPDI register of SIUL)
PDIx = ‘0’
Figure 13. I/O input DC electrical characteristics definition
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
39
Table 17. DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V]=0)
Symbol
Conditions
Min
1
Max
Unit
VIL
D Minimum low level input voltage
—
–0.1
—
V
VIL
P Maximum level input voltage
—
—
0.35 VDD_HV_IOx
V
VIH
P Minimum high level input voltage
—
0.65 VDD_HV_IOx
—
V
VIH
1
D Maximum high level input voltage
—
—
VDD_HV_IOx + 0.1
VHYS
T Schmitt trigger hysteresis
—
0.1 VDD_HV_IOx
—
V
VOL_S
P Slow, low level output voltage
IOL = 3 mA
—
0.1 VDD_HV_IOx
V
VOH_S
P Slow, high level output voltage
IOH = –3 mA
0.8VDD_HV_IOx
—
V
VOL_M
P Medium, low level output voltage IOL = 3 mA
—
0.1 VDD_HV_IOx
V
VOH_M
P Medium, high level output
voltage
IOH = –3 mA
0.8 VDD_HV_IOx
—
V
VOL_F
P Fast, low level output voltage
IOL = 3 mA
—
0.1 VDD_HV_IOx
V
VOH_F
P Fast, high level output voltage
IOH = –3 mA
0.8 VDD_HV_IOx
—
V
VOL_SYM
P Symmetric, low level output
voltage
IOL = 3 mA
—
0.1 VDD_HV_IOx
V
VOH_SYM
P Symmetric, high level output
voltage
IOH = –3 mA
0.8 VDD_HV_IOx
—
V
P Equivalent pull-up current
VIN = VIL
–130
—
µA
VIN = VIH
—
–10
VIN = VIL
10
—
VIN = VIH
—
130
IPU
IPD
1
Parameter
P Equivalent pull-down current
V
µA
IIL
P Input leakage current
(all bidirectional ports)
TA = –40 to
125 °C
–1
1
µA
IIL
P Input leakage current
(all ADC input-only ports)
TA = –40 to
125 °C
–0.5
0.5
µA
IVPP
P Input leakage current on VPP
leakage pad
—
–5
5
μA
CIN
D Input capacitance
—
—
10
pF
“SR” parameter values must not exceed the absolute maximum ratings shown in Table 5.
MPC5604P Microcontroller Data Sheet, Rev. 5
40
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Table 18. Supply current (5.0 V, NVUSRO[PAD3V5V]=0)
Value1
Symbol
I
DD_LV_CORE
Parameter
T
Supply RUN - Maximum Mode2
current
RUN - Typical
P
Conditions
V
DD_LV_CORE
externally forced at 1.3 V
Mode3
RUN - Maximum Mode4
V
DD_LV_CORE
Unit
Typ
Max
40 MHz
62
77
64 MHz
71
88
40 MHz
45
56
64 MHz
52
65
64 MHz
60
TBD
—
1.5
10
mA
externally forced at 1.3 V
HALT Mode5
V
DD_LV_CORE
externally forced at 1.3 V
IDD_FLASH
IDD_ADC
T
T
STOP Mode6
VDD_LV_CORE
externally forced at 1.3 V
—
1
10
FLASH supply current
during read
VDD_HV_FL at 5.0 V
—
10
12
FLASH supply current
during erase operation
on 1 flash module
VDD_HV_FL at 5.0 V
—
15
19
ADC17
3.5
5
ADC0
3
4
ADC17
0.8
1
ADC supply current - Maximum Mode2 VDD_HV_AD0 at 5.0 V
VDD_HV_AD1 at 5.0 V
ADC Freq = 16MHz
ADC supply current - Typical Mode3
ADC0
I
DD_OSC
1
2
3
4
5
6
7
T
OSC supply current
VDD_OSC at 5.0 V
8 MHz
0.005 0.006
2.6
3.2
All values to be confirmed after characterization/data collection.
Maximum mode: FlexPWM, ADCs, CTU, DSPI, LINFlex, FlexCAN, 15 output pins, 1st and 2nd PLL enabled, 125 °C ambient.
I/O supply current excluded.
Typical mode configurations: DSPI, LINFlex, FlexCAN, 15 output pins, 1st PLL only, 105 °C ambient. I/O supply current
excluded.
Code fetched from Ram, PLL0: 64 MHz system clock (x4 multiplier with 16MHz XTAL), PLL1 is ON @ PHI_div2 = 120 Mhz
and PHI_div3 = 80 Mhz, auxiliary clock sources set that all peripherals receive maximum frequency, all peripheral enabled.
Halt mode configurations: Code fetched from RAM, C & D FLASH in low power mode, OSC/PLL0/PLL1 are OFF, Core clock
frozen, all peripherals are disabled.
STOP "P" mode DUT configuration: Code fetched from RAM, C & D FLASH off, OSC/PLL0/PLL1 are OFF, Core clock frozen,
all peripherals are disabled.
Includes Temperature Sensor current consumption.
3.8.3
DC Electrical characteristics (3.3 V)
Table 19 gives the DC electrical characteristics at 3.3 V (3.0 V < VDD_HV_IOx < 3.6 V, NVUSRO[PAD3V5V]=1) as described
in Figure 14.
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
41
VIN
VDD
VIH
VHYS
VIL
PDIx = ‘1’
(GPDI register of SIUL)
PDIx = ‘0’
Figure 14. I/O input DC electrical characteristics definition
Table 19. DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V]=1)1
Symbol
Parameter
Conditions
Min
Max
Unit
—
V
VIL
D Minimum low level input voltage
—
–0.12
VIL
P Maximum low level input voltage
—
—
0.35 VDD_HV_IOx
V
VIH
P Minimum high level input voltage
—
0.65 VDD_HV_IOx
—
V
D Maximum high level input
voltage
—
VHYS
T
—
VOL_S
P Slow, low level output voltage
IOL = 1.5 mA
VOH_S
P Slow, high level output voltage
IOH = –1.5 mA
VOL_M
P Medium, low level output voltage IOL = 2 mA
VOH_M
P Medium, high level output
voltage
VOL_F
VOH_F
VIH
VDD_HV_IOx +
V
0.1 VDD_HV_IOx
—
V
—
0.5
V
VDD_HV_IOx – 0.8
—
V
—
0.5
V
IOH = –2 mA
VDD_HV_IOx – 0.8
—
V
P Fast, high level output voltage
IOL = 1.5 mA
—
0.5
V
P Fast, high level output voltage
IOH = –1.5 mA
VDD_HV_IOx – 0.8
—
V
VOL_SYM
P Symmetric, high level output
voltage
IOL = 1.5 mA
—
0.5
V
VOH_SYM
P Symmetric, high level output
voltage
IOH = –1.5 mA
VDD_HV_IOx – 0.8
—
V
P Equivalent pull-up current
VIN = VIL
–130
—
µA
VIN = VIH
—
–10
IPU
Schmitt trigger hysteresis
—
0.12
MPC5604P Microcontroller Data Sheet, Rev. 5
42
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Table 19. DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V]=1)1 (continued)
Symbol
2
Conditions
P Equivalent pull-down current
IPD
1
Parameter
Min
Max
Unit
VIN = VIL
10
—
µA
VIN = VIH
—
130
IIL
P Input leakage current
(all bidirectional ports)
TA = –40 to
125 °C
—
1
µA
IIL
P Input leakage current
(all ADC input-only ports)
TA = –40 to
125 °C
—
0.5
µA
IVPP
P Input leakage current on VPP
leakage pad
—
–5
5
μA
CIN
D Input capacitance
—
—
—
pF
These specifications are design targets and subject to change per device characterization.
“SR” parameter values must not exceed the absolute maximum ratings shown in Table 5.
Table 20. Supply current (3.3 V, NVUSRO[PAD3V5V]=1)
Value1
Symbol
I
DD_LV_CORE
Parameter
T
Unit
Typ
Max
40 MHz
62
77
64 MHz
71
89
40 MHz
45
56
64 MHz
53
66
64 MHz
60
TBD
—
1.5
10
—
1
10
FLASH supply current during read on VDD_HV_FL at 3.3 V
single mode
—
8
10
FLASH supply current
during erase operation
on single mode
—
10
12
ADC17
2.5
4
ADC0
2
4
0.8
1
Supply RUN - Maximum Mode2
current
RUN - Typical Mode
P
Conditions
RUN - Maximum
V
DD_LV_CORE
externally forced at 1.3 V
3
Mode4
V
DD_LV_CORE
mA
externally forced at 1.3 V
HALT Mode5
V
DD_LV_CORE
externally forced at 1.3 V
STOP Mode6
IDD_FLASH
IDD_ADC
T
T
VDD_LV_CORE
externally forced at 1.3 V
VDD_HV_FL at 3.3 V
ADC supply current - Maximum Mode2 VDD_HV_AD0 at 3.3 V
VDD_HV_AD1 at 3.3 V
ADC Freq = 16MHz
ADC supply current - Typical Mode3
ADC1
7
ADC0
I
DD_OSC
1
2
T
OSC supply current
VDD_OSC at 3.3 V
8 MHz
0.005 0.006
2.4
3
All values to be confirmed after characterization/data collection.
Maximum mode: FlexPWM, ADCs, CTU, DSPI, LINFlex, FlexCAN, 15 output pins, 1st and 2nd PLL enabled, 125 °C ambient.
I/O supply current excluded.
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
43
3
Typical mode: DSPI, LINFlex, FlexCAN, 15 output pins, 1st PLL only, 105 °C ambient. I/O supply current excluded.
Code fetched from Ram, PLL0: 64 MHz system clock (x4 multiplier with 16MHz XTAL), PLL1 is ON @ PHI_div2 = 120 Mhz
and PHI_div3 = 80 Mhz, auxiliary clock sources set that all peripherals receive maximum frequency, all peripheral enabled.
5
Halt mode configurations: Code fetched from RAM, C & D FLASH in low power mode, OSC/PLL0/PLL1 are OFF, Core clock
frozen, all peripherals are disabled.
6 STOP "P" mode DUT configuration: Code fetched from RAM, C & D FLASH off, OSC/PLL0/PLL1 are OFF, Core clock frozen,
all peripherals are disabled.
7
Includes Temperature Sensor current consumption.
4
3.8.4
I/O pad current specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a VDD/VSS supply pair as
described in Table 21.
Table 21. I/O supply segment
Supply segment
Package
1
2
3
4
5
6
144 LQFP
pin8 – pin20
100 LQFP
pin15 – pin26 pin27 – pin38 pin41 – pin46 pin51 – pin61 pin64 – pin86 pin89 – pin10
7
pin23 – pin38 pin39 – pin55 pin58 – pin68 pin73 – pin89 pin92 – pin125 pin128 – pin5
—
Table 22 provides the weight of concurrent switching I/Os.
In order to ensure device functionality, the sum of the weight of concurrent switching I/Os on a single segment should remain
below the 100%.
Table 22. I/O weight
144 LQFP
100 LQFP
PAD
Weight 5V Weight 3.3V Weight 5V Weight 3.3V
NMI
1%
1%
1%
1%
PAD[6]
6%
5%
14%
13%
PAD[49]
5%
4%
14%
12%
PAD[84]
14%
10%
—
—
PAD[85]
9%
7%
—
—
PAD[86]
9%
6%
—
—
MODO0
12%
8%
—
—
PAD[7]
4%
4%
11%
10%
PAD[36]
5%
4%
11%
9%
PAD[8]
5%
4%
10%
9%
PAD[37]
5%
4%
10%
9%
PAD[5]
5%
4%
9%
8%
PAD[39]
5%
4%
9%
8%
PAD[35]
5%
4%
8%
7%
PAD[87]
12%
9%
—
—
MPC5604P Microcontroller Data Sheet, Rev. 5
44
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Table 22. I/O weight
144 LQFP
100 LQFP
PAD
Weight 5V Weight 3.3V Weight 5V Weight 3.3V
PAD[88]
9%
6%
—
—
PAD[89]
10%
7%
—
—
PAD[90]
15%
11%
—
—
PAD[91]
6%
5%
—
—
PAD[57]
8%
7%
8%
7%
PAD[56]
13%
11%
13%
11%
PAD[53]
14%
12%
14%
12%
PAD[54]
15%
13%
15%
13%
PAD[55]
25%
22%
25%
22%
PAD[96]
27%
24%
—
—
PAD[65]
1%
1%
1%
1%
PAD[67]
1%
1%
—
—
PAD[33]
1%
1%
1%
1%
PAD[68]
1%
1%
—
—
PAD[23]
1%
1%
1%
1%
PAD[69]
1%
1%
—
—
PAD[34]
1%
1%
1%
1%
PAD[70]
1%
1%
—
—
PAD[24]
1%
1%
1%
1%
PAD[71]
1%
1%
—
—
PAD[66]
1%
1%
1%
1%
PAD[25]
1%
1%
1%
1%
PAD[26]
1%
1%
1%
1%
PAD[27]
1%
1%
1%
1%
PAD[28]
1%
1%
1%
1%
PAD[63]
1%
1%
1%
1%
PAD[72]
1%
1%
—
—
PAD[29]
1%
1%
1%
1%
PAD[73]
1%
1%
—
—
PAD[31]
1%
1%
1%
1%
PAD[74]
1%
1%
—
—
PAD[30]
1%
1%
1%
1%
PAD[75]
1%
1%
—
—
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
45
Table 22. I/O weight
144 LQFP
100 LQFP
PAD
Weight 5V Weight 3.3V Weight 5V Weight 3.3V
PAD[32]
1%
1%
1%
1%
PAD[76]
1%
1%
—
—
PAD[64]
1%
1%
1%
1%
PAD[0]
23%
20%
23%
20%
PAD[1]
21%
18%
21%
18%
PAD[107]
20%
17%
—
—
PAD[58]
19%
16%
19%
16%
PAD[106]
18%
16%
—
—
PAD[59]
17%
15%
17%
15%
PAD[105]
16%
14%
—
—
PAD[43]
15%
13%
15%
13%
PAD[104]
14%
13%
—
—
PAD[44]
13%
12%
13%
12%
PAD[103]
12%
11%
—
—
PAD[2]
11%
10%
11%
10%
PAD[101]
11%
9%
—
—
PAD[21]
10%
8%
10%
8%
TMS
1%
1%
1%
1%
TCK
1%
1%
1%
1%
PAD[20]
16%
11%
16%
11%
PAD[3]
4%
3%
4%
3%
PAD[61]
9%
8%
9%
8%
PAD[102]
11%
10%
—
—
PAD[60]
11%
10%
11%
10%
PAD[100]
12%
10%
—
—
PAD[45]
12%
10%
12%
10%
PAD[98]
12%
11%
—
—
PAD[46]
12%
11%
12%
11%
PAD[99]
13%
11%
—
—
PAD[62]
13%
11%
13%
11%
PAD[92]
13%
12%
—
—
VPP_TEST
1%
1%
1%
1%
PAD[4]
14%
12%
14%
12%
MPC5604P Microcontroller Data Sheet, Rev. 5
46
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Table 22. I/O weight
144 LQFP
100 LQFP
PAD
Weight 5V Weight 3.3V Weight 5V Weight 3.3V
PAD[16]
13%
12%
13%
12%
PAD[17]
13%
11%
13%
11%
PAD[42]
13%
11%
13%
11%
PAD[93]
12%
11%
—
—
PAD[95]
12%
11%
—
—
PAD[18]
12%
10%
12%
10%
PAD[94]
11%
10%
—
—
PAD[19]
11%
10%
11%
10%
PAD[77]
10%
9%
—
—
PAD[10]
10%
9%
10%
9%
PAD[78]
9%
8%
—
—
PAD[11]
9%
8%
9%
8%
PAD[79]
8%
7%
—
—
PAD[12]
7%
7%
7%
7%
PAD[41]
7%
6%
7%
6%
PAD[47]
5%
4%
5%
4%
PAD[48]
4%
4%
4%
4%
PAD[51]
4%
4%
4%
4%
PAD[52]
5%
4%
5%
4%
PAD[40]
5%
5%
6%
5%
PAD[80]
9%
8%
—
—
PAD[9]
10%
9%
11%
10%
PAD[81]
10%
9%
—
—
PAD[13]
10%
9%
12%
11%
PAD[82]
10%
9%
—
—
PAD[22]
10%
9%
13%
12%
PAD[83]
10%
9%
—
—
PAD[50]
10%
9%
14%
12%
PAD[97]
10%
9%
—
—
PAD[38]
10%
9%
14%
13%
PAD[14]
9%
8%
14%
13%
PAD[15]
9%
8%
15%
13%
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
47
3.9
Temperature sensor electrical characteristics
Table 23. Temperature sensor electrical characteristics
Symbol
—
Conditions
P Accuracy
Min
Max
Unit
TJ = –40 °C to TA = 25 °C
TBD
TBD
°C
TJ = TA to 125 °C
TBD
TBD
°C
1.5
—
µs
D Minimum sampling period
TS
3.10
Parameter
Main oscillator electrical characteristics
The MPC5604P provides an oscillator/resonator driver.
Table 24. Main oscillator electrical characteristics (5.0 V, NVUSRO[PAD3V5V]=0)
Symbol
Parameter
Min
Max
Unit
fOSC
SR Oscillator frequency
4
40
MHz
gm
P Transconductance
6.5
25
mA/V
1
—
V
8
—
ms
T Oscillation amplitude on EXTAL pin
VOSC
T Start-up
tOSCSU
time1,2
1
The start-up time is dependent upon crystal characteristics, board leakage, etc., high ESR and excessive capacitive
loads can cause long start-up time.
2 Value captured when amplitude reaches 90% of EXTAL
Table 25. Main oscillator electrical characteristics (3.3 V, NVUSRO[PAD3V5V]=1)
Symbol
Parameter
Min
Max
Unit
fOSC
SR Oscillator frequency
4
40
MHz
gm
P Transconductance
4
20
mA/V
T Oscillation amplitude on EXTAL pin
1
—
V
8
—
ms
VOSC
T Start-up
tOSCSU
time1,2
1
The start-up time is dependent upon crystal characteristics, board leakage, etc., high ESR and excessive capacitive
loads can cause long start-up time.
2 Value captured when amplitude reaches 90% of EXTAL
Table 26. Input clock characteristics
Symbol
Parameter
Min
Typ
Max
Unit
fOSC
SR Oscillator frequency
4
—
40
MHz
fCLK
SR Frequency in bypass
—
—
64
MHz
trCLK
SR Rise/fall time in bypass
—
—
1
ns
47.5
50
52.5
%
tDC
SR Duty cycle
MPC5604P Microcontroller Data Sheet, Rev. 5
48
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
3.11
FMPLL electrical characteristics
Table 27. PLLMRFM electrical specifications1
(VDDPLL = 3.0 V to 3.6 V, VSS = VSSPLL = 0 V, TA = TL to TH)
Value
Symbol
Parameter
Conditions
Unit
min
max
Crystal reference
4
40
MHz
fref_crystal
fref_ext
D
PLL reference frequency range2
fpll_in
D
Phase detector input frequency range
(after pre-divider)
—
4
16
MHz
fFMPLLO
D
Clock frequency range in normal
mode
—
4
120
MHz
fFREE
P
Free running frequency
Measured using
clock division —
typically /16
20
150
MHz
fsys
D
On-chip PLL frequency2
—
16
120
MHz
tCYC
D
System clock period
—
—
1 / fsys
ns
fLORL
fLORH
D
Loss of reference frequency window3
Lower limit
1.6
3.7
MHz
Upper limit
24
56
fSCM
D
Self-clocked mode frequency4,5
20
150
MHz
CJITTER
T
CLKOUT
period
jitter6,7,8,9
UT
—
Short-term jitter10
fSYS maximum
-4
4
% fCLKOUT
Long-term jitter (avg.
over 2 ms interval)
fPLLIN = 16 MHz
(resonator),
fPLLCLK @ 64
MHz, 4000
cycles
—
10
ns
tlpll
D
PLL lock time 11, 12
—
—
200
μs
tdc
D
Duty cycle of reference
—
40
60
%
fLCK
D
Frequency LOCK range
—
-6
6
% fsys
fUL
D
Frequency un-LOCK range
—
-18
18
% fsys
fCS
fDS
D
Modulation Depth
Center spread
±0.25
±4.013
%fsys
Down Spread
-0.5
-8.0
fMOD
D
—
70
Modulation frequency14
—
kHz
1
All values given are initial design targets and subject to change.
Considering operation with PLL not bypassed.
3
“Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked
mode.
4
Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside
the fLOR window.
2
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
49
5
fVCO self clock range is 20-150 MHz. fSCM represents fSYS after PLL output divider (ERFD) of 2 through 16 in
enhanced mode.
6
This value is determined by the crystal manufacturer and board design.
7
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum
fSYS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock
signal. Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency
increase the CJITTER percentage for a given interval.
8
Proper PC board layout procedures must be followed to achieve specifications.
9
Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER and
either fCS or fDS (depending on whether center spread or down spread modulation is enabled).
10
Short term jitter is measured on the clock rising edge at cycle n and cycle n+4.
11
This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for
this PLL, load capacitors should not exceed these limits.
12
This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits
in the synthesizer control register (SYNCR).
13
This value is true when operating at frequencies above 60 MHz, otherwise fCS is 2% (above 64 MHz).
14 Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50kHz.
3.12
16 MHz RC oscillator electrical characteristics
Table 28. 16 MHz RC oscillator electrical characteristics
Symbol
fRC
ΔRCMVAR
ΔRCMTRIM
ΔRCMSTEP
1
Parameter
Conditions
Min
Typ
Max
Unit
TA = 25 °C
—
16
—
MHz
P Fast internal RC oscillator variation
over temperature and
supply with respect to fRC at TA = 25 °C
in high-frequency configuration
—
-5
—
5
%
P Post Trim Accuracy: The variation of the
PTF1 from the 16 MHz
TA = 25 °C
-1
—
1
%
P Fast internal RC oscillator trimming
step
TA = 25 °C
—
1.6
—
%
P RC oscillator frequency
PTF = Post Trimming Frequency: The frequency of the output clock after trimming at typical supply voltage and
temperature
MPC5604P Microcontroller Data Sheet, Rev. 5
50
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
3.13
Analog-to-digital converter (ADC) electrical characteristics
The device provides a 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter.
Offset Error OSE
Gain Error GE
1023
1022
1021
1020
1019
1 LSB ideal = VDD_ADC / 1024
1018
(2)
code out
7
(1)
6
(1) Example of an actual transfer curve
5
(5)
(2) The ideal transfer curve
(3) Differential non-linearity error (DNL)
4
(4) Integral non-linearity error (INL)
(4)
(5) Center of a step of the actual transfer curve
3
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
1017 1018 1019 1020 1021 1022 1023
Vin(A) (LSBideal)
Offset Error OSE
Figure 15. ADC characteristics and error definitions
3.13.1
Input impedance and ADC accuracy
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor
with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as
possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; further, it sources charge
during the sampling phase, when the analog signal source is a high-impedance source.
A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC
filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
51
be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal
(bandwidth) and the equivalent input impedance of the ADC itself.
In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: CS being
substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path
to ground. For instance, assuming a conversion rate of 1 MHz, with CS equal to 3 pF, a resistance of 330 kΩ is obtained (REQ
= 1 / (fc×CS), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage
partitioning between this resistance (sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit
must be designed to respect the Equation 4:
Eqn. 4
R S + R F + R L + R SW + R AD
V A • --------------------------------------------------------------------------- < 1
--- LSB
R EQ
2
Equation 4 generates a constraint for external network design, in particular on resistive path. Internal switch resistances (RSW
and RAD) can be neglected with respect to external resistances.
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
VDD
Source
RS
VA
Filter
RF
Current Limiter
RL
CF
Channel
Selection
Sampling
RSW1
RAD
CP1
CP2
RS Source Impedance
RF Filter Resistance
CF Filter Capacitance
Current Limiter Resistance
RL
RSW1 Channel Selection Switch Impedance
RAD Sampling Switch Impedance
CP Pin Capacitance (two contributions, CP1 and CP2)
CS Sampling Capacitance
Figure 16. Input equivalent circuit
A second aspect involving the capacitance network shall be considered. Assuming the three capacitances CF, CP1 and CP2 are
initially charged at the source voltage VA (refer to the equivalent circuit reported in Figure 16): A charge sharing phenomenon
is installed when the sampling phase is started (A/D switch close).
MPC5604P Microcontroller Data Sheet, Rev. 5
52
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Voltage Transient on CS
VCS
VA
VA2
ΔV < 0.5 LSB
1
2
τ1 < (RSW + RAD) CS << TS
τ2 = RL (CS + CP1 + CP2)
VA1
TS
t
Figure 17. Transient Behavior during Sampling Phase
In particular two different transient periods can be distinguished:
•
A first and quick charge transfer from the internal capacitance CP1 and CP2 to the sampling capacitance CS occurs (CS
is supposed initially completely discharged): considering a worst case (since the time constant in reality would be
faster) in which CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and CS are in series,
and the time constant is
CP • CS
τ 1 = ( R SW + R AD ) • --------------------CP + CS
Eqn. 5
Equation 5 can again be simplified considering only CS as an additional worst condition. In reality, the transient is
faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time TS
is always much longer than the internal time constant:
Eqn. 6
τ 1 < ( R SW + R AD ) • C S « T S
The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the voltage VA1 on the capacitance
according to Equation 7:
Eqn. 7
V A1 • ( C S + C P1 + C P2 ) = V A • ( C P1 + C P2 )
•
A second charge transfer involves also CF (that is typically bigger than the on-chip capacitance) through the resistance
RL: again considering the worst case in which CP2 and CS were in parallel to CP1 (since the time constant in reality
would be faster), the time constant is:
Eqn. 8
τ 2 < R L • ( C S + C P1 + C P2 )
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
53
In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed
well before the end of sampling time TS, a constraints on RL sizing is obtained:
Eqn. 9
10 • τ 2 = 10 • R L • ( C S + C P1 + C P2 ) < TS
Of course, RL shall be sized also according to the current limitation constraints, in combination with RS (source
impedance) and RF (filter resistance). Being CF definitively bigger than CP1, CP2 and CS, then the final voltage VA2
(at the end of the charge transfer transient) will be much higher than VA1. Equation 10 must be respected (charge
balance assuming now CS already charged at VA1):
Eqn. 10
VA2 • ( C S + C P1 + C P2 + C F ) = V A • C F + V A1 • ( C P1 + C P2 + C S )
The two transients above are not influenced by the voltage source that, due to the presence of the RFCF filter, is not able to
provide the extra charge to compensate the voltage drop on CS with respect to the ideal source VA; the time constant RFCF of
the filter is very high with respect to the sampling time (TS). The filter is typically designed to act as anti-aliasing.
Analog Source Bandwidth (VA)
TC ≤ 2 RFCF (Conversion Rate vs. Filter Pole)
fF = f0 (Anti-aliasing Filtering Condition)
Noise
2 f0 ≤ fC (Nyquist)
f0
f
Anti-Aliasing Filter (fF = RC Filter pole)
fF
f
Sampled Signal Spectrum (fC = conversion Rate)
f0
fC
f
Figure 18. Spectral representation of input signal
Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, fF),
according to the Nyquist theorem the conversion rate fC must be at least 2f0; it means that the constant time of the filter is greater
than or at least equal to twice the conversion period (TC). Again the conversion period TC is longer than the sampling time TS,
which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a
specific channel): in conclusion it is evident that the time constant of the filter RFCF is definitively much higher than the
sampling time TS, so the charge level on CS cannot be modified by the analog signal source during the time in which the
sampling switch is closed.
The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage
drop on CS; from the two charge balance equations above, it is simple to derive Equation 11 between the ideal and real sampled
voltage on CS:
MPC5604P Microcontroller Data Sheet, Rev. 5
54
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Eqn. 11
VA
C P1 + C P2 + C F
------------ = -------------------------------------------------------V A2
C P1 + C P2 + C F + C S
From this formula, in the worst case (when VA is maximum, that is for instance 5 V), assuming to accept a maximum error of
half a count, a constraint is evident on CF value:
Eqn. 12
C F > 2048 • C S
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
55
3.13.2
ADC conversion characteristics
Table 29. ADC conversion characteristics
Symbol
fCK
fs
tADC_S
Parameter
Value
Conditions1
Unit
Min
Typ
Max
SR ADC Clock frequency
(depends on ADC
configuration)
(The duty cycle depends on
AD_clk2 frequency)
—
33
—
60
MHz
SR Sampling frequency
—
—
—
1.53
MHz
D Sample time4
fADC = 20 MHz,
INPSAMP = 3
125
ns
fADC = 9 MHz,
INPSAMP = 255
tADC_C
P Conversion time5
fADC = 20 MHz6,
INPCMP = 1
28.2
µs
0.650
—
—
µs
CS7
D ADC input sampling
capacitance
—
—
—
2.5
pF
CP17
D ADC input pin capacitance 1
—
—
—
3
pF
7
D ADC input pin capacitance 2
—
—
—
1
pF
D Internal resistance of analog
source
VDD_HV_ADC = 5 V+/-10%
—
—
0.6
kΩ
VDD_HV_ADC = 3.3 V+/-10%
—
—
3
kΩ
—
—
—
2
kΩ
-5
—
5
mA
CP2
RSW1
7
RAD7
D Internal resistance of analog
source
IINJ
T Input current injection
Current injection on one ADC input,
different from the converted one.
Remains within TUE spec.
INL
P Integral Non Linearity
No overload
–1.5
—
1.5
LSB
DNL
P Differential Non Linearity
No overload
–1.0
—
1.0
LSB
OFS
T Offset error
—
—
±1
—
LSB
GNE
T Gain error
—
—
±1
—
LSB
TUE
P Total unadjusted error
without current injection
—
-2.5
—
2.5
LSB
TUE
T Total unadjusted error with
current injection
—
-3
—
3
LSB
1
VDD = 3.3 V to 3.6 V / 4.5 V to 5.5 V, TA = –40 to +125 °C, unless otherwise specified and analog input voltage from
VSS_HV_ADCx to VDD_HV_ADCx.
2
AD_clk clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.
3 When configured to allow 60 MHz ADC, the minimum ADC clock speed is 9 MHz, below which precision is lost.
4 During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC_S. After the
end of the sample time tADC_S, changes of the analog input voltage have no effect on the conversion result. Values
for the sample clock tADC_S depend on programming.
MPC5604P Microcontroller Data Sheet, Rev. 5
56
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
5
This parameter includes the sample time tADC_S.
20 MHz ADC clock. Specific prescaler is programmed on MC_PLL_CLK to provide 20 MHz clock to the ADC.
7
See Figure 16.
6
3.14
Flash memory electrical characteristics
Table 30. Program and erase specifications
Min Value
Typical
Value1
Initial
Max2
Max3
Unit
P Double Word (64 bits) Program Time4
—
22
50
500
μs
P Bank Program (512KB)4, 5
—
1.45
1.65
33
s
P Bank Program (64KB)
—
0.18
0.21
4.10
s
T16kpperase
P 16 KB Block Pre-program and Erase Time
—
300
500
5000
ms
T32kpperase
P 32 KB Block Pre-program and Erase Time
—
400
600
5000
ms
T128kpperase
P 128 KB Block Pre-program and Erase Time
—
800
1300
7500
ms
Symbol
Tdwprogram
TBKPRG
Parameter
4, 5
1
2
3
4
5
Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to
change pending device characterization.
Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
The maximum program & erase times occur after the specified number of program/erase cycles. These maximum
values are characterized but not guaranteed.
Actual hardware programming times. This does not include software overhead.
Typical Bank programming time assumes that all cells are programmed in a single pulse. In reality some cells will
require more than one pulse, adding a small overhead to total bank programming time (see Initial Max column).
Table 31. Flash module life1
Value
Symbol
Conditions
Unit
Min
Typ
—
P/E
C Number of program/erase cycles per block
for 16 Kbyte blocks over the operating
temperature range (TJ)
—
100,000
P/E
C Number of program/erase cycles per block
for 32 Kbyte blocks over the operating
temperature range (TJ)
—
10,000
100,000 cycles
(TBC)
P/E
C Number of program/erase cycles per block
for 128 Kbyte blocks over the operating
temperature range (TJ)
—
1,000
100,000 cycles
(TBC)
Blocks with 0 – 1,000
P/E cycles
20
—
years
Blocks with 10,000 P/E
cycles
10
—
years
Blocks with 100,000 P/E
cycles
5
—
years
Retention
1
Parameter
C Minimum data retention at 85 °C average
ambient temperature2
cycles
TBD: To be defined
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
57
2
Ambient temperature averaged over duration of application, not to exceed recommended product operating
temperature range.
Table 32. Flash read access timing
Symbol
Fmax
1
3.15
C
Parameter
C Maximum working frequency at given number
of WS in worst conditions
Conditions1
Max
Unit
2 wait states
66
MHz
0 wait states
18
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 to 125 °C, unless otherwise specified
AC Specifications
3.15.1
Pad AC Specifications
Table 33. Output pin transition times
Symbol
C
Ttr CC D Output transition time output pin3
SLOW configuration
T
Typ
Max
—
—
50
—
—
100
—
—
125
—
—
40
—
—
50
—
—
75
—
—
10
—
—
20
—
—
40
—
—
12
—
—
25
—
—
40
—
—
4
—
—
6
—
—
12
—
—
4
—
—
7
CL = 100 pF
—
—
12
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
4
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
5
CL = 25 pF
CL = 50 pF
CL = 100 pF
D
CL = 25 pF
T
CL = 50 pF
VDD = 5.0 V ± 10%,
PAD3V5V = 0
VDD = 3.3 V ± 10%,
PAD3V5V = 1
CL = 100 pF
D
pin3
CL = 25 pF
CL = 50 pF
D
CL = 100 pF
D
CL = 25 pF
T
CL = 50 pF
VDD = 5.0 V ± 10%,
PAD3V5V = 0
SIUL.PCRx.SRC = 1
VDD = 3.3 V ± 10%,
PAD3V5V = 1
SIUL.PCRx.SRC = 1
CL = 100 pF
D
Ttr CC D Output transition time output
FAST configuration
pin3
CL = 25 pF
CL = 50 pF
VDD = 5.0 V ± 10%,
PAD3V5V = 0
SIUL.PCRx.SRC = 1
CL = 100 pF
CL = 25 pF
CL = 50 pF
Tsim CC T Symmetric, same drive strength
between N and P transistor
1
Unit
Min
D
Ttr CC D Output transition time output
MEDIUM configuration
T
Value2
Conditions1
Parameter
VDD = 3.3 V ± 10%,
PAD3V5V = 1
SIUL.PCRx.SRC = 1
ns
ns
ns
ns
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
MPC5604P Microcontroller Data Sheet, Rev. 5
58
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
2
3
All values need to be confirmed during device validation.
CL includes device and package capacitances (CPKG < 5 pF).
3.16
3.16.1
AC Timing Characteristics
RESET Pin Characteristics
The MPC5604P implements a dedicated bidirectional RESET pin.
VDD
VDDMIN
VRESET
VIH
VIL
device reset forced by VRESET
device start-up phase
TPOR
Figure 19. Start-up reset requirements
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
59
VRESET
hw_rst
VDD
‘1’
VIH
VIL
‘0’
filtered by
hysteresis
filtered by
lowpass filter
WFRST
filtered by
lowpass filter
unknown reset
state
device under hardware reset
WFRST
WNFRST
Figure 20. Noise filtering on reset signal
Table 34. RESET electrical characteristics
Symbol
C
Parameter
Value2
Conditions1
Unit
Min
Typ
Max
VIH
SR P Input High Level CMOS
(Schmitt Trigger)
—
0.65VDD
—
VDD+0.4
V
VIL
SR P Input low Level CMOS
(Schmitt Trigger)
—
−0.4
—
0.35VDD
V
VHYS
CC C Input hysteresis CMOS
(Schmitt Trigger)
—
0.1VDD
—
—
V
VOL
CC P Output low level
Push Pull, IOL = 2mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
—
—
0.1VDD
V
Push Pull, IOL = 1mA,
VDD = 5.0 V ± 10%, PAD3V5V = 13
—
—
0.1VDD
Push Pull, IOL = 1mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
—
—
0.5
MPC5604P Microcontroller Data Sheet, Rev. 5
60
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Table 34. RESET electrical characteristics (continued)
Symbol
C
Value2
1
Parameter
Conditions
Unit
Min
Typ
Max
CL = 25pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
10
CL = 50pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
20
CL = 100pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
40
CL = 25pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
12
CL = 50pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
25
CL = 100pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
40
WFRST SR P RESET input filtered
pulse
—
—
—
40
ns
WNFRST SR P RESET input not filtered
pulse
—
500
—
—
ns
—
—
1
ms
VDD = 3.3 V ± 10%, PAD3V5V = 1
10
—
150
µA
VDD = 5.0 V ± 10%, PAD3V5V = 0
10
—
150
10
—
250
Ttr
CC D Output transition time
output pin4
MEDIUM configuration
TPOR
CC D maximum delay before
monotonic VDD_HV supply ramp
internal reset is released
after all VDD_HV reach
nominal supply
|IWPU| CC P Weak pull-up current
absolute value
VDD = 5.0 V ± 10%, PAD3V5V =
15
ns
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
All values need to be confirmed during device validation.
3 This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of
device reference manual).
4 C includes device and package capacitance (C
L
PKG < 5 pF).
5
The configuration PAD3V5 = 1 when VDD = 5 V is only transient configuration during power-up. All pads but RESET
and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
1
2
3.16.2
IEEE 1149.1 interface timing
Table 35. JTAG pin AC electrical characteristics
No.
Symbol
C
Parameter
Conditions Min Max Unit
1
tJCYC
CC
D TCK cycle time
—
100
—
ns
2
tJDC
CC
D TCK clock pulse width (measured at VDD_HV_IOx/2)
—
40
60
ns
3
tTCKRISE
CC
D TCK rise and fall times (40% - 70%)
—
—
3
ns
D TMS, TDI data setup time
—
5
—
ns
4
tTMSS, tTDIS CC
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
61
Table 35. JTAG pin AC electrical characteristics (continued)
No.
Symbol
C
5 tTMSH, tTDIH CC
Parameter
Conditions Min Max Unit
D TMS, TDI data hold time
—
25
—
ns
6
tTDOV
CC
D TCK low to TDO data valid
—
—
40
ns
7
tTDOI
CC
D TCK low to TDO data invalid
—
0
—
ns
8
tTDOHZ
CC
D TCK low to TDO high impedance
—
40
—
ns
11
tBSDV
CC
D TCK falling edge to output valid
—
—
50
ns
12
tBSDVZ
CC
D TCK falling edge to output valid out of high impedance
—
—
50
ns
13
tBSDHZ
CC
D TCK falling edge to output high impedance
—
—
50
ns
14
tBSDST
CC
D Boundary scan input valid to TCK rising edge
—
50
—
ns
15
tBSDHT
CC
D TCK rising edge to boundary scan input invalid
—
50
—
ns
TCK
2
3
2
1
3
Figure 21. JTAG test clock input timing
MPC5604P Microcontroller Data Sheet, Rev. 5
62
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
TCK
4
5
TMS, TDI
6
7
8
TDO
Figure 22. JTAG test access port timing
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
63
TCK
11
13
Output
Signals
12
Output
Signals
14
15
Input
Signals
Figure 23. JTAG boundary scan timing
3.16.3
Nexus timing
Table 36. Nexus debug port timing1
Value
No.
1
Symbol
tMCYC
C
Parameter
CC D MCKO cycle time
valid2
Unit
Min
Typ
Max
32
—
—
ns
—
—
6
ns
2
tMDOV
CC D MCKO low to MDO data
3
tMSEOV
CC D MCKO low to MSEO data valid2
—
—
6
ns
4
tEVTOV
CC D MCKO low to EVTO data valid2
—
—
6
ns
CC D TCK cycle time
643
—
—
ns
5
tTCYC
MPC5604P Microcontroller Data Sheet, Rev. 5
64
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Table 36. Nexus debug port timing1 (continued)
Value
No.
6
7
Symbol
C
Parameter
Unit
Min
Typ
Max
tNTDIS
CC D TDI data setup time
6
—
—
ns
tNTMSS
CC D TMS data setup time
6
—
—
ns
tNTDIH
CC D TDI data hold time
10
—
—
ns
tNTMSH
CC D TMS data hold time
10
—
—
ns
8
tTDOV
CC D TCK low to TDO data valid
—
—
35
ns
9
tTDOI
CC D TCK low to TDO data invalid
6
—
—
ns
1
All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal.
MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
3 Lower frequency is required to be fully compliant to standard.
2
1
MCKO
2
3
4
MDO
MSEO
EVTO
Output Data Valid
Figure 24. Nexus output timing
TCK
EVTI
EVTO
5
Figure 25. Nexus event trigger and test clock timings
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
65
TCK
6
7
TMS, TDI
9
8
TDO
Figure 26. Nexus TDI, TMS, TDO timing
3.16.4
External interrupt timing (IRQ pin)
Table 37. External interrupt timing1
No.
Symbol
C
Parameter
Conditions
Min
1
tIPWL
CC
D
IRQ pulse width low
—
4
2
tIPWH
CC
D
IRQ pulse width high
—
4
3
tICYC
CC
D
IRQ edge to edge
time2
—
4+N
Max Unit
3
—
tCYC
—
tCYC
—
tCYC
1
IRQ timing specified at fSYS = 64 MHz and VDD_HV_IOx = 3.0 V to 5.5 V, TA = TL to TH, and CL = 200pF with SRC = 0b00.
Applies when IRQ pins are configured for rising edge or falling edge events, but not both.
3 N= ISR time to clear the flag
2
MPC5604P Microcontroller Data Sheet, Rev. 5
66
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
IRQ
1
2
3
Figure 27. External interrupt timing
3.16.5
DSPI timing
Table 38. DSPI timing
No.
Symbol
CC
1
C
D
Parameter
DSPI cycle time
tSCK
Conditions
Min
Max
Master (MTFE = 0)
60
—
Slave (MTFE = 0)
60
—
Unit
ns
2
tCSC
CC
D
CS to SCK delay
—
16
—
ns
3
tASC
CC
D
After SCK delay
—
26
—
ns
4
tSDC
CC
D
SCK duty cycle
—
5
tA
CC
D
Slave access time
SS active to SOUT valid
—
TBD
ns
6
tDIS
CC
D
Slave SOUT disable time
SS inactive to SOUT High-Z or invalid
—
16
ns
7
tPCSC CC
D
PCSx to PCSS time
—
13
—
ns
8
tPASC CC
D
PCSS to PCSx time
—
13
—
ns
Master (MTFE = 0)
35
—
Slave
4
—
Master (MTFE = 1, CPHA = 0)
35
—
Master (MTFE = 1, CPHA = 1)
35
—
Master (MTFE = 0)
-5
—
Slave
4
—
Master (MTFE = 1, CPHA = 0)
11
—
Master (MTFE = 1, CPHA = 1)
-5
—
CC
9
Data setup time for inputs
D
tSUI
CC
10
tHI
0.4 * tSCK 0.6 * tSCK
ns
ns
Data hold time for inputs
D
ns
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
67
Table 38. DSPI timing (continued)
No.
Symbol
C
Parameter
Conditions
Data valid (after SCK edge)
11
tSUO
CC
tHO
CC
Max
Master (MTFE = 0)
—
12
Slave
—
36
Master (MTFE = 1, CPHA = 0)
—
12
Master (MTFE = 1, CPHA = 1)
—
12
Master (MTFE = 0)
-2
—
Slave
6
—
Master (MTFE = 1, CPHA = 0)
6
—
Master (MTFE = 1, CPHA = 1)
-2
—
D
Unit
ns
Data hold time for outputs
12
Min
D
ns
2
3
PCSx
1
4
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
9
SIN
10
First Data
Data
12
SOUT
First Data
Last Data
11
Data
Last Data
Figure 28. DSPI classic SPI timing - master, CPHA = 0
MPC5604P Microcontroller Data Sheet, Rev. 5
68
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
PCSx
SCK Output
(CPOL=0)
10
SCK Output
(CPOL=1)
9
Data
First Data
SIN
Last Data
12
SOUT
11
Data
First Data
Last Data
Figure 29. DSPI classic SPI timing - master, CPHA = 1
3
2
SS
1
4
SCK Input
(CPOL=0)
4
SCK Input
(CPOL=1)
5
SOUT
First Data
9
SIN
12
11
Data
Last Data
Data
Last Data
6
10
First Data
Figure 30. DSPI classic SPI timing - slave, CPHA = 0
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
69
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
SOUT
First Data
9
SIN
Data
Last Data
Data
Last Data
10
First Data
Figure 31. DSPI classic SPI timing - slave, CPHA = 1
3
PCSx
4
1
2
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
9
SIN
First Data
10
12
SOUT
First Data
Last Data
Data
11
Data
Last Data
Figure 32. DSPI modified transfer format timing - master, CPHA = 0
MPC5604P Microcontroller Data Sheet, Rev. 5
70
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
PCSx
SCK Output
(CPOL=0)
SCK Output
(CPOL=1)
10
9
SIN
First Data
Last Data
Data
12
First Data
SOUT
11
Last Data
Data
Figure 33. DSPI modified transfer format timing - master, CPHA = 1
3
2
SS
1
SCK Input
(CPOL=0)
4
4
SCK Input
(CPOL=1)
SOUT
First Data
Data
First Data
6
Last Data
10
9
SIN
12
11
5
Data
Last Data
Figure 34. DSPI modified transfer format timing - slave, CPHA = 0
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
71
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
First Data
SOUT
9
Last Data
Data
Last Data
10
First Data
SIN
Data
Figure 35. DSPI modified transfer format timing - slave, CPHA = 1
7
8
PCSS
PCSx
Figure 36. DSPI PCS strobe (PCSS) timing
MPC5604P Microcontroller Data Sheet, Rev. 5
72
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
4
Package characteristics
4.1
Package mechanical data
4.1.1
144 LQFP mechanical outline drawing
L
Figure 37. 144 LQFP package mechanical drawing (part 1)
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
73
Figure 38. 144 LQFP package mechanical drawing (part 2)
MPC5604P Microcontroller Data Sheet, Rev. 5
74
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
4.1.2
100 LQFP Mechanical Outline Drawing
Figure 39. 100 LQFP package mechanical drawing (part 1)
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
75
Figure 40. 100 LQFP package mechanical drawing (part 2)
MPC5604P Microcontroller Data Sheet, Rev. 5
76
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Figure 41. 100 LQFP package mechanical drawing (part 3)
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
77
5
Ordering Information
Table 39 shows the orderable part numbers for the MPC5604P series.
Table 39. Orderable Part Number Summary
Part Number
Code Flash /
Data Flash (EE)
(KB)
SRAM (KB)
Package
Characteristics
MPC5604PEFMLQ
512 / 64
40
144 LQFP
FlexRay
MPC5604PEFMLL
512 / 64
40
100 LQFP
FlexRay
MPC5603PEFMLQ
384 / 64
36
144 LQFP
FlexRay
MPC5603PEFMLL
384 / 64
36
100 LQFP
FlexRay
Commercial product code structure
Example code:
M
PC
56
0
4
P
G
F0
M
LQ
7
R
Qualification Status
PowerPC Core
Automotive Platform
Core Version
Flash Size (core dependent)
Product
Optional Fields
Fab & Mask Revision
Temperature spec.
Package Code
Frequency
R = Tape & Reel (blank if Tray)
Qualification Status
Flash Size (z0 core)
Temperature spec.
M = MC status
S = Automotive qualified
P = PC status
3 = 384 KB
4 = 512 KB
V = –40°C to 105°C
M = –40°C to 125°C
Product
Package Code
Automotive Platform
P = Pictus
LL = 100 LQFP
LQ = 144 LQFP
56 = PPC in 90nm
Optional fields
Core Version
E = Data Flash (blank if none)
0 = e200z0
F = FlexRay
Frequency
7= 64 MHz
MPC5604P Microcontroller Data Sheet, Rev. 5
78
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
6
Document revision history
Table 40 summarizes revisions to this document.
Table 40. Revision history
Revision
Date
Substantive changes
Rev. 1
8/2008
Initial release
Rev. 2
11/2008
Table 4:
TDO and TDI pins (Port pins B[4:5] are single function pins.
Table 8, Table 9:
Thermal characteristics added.
Table 11, Table 12:
EMI testing specifications split into separate tables for Normal mode and Airbag mode;
data to be added in a later revision.
Table 16, Table 17, Table 19, Table 20:
Supply current specifications split into separate tables for Normal mode and Airbag mode;
data to be added in a later revision.
Table 19:
•
•
•
•
Values for IOL and IOH (in Conditions column) changed.
Max values for VOH_S, VOH_M, VOH_F and VOH_SYM deleted.
VILR max value changed.
IPUR min and max values changed.
Table 23:
Sensitivity value changed.
Table 30:
Most values in table changed.
Rev. 3
2/2009
•
•
•
•
•
•
Description of system requirements, controller characteristics and how
controller characteristics are guaranteed updated.
Electrical parameters updated.
EMI characteristics are now in one table; values have been updated.
ESD characteristics are now in one table.
Electrical parameters are identified as either system requirements or controller
characteristics. Method used to guarantee each controller characteristic is noted
in table.
AC Timings: 1149.1 (JTAG) Timing, Nexus Timing, External Interrupt Timing,
and DSPI Timing sections deleted
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
79
Table 40. Revision history (continued)
Revision
Date
Substantive changes
Rev. 4
24/6/2009
Through all document:
– Replaced all “RESET_B” occurrences with “RESET” through all document.
– AC Timings: 1149.1 (JTAG) Timing, Nexus Timing, External Interrupt Timing, and
DSPI Timing sections inserted again.
– Electrical parameters updated.
Section 1, “Overview:
– Minor editorial clean-up.
– Specified LIN 2.1 in communications interfaces feature.
Table 2
– Added row for Data Flash.
Table 2
– Added a footnote regarding the decoupling capacitors.
Table 4
– Removed the “other function“ column.
– Rearranged the contents.
Table 12
– Updated definition of Condition column.
Table 18
– merged in an unique Table the power consumption data related to "Maximum
mode" and "Airbag mode".
Table 20
– merged in an unique Table the power consumption data related to "Maximum
mode" and "Airbag mode".
Table 28
– Updated the parameter definition of ΔRCMVAR.
– Removed the condition definition of ΔRCMVAR.
Table 28
– Added tADC_C and TUE rows.
Table 29
– Added tADC_C and TUE rows.
– Removed Rsw2.
Table 32
– Added.
Table 29
– Updated and added footnotes.
Section 3.16.1, “RESET Pin Characteristics
– Replaces whole section.
Table 38
– Renamed the “Flash (KB)“ heading column in “Code Flash / Data Flash (EE) (KB)“
– Replaced the value of RAM from 32 to 36KB in the last four rows.
MPC5604P Microcontroller Data Sheet, Rev. 5
80
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Table 40. Revision history (continued)
Revision
Date
Substantive changes
Rev. 5
06/10/2009
- Removed B[4] and B[5] rows from “Pin muxing” table and inserted them on “System
pins” table.
- Updated package pinout.
- Rewrote entirely section “Power Up/dpwn Sequencing“ section.
- Renamend “VDD_LV_PLL“ and “VSS_LV_PLL“ supply pins with respectively “VDD_LV_COR3“
and “VSS_LV_COR3”.
- Added explicative figures on “Electrical characteristics” section.
- Updated “Thermal characteristics“ for 100-pin.
- Proposed two different configuration of “voltage regulator.
- Inserted Power Up/Down sequence.
- Added explicative figures on “DC Electrical characteristics”.
- Added “I/O pad current specification” section.
- Renamed the “Airbag mode” with “Typical mode“and updated the values on “supply
current” tables.
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
81
MPC5604P Microcontroller Data Sheet, Rev. 5
82
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
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Document Number: MPC5604P
Rev. 5
November 2009
MPC5604P Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
83
MPC5604P Microcontroller Data Sheet, Rev. 5
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