SL74HC273 Octal D Flip-Flop with Common Clock and Reset High-Performance Silicon-Gate CMOS The SL74HC273 is identical in pinout to the LS/ALS273. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device consists of eight D flip-flops with common Clock and Reset inputs. Each flip-flop is loaded with a low-to-high transition of the Clock input. Reset is asynchronous and active low. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 µA • High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION SL74HC273N Plastic SL74HC273D SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE PIN 20=VCC PIN 10 = GND Inputs Reset Clock D Q L X X L H H H H L L X no change X no change H L H X = don’t care SLS System Logic Semiconductor Output SL74HC273 MAXIMUM RATINGS * Symbol Parameter Value Unit -0.5 to +7.0 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Input Current, per Pin ±20 mA DC Output Current, per Pin ±35 mA ICC DC Supply Current, VCC and GND Pins ±75 mA PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW -65 to +150 °C 260 °C VOUT IIN IOUT Tstg TL Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, t f Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min Max Unit 2.0 6.0 V 0 VCC V -55 +125 °C 0 0 0 1000 500 400 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. SLS System Logic Semiconductor SL74HC273 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Guaranteed Limit Test Conditions V 25 °C to -55°C ≤85 °C ≤125 °C Unit Minimum High-Level Input Voltage VOUT=0.1 V or VCC-0.1 V IOUT≤ 20 µA 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V VIL Maximum Low -Level Input Voltage VOUT=0.1 V or VCC-0.1 V IOUT ≤ 20 µA 2.0 4.5 6.0 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 V VOH Minimum High-Level Output Voltage VIN=VIH or VIL IOUT ≤ 20 µA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 VIN= VIL or VIH IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 Symbol Parameter VIH VIN=VIH or VIL IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA VOL Maximum Low-Level Output Voltage VIN= VIL or VIH IOUT ≤ 20 µA V IIN Maximum Input Leakage Current VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA ICC Maximum Quiescent Supply Current (per Package) VIN=VCC or GND IOUT=0µA 6.0 4.0 40 160 µA SLS System Logic Semiconductor SL74HC273 AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input t r=t f=6.0 ns) VCC Guaranteed Limit V 25 °C to -55°C ≤85°C ≤125°C Unit Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) 2.0 4.5 6.0 6.0 30 35 5.0 24 28 4.0 20 24 MHz tPLH, t PHL Maximum Propagation Delay, Clock to Q (Figures 1 and 4) 2.0 4.5 6.0 145 29 25 180 36 31 220 44 38 ns tPHL Maximum Propagation Delay , Reset to Q (Figures 2 and 4) 2.0 4.5 6.0 145 29 25 180 36 31 220 44 38 ns Maximum Output Transition Time, Any Output (Figures 1 and 4) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns - 10 10 10 pF Symbol fmax tTLH, t THL CIN Parameter Maximum Input Capacitance Power Dissipation Capacitance (Per Enabled Output) CPD Typical @25°C,VCC=5.0 V Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC 48 pF TIMING REQUIREMENTS (CL=50pF,Input t r=t f=6.0 ns) VCC Guaranteed Limit Symbol Parameter V 25 °C to-55°C ≤85°C ≤125°C Unit tSU Minimum Setup Time, Data to Clock (Figure 3) 2.0 4.5 6.0 60 12 10 75 15 13 90 18 15 ns th Minimum Hold Time, Clock to Data (Figure 3) 2.0 4.5 6.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 ns trec Minimum Recovery Time, Reset Inactive to Clock (Figure 2) 2.0 4.5 6.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 ns tw Minimum Pulse Width, Clock (Figure 1) 2.0 4.5 6.0 60 12 10 75 15 13 90 18 15 ns tw Minimum Pulse Width, Reset (Figure 2) 2.0 4.5 6.0 60 12 10 75 15 13 90 18 15 ns tr, tf Maximum Input Rise and Fall Times (Figure 1) 2.0 4.5 6.0 1000 500 400 1000 500 400 1000 500 400 ns SLS System Logic Semiconductor SL74HC273 Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Test Circuit EXPANDED LOGIC DIAGRAM SLS System Logic Semiconductor