LMC6762 www.ti.com SNOS739D – JULY 1997 – REVISED MARCH 2013 LMC6762 Dual MicroPower Rail-To-Rail Input CMOS Comparator with Push-Pull Output Check for Samples: LMC6762 FEATURES DESCRIPTION • • The LMC6762 is an ultra low power dual comparator with a maximum supply current of 10 μA/comparator. It is designed to operate over a wide range of supply voltages, from 2.7V to 15V. The LMC6762 has ensured specifications at 2.7V to meet the demands of 3V digital systems. 1 2 • • • • • (Typical Unless Otherwise Noted) Low Power Consumption (Max): IS = 10 μA/comp Wide Range of Supply Voltages: 2.7V to 15V Rail-To-Rail Input Common Mode Voltage Range Rail-To-Rail Output Swing (Within 100 mV of the Supplies, @ V+ = 2.7V, and ILOAD = 2.5 mA) Short Circuit Protection: 40 mA Propagation Delay (@ V+ = 5V, 100 mV Overdrive): 4 μs APPLICATIONS • • • • • • • Laptop Computers Mobile Phones Metering Systems Hand-Held Electronics RC Timers Alarm and Monitoring Circuits Window Comparators, Multivibrators Connection Diagram The LMC6762 has an input common-mode voltage range which exceeds both supplies. This is a significant advantage in low-voltage applications. The LMC6762 also features a push-pull output that allows direct connections to logic devices without a pull-up resistor. A quiescent power consumption of 50 μW/amplifier (@ V+ = 5V) makes the LMC6762 ideal for applications in portable phones and hand-held electronics. The ultra-low supply current is also independent of power supply voltage. Ensured operation at 2.7V and a rail-to-rail performance makes this device ideal for battery-powered applications. Refer to the LMC6772 datasheet for an open-drain version of this device. Typical Application 8-Pin PDIP/SOIC Top View Zero Crossing Detector These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1997–2013, Texas Instruments Incorporated LMC6762 SNOS739D – JULY 1997 – REVISED MARCH 2013 www.ti.com Absolute Maximum Ratings (1) (2) ESD Tolerance (3) 2 KV Differential Input Voltage (V+)+0.3V to (V−)−0.3V Voltage at Input/Output Pin (V+)+0.3V to (V−)−0.3V Supply Voltage (V+–V−) 16V Current at Input Pin ±5 mA Current at Output Pin (4) (5) ±30 mA Current at Power Supply Pin, LMC6762 40 mA Lead Temperature (Soldering, 10 seconds) 260°C −65°C to +150°C Storage Temperature Range Junction Temperature (6) (1) (2) (3) (4) (5) (6) 150°C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the electrical characteristics. If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. Human body model, 1.5 kΩ in series with 100 pF. Do not short circuit output to V+, when V+ is greater than 12V or reliability will be adversely affected. Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30 mA over long term may adversely affect reliability. The maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(max) – TA)/θJA.All numbers apply for packages soldered directly into a PC board. Operating Ratings (1) 2.7 ≤ VS ≤ 15V Supply Voltage −40°C ≤ TJ ≤ +85°C Junction Temperature Range LMC6762AI, LMC6762BI Thermal Resistance (θJA) P0008E Package, 8-Pin PDIP 100°C/W D0008A Package, 8-Pin SOIC 172°C/W (1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the electrical characteristics. 2.7V Electrical Characteristics Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 2.7V, V− = 0V, VCM = V+/2. Boldface limits apply at the temperature extremes. Symbol VOS Parameter Conditions Input Offset Voltage TCVOS Typ (1) 3 Input Offset Voltage LMC6762AI Limit (2) LMC6762BI Units Limit (2) 5 15 mV 8 18 max 2.0 μV/°C 3.3 μV/Month Temperature Drift Input Offset Voltage See (3) Average Drift IB Input Current 0.02 pA IOS Input Offset Current 0.01 pA CMRR Common Mode Rejection Ratio 75 dB PSRR Power Supply Rejection Ratio ±1.35V < VS < ±7.5V 80 dB AV Voltage Gain (By Design) 100 dB (1) (2) (3) 2 Typical Values represent the most likely parametric norm. All limits are specified by testing or statistical analysis. Input Offset Voltage Average Drift is calculated by dividing the accelerated operating life drift average by the equivalent operational time. The Input Offset Voltage Average Drift represents the input offset voltage change at worst-case input conditions. Submit Documentation Feedback Copyright © 1997–2013, Texas Instruments Incorporated Product Folder Links: LMC6762 LMC6762 www.ti.com SNOS739D – JULY 1997 – REVISED MARCH 2013 2.7V Electrical Characteristics (continued) Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 2.7V, V− = 0V, VCM = V+/2. Boldface limits apply at the temperature extremes. Symbol VCM Parameter Input Common-Mode Conditions CMRR > 55 dB Typ (1) LMC6762AI Limit (2) 3.0 VOH Output Voltage High ILOAD = 2.5 mA 2.9 V 2.7 2.7 min −0.2 −0.2 V 0.0 0.0 max 2.4 2.4 V 2.3 2.3 min 0.3 0.3 V 0.4 0.4 max 20 20 μA 25 25 max 2.5 VOL Output Voltage Low ILOAD = 2.5 mA 0.2 IS Supply Current For Both Comparators 12 Units Limit (2) 2.9 Voltage Range −0.3 LMC6762BI (Output Low) 5.0V and 15.0V Electrical Characteristics Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 5.0V and 15.0V, V− = 0V, VCM = V+/2. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Typ (1) VOS Input Offset Voltage 3 TCVOS Input Offset Voltage V+ = 5V 2.0 Temperature Drift V+ = 15V 4.0 Input Offset Voltage V+ = 5V (3) + (3) LMC6762AI Limit (2) LMC6762BI Limit (1) 5 15 8 18 Units mV max μV/°C μV/Month 3.3 Average Drift V = 15V IB Input Current V = 5V 0.04 pA IOS Input Offset Current V+ = 5V 0.02 pA CMRR + 4.0 Common Mode V = 5V 75 dB Rejection Ratio V+ = 15V 82 dB PSRR Power Supply Rejection Ratio ±2.5V < VS < ±5V 80 dB AV Voltage Gain (By Design) 100 VCM Input Common-Mode V+ = 5.0V 5.3 Voltage Range CMRR > 55 dB V+ = 15.0V 5.2 V 5.0 5.0 min −0.3 −0.2 −0.2 V 0.0 0.0 max 15.3 15.2 15.2 V 15.0 15.0 min −0.2 −0.2 V 0.0 0.0 max 4.6 4.6 V 4.45 4.45 min 14.6 14.6 V 14.45 14.45 min CMRR > 55 dB −0.3 VOH Output Voltage High V+ = 5V 4.8 ILOAD = 5mA V+ = 15V 14.8 ILOAD = 5 mA (1) (2) (3) dB 5.2 Typical Values represent the most likely parametric norm. All limits are specified by testing or statistical analysis. Input Offset Voltage Average Drift is calculated by dividing the accelerated operating life drift average by the equivalent operational time. The Input Offset Voltage Average Drift represents the input offset voltage change at worst-case input conditions. Submit Documentation Feedback Copyright © 1997–2013, Texas Instruments Incorporated Product Folder Links: LMC6762 3 LMC6762 SNOS739D – JULY 1997 – REVISED MARCH 2013 www.ti.com 5.0V and 15.0V Electrical Characteristics (continued) Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 5.0V and 15.0V, V− = 0V, VCM = V+/2. Boldface limits apply at the temperature extremes. Symbol VOL Parameter Conditions V+ = 5V Output Voltage Low LMC6762AI Typ (1) 0.2 ILOAD = 5 mA V+ = 15V 0.2 ILOAD = 5 mA IS Supply Current For Both Comparators 12 (Output Low) ISC Short Circuit Current Sourcing (4) Units Limit (1) 0.4 0.4 V 0.55 0.55 max 0.4 0.4 V 0.55 0.55 max 20 20 μA 25 25 max 30 Sinking, VO = 12V + LMC6762BI Limit (2) (4) mA 45 + Do not short circuit output to V , when V is greater than 12V or reliability will be adversely affected. AC Electrical Characteristics Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 5V, V− = 0V, VCM = VO = V+/2. Boldface limits apply at the temperature extreme. Symbol Parameter Conditions Typ (1) LMC6762AI Limit tRISE Rise Time f = 10 kHz, CL = 50 pF, (2) LMC6762BI Limit Units (2) 0.3 μs 0.3 μs Overdrive = 10 mV (3) (4) tFALL Fall Time f = 10 kHz, CL = 50 pF, Overdrive = 10 mV tPHL (3) (4) Propagation Delay f = 10 kHz, Overdrive = 10 mV 10 μs (High to Low) CL = 50 pF (3) (4) Overdrive = 100 mV 4 μs Overdrive = 10 mV 10 μs CL = 50 pF (3) (4) Overdrive = 100 mV 4 μs Propagation Delay f = 10 kHz, Overdrive = 10 mV 6 μs (Low to High) CL = 50 pF (3) (4) Overdrive = 100 mV 4 μs V+ = 2.7V, Overdrive = 10 mV 7 μs Overdrive = 100 mV 4 μs + V = 2.7V, f = 10 kHz, tPLH f = 10 kHz, CL = 50 pF (3) (4) (1) (2) (3) (4) 4 Typical Values represent the most likely parametric norm. All limits are specified by testing or statistical analysis. CL includes the probe and jig capacitance. The rise and fall times are measured with a 2V input step. The propagation delays are also measured with a 2V input step. Submit Documentation Feedback Copyright © 1997–2013, Texas Instruments Incorporated Product Folder Links: LMC6762 LMC6762 www.ti.com SNOS739D – JULY 1997 – REVISED MARCH 2013 Typical Performance Characteristics + V = 5V, Single Supply, TA = 25°C unless otherwise specified Supply Current vs Supply Voltage (Output High) Supply Current vs Supply Voltage (Output Low) Figure 1. Figure 2. Input Current vs Common-Mode Voltage Input Current vs Common-Mode Voltage Figure 3. Figure 4. Input Current vs Common-Mode Voltage Input Current vs Temperature Figure 5. Figure 6. Submit Documentation Feedback Copyright © 1997–2013, Texas Instruments Incorporated Product Folder Links: LMC6762 5 LMC6762 SNOS739D – JULY 1997 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) + V = 5V, Single Supply, TA = 25°C unless otherwise specified 6 ΔVOS vs ΔVCM ΔVOS vs ΔVCM Figure 7. Figure 8. ΔVOS vs ΔVCM Output Voltage vs Output Current (Sourcing) Figure 9. Figure 10. Output Voltage vs Output Current (Sourcing) Output Voltage vs Output Current (Sourcing) Figure 11. Figure 12. Submit Documentation Feedback Copyright © 1997–2013, Texas Instruments Incorporated Product Folder Links: LMC6762 LMC6762 www.ti.com SNOS739D – JULY 1997 – REVISED MARCH 2013 Typical Performance Characteristics (continued) + V = 5V, Single Supply, TA = 25°C unless otherwise specified Output Voltage vs Output Current (Sinking) Output Voltage vs Output Current (Sinking) Figure 13. Figure 14. Output Voltage vs Output Current (Sinking) Output Short Circuit Current vs Supply Voltage (Sourcing) Figure 15. Figure 16. Output Short Circuit Current vs Supply Voltage (Sinking) Response Time for Overdrive (tPLH) Figure 17. Figure 18. Submit Documentation Feedback Copyright © 1997–2013, Texas Instruments Incorporated Product Folder Links: LMC6762 7 LMC6762 SNOS739D – JULY 1997 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) + V = 5V, Single Supply, TA = 25°C unless otherwise specified 8 Response Time for Overdrive (tPHL) Response Time for Overdrive (tPLH) Figure 19. Figure 20. Response Time for Overdrive (tPHL) Response Time for Overdrive (tPLH) Figure 21. Figure 22. Response Time for Overdrive (tPHL) Response Time vs Capacitive Load Figure 23. Figure 24. Submit Documentation Feedback Copyright © 1997–2013, Texas Instruments Incorporated Product Folder Links: LMC6762 LMC6762 www.ti.com SNOS739D – JULY 1997 – REVISED MARCH 2013 APPLICATION HINTS Input Common-Mode Voltage Range At supply voltages of 2.7V, 5V and 15V, the LMC6762 has an input common-mode voltage range which exceeds both supplies. As in the case of operational amplifiers, CMVR is defined by the VOS shift of the comparator over the common-mode range of the device. A CMRR (ΔVOS/ΔVCM) of 75 dB (typical) implies a shift of < 1 mV over the entire common-mode range of the device. The absolute maximum input voltage at V+ = 5V is 200 mV beyond either supply rail at room temperature. Figure 25. An Input Signal Exceeds the LMC6762 Power Supply Voltages with No Output Phase Inversion A wide input voltage range means that the comparator can be used to sense signals close to ground and also to the power supplies. This is an extremely useful feature in power supply monitoring circuits. An input common-mode voltage range that exceeds the supplies, 20 fA input currents (typical), and a high input impedance makes the LMC6762 ideal for sensor applications. The LMC6762 can directly interface to sensors without the use of amplifiers or bias circuits. In circuits with sensors which produce outputs in the tens to hundreds of millivolts, the LMC6762 can compare the sensor signal with an appropriately small reference voltage. This reference voltage can be close to ground or the positive supply rail. Low Voltage Operation Comparators are the common devices by which analog signals interface with digital circuits. The LMC6762 has been designed to operate at supply voltages of 2.7V without sacrificing performance to meet the demands of 3V digital systems. At supply voltages of 2.7V, the common-mode voltage range extends 200 mV (ensured) below the negative supply. This feature, in addition to the comparator being able to sense signals near the positive rail, is extremely useful in low voltage applications. Figure 26. Even at Low-Supply Voltage of 2.7V, an Input Signal which Exceeds the Supply Voltages Produces No Phase Inversion at the Output At V+ = 2.7V, propagation delays are tPLH = 4 μs and tPHL = 4 μs with overdrives of 100 mV. Please refer to the performance curves for more extensive characterization. Submit Documentation Feedback Copyright © 1997–2013, Texas Instruments Incorporated Product Folder Links: LMC6762 9 LMC6762 SNOS739D – JULY 1997 – REVISED MARCH 2013 www.ti.com Shoot-Through Current The shoot-through current is defined as the current surge, above the quiescent supply current, between the positive and negative supplies of a device. The current surge occurs when the output of the device switches states. This transient switching current results in glitches in the supply voltage. Usually, glitches in the supply lines are compensated by bypass capacitors. When the switching currents are minimal, the values of the bypass capacitors can be reduced considerably. Figure 27. LMC6762 Circuit for Measurement of the Shoot-Through Current Figure 28. Measurement of the Shoot-Through Current From Figure 27 and Figure 28 the shoot-through current for the LMC6762 can be approximated to be 0.2 mA (200 mV/1 kΩ). The duration of the transient is measured as 1 μs. The values needed for the local bypass capacitors can be calculated as follows: Area of Δ = ½ (1 μs × 200 μA) = 100 pC If the local bypass capacitor has to provide this charge of 100 pC, the minimum value of the local capacitor to prevent local degradation of VCC can be calculated. Suppose that the maximum voltage droop that the system can tolerate is 100mV, ΔQ = C * (ΔV) →C = (ΔQ/ΔV) = 100 pC/100 mV = 0.001 μF The low internal feedthrough current of the LMC6762 thus requires lower values for the local bypass capacitors. In applications where precision is not critical, this is a significant advantage, as lower values of capacitors result in savings of board space, and cost. 10 Submit Documentation Feedback Copyright © 1997–2013, Texas Instruments Incorporated Product Folder Links: LMC6762 LMC6762 www.ti.com SNOS739D – JULY 1997 – REVISED MARCH 2013 It is worth noting here that the delta shift of the power supply voltage due to the transient currents causes a threshold shift of the comparator. This threshold shift is reduced by the high PSRR of the comparator. However, the value of the PSRR applicable in this instance is the transient PSRR and not the DC PSRR. The transient PSRR is significantly lower than the DC PSRR. Generally, it is a good goal to reduce the delta voltage on the power supply to a value equal to or less than the hysteresis of the comparator. For example, if the comparator has 50 mV of hysteresis, it would be reasonable to increase the value of the local bypass capacitor to 0.01 μF to reduce the voltage delta to 10 mV. Output Short Circuit Current The LMC6762 has short circuit protection of 40 mA. However, it is not designed to withstand continuous short circuits, transient voltage or current spikes, or shorts to any voltage beyond the supplies. A resistor is series with the output should reduce the effect of shorts. For outputs which send signals off PC boards additional protection devices, such as diodes to the supply rails, and varistors may be used. Hysteresis If the input signal is very noisy, the comparator output might trip several times as the input signal repeatedly passes through the threshold. This problem can be addressed by making use of hysteresis as shown below. Figure 29. Canceling the Effect of Input Capacitance The capacitor added across the feedback resistor increases the switching speed and provides more short term hysteresis. This can result in greater noise immunity for the circuit. Spice Macromodel A • • • Spice Macromodel is available for the LMC6762. The model includes a simulation of: Input common-mode voltage range Quiescent and dynamic supply current Input overdrive characteristics and many more characteristics as listed on the macromodel disk. A SPICE macromodel of this and many other op amps is available at no charge from the WEBENCH Design Center Team at http://www.ti.com/ww/en/analog/webench/ Submit Documentation Feedback Copyright © 1997–2013, Texas Instruments Incorporated Product Folder Links: LMC6762 11 LMC6762 SNOS739D – JULY 1997 – REVISED MARCH 2013 www.ti.com Typical Applications One-Shot Multivibrator Figure 30. One-Shot Multivibrator A monostable multivibrator has one stable state in which it can remain indefinitely. It can be triggered externally to another quasi-stable state. A monostable multivibrator can thus be used to generate a pulse of desired width. The desired pulse width is set by adjusting the values of C2 and R4. The resistor divider of R1 and R2 can be used to determine the magnitude of the input trigger pulse. The LMC6762 will change state when V1 < V2. Diode D2 provides a rapid discharge path for capacitor C2 to reset at the end of the pulse. The diode also prevents the non-inverting input from being driven below ground. Bi-Stable Multivibrator Figure 31. Bi-Stable Multivibrator A bi-stable multivibrator has two stable states. The reference voltage is set up by the voltage divider of R2 and R3. A pulse applied to the SET terminal will switch the output of the comparator high. The resistor divider of R1, R4, and R5 now clamps the non-inverting input to a voltage greater than the reference voltage. A pulse applied to RESET will now toggle the output low. Zero Crossing Detector Figure 32. Zero Crossing Detector 12 Submit Documentation Feedback Copyright © 1997–2013, Texas Instruments Incorporated Product Folder Links: LMC6762 LMC6762 www.ti.com SNOS739D – JULY 1997 – REVISED MARCH 2013 A voltage divider of R4 and R5 establishes a reference voltage V1 at the non-inverting input. By making the series resistance of R1 and R2 equal to R5, the comparator will switch when VIN = 0. Diode D1 insures that V3 never drops below −0.7V. The voltage divider of R2 and R3 then prevents V2 from going below ground. A small amount of hysteresis is setup to ensure rapid output voltage transitions. Oscillator Figure 33. Square Wave Generator Figure 33 shows the application of the LMC6762 in a square wave generator circuit. The total hysteresis of the loop is set by R1, R2 and R3. R4 and R5 provide separate charge and discharge paths for the capacitor C. The charge path is set through R4 and D1. So, the pulse width t1 is determined by the RC time constant of R4 and C. Similarly, the discharge path for the capacitor is set by R5 and D2. Thus, the time t2 between the pulses can be changed by varying R5, and the pulse width can be altered by R4. The frequency of the output can be changed by varying both R4 and R5. Submit Documentation Feedback Copyright © 1997–2013, Texas Instruments Incorporated Product Folder Links: LMC6762 13 LMC6762 SNOS739D – JULY 1997 – REVISED MARCH 2013 www.ti.com Figure 34. Time Delay Generator The circuit shown above provides output signals at a prescribed time interval from a time reference and automatically resets the output when the input returns to ground. Consider the case of VIN = 0. The output of comparator 4 is also at ground. This implies that the outputs of comparators 1, 2, and 3 are also at ground. When an input signal is applied, the output of comparator 4 swings high and C charges exponentially through R. This is indicated above. The output voltages of comparators 1, 2, and 3 switch to the high state when VC1 rises above the reference voltage VA, VB and VC. A small amount of hysteresis has been provided to insure fast switching when the RC time constant is chosen to give long delay times. 14 Submit Documentation Feedback Copyright © 1997–2013, Texas Instruments Incorporated Product Folder Links: LMC6762 LMC6762 www.ti.com SNOS739D – JULY 1997 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision C (March 2013) to Revision D • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 14 Submit Documentation Feedback Copyright © 1997–2013, Texas Instruments Incorporated Product Folder Links: LMC6762 15 PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LMC6762AIM NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 LMC67 62AIM LMC6762AIM/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) SN | CU SN Level-1-260C-UNLIM -40 to 85 LMC67 62AIM LMC6762AIMX NRND SOIC D 8 2500 TBD Call TI Call TI -40 to 85 LMC67 62AIM LMC6762AIMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) SN | CU SN Level-1-260C-UNLIM -40 to 85 LMC67 62AIM LMC6762BIM NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 LMC67 62BIM LMC6762BIM/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) SN | CU SN Level-1-260C-UNLIM -40 to 85 LMC67 62BIM LMC6762BIMX NRND SOIC D 8 2500 TBD Call TI Call TI -40 to 85 LMC67 62BIM LMC6762BIMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) SN | CU SN Level-1-260C-UNLIM -40 to 85 LMC67 62BIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 1-Nov-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMC6762AIMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMC6762AIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMC6762BIMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMC6762BIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMC6762AIMX SOIC D 8 2500 367.0 367.0 35.0 LMC6762AIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMC6762BIMX SOIC D 8 2500 367.0 367.0 35.0 LMC6762BIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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