M65818AFP
Digital Amplifier Processor of S-Master* Technology
REJ03F0019-0100Z
Rev.1.00
Sep.04.2003
Description
The M65818AFP is a S-Master technique processor for digital amplifier enable to convert from multi liner-PCM digital
input signal to high precise switching-pulse digital output without analog processing.
The M65818AFP has built-in 24bit sampling rate converter and digital-gain-controller.
The M65818AFP enables to realize high precise (X`tal oscillation precision) fully digital amplifier systems combining
with power driver IC.
Features
• Built-in 24bit Sampling Rate Converter.
Input Signal Sampling Rate
from 32KHz to 192KHz(24bit Maximum).
4 kinds of Digital Input Format.
• Built-in L/R Independent Digital Gain Control.
• Built-in Soft Mute Function with Exponential Approximate-Curve.
• Correspondence for SACD signal (64Fs 1bit,Fs=44.1KHz).
• Direct Output from Sampling Rate Converter.
• 3.3V and 5.0V Power Supply Operation at Output Clock, Input Data, and Control Signal Port
Main Applications
• Master Clock
Primary Clock: 256Fsi/512Fsi Secondary Clock: 1024Fso/512Fso
• Input Signal Format:
MSB First Right Justified(16/20/24bit),MSB First Left Justified(24bit)
LSB First Right Justified(24bit),I2S(24bit)
• Input Signal Sampling Rate from 32kHz to 192kHz.
• 8Fs Input Mode: Correspondence for External Digital Filter, Sampling Rate Converter Outputs.
• Gain Control Function:
+30dB~ -∞dB(0.1dB Step until -96dB, -138dB Minimum)
• Third Order ∆Σ (16Fso:6bit/5bit,32Fso: 5bit)
• Sampling Rate Converter Output :MSB First Left justified /Lch,Rch Independent/32BCK
Recommended Operating Conditions
Logic Block:3.3V±10%, PWM Buffer Block : 5.0V±10%
(** "S-Master" is the digital amplifier technology developed by Sony Corporation.
"S-Master" is a trademark of Sony Corporation.
Rev.1.00, Sep.04.2003, page 1 of 38
M65818AFP
System Block Diagram
M65818AFP
External
Input
CD
DVD Audio
etc.
LRCK
BCK
DATA
256fsi
/512fsi
SACD
DSD
24bit
Sampling
Rate
Converter
32kHz
to
192kHz
Clock
DSD
Interface
Level
Control
+30dB
to
MCU I/F
∆Σ
Clock
1024fs/512fs
Rev.1.00, Sep.04.2003, page 2 of 38
Stream
Power
Driver
LC
Filter
Stream
Power
Driver
LC
Filter
PWM
M65818AFP
1. Pin Configuration (Top View)
(3.3V/5V System)
P
G
M
U
T
E
(3.3V System)(5V System )
N
S
P
M
U
T
E
S
C
D
T
S
C
S
H
I
F
T
S
C
L
A
T
C
H
MM
OO
DD
EE
2 1
D
V
d
d
M
C
K
S
E
L
D
V
s
s
X
V
s
s
X
V
s
s
X
f
s
o
I
N
X
V
d
d
V
s
s
L
V
s
s
L
1
+
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
INIT
SYNC
DATA
BCK
LRCK
FsiI
DSD128Fs
DSD64Fs
DSDR
DSDL
DSDCKSEL1
DSDCKSEL2
DSDCKIO
TEST1
TEST2
CKCTL1
CKCTL2
BFVdd
EXIOSEL
EXDATAL
EXDATAR
EXBCK
EXWCK
XfsiIN
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
C
K
O
U
T
1
C
K
O
U
T
2
C
K
O
U
T
3
B
F
V
s
s
(3.3V/5V System)
Rev.1.00, Sep.04.2003, page 3 of 38
D
V
s
s
T
E
S
T
3
O
F
L
F
L
A
G
S
F
L
A
G
F
s
o
C
K
O
F
s
o
I
D
V
d
d
X
O
V
d
d
XX
f O
sV
o s
Os
U
T
V
s
s
R
(3.3V System)(5V System)
V
s
s
R
2
+
OUTL1+
VddL1+
VddL1OUTL1VssL1VssL2OUTL2VddL2VddL2+
OUTL2+
VssL2+
VddL
VddR
VssR1+
OUTR1+
VddR1+
VddR1OUTR1VssR1VssR2OUTR2VddR2VddR2+
OUTR2+
(5V System)
(5V System)
M65818AFP
A-1 Difference between M65818AFP and M65817AFP
M65818AFP has added the following functions to M65817AFP.
M65817AFP
M65818AFP
PWM Output Form
General Pulse Width Modulation
Reverse Output
Pins Function of PWM
Output "OUTL1-/R1-"
Reverse Phase between
OUTL1+/R1+ and OUTL1-/R1-
Selectable 4 kind of Output Form (Refer to
M65818AFP Data Sheet: P28/38
System1Mode bit22,23)
Selectable phase between OUTL1+/R1+
and OUTL1-/R1- to Same/Reverse (Refer to
M65818AFP Data Sheet: P28/38
System1Mode bit24)
∆ΣOperation Ratio
16fso Fixed
Selection of Muting operation at
Primary Side Asynchronous
Detection
PWM Output Duty 50% Mute at
primary side asynchronous detection
Selection of External 8Fs
Data Input Mode
Only synchronize to secondary side
clock (Input the data to Gain Control
Block)
Selectable operation ratio to 16fso/32fso
(Refer to M65818AFP Data Sheet: P31/38
System2 Mode bit16)
Selectable PWM Output Duty 50% Mute
On/Off at primary side asynchronous
detection (Refer to M65818AFP Data Sheet:
P28/38 System1Mode bit20 )
Added the function of synchronization to
primary side clock:
Input the data to Sampling Rate Converter
(Refer to M65818AFP Data Sheet: P28/38
System1Mode bit21)
A-2 The Example of Evaluation Circuit
+
OUTL1+24
OUTL1- 21
OUTL2- 18
OUTL2+15
+
+
-
DATA 43
BCK 44 M65818AFP
LRCK 45
+
OUTR1+10
OUTR1- 7
OUTR2- 4
OUTR2+ 1
+
+
-
+
-
Reference Characteristics
Condition
S/N
104dB(typ)
THD+N
0.0014%(typ)
•
•
•
•
•
•
•
Rev.1.00, Sep.04.2003, page 4 of 38
+
-
Input Signal : 1kHz 0dB Full scale sine wave
Fs : Primary Clock 44.1kHz, Secondary Clock 48kHz
PWM Output Format1
AC dithering E
DC dithering 0.1%
Gain Data Setting:(Index)10000b/(Mantissa)10000000b
THD+N : Filter 20kHz LPF S/N : Filter 20kHz LPF + JIS-A
Rev.1.00, Sep.04.2003, page 5 of 38
DSDR 49
DSDL 50
DSD128Fs 47
DSD64Fs 48
LRCK 45
DATA 43
BCK 44
EXDATAR 61
EXBCK 62
EXWCK63
EXDATAL 60
S
S
P
P
E
X
I
O
S
E
L
59
C
K
S C
Y T
N L
C 1
42 56
F
s
o
C
K
O
73
C
K
O
U
T
1
65
C
K
O
U
T
2
66
C
K
O
U
T
3
67
M
O
D
E
2
M
O
D
E
1
S S
C C
S L
H A
I T
F C
T H
S
C
D
T
D
S
D
C
K
I
O
D
S
D
C
K
S
E
L
1
D
S
D
C
K
S
E
L
2
35 34
Serial
Control
Gain
Control
Clock
Generator
(Secondary)
M
C
K F
S s
E o
L
I
32 74
38 37 36
C
K
C
T
L
2
57
51 52 53
Down Sampling
Filter
Sampling
Rate Converter
Clock
Generator
(Primary)
F
s
i
I
46
X
f
s
i
I
N
64
X
f
s
o
O
U
T
77
O
F
L
F
L
A
G
71
S
F
L
A
G
72
I
N
I
T
41
N
S
P
M
U
T
E
P
G
M
U
T
E
39 40
INIT/MUTE
∆Σ
X
f
s
o
I
N
28
T
E
S
T
3
T
E
S
T
1
T
E
S
T
2
70
54 55
PWM
10
7
4
1
24
21
18
15
OUTR1+
OUTR1OUTR2OUTR2+
OUTL1+
OUTL1OUTL2OUTL2+
M65818AFP
2. Block Diagram
M65818AFP
3. Pin Descriptions
Pin
No.
Name
I/O
1
2
OUTR2+
VddR2+
O
3
4
VddR2OUTR2-
5
6
VssR2VssR1-
7
8
OUTR1VddR1-
9
10
VddR1+
OUTR1+
11
12
O
O
Description
Output
Current
5V/3.3V
Signal Level
Rch PWM2(+) Output
Power Supply for Rch PWM2(+) (5V)
5V
Power Supply for Rch PWM2(-) (5V)
Rch PWM2 (-) Output
5V
GND for Rch PWM2(-)
GND for Rch PWM1(-)
5V
Rch PWM1 (-) Output
Power Supply for Rch PWM1(-) (5V)
Power Supply for Rch PWM1(+) (5V)
Rch PWM1 (+) Output
5V
VssR1+
VddR
GND for Rch PWM1(+)
Power Supply for Rch PWM (5V)
13
14
VddL
VssL2+
Power Supply for Lch PWM (5V)
GND for Lch PWM2(+)
15
16
OUTL2+
VddL2+
5V
17
18
VddL2OUTL2-
19
20
VssL2VssL1-
21
22
OUTL1VddL1-
23
24
VddL1+
OUTL1+
25
26
VssL1+
VssL
27
28
XVdd
XfsoIN
29
30
O
O
O
O
Lch PWM2 (+) Output
Power Supply for Lch PWM2(+) (5V)
Power Supply for Lch PWM2(-) (5V)
Lch PWM2 (-) Output
5V
GND for Lch PWM2(-)
GND for Lch PWM1(-)
5V
Lch PWM1 (-) Output
Power Supply for Lch PWM1(-) (5V)
Power Supply for Lch PWM1(+) (5V)
Lch PWM1 (+) Output
5V
GND for Lch PWM1(+)
GND for Lch PWM
Power Supply for Master Clock Buffer
Secondary Master Clock
Input:1024Fso/512Fso
5V
XVss
XVss
GND for Master Clock Buffer
GND for Master Clock Buffer
31
32
DVss
MCKSEL
I
GND for Digital Block
Secondary Master Clock Selection;
L:1024Fso, H:512Fso
3.3V
33
34
DVdd
MODE1
I
Power Supply for Digital Block (3.3V)
Input Mode Selection 1
5V/3.3V
35
36
MODE2
SCLATCH
I
I
Input Mode Selection 2
Serial Control•Latch Signal Input
5V/3.3V
5V/3.3V
37
38
SCSHIFT
SCDT
I
I
Serial Control•Shift Clock Input
Serial Control•Data Input
5V/3.3V
5V/3.3V
39
40
NSPMUTE
PGMUTE
I
I
PWM Duty 50% Mute (L :Active)
PWM G-MUTE (L :Active)
5V/3.3V
5V/3.3V
O
I
Rev.1.00, Sep.04.2003, page 6 of 38
M65818AFP
Output
Current
5V/3.3V
Signal Level
Initialize Input(Power Supply Reset): ;
L:Reset, H:Release
Synchronous Set of System Clock (at Rising
Edge)
5V/3.3V
5V/3.3V
DATA Input (CD/MD / DVD audio mode)
PCM Signal
BCK Input (CD/MD / DVD audio mode) PCM
Signal
5V/3.3V
5V/3.3V
5V/3.3V
I
LRCK Input (CD/MD / DVD audio mode)
PCM Signal
Primary Fsi Clock Input (SACD mode)
5V/3.3V
DSD128Fs
DSD64Fs
I/O
I/O
SACD Interface Clock(128Fs)
SACD Interface Clock(64Fs)
2mA/1.5mA
2mA/1.5mA
5V/3.3V
5V/3.3V
49
50
DSDR
DSDL
I
I
SACD Rch Data Input
SACD Lch Data Input
5V/3.3V
5V/3.3V
51
52
DSDCKSEL1
DSDCKSEL2
I
I
SACD Interface Selection 1
SACD Interface Selection 2
5V/3.3V
5V/3.3V
53
DSDCKIO
I
5V/3.3V
54
TEST1
I
I/O Selection for SACD(64Fs,128Fs)Clock
L:input,H:output
TEST1 must be connected to GND.
5V/3.3V
55
56
TEST2
CKCTL1
I
I
TEST2 must be connected to GND.
fso System Clock(CKOUT1,2,3) Output
Selection 1
5V/3.3V
5V/3.3V
57
CKCTL2
I
5V/3.3V
58
BFVdd
fso System Clock(CKOUT1,2,3) Output
Selection 2
Power Supply for Input/Output
(3.3V/5V)Buffer
59
EXIOSEL
I
5V/3.3V
60
EXDATAL
I/O
8Fs Data Input/Output Selection L:Input
H:Output
8Fs Data Lch
2mA/1.5mA
5V/3.3V
61
62
EXDATAR
EXBCK
I/O
I/O
8Fs Data Rch
BCK for 8fs Data (32BCK=1WCK)
2mA/1.5mA
2mA/1.5mA
5V/3.3V
5V/3.3V
63
64
EXWCK
XfsiIN
I/O
I
Word Clock for 8fs Data (1WCK=32BCK)
Primary Master Clock Input (256fsi/512fsi)
2mA/1.5mA
5V/3.3V
5V/3.3V
65
66
CKOUT1
CKOUT2
O
O
fso System Clock Output 1
fso System Clock Output 2
4mA/3mA
4mA/3mA
5V/3.3V
5V/3.3V
67
68
CKOUT3
BFVss
O
fso System Clock Output 3
GND for Digital Block Input/Output Buffer
4mA/3mA
5V/3.3V
69
70
DVss
TEST3
I
GND for Digital Block
TEST3 must be connected to GND.
3.3V
71
OFLFLAG
O
2mA
3.3V
72
SFLAG
O
Overflow Detector Flag of Digital Operation
(H :Active)
Asynchronous Flag (H :Active)
2mA
3.3V
73
74
FsoCKO
FsoI
O
I
Secondary Fso Clock Output
Secondary Fso Clock Input
4mA
3.3V
3.3V
75
76
DVdd
XOVdd
Power Supply for Digital Block(3.3V)
Power Supply for Secondary Master Clock
Buffer(5V)
Pin
No.
Name
I/O
Description
41
INIT
I
42
SYNC
I
43
DATA
I
44
BCK
I
45
LRCK
I
46
FsiI
47
48
Rev.1.00, Sep.04.2003, page 7 of 38
M65818AFP
Pin
No.
Name
I/O
Description
77
XfsoOUT
O
78
XOVss
Buffered Output of Secondary Master Clock
(1024/512fso)
GND for Secondary Master Clock Buffer
79
80
VssR
VssR2+
GND for Rch PWM
GND for Rch PWM2(+)
Output
Current
5V/3.3V
Signal Level
2mA
5V
4. Electrical Characteristics
Absolute Maximum Ratings
Parameter
Symbol
Min.
Typ.
Max
Unit
Conditions
Supply Voltage
PWMVdd
BFVdd
−0.3
−0.3
6.0
6.0
V
V
5V XVdd, XOVdd, and Vdd (PWM).
5.0V System
−0.3
−0.3
4.2
Vdd+0.3V
V
V
3.3V System
Input Voltage Range
DVdd
Vi (5.0V)
Vi (3.3V)
Pd
−0.3
600
Vdd+0.3V
Power Dissipation
V
mW
Storage Temperature
Tstg
−40
125
Ta=60 °C
°C
Recommended Operating Conditions
Parameter
Symbol
Min.
Typ.
Max
Unit
Conditions
Supply Voltage
PWMVdd
4.5
5.0
5.5
V
5V XVdd, XOVdd, and Vdd (PWM).
BFVdd
4.5
3.0
5.0
3.3
5.5
3.6
V
V
5.0V function
3.3V function
DVdd
Ta
3.0
−20
3.3
3.6
75
V
°C
XFsoIN
XFsiIN
16
8
50
25
MHz
MHz
Operating Temperature
Operating Frequency
Rev.1.00, Sep.04.2003, page 8 of 38
M65818AFP
DC Characteristics
(Ta=25°C, PWMVdd=5V, DVdd=3.3V: Unless otherwise specified.)
Parameter
Symbol
Min.
Typ.
Max
Unit
Conditions
H Level Input Voltage
VIH5
0.75Vdd
V
BFVdd=4.5 to 5.5V
VIH3
0.75Vdd
V
BFVdd=3.0 to 3.6V
L Level Input Voltage
VIL5
VIL3
0.25Vdd
0.25Vdd
V
V
BFVdd=4.5 to 5.5V
BFVdd=3.0 to 3.6V
Input Leak Current
"H"Level Output
Voltage
Ileak
VOH5
Vdd − 0.5
10
µA
V
BFVdd=4.5 to 5.5V IOH5=−2.0mA
VOH3
Vdd − 0.5
V
BFVdd=3.0 to 3.6V IOH3=−1.5mA
VOH5
VOH3
Vdd − 0.5
Vdd − 0.5
V
V
BFVdd=4.5 to 5.5V IOH5=−4.0mA
BFVdd=3.0 to 3.6V IOH3=−3.0mA
"L" Level Output
Voltage
DSD128Fs
DSD64Fs
EXDATAL
EXDATAR
EXBCK
EXWCK
CKOUT1
CKOUT2
CKOUT3
XfsoOUT
OFLFAG
SFLAG
FsoCKO
OUTLXX
OUTRXX
DSD128Fs
DSD64Fs
EXDATAL
EXDATAR
EXBCK
EXWCK
CKOUT1
CKOUT2
CKOUT3
XfsoOUT
OFLFAG
SFLAG
FsoCKO
OUTLXX
OUTRXX
Power Supply Current
VOH5
Vdd − 0.5
V
BFVdd=4.5 to 5.5V IOH5=−2.0mA
VOH3
Vdd − 0.5
V
BFVdd=3.0 to 3.6V IOH3=−2.0mA
VOH5
Vdd − 0.5
V
VddLXX/RXX=4.5V to 5.5V
IOH5=−4.0mA
VOL5
VOL3
0.5
0.5
V
V
BFVdd=4.5 to 5.5V IOH5=2.0mA
BFVdd=3.0 to 3.6V IOH3=1.5mA
VOL5
0.5
V
BFVdd=4.5 to 5.5V IOH5=4.0mA
VOL3
0.5
V
BFVdd=3.0 to 3.6V IOH3=3.0mA
VOL5
VOL3
0.5
0.5
V
V
BFVdd=4.5 to 5.5V IOH5=2.0mA
BFVdd=3.0 to 3.6V IOH3=2.0mA
VOL5
0.5
V
VddLXX/RXX=4.5V to 5.5V
IOH5=4.0mA
BFVdd=5V
Idd
33
mA
5. Explanation of Operation
5.1. MODE1, MODE2
34 35
The states of MODE1 and MODE2 pins select input signal mode.
MODE1 and MODE2 are control pins for input signal mode (Normal / SACD / External 8fs Input).
These are selectable as follows.
Pin
Name / MODE
Normal
External 8fs Data
SACD-fsi
SACD-fso
34
MODE1
L
L
H
H
35
MODE2
L
H
L
H
Rev.1.00, Sep.04.2003, page 9 of 38
M65818AFP
• Normal mode
The Normal is data input mode from CD,MD,DVD etc.
Input pins are DATA,BCK, and LRCK.
• External 8fs Data mode
In this mode, the 8fs rate data inputted from external device.
Input pins are EXDATAL,EXDATAR,EXBCK and EXWCK.
The data synchronized with the clock of EXBCK,EXWCK pins are inputted into EXDATAL,EXDATAR pins .
Selectable "Input for primary side synchronization" and "Input for secondary side synchronization"
by the serial control System1 mode bit21(EXMODE)
In the case of primary side synchronization, the data inputted to the Sampling Rate Converter block.
In the case of secondary side synchronization, the data inputted to Gain Control block.
• SACD-fsi mode
In this mode, SACD format data inputted.
Input pins are DSDL,DSDR,DSD128Fs and DSD64Fs.
The clock of a Down Sampling Filter is given from a *primary side, and down sampled data are
inputted into the Sampling Rate Converter block.
The data synchronized with the clock of DSD128Fs,DSD64Fs pins are inputted into DSDL,DSDR pins.
• SACD-fso mode
In this mode, SACD format data inputted.
Input pins are DSDL,DSDR,DSD128Fs and DSD64Fs.
The clock of a Down Sampling Filter is given from a *secondary side, and down sampled data are
inputted into the Gain Control block.
The data synchronized with the clock of DSD128Fs,DSD64Fs pins are inputted into DSDL,DSDR pins.
* primary clock: This clock means input side clock System of the sampling rate converter.
secondary clock: This clock means output side clock System of the sampling rate converter. The block after Sampling
Rate Converter ( Gain Control Block, .∆Σ Block, and PWM Block) operate with secondary clock
"fsi", "fso", and "fs" are defined as follows in this data sheet.
fsi: The primary side Sampling Frequency
fso: The secondary side Sampling Frequency
fs: The sampling frequency which can be set as both by the side of primary and secondary .
(External 8fs Data , SACD Data etc.)
Rev.1.00, Sep.04.2003, page 10 of 38
M65818AFP
5.2. SCDT, SCSHIFT, SCLATCH
38 37 36
SCDT,SCSHIFT,and SCLATCH are input pins for setting M65818AFP's operation.
Input format of SCDT, SCSHIFT and SCLATCH is shown below.
• Input format of SCDT, SCSHIFT, and SCLATCH.
bit1
SCDT
24
20
15
10
5
1
SCSHIFT
SCLATCH
• Mode Setting
The operating Mode are classified in four and assigned by bit1and bit2. These four functions are shown below.
(bit1 and bit2 ) = ( "L" and "L" ) Gain control mode: Gain control.
(bit1 and bit2 ) = ( "L "and "H" ) System1 Mode: Primary block initialization, etc.
(bit1 and bit2 ) = ( "H" and "L" ) System2 Mode : Secondary block initialization, etc.
(bit1 and bit2 ) = ( "H" and "H" ) Test mode ( setting prohibition )
Refer to Chapter 6 about these four setting in detail.
5.3. DATA, BCK, LRCK
43 44 45
DATA, BCK and LRCK are input pins under condition of `Normal ` mode.
Input formats are supported by following 4 ways, and are set by Serial Control, "System1 Mode, bit3 and bit4".
Input data length are selectable in the case of "MSB First Right Justified"
(Serial Control "System1 Mode, bit5, 6").
and Input Signal Sampling Rate(1/2/4fsi) are set by Serial Control,"System1 Mode, bit7,8"
Input formats are shown in following figures.
Rev.1.00, Sep.04.2003, page 11 of 38
M65818AFP
• Input Formats of DATA, BCK, and LRCK
1/fsi, 1/2fsi, 1/4fsi
Left
LRCK
Right
BCK
MSB
LSB
MSB
DATA
(24bit)
LSB
24cycle
24cycle
MSB first left justified(24bit)
1/fsi, 1/2fsi, 1/4fsi
Right
Left
LRCK
BCK
LSB
MSB
LSB
MSB
DATA
(16bit)
16 cycle
MSB
DATA
(20bit)
LSB
16 cycle
MSB
20 cycle
20 cycle
LSB
MSB
DATA
(24bit)
LSB
MSB
LSB
24 cycle
24 cycle
MSB first right justified(16bit, 20bit, 24bit)
1/fsi, 1/2fsi, 1/4fsi
Right
Left
LRCK
BCK
LSB
LSB
MSB
DATA
(24bit)
MSB
24 cycle
24 cycle
LSB first right justified(24bit)
1/fsi, 1/2fsi, 1/4fsi
Left
LRCK
Right
BCK
1 BCK
1 BCK
MSB
DATA
(24bit)
MSB
LSB
24 cycle
LSB
24 cycle
I2S(24bit)
5.4. EXBCK, EXWCK, EXDATAL, EXDATAR, EXIOSEL
62 63 60 61 59
When "input signal mode" is "external 8fs data mode", regardless of a setup of EXIOSEL pin, the data of 8fs rate are
inputted from EXDATAL, EXDATAR pins.
By setup of serial control "System1 mode:bit21", Primary Side Synchronous Input or Secondary Side Synchronous
Input can be selected.
In case an external 8fs data input is secondary side synchronous , the data is inputted to Gain Control Block.
Rev.1.00, Sep.04.2003, page 12 of 38
M65818AFP
In case an external 8fs data input is primary side synchronous , the data is inputted to Sampling Rate Converter Block.
When "input signal mode" is except a "external 8fs data mode", the output data of sampling rate converter are outputted
from EXDATAL,EXDATAR pins setting up EXIOSEL pin into "H".
When "input signal mode" is except a "external 8fs data mode", EXBCK, EXWCK, EXDATAL, EXDATAR pins
serve as input terminals by setting up EXIOSEL pin into "L" .
Therefore, when not using "external 8fs data mode", EXIOSEL can be set to "L" and other four pins (EXBCK,
EXWCK, EXDATAL, EXDATAR) can be fixed to "L" or "H".
EXDATAL,EXDATAR,EXBCK, and EXWCK pin's input/output format is following figure.
Input Signal Mode
EXIOSEL
pin
EXMODE
Flag
EXWCK,EXBCK,EXDATAL,EXDATAR
Input / Output
"External 8fs Mode"
(MODE1,2=L,H)
X
L
Secondary Side Synchronous 8fs Data Input
(24 bit effective)
Primary Side Synchronous 8fs Data Input
(Upper 20bit effective)
H
Except "External 8fs
Mode"
(Except MODE1,2=L,H)
•
X
L
H
Input ("L" or "H" fixed)
Internal Sampling Rate Converter Output
EXDATAL, EXDATAR, EXBCK, and EXWCK input/output format
EXWCK
8fs
EXBCK
256fs
EXDATAL
/EXDATAR
LSB
MSB
23 22 21 20
9 8 7
1
0
MSB first left justified (24bit)
5.5. DSDL, DSDR, DSD128Fs, DSD64Fs, DSDCKSEL1, DSDCKSEL2, DSDCKIO 50 49 47 48 51 52 53
When "input signal mode" is "SACD-fsi Mode" or "SACD-fso Mode", the data is inputted to DSDL,DSDR pins.
Under `SACD-fsi ` mode, the clock of a Down Sampling Filter is given from a primary side, and down sampled data
are inputted into the Sampling Rate Converter block.
Under `SACD-fso ` mode, the clock of a Down Sampling Filter is given from a *secondary side, and down sampled
data a inputted into the Gain Control block.
The states of DSDCKSEL1,DSDCKDEL2 pins select 4 "SACD timing mode".
DSDCKIO pin select input or output pin-type of DSD128Fs/DSD64Fs clock for data fetch.
The relations of DSDCKSEL1 and DSDCKSEL2 pins and SACD input format mode setting are following figures.
DSDCKSEL1
DSDCKSEL2
SACD timing mode
L
L
L
H
mode1
mode2
H
H
L
H
mode3
mode4
Rev.1.00, Sep.04.2003, page 13 of 38
M65818AFP
Setting of DSDCKIO is following table.
DSDCKIO
Selection of DSD64fs and DSD128fs I/O
L
H
Input mode
Output mode
• SACD Input Format
mode1
DSDL/R (input data)
DSD128fs
D0
XD1 D2 XD2
XD3
D3
64fs
mode2
DSDL/R (input data)
DSD64fs
D1
128fs
DSD64fs
DSD128fs
XD0
D0 XD0
D1
XD1
D2
XD2 D3
XD3
128fs
64fs
mode3
DSDL/R (input data)
D0
XD0 D1
XD1 D2 XD2
D3
XD3
128fs
DSD128fs
64fs
DSD64fs
mode4
DSDL/R (input data)
DSD128fs
D0
D1
D2
64fs
DSD64fs
* D0:Positive phase data,
XD0:Negative phase data (reversal)
Positive phase data are fetched at the timing of "O" marks in upper figure.
5.6. MCKCEL, XfsoIN, XfsoOUT
32 28 77
XfsoIN pin is secondary master clock input.
The state of MCKSEL pin selects secondary master clock.
MCKSEL
XfsoIN
L
H
1024fso
512fso
XfsoOUT pin is buffered-output from XfsoIN pin's input clock.
Rev.1.00, Sep.04.2003, page 14 of 38
D3
M65818AFP
5.7. XfsiIN
64
XfsiIN pin is primary master clock input.
Frequency of primary master clock must be selected by the serial control "System2 mode:bit3".
bit3(IMCKSEL)
XfsiIN
H
L
512fsi
256fsi
• The relations between input signal sampling rate and master clock frequency.
Input sampling rate
Primary clock 512fsi/256fsi[Hz]
Secondary clock 1024fso/512fso[Hz]
1fsi: 32k / 2fsi: 64k / 4fsi: 128k
16.384M/8.192M
32.768M/16.384M
1fsi: 44.1k / 2fsi: 88.2k / 4fsi: 176.4k
1fsi: 48k / 2fsi: 96k / 4fsi: 192k
22.579M/11.290M
24.576M/12.288M
49.152M/24.576M
Input signal and primary clock are related to synchronization. The primary clock frequency are 512 or 256 times as
much as the input signal fsi ( 32k, 44.1k and 48k.)
The primary and secondary clock are related to independence. ( asynchronization )
At 1024fso setting, secondary clock= frequency range from 32.768MHz to 49.152MHz.
At 512fso setting, secondary clock = frequency range from 16.384MHz to 24.576MHz.
56 57 65 66 67
5.8. CKCTL1, CKCTL2, CKOUT1, CKOUT2, CKOUT3
CKOUT1, CKOUT2, and CKOUT3 pins are divided-clock output from secondary clock.
At power on, these frequency is free-running.
The states of CKCTL1 and CKCTL2 pins selects clock frequency of CKOUT1,CKOUT2,and CKOUT3 pins.
The setting table of CKCTL1 and CKCTL2 pins is shown below.
CKCTL1
CKCTL2
CKOUT1
CKOUT2
CKOUT3
L
L
L
H
L
256Fso
L
16Fso
L
8Fso
H
H
L
H
512Fso
512Fso
256Fso
256Fso
16Fso
8Fso
5.9. FsoCKO
73
FsoCKO is clock output pin of 1fso frequency. The output is divided-clock of XfsoIN, and frequency is free-running
at power on. FsoCKO pin's clock is utilized for a synchronization in case that have used plural M65818AFP,take a
synchronization between M65818AFP and other external devices.
Detail explanation is shown in next paragraph, "SYNC".
5.10. SYNC, FsoI, FsiI, SFLAG
42 74 46 72
M65818AFP synchronizes in clock input from the external source devices. So it makes synchronized operation between
source devices or another M65818AFP ( in case of Multi channel Operation )
The clock which can be set as the object of an synchronization is a clock of FsoI (1fso), FsiI (1fsi), LRCK (1/2/4 fsi),
and EXWCK (8fs). The object clock changes by input signal mode setting.
These relations are shown in following table.
Rev.1.00, Sep.04.2003, page 15 of 38
M65818AFP
M65818AFP detects rise edge of these synchronized clock in normal operation, and the M65818AFP does operation of
resynchronization in case that the cycle has changed.
In addition, the M65818AFP re-synchronizes for a synchronized clock, in case that M65818AFP detects SYNC pin's
rises edge, too.
This SYNC function exists also in serial control "System2 mode:bit6" under the same name.
While re-synchronizing, SFLAG pin outputs "H" and data is muted inside.
`Synchronization detection` clock
Input Signal Mode
Primary Side
Normal
External 8fs Data
Primary Side Synchronization
LRCK
FsoI
EXWCK *
FsoI
FsiI
FsoI
FsoI
Secondary Side Synchronization
SACD-fsi
Secondary Side
SACD-fso
FsoI
* Internal 8 dividing clock
In the case of using Multiplex(for multi channel application) and Single (for 2ch application) , detail explanation is
shown according to each "signal input mode" below.
• Normal Mode
<Multiplex use>
The primary side: It synchronizes with LRCK. All ICs synchronize with an input device by connecting common
LRCK.
The Secondary side: It synchronizes with FsoCKO of Master IC. One of M65818AFP becomes a master IC, and the
synchronization between ICs is carried out by FsoCKO of Master IC.
FsoCKO pin outputted from this master IC is entered each FsoI pins of master and slave ICs.
<Single use>
The primary side: It synchronizes with LRCK. Therefore M65818AFP synchronizes with source devices.
The secondary side: there is no need for external devices and other ICs to synchronize, therefore FsoCKO is
connected to FsoI, In other way, By setting secondary side asynchronous detection to "disable" with "ASYNCEN2"
flag(Serial Control,System2 mode,bit8), FsoI can also be considered as fixation.
In this mode, M65818AFP always perform synchronous detection between LRCK pin's clock in primary side.
Therefore with regardless to a setup by the serial control "System1 mode:bit16(ASYNCEN1)", the synchronous
detection perform as ` forced-enable`.
• External 8fs Data Mode (The case of primary side synchronization)
<Multiplex use>
The primary side: M65818AFP synchronizes with EXWCK (internal 8 dividing clock). All ICs synchronize with
an input device by connecting common EXWCK.
The secondary side: M65818AFP synchronizes with FsoCKO of Master IC. One of M65818AFP becomes a master
IC, and the synchronization between ICs is carried out by FsoCKO of Master IC.
FsoCKO pin outputted from this master IC is entered each FsoI pins of master and slave ICs.
Rev.1.00, Sep.04.2003, page 16 of 38
M65818AFP
<Single use>
The primary side: M65818AFP synchronizes with EXWCK (internal 8 dividing clock).
Thereby it synchronize with an input device.
The secondary side: there is no need for external devices and other ICs to synchronize, therefore FsoCKO is
connected to FsoI, In other way,
By setting secondary side asynchronous detection to "disable" with "ASYNCEN2" flag(Serial Control,System2
mode,bit8), FsoI can also be considered as fixation.
In this mode, M65818AFP always perform synchronous detection between EXWCK pin's clock in primary side.
Therefore with regardless to a setup by the serial control "System1 mode:bit16(ASYNCEN1)", the synchronous
detection perform as ` forced-enable`.
• External 8fs Data Mode (The case of secondary side synchronization)
<Multiplex use and Single use> (common)
The primary side: Synchronous operation does not carry out since internal sampling rate converter is not used.
In this mode, asynchronous detection by the primary side is set to disable by force.
Therefore with regardless to a setup by the serial control "System1 mode:bit16(ASYNCEN1)", the synchronous
detection perform as ` forced-disable`.
The Secondary Side: M65818AFP synchronizes with FsoCKO of Master IC (in single use, it is own IC).
One of the M65818AFP becomes a master, and the synchronization between ICs is carried out by FsoCKO of
Master IC.FsoCKO pin outputted from this master IC is entered each FsoI pins of master and slave ICs.
Moreover, the rise edge of FsoCKO sent from M65818AFP and the rise edge of EXWCK (8fs) which comes from
the external device need to be with a synchronous phase.
• SACD-fsi Mode
<Multiplex use>
The primary side: M65818AFP synchronizes with FsiI inputted in common to each IC. And primary side
synchronous DSD128Fs/DSD64Fs are used as a clock in common to all ICs.
Thus, DSD128 Fs/DSD64Fs in common to all ICs is inputted (all IC DSDCKIO=L) or the DSD128 Fs/DSD64Fs
output (DSDCKIO="H") generated by dividing of the primary side master clock within Master IC is inputted Into
the DSD128 Fs/DSD64Fs (DSDCKIO="L") of other slaves IC. The synchronous operation of the SACD input in
the case of multi is possible by doing in this way.
The secondary side: M65818AFP synchronizes with FsoCKO of Master IC. One of M65818AFP becomes a master
IC, and the synchronization between ICs is carried out by FsoCKO of Master IC.
FsoCKO pin outputted from this master IC is entered each FsoI pins of master and slave ICs.
<Single use>
The primary side: Input to FsiI pin or set FsiI as fixed by setting primary side asynchronous detection to disable by
serial control "System1 mode:bit16 (ASYNCEN1)".
The secondary side: there is no need for external devices and other ICs to synchronize, therefore FsoCKO is
connected to FsoI, In other way, By setting secondary side asynchronous detection to "disable" with "ASYNCEN2"
flag(Serial Control,System2 mode,bit8), FsoI can also be considered as fixation.
Rev.1.00, Sep.04.2003, page 17 of 38
M65818AFP
• SACD-fso Mode
<Multiplex use>
The primary side: Synchronous operation does not carry out since internal sampling rate converter is not used.
In this mode, asynchronous detection by the primary side is set to disable by force.
Therefore with regardless to a setup by the serial control "System1 mode:bit16(ASYNCEN1)", the synchronous
detection perform as ` forced-disable`.
The secondary side: M65818AFP synchronizes with FsoCKO of Master IC. One of M65818AFP becomes a master
IC, and the synchronization between ICs is carried out by FsoCKO of Master IC.
FsoCKO pin outputted from this master IC is entered each FsoI pins of master and slave ICs.
And DSD128Fs/DSD64Fs for secondary synchronization are connected as a clock in common to all ICs. Thus,
DSD128 Fs/DSD64Fs in common to all ICs is inputted (all IC DSDCKIO="L") or the DSD128 Fs/DSD64Fs
output (DSDCKIO="H") generated by dividing of the primary side master clock within Master IC is inputted into
the DSD128 Fs/DSD64Fs (DSDCKIO="L") of other slaves IC.
The synchronous operation of the SACD input in the case of multi is possible by doing in this way.
<Single use>
The primary side: Synchronous operation does not carry out since internal sampling rate converter is not used.
In this mode, asynchronous detection by the primary side is set to disable by force.
Therefore with regardless to a setup by the serial control "System1 mode:bit16(ASYNCEN1)", the synchronous
detection perform as ` forced-disable`.
The secondary side: there is no need for external devices and other ICs to synchronize, therefore FsoCKO is
connected to FsoI, In other way, By setting secondary side asynchronous detection to "disable" with "ASYNCEN2"
flag(Serial Control,System2 mode,bit8), FsoI can also be considered as fixation.
Rev.1.00, Sep.04.2003, page 18 of 38
M65818AFP
The examples of a connection diagram
The case of the multi use (6ch) in each input mode are shown in the following figure.
Normal Mode
LRCK (Primary)
ASYNCEN1=don't care
ASYNCEN2=enable
Master FsoCKO
(Secondary)
LRCK
FsiI
FsoI
EXWCK
Slave
LRCK
FsoI
FsiI
EXWCK
Slave
LRCK
FsoI
FsiI
EXWCK
External 8fs Data Mode
(The case of secondaryside synchronization)
External 8fs Data Mode
(The Case of Primary Side Synchronization)
ASYNCEN1=don't care
ASYNCEN2=enable
ASYNCEN1=don't care
ASYNCEN2=enable
Master FsoCKO
(Secondary)
LRCK
EXWCK (Primary)
FsiI
FsoI
EXWCK
Slave
Master
EXWCK
(Secondary)
LRCK
FsiI
FsoI
EXWCK
FsoCKO
(Secondary)
Slave
LRCK
LRCK
FsoI
FsiI
EXWCK
FsoI
FsiI
EXWCK
Slave
Slave
LRCK
FsiI
FsoI
EXWCK
LRCK
FsiI
FsoI
EXWCK
SACD-fsi Mode
ASYNCEN1=enableMaster : DSDCKIO=L
DSD128Fs/64Fs ASYNCEN2=enableSlave : DSDCKIO=L
(Primary)
Master FsoCKO
LRCK
(Secondary)
FsiI (Primary)
FsiI
FsoI
EXWCK
DSD128Fs/64Fs
(Primary)
Master
LRCK
FsiI (Primary)
Slave
LRCK
ASYNCEN1=enable Master : DSDCKIO=H
ASYNCEN2=enable Slave : DSDCKIO=L
FsoCKO
(Secondary)
FsiI
FsoI
EXWCK
Slave
LRCK
FsoI
FsoI
FsiI
EXWCK
FsiI
EXWCK
Slave
Slave
LRCK
FsoI
FsiI
EXWCK
LRCK
FsoI
FsiI
EXWCK
SACD-fso Mode
ASYNCEN1=don't care Master : DSDCKIO=L
ASYNCEN2=enable Slave : DSDCKIO=L
Master
LRCK
FsiI
FsoI
EXWCK
Slave
LRCK
FsoI
FsiI
EXWCK
ASYNCEN1=don't care Master : DSDCKIO=H
ASYNCEN2=enable
Slave : DSDCKIO=L
Master
DSD128Fs/64Fs
(Secondary)
LRCK
FsiI
FsoI
EXWCK
Slave
LRCK
FsoI
FsiI
EXWCK
Slave
Slave
LRCK
FsoI
FsiI
EXWCK
LRCK
FsoI
FsiI
EXWCK
Rev.1.00, Sep.04.2003, page 19 of 38
DSD128Fs/64Fs
(Secondary)
M65818AFP
The examples of a connection diagram
The case of the single use (2ch) in each input mode are shown in the following figure.
Normal Mode
LRCK (Primary)
ASYNCEN1=don't care
ASYNCEN2=enable
FsoCKO
LRCK
ASYNCEN1=don't care
ASYNCEN2=disable
LRCK (Primary)
FsiI
FsoI
EXWCK
LRCK
FsoI
FsiI
EXWCK
External 8fs Data Mode (The Case of Primary Side Synchronization)
ASYNCEN1=don't care
ASYNCEN2=enable
FsoCKO
LRCK
FsiI
FsoI
EXWCK
EXWCK (Primary)
ASYNCEN1=don't care
ASYNCEN2=disable
LRCK
EXWCK (Primary)
FsoI
FsiI
EXWCK
External 8fs Data Mode (The case of secondary side synchronization)
ASYNCEN1=don't care
ASYNCEN2=enable
EXWCK (Secondary)
FsoCKO
(Secondary)
LRCK
FsiI
FsoI
EXWCK
SACD-fsi Mode
DSD128Fs/64Fs
(Primary)
FsiI (Primary)
DSDCKIO=L
ASYNCEN1=enable
ASYNCEN2=enable
LRCK
FsoI
FsiI
EXWCK
DSD128Fs/64Fs
(Primary)
FsoCKO
DSDCKIO=H
ASYNCEN1=disable
ASYNCEN2=disable
LRCK
FsoI
FsiI
EXWCK
SACD-fso Mode
DSDCKIO=L
ASYNCEN1=don't care
ASYNCEN2=enable
LRCK
FsoI
FsiI
EXWCK
Rev.1.00, Sep.04.2003, page 20 of 38
DSDCKIO=H
ASYNCEN1=don't care
ASYNCEN2=disable
FsoCKO
DSD128Fs/64Fs
(Secondary)
LRCK
FsoI
FsiI
EXWCK
DSD128Fs/64Fs
(Secondary)
M65818AFP
5.11. OFLFLAG
71
OFLFLAG pin is output the 'over flow flag' in the operation. OFLFLAG pin outputs "H" level by detection of over
flow from Gain Control Block and others.
The "H" level width is over 0.6msec, so detection result is held.
5.12. OUTL1+, OUTL1-, OUTL2+, OUTL2-, OUTR1+, OUTR1-, OUTR2+, OUTR2OUTL1+, OUTL1-, OUTL2+, OUTL2-, OUTR1+, OUTR1-, OUTR2+, and OUTR2- pins are pulse output modulated
∆Σ output signal to PWM signal.
These pins are connected to external Power Driver ICs.
PWM Output Form 1, 2, 3 and 4 can be selected by serial control data(System1 mode:bit22,23 ).
PWM Output Form1 : General Modulation
PWM Output Form2 : Symmetrical Modulation
PWM Output Form3 : Modulation returned with time domain.
(The rise and fall edge of Lch and Rch in a term are reverse.)
PWM Output Form4: Modulation returned with time domain.
(The rise and fall edge of Lch and Rch in a term are same timing.)
In each 4 forms, the operating rate and bit length of PWM Output can be changed following the setting of ∆Σ And the output
mute function and the output pins reverse function, can be controlled by the pin setting or serial control.
The PWM output control is shown in the following table.
Item
Operation
Setting Operation
Output Form
Output Form Selection
1,2,3,4
Set up by the serial control system 1 mode
bit 22,23 (PWM MODE 0 and 1).
(Refer to Chapter 6.2. system 1 mode for details)
Operating Rate and Data
Bit Length
Select to
16fso/6bit ,16fso/5bit
,32fso/5bit from operating
rate and data bit length of
∆Σ.
PWM operation are
synchronized by this
setting.
Set up by the serial control system 2 mode bit16 and bit17.
(Refer to Chapter 6.3. system 2 mode for details.)
Output Muting
Duty 50% Mute
Set NSPMUTE pin "L" or set up by serial control System 2
mode bit14 (NSPMUTE) "H".
(Refer to Chapter 5.13.NSPMUTE pin description and
6.3.system2 mode for details)
Set PGMUTE pin "L" or set up by serial control system2 mode
bit15(PGMUTE) "H".
(Refer to Chapter 5.14.PGMUTE pin description and 6.3
system2 mode for details)
Set up by serial control system2 mode bit9
(CHSEL ).
Absolute Zero Mute
Reverse Output
Pins Function
Reverse on Lch and Rch
of output pins.
Reverse for OUTL1- and
OUTR1- of output pins.(
Output OUTL1+ /R1+
data to OUTL1- /OUTR1data.)
Rev.1.00, Sep.04.2003, page 21 of 38
Set up by serial control system1 mode bit124(PWMHP).
(Refer to Chapter 6.2. system1 mode for details.)
M65818AFP
5.13. NSPMUTE
39
NSPMUTE pin is input to make for PWM output to 50% duty mute.
"L": PWM output 50% duty Mute. '"H": Mute release.
5-14. PGMUTE
40
PGMUTE pin is input to make PWM output to absolute zero mute.
"L": PWM output mute.
The case of System1 mode:bit24,PWMHP = "L"
OUTL1 (+), OUTL2 (+), OUTR1 (+), OUTR2 (+) : "L" fixed
OUTL1 (-), OUTL2 (-), OUTR1 (-), OUTR2 (-) : "H" fixed
The case of System1 mode:bit24,PWMHP = "H"
OUTL1 (+), OUTL2 (+), OUTR1 (+), OUTR2 (+) ,OUTL1(-),OUTR1(-) : "L" fixed
OUTL2 (-), OUTR2 (-) : "H" fixed
"H": MUTE release.
5.15 INIT
41
INIT is the pin for reset to all functions of M65818AFP.
"L" level : (1). Clear of data memory. (2). Initialization of Serial Control.
(3). PWM output Duty 50 %.
"L" period needs more than 5 msec.
"H" level : usual operation.
"L">"H" rise edge: Resynchronization treatment, which is same at SYNC function.
5.16. TEST1, TEST2, TEST3
TEST1,TEST2, and TEST3 pins are test input for factory shipping test of M65818AFP.
TEST1,TEST2, and TEST3 pins must be tied to "L" level on usual operation.
5.17. Power Supply and GND
Power supply and GND routes have 5 isolated lines.
(1)VddL1+, VssL1+, VddL1-, VssL1-, VddL2+, VssL2+, VddL2-, VssL2-, VddR1+, VssR1+, VddR1-, VssR1-,
VddR2+, VssR2+, VddR2-, VssR2-, VssL, VddL, VssR, VddR
These pins are Power supply and GND for PWM output buffer block.
It has a pair of independent Power Supply, and GND to each 8 output pin. Power Supply voltage must be fixed at 5.0V.
(2)XVdd, XVss
27 29 30
These pins are Power supply and GND for XfsoIN clock input block.
Power Supply voltage must be fixed at 5.0V.
(3)XOVdd, XOVss
76 78
These pins are Power supply and GND for XfsoOUT clock output block.
Power Supply voltage must be fixed at 5.0V.
(4)DVdd, DVss
75 69
These pins are Power supply and GND for digital block and fixed input/output
buffer only for 3.3V (32,70-74 pins). Power Supply voltage must be fixed at 3.3V
Rev.1.00, Sep.04.2003, page 22 of 38
M65818AFP
(5)BFVdd, BFVss
58 68
These pins are Power supply and GND for input/output buffer (3.3V/5V ). In a case that BFVdd pin
is applied at 5.0V, input/output voltage level of 34-67pins becomes 5.0V signal level. In another case
that BFVdd pin is supplied at 3.3V, input/output pins (34-67 pins) becomes 3.3V signal level.
5.18. Power sequences
System power-on sequencing
* Refer to following figure.
System power-on sequencing
* Refer to following figure.
Power( Vddxxx,XVdd,
XOVdd, DVdd, BFVdd)
Power OFF Power ON
Master clock
( XfsoIN, XfsiIN)
INIT
SCDT
SCSHIFT
X
X
X
Over 5msec(*1)
Over 0sec(*2)
X
X
SCLATCH
Over 2/fso(*3)
*1 After a power supply and Master clock become to stable, INIT pin must be "L" over 5 msec.
*2 Data transfer is possible right after INIT release.
*3 Until SCLATCH is operated, a period over 2/fso ( fso=48kHz, over 42usec ) is necessary after INIT
release.
Rev.1.00, Sep.04.2003, page 23 of 38
M65818AFP
6. Serial Control
6.1. Gain Control Mode
No setting bits means "Don't care".
bit
Flag Name
Functional Explanation
1
2
MODE1
MODE2
3
4
H
L
INIT
Mode Setting 1
Mode Setting 2
"L" fixed
"L" fixed
TEST1
TEST2
Test Mode 1
Test Mode 2
"L" fixed
"L" fixed
L
L
5
6
NSLMT1
NSLMT2
Output Limit 1
Output Limit 1
Refer to Table 6-1-2.
7
GCONT1
L / R independence
L/R common
L
8
GCONT2
Channel selection for Gain
Control Block 1
Channel selection for Gain
Control Block 2
Lch
Rch
L
L
L
9
10
11
12
GAIN0
Gain Data Index (MSB)
H
13
14
GAIN1
GAIN2
Gain Data Index
Gain Data Index
L
L
15
16
GAIN3
GAIN4
Gain Data Index
Gain Data Index (LSB)
L
L
17
18
GAIN5
GAIN6
Gain Data Mantissa (MSB)
Gain Data Mantissa
H
L
19
20
GAIN7
GAIN8
Gain Data Mantissa
Gain Data Mantissa
L
L
21
22
GAIN9
GAIN10
Gain Data Mantissa
Gain Data Mantissa
L
L
23
24
GAIN11
GAIN12
Gain Data Mantissa
Gain Data Mantissa (LSB)
L
L
• Output Limit (bit5,bit6:NSLMT1 ,NSLMT2 )
The M65818AFP has Over Flow Limit function which detects by input signal level and limit gain control.
Limit value is set by Gain Control Mode :bit5,bit6 ”NSLMT1, NSLMT2” and System2 Mode:bit17"NSOBIT".
The limit value setting of Gain control block and PWM output.
Table (6-1-1a). Limit Value [In the case of 6bit mode, System2 mode:bit17(NSOBIT)="L"]
DSLMT1
DSLMT2
Gain Block
L
L
±0.9375
63 values (±31)
H
L
L
H
±0.90625
±0.875
61 values (±30)
59 values (±29)
H
H
±0.84375
57 values (±28)
Rev.1.00, Sep.04.2003, page 24 of 38
PWM Output (Limit Value from DS Block )
M65818AFP
Table (6-1-1b). Limit Value [In the case of 5bit mode System2 mode:bit17(NSOBIT)="H"]
DSLMT1
DSLMT2
Limit Value of Gain
PWM Output Value (Limit Value from ∆Σ Block)
L
H
L
L
±0.90625
±0.875
31 values (±15)
31 values (±15)
L
H
H
H
±0.84375
±0.8125
29 values (±14)
29 values (±14)
• Channel Selection for Gain Control Block (bit7,bit8:GCONT1 ,GCONT2 )
These bit selection enable to control gain data "L/R common" or "L/R independence".
GCONT1 :"L"…L/Rch common, "H"…L/Rch independence.
GCONT2 :"L"…Rch only, "H"…Lch only.
Bit8 is available only the case of `bit7 = "H"`.
• The index and Mantissa part of Gain Data. (bit12 -bit24,: GAIN0 -GAIN12 )
The Gain value is set from bit12 to bit24.
Index part: bit12 (MSB) to bit16(LSB)
Mantissa part: bit17 (MSB) to bit24 (LSB)
The Gain Data is assigned 13bits, composed of Index part 5bits and of Mantissa part 8bits,
The range of Index parts is following statements.
-16
Index part: 10100b(16.0) to 10000b(1.0) to 00000b( 2 )
The range of mantissa part is following as statement.
Index part; 10100b to 00001b: Mantissa part; 11111111b to 10000000b (128 step/1 Index).
Index part;00000b: Mantissa part; 11111111b to00000000b (256 step).
Initial value: Index part: 10000b Mantissa part:10000000b
infinity zero: Index part: 00000b Mantissa part:00000000b
# Notice of GAIN value Setting continuously
In the case of GAIN value Setting continuously, for example of Setting L/Rch independently, please take the interval
time (pulse interval time of SCLATCH signal) more than 1/fso.For example, in the case of fso=48kHz, please take the
interval time more than 21µsec.
• The Gain Data and Audio Output Level.
Gain data consists of 13bits (Index part; 5bit, Mantissa part; 8bit ).
e.g. 10000b(1.0)/10000000b(0.5) means 0.5(0dB).
Rev.1.00, Sep.04.2003, page 25 of 38
M65818AFP
Table (6-1-2). The Gain Data and Output Level
Gain Data
Polarity
Absolute Output Value
10100/11111111 (b)
to
10001/10000000 (b)
to
10000/10000000 (b)
+
01111/11111111 (b)
to
00000/10000000 (b)
to
00000/00000001 (b)
00000/00000000 (b)
Output Level
15.9375
to
1.0
to
0.5
+30.069dB
to
+6.021dB
to
0dB
0.498046875
to
-16
0.5*
to
0.00390625*2-16
infinity zero
-0.0340dB
to
-96.330dB
to
-138.474dB
-∞
• Calculation method of Gain value.
The way to calculation of Gain value from Gain Data is following equation.
Gain value = 20log [ 2
<Index data (decimal value)-16>
X
Mantissa data (decimal value)
128
• Soft Mute.
The Soft Mute function is executed by setting of Gain Data as 00000/00000000b
( "/" :means dividing point between index part and mantissa part).
The release from Soft Mute function must be executed by setting the gain data before soft mute.
The Soft Mute function and release from there don't have linear curve but
have characteristics of approximate exponential curve.
Output amplitude
16
0.5
T = xxxx/Fs(sec)
0
t
T
00000/00000000b
Rev.1.00, Sep.04.2003, page 26 of 38
\
T
10000/10000000b setting
]
dB
M65818AFP
• Operating time of Soft Mute
Total steps from Maximum value(10100b/11111111b) to Minimum value(00000b/00000000b)
(128steps/1 index) × (20index (10100b-10000b)) +256steps = 2816steps.
The transition term of up and down depend on 2fso clock.
Therefore, in case of fso=48kHz, T=1/2fso=10.416µsec/step, transition term are following.
From Maximum value (10100b/11111111b) to Minimum value (00000b/00000000b) : 2816T=29.333msec.
From 0dB value (10000b/10000000b) to Minimum value (00000b/0000000b) : 2304T=24msec
6dB transition term (when over 00000b/10000000b (=-96dB) value ) : 128T=1.333msec.
• Soft Attenuate.
Transition from older Gain Attenuation to newer Gain Attenuation always operates with Soft Mute function.
For example, in case of Gain1 > Gain3 > Gain2, transition process is shown below.
At first, GAIN1 is operated, then second, GAIN2 is operated.
In case that GAIN2 is operated faster than GAIN1 of transition completion (refer to "A" situation in figure)
GAIN1 is ignored and data approaches at GAIN2.
Further, GAIN3 is operated faster than GAIN2 of transition completion( Refer to "B" or "C" situation in figure),
GAIN2 is ignored and data approaches at GAIN3.
Gain
1.0
A
(GAIN1)
B
(GAIN3)
0
C
-1.0
(GAIN2)
t
Rev.1.00, Sep.04.2003, page 27 of 38
M65818AFP
6.2. System1 Mode
bit
Flag Name
Functional Explanation
H
L
INIT
1
2
MODE1
MODE2
Mode Setting 1
Mode Setting 2
"H" fixed
"L" fixed
3
4
IFMT0
IFMT1
Input Format Selection
Refer to Table 6-2-1.
L
L
5
6
IBIT0
IBIT1
Setting for Input Word Length
Refer to Table 6-2-2.
L
L
7
8
ISF0
ISF1
Input Sampling Rate Selection
Refer to Table 6-2-3.
L
L
9
EMPFS1
Fs selection for De-emphasis
Filter
Refer to Table 6-2-4.
L
10
EMPFS2
11
12
DF1IMUTE
DF2IMUTE
L
Zero Mute of DATA input
Zero Mute at sampling rate
converter input
Active
Active
Non-active
Non-active
L
13
14
don't care
don't care
15
16
don't care
enable
disable
L
PWM:duty 50%
L
Sync. by secondary
side
L
ASYNCEN1
synchronous Detection Flag for
Primary Side
17
18
don't care
don't care
19
20
ASYNC1MODE
Select process under
asynchronization in primary side
21
EXMODE
22
PWMMODE0
Mode select of external 8fs data
input
Selection of Output PWM Form
23
24
PWMMODE1
PWMHP
Reverse Phase of OUTL1-/R1-
don't care
Zero Mute
Sync. by primary
side
Refer to Table 6-2-5
Active
L
Non-active
Table 6-2-1 Input Format
bit
Flag Name
MSB First Left
Justified
3
4
IFMT0
IFMT1
L
L
2
MSB First Right
Justified
LSB First Right
Justified
IS
H
L
L
H
H
H
Table 6-2-2 Setting for Input Data Word Length
bit
Flag Name
16bit
20bit
24bit
Don't use
5
IBIT0
L
H
L
H
6
IBIT1
L
L
H
H
Table 6-2-3 Input Sampling Rate Selection (fsi: 32k to 48kHz 2fsi: 64k to 96kHz, 4fsi: 128k to 192kHz)
bit
Flag Name
fsi
2fsi
4fsi
7
ISF0
L
H
L
H
8
ISF1
L
L
H
H
Rev.1.00, Sep.04.2003, page 28 of 38
Don't use
L
L
M65818AFP
Table 6-2-4 Fs Selection for De-emphasis filter (De-emphasis is "ON" except for bit9=L and bit10=L)
bit
Flag Name
32.0K
44.1K
48.0K
OFF
9
10
EMPFS1
EMPFS2
H
H
L
H
H
L
L
L
Table 6-2-5 Selection of PWM Output form
bit
Flag Name
PWM Output
Form
PWM Output
Form
PWM Output
Form
PWM Output Form
22
23
PWMMODE0
PWMMODE1
L
L
H
L
L
H
H
H
*Output Form 2 is available only under following conditions.
MCKSEL="L" (Secondary Side Master Clock 1024fso) , Serial Control System2 mode,
bit17( NSOBIT) = "H" (5bit), bit16( NSSPEED) = "L" (16fso).
In case of the setting and release for PWM Output Form 2,
Refer to "The NOTE1 at setting PWM output Form 2" on next page.
• Selection of Input format (bit3,bit4:IFMT0,IFMT1)
Selection of Input format function is available only condition of `Normal` mode.
Refer to Table 6-2-1
Otherwise, Selection of Input format function is unavailable under conditions of `External 8fs Input`
and `SACD Input` modes (Interlocked with MODE1 and MODE2 pins).
Detail setting of `External 8fs Input` and `SACD` modes are shown in Chapter 5-4 and 5-5.
• Setting of Input Word Length (bit5,bit6:IBIT0,IBIT1).
2.
Setting of Input Data Word Length is available only MSB First Right Justified.
Refer to Table 6-2-
• Selection of Input Sampling Rate (bit7,bit8:ISF0,ISF1).
3.
Refer to Table 6-2-
• Fs Selection for De-emphasis Filter on/off (bit9, bit10 : EMPFS1, EMPFS2).
4.
(bit9,bit10): ("L","L")…
De-emphasis Filter is "off".
except ("L","L")… De-emphasis Filter on (Fs setting).
Refer to Table 6-2-
• Zero Mute at data input (bit11: DF1IMUTE).
DF1IMUTE :
"L"…Mute release.
"H"…Mute.
The input data from DATA pin under normal mode is muted in this setting.
• Zero Mute at Sampling Rate Converter Input (bi12: DF2IMUTE).
DF2IMUTE :
"L"…Mute release.
"H"…Mute.
DF2IMUTE is available for sampling rate converter input data.
DF2IMUTE executes zero mute of input data from DATA pin under condition of `Normal` mode and
from DSDL/DSDR pins under condition of `SACD-fsi ` mode.
Rev.1.00, Sep.04.2003, page 29 of 38
M65818AFP
• "Enable" of Primary Side Asynchronous Detection Flag (bi16: ASYNCEN1).
Bit16 controls "enable"/"disable" of primary-side-asynchronous-detection-circuit.
ASYNCEN1 :
"L"…disable.
"H"…enable.
Under condition of ASYNCEN1 ="L", primary side asynchronous detection is unavailable whether the clock is not
inputted to FsiI pin, thereby M65818AFP does not operate function under asynchronization, for instance mute
operation. However, Primary Side Asynchronous Detection is available only condition of `SACD-Fsi` mode.
• Selection of Muting operation at primary Side Asynchronous Detection (bit20:ASYNC1MODE)
"L" …Duty 50% Mute of PWM output at primary side asynchronous detection.
"H"… Input Zero Mute of the gain control at primary side asynchronous detection.
(PWM Output 50% Mute doesn't be operated in this setting.)
• Selection of Data Input Mode for external 8fs.(bit21: EXMODE)
"L"…A setup in case an external 8fs data input is secondary side synchronous.
(Data is inputted to Gain Control Block)
"H"…A setup in case an external 8fs data input is primary side synchronous.
(Data is inputted to Sampling Rate Converter Block)
• Selection of PWM output form (bit22, 23:PWMMODE 0 and 1)
5.
The selection of PWM output form 1, 2, 3, and 4 , refer to Chapter 5-12 for the details.
Refer to Table 6-2-
*NOTE1 : At the setting of PWM Output Form2
PWM Output Form2 enable to operate the following conditions.
bit17 NSOBIT) "H" (5bit), bit16(NSSPEED)="L"(16 fso)
Only in terminal MCKSEL="L" (secondary side master clock 1024 fso)
In the case of setting and release for PWM Output Form2, set both flags as follows.
• Serial Control System1 Mode, bit 22, 23 (PWMMODE0,1 )
• Serial Control System2 Mode: bit16 (NSSPEED), bit17 (NSOBIT)
<The case of the setting for PWM output form2>
(1) Set to Serial Control System2 mode : bit17(NSOBIT)="H"
bit16(NSSPEED )="L".
(To be set as MCKSEL="L" in advance is required.)
(2) Serial control System1 mode:bit22, 23(PWMMODE0,1)="H","L"
When a setup of both (1) and (2) is completed, it changes to Form2. When (2) is set up before (1), The term until
a setup of (1) holds the last PWM Output Form.
<The case of release for PWM output form2>
(1) Serial control System1 mode:bit22, bit 23 (PWMMODE 0 , 1) is set as the Form to be used.
(2) Serial Control System2 mode:bit17(NSOBIT),bit16(NSSPEED) is set the condition to be used.
When a setup of (1) is completed, PWM Output Form changes. When (2) is set up before (1), a term until a
setup of (1) is worked keeps the Form 2 in the state of serial control System2 mode:bit17(NSOBIT) ="H",
bit16(NSSPEED) ="L".
Rev.1.00, Sep.04.2003, page 30 of 38
M65818AFP
*NOTE2; Selection of PWM output form
Pay attention in selection and setting above-mentioned that a noise may occur by internal clock changes when setting of
MCKSEL pin is changed and the serial control System2 mode:
bit17 (NSOBIT) and bit16 (NSSPEED).
Since especially MCKSEL pin sets up an internal master clock, use with a fixed value recommended.
In changing MCKSEL, initialization with INIT pin and a re-setup of all the bits by serial control are needed after
changing MCKCEL.
• Reverse Phase of PWM Output OUTL1(-) / OUTR1(-) (bit24:PWMHP)
"L"…PWM Output OUTL1(-) / OUTR1(-) are reverse phase as the PWM output OUTL1(+) / OUTR1(+) .
"H"…PWM Output OUTL1(-) / OUTR1(-) are same phase as the PWM output OUTL1(+) / OUTR1(+) .
In this mode, the signal which added OUTL1(-) / OUTR1(-) and OUTL2(-) / R2(-) by external resistance can be
given to LPF / Headphone Amplifier.
6.3. System2 Mode (Secondary side)
bit
Flag Name
Functional Explanation
H
1
MODE1
Mode Setting 1
"H" fixed
2
3
MODE2
IMCKSEL
4
5
DSDFCO0
DSDFCO1
Mode Setting 2
Input Master Clock Selection
Filter Coefficient of Down
Sampling
6
SYNC
Resynchronization
7
XFsoOEN
8
ASYNCEN2
512fsi
L
INIT
"L" fixed
256fsi
L
Refer to Table 6-3-1.
L
L
L
XfsoOUT pin output "enable"
L->H :
Resynchronization.
disable
enable
L
Asynchronous Detection Flag for
enable
disable
L
secondary Side
9
CHSEL
L / R inversion of PWM
output
Active
Non-active
L
10
11
DRPOL
SRCRST
∆ΣBlock: Rch Input Phase
Negative-phase
Active
Positive-phase
Non-active
L
L
12
13
GIMUTE
don't care
Active
Non-active
L
14
NSPMUTE
Active
Non-active
L
15
PGMUTE
Zero Mute at Gain Control
Input Clock
Duty 50 percent Mute of
PWM Output
G_MUTE of PWM Output
Data
Active
Non-active
L
16
17
NSSPEED
NSOBIT
32fso
5 bits (31 value)
16fso
6 bits (63 value)
L
L
Negative-phase
Positive-phase
L
18
DCDRPOL
19
DCDSEL0
20
21
DSDSEL1
ACDRPOL
22
23
ACDSEL0
ACDSEL1
24
ACDSEL2
Sampling Rate Converter
Reset
∆Σ Block: Operation Speed
∆Σ Block: Setting of Output
Bit Number
∆Σ Block: Rch Phase of DC
dithering
∆ΣBlock: DC dithering
Selection
Refer to Table 6-3-2
∆Σ Block: Rch Phase of AC
Negative-phase
dithering
∆Σ Block: AC dithering
selection
Refer to Table 6-3-3
Rev.1.00, Sep.04.2003, page 31 of 38
L
Positive-phase
L
L
L
L
L
M65818AFP
Table 6-3-1 Setting of Down Sampling Filter Coefficient
bit
Flag Name
ROM1
ROM2
ROM3
ROM4
4
5
DSDFCO0
DSDFCO1
L
L
H
L
L
H
H
H
Table 6-3-2 DC dithering Selection at ∆Σ Block
bit
Flag Name
Non-dithering
DC dithering
0.1%
DC dithering
0.2%
DC dithering0.4%
19
20
DCDSEL0
DCDSEL1
L
L
H
L
L
H
H
H
Non-dithering
AC dithering A
AC dithering C
AC dithering E
L
Table 6-3-3 AC dithering Selection at ∆Σ Block
bit
Flag Name
22
ACDSEL0
don't care
L
L
23
ACDSEL1
L
H
L
H
24
ACDSEL2
L
L
H
H
Table 6-3-4 Setup Operating Rate & Bit Length of ∆Σ Block
bit
Flag / Pin
Name
16fso,6bit
16fso,5bit
16fso,5bit
32fso,5bit
16
17
NSSPEED
NSOBIT
L
L
L
H
X
X
H
H
pin
MCKSEL
L(Secondary
Clock1024fso)
L(Secondary
Clock1024fso)
L(Secondary
Clock512fso)
L(Secondary
Clock1024fso)
• Input Master Clock Selection (bit3:IMCKSEL).
"L":256fsi
"H":512fsi ("512fsi" are divided into half "256fsi" and operate as primary master clock.)
• Selection of Down Sampling Filter Coefficient for SACD input (bi4, bit5: DSFCO 0,DSFCO 1).
Refer to Table 6-3-1.
• Resynchronization (bit6: SYNC).
Resynchronization function is same at SYNC pin's function. Refer to Operation Explanation, Chapter 5.10.
Resynchronization process starts by SYNC rise edge,
therefore SYNC level must be fixed to "L" just before SYNC operation.
• "Enable" of XfsoOUT pin Output(bit7: XfsoOEN).
"L": Clock Output (enable), "H": L fixed (disable)
• Flag to "Enable" Asynchronous Detection for Secondary Block (bit8: ASYNCEN2).
ASYNCEN2 : "L"…disable.
"H"…enable.
Under condition of ASYNCEN2="L", secondary side asynchronous detection is in-effective under asynchronous
position, whether Fsol Clock is not inputted, there by M65818AFP does not operate function for instance mute
operation.
Rev.1.00, Sep.04.2003, page 32 of 38
M65818AFP
• Reverse Lch/Rch for PWM Output pins(bit9: CHSEL).
"L": Lch/Rch no reverse, "H": Lch/Rch reverse.
• ∆Σ: Rch Input Phase (bit10: DRPOL).
"L"…. Same phase ("Through")
"H"…..This setting makes ∆Σ Rch Input in reverse, further makes PWM block input phase reverse, ultimately
phase becomes positive phase ( Input pin and Output pin's phase is same).
• Sampling Rate Converter Block Reset (Initialize function) (bit11: SRCRST).
"L" …..normal operation
"H" to "L" edge…..Reset ( Initialize function)
• Zero Mute of Gain Control Input (bit13: GIMUTE).
"L"…Mute release, "H"…Mute.
• Duty 50% Mute of PWM Output (bit14: NSPMUTE).
Fixed PWM duty 50% Mute
"L"…..Mute release
"H"….. Mute
This function exists also in a pin by the same name.(This Mute function can be set either NSPMUTE flag or
NSPMUTE pin.)
• G-Mute for PWM Output Data (bit15: PGMUTE)
At G-MUTE flag = H , PGMUTE pin fixes each PWM Output as followings.
"L"….. Mute release "H"….. Fixed Mute for PWM Output (Fixed value as follows)
<Serial Control (System1 Mode :bit24) PWMHP="L" >
OUTL1(+) and OUTR1(+) ="L" , OUTL2(+) and OUTR2(+) = "L"
OUTL1(-) and OUTR1(-) ="H" , OUTL2(-) and OUTR2(-) = "H"
<Serial control (system1 mode; bit24) PWMHP="H">
OUTL1(+) and OUTR1(+) ="L" , OUTL2(+) and OUTR2(+) = "L"
OUTL1(-) and OUTR1(-) ="L" , OUTL2(-) and OUTR2(-) = "H"
This function exists also in a pin by the same name.(This Mute function can be set either PGMUTE flag or
PGMUTE pin.)
•
∆ΣBlock : operating rate (bit16: NSSPEED).
Refer to Table 6-3-4.
"L"…16fso
"H"…32fso *Enable only MCKSEL="L"(1024fso), NSOBIT="H" only.
(Except for this condition, Operating rate automatically becomes 16fso.)
•
∆Σ Block : The setting of bit length (bit17: NSOBIT).
Refer to Table 6-3-4.
NSOBIT selects bit length for ∆Σ operation. This is set by force as 5bit at MCKSEL="H".
"L"…6bit (63 value)
"H"…5bit (31value)
• ∆ΣBlock: DC dithering Rch Phase (bit18: DCDRPOL).
"L"…Same phase
"H"…Reverse phase
•
∆Σ Block: DC dithering Selection (bit19,bit20: DCDSEL0,DCDSEL1).
Rev.1.00, Sep.04.2003, page 33 of 38
Refer to Table 6-3-2.
M65818AFP
• ∆ΣBlock: AC dithering Rch Phase (bit21: ACDRPOL).
"L"…Same phase
"H"…Reverse phase
• ∆Σ Block: AC dithering Selection (bit22,bit23,bit24: ACDSEL0,ACDSEL1,ACDSEL2).
Refer to Table 6-3-3.
7.1. AC Characteristics Lists.
(Ta=25 °C, PWM Vdd=5V, DVdd=3.3V)
AC Characteristics
Parameter
Symbol
XfsoIN duty ratio
duty(XfsoIN)
XfsiIN duty ratio
duty(XfsiIN)
SCSHIFT pulse time
Conditions
Min.
Typ.
Max.
Units
40
50
60
%
512fsi
30
50
70
%
256fsi
40
160
50
60
tw(SCSHIFT)
nsec
nsec
SCDT setup time
SCDT hold time
tsu(SCDT)
th(SCDT)
80
80
nsec
nsec
SCLATCH pulse width
SCLATCH setup time
tw(SCLATCH)
tsu(SCLATCH)
160
160
nsec
nsec
SCLATCH hold time
BCK pulse width
th(SCLATCH)
tw(BCK)
160
35
nsec
nsec
DATA setup time
DATA hold time
tsu(DATA)
th(DATA)
20
20
nsec
nsec
LRCK setup time
LRCK hold time
tsu(LRCK)
th(LRCK)
20
20
nsec
nsec
EXBCK pulse time
EXWCK setup time
tw(EXBCK)
tsu(EXWCK)
35
20
nsec
nsec
EXWCK hold time
EXDATA L / R setup time
th(EXWCK)
tsu(EXDATA)
20
20
nsec
nsec
EXDATA L / R hold time
EXDATA L / R output delay time
th(EXDATA)
tpd(EXDATA)
EXWCK output delay time
DSD128fs pulse width
tpd(EXWCK)
tw(DSDCK128)
DSD64fs pulse width
DSD64fs setup time
tw(DSDCK64)
tsu(DSDCK64)
DSD64fs hold time
DSD L / R setup time
th(DSDCK64)
tsu(DATA)
DSD L / R hold time
SYNC pulse width
th(DATA)
tw(SYNC)
Rev.1.00, Sep.04.2003, page 34 of 38
20
Output load capacity 10 [pF]
1.0
Output load capacity 10 [pF]
1.0
nsec
nsec
70
nsec
nsec
mode 1, 3
140
40
nsec
nsec
mode 1, 3
mode 1, 2, 3, and 4
40
40
nsec
nsec
mode 1, 2, 3, and 4
40
160
nsec
nsec
M65818AFP
7.2. AC Characteristics Timing Chart
(1) XfsoIN, XfsiIN Duty Ratio
twhl
twh
twl
duty (XfsoIN,XfiIN) =
twh
twhl
(2) SCSHIFT, SCDT, SCLATCH input timing Chart
tw(SCSHIFT)
SCSHIFT
tsu(SCDT)
tw(SCSHIFT)
th(SCDT)
SCDT
tw(SCLATCH)
SCLATCH
tsu(SCLATCH)
th(SCLATCH)
(3) BCK, DATA, and LRCK Input timing Chart
tw(BCK)
tw(BCK)
BCK
tsu(DATA)
th(DATA)
DATA
th(LRCK)
tsu(LRCK)
LRCK
(4) EXBCK, EXDATAL, EXDATAR, EXWCK input timing Chart
tw(EXBCK)
tw(EXBCK)
EXBCK
tsu(EXDATA)
EXDATAL
EXDATAR
th(EXDATA)
th(EXWCK)
EXWCK
(5) EXBCK, EXDATAL, EXDATAR, EXWCK output timing Chart
tw(EXBCK)
tw(EXBCK)
EXBCK
EXDATAL
EXDATAR
tpd(EXDATA)
tpd(EXWCK)
EXWCK
Rev.1.00, Sep.04.2003, page 35 of 38
tsu(EXWCK)
M65818AFP
(6) DSD64Fs, DSD128Fs, DSDL, DSDR Input Timing Chart
mode1
tw(DSDCK128)
tw(DSDCK128)
DSD128Fs
tw(DSDCK64)
tsu(DSDCK64)
DSD64Fs
tsu(DATA)
tw(DSDCK64)
th(DSDCK64)
th(DATA)
DSDL
DSDR
mode2
tw(DSDCK64)
tw(DSDCK64)
DSD64Fs
tsu(DATA)
th(DATA)
DSDL
DSDR
mode3
tw(DSDCK128) tw(DSDCK128)
DSD128FS
tw(DSDCK64)
tw(DSDCK64)
tsu(DSDCK64)
th(DSDCK64)
tsu(DATA)
th(DATA)
DSD64Fs
DSDL
DSDR
mode4
tw(DSDCK64)
tw(DSDCK64)
tsu(DATA)
th(DATA)
DSD64Fs
DSDL
DSDR
Rev.1.00, Sep.04.2003, page 36 of 38
M65818AFP
8. Application Example
External 8fs Data
Input: External Sampling
Rate Converter
Output: External DAC
DSP
SACD
Decoder
E
X
D
A
T
A
(Primary Side Clock)L
LRCK
BCK
DATA
XfsiIN
E
X
D
A
T
A
R
E
X
B
C
K
External 8FsData Input/Output Setting
L: Input H: Output
E
X
W
C
K
E
X
I
O
S
E
L
MCKSEL
XFsoIN
(Secondary Side Clock)
Select shift clock I/O for DSD
L: Input
H: Output
Oscillator
XFsoOUT
DSD128FS
DSD64Fs
DSDR
DSDL
FsiI
Secondary Clock Output
OUTL1+
OUTL1OUTL2+
OUTL2-
(Clock for a primary side synchronization)
Set Timing 1
SACD Interface
Set Timing 2
SACD Interface
Set Secondary Clock
L:1024Fso H:512Fso
Power
Driver
DSDCKSEL1
DSDCKSEL2
M65818AFP
DSDCKIO
OUTR1+
OUTR1OUTR2+
Power
Driver
OUTR2-
MCU
Initialize
Mute Input
Re-Synchronization
Set Input Mode1
Set Input Mode 2
SCDT
SCSHIFT
SCLATCH
FsoCKO
FsoI
INIT
PGMUTE
NSPMUTE
SYNC
MODE1
MODE2
T
E
S
T
1
T
E
S
T
2
T
E
S
T
3
O
F
L
F
L
A
G
S
F
L
A
G
Flag Output
Rev.1.00, Sep.04.2003, page 37 of 38
Clock for a secondary side synchronization
(for Multi channel use)
CKCTL1
CKCTL2
Set Secondary Clock 1
Set Secondary Clock 2
CKOUT1
CKOUT2
Secondary Clock Output 1
CKOUT3
Secondary Clock Output 3
Secondary Clock Output 2
y
e
b
40
x
41
24
65
64
25
HD
D
JEDEC Code
—
1
80
EIAJ Package Code
QFP80-P-1420-0.80
E
M
F
Weight(g)
1.58
A
Detail F
Lead Material
Alloy 42
L1
c
L
b2
I2
MD
ME
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
x
y
Dimension in Millimeters
Min
Nom
Max
—
—
3.05
0.1
0.2
0
2.8
—
—
0.3
0.35
0.45
0.13
0.15
0.2
13.8
14.0
14.2
19.8
20.0
20.2
0.8
—
—
16.5
16.8
17.1
22.5
22.8
23.1
0.4
0.6
0.8
1.4
—
—
—
—
0.2
0.1
—
—
0˚
10˚
—
0.5
—
—
1.3
—
—
14.6
—
—
—
—
20.6
Recommended Mount Pad
Symbol
I2
MD
Plastic 80pin 14✕20mm body QFP
e
b2
MMP
A2
Rev.1.00, Sep.04.2003, page 38 of 38
A1
ME
80P6N-A
M65818AFP
Package Dimensions
HE
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of
nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they
do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party.
2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts,
programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these
materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers
contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed
herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page
(http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information
as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage,
liability or other loss resulting from the information contained herein.
5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially
at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained
herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be
imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.
http://www.renesas.com
© 2003. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon 0.0