E2F0026-29-63
¡ Semiconductor
MSM7653
¡ Semiconductor
This version: Jun.
1999
MSM7653
Previous version: Jun. 1998
NTSC/PAL Digital Video Encoder
GENERAL DESCRIPTION
The MSM7653 is a digital NTSC/PAL encoder. By inputting digital image data conforming to
ITU Rec. 656 or ITURBT 601, it outputs selected analog composite video signals, analog S video
signals. For the scanning system, interlaced or noninterlaced mode can be selected.
Since the MSM7653 is provided with pins dedicated to overlay function, text and graphics can
be superimposed on a video signal.
In addition, this encoder has an internal 10-bit DAC. So, when compared with using a conventional
analog encoder, the number of components, the board space, and points of adjustment can
greatly be reduced, thereby realizing a low cost and high-accuracy system.
The MSM7653 provides the optional functions such as Macrovision Rev. 7.01 (note 1) (note 2) and
Closed Caption Signal Generation Function.
The host interface provided conforms to Philips's I2C specifications, which reduces
interconnections between this encoder and mounting components.
The internal synchronization signal generator (SSG) allows the MSM7653 to operate in master
mode.
FEATURES
• Video signal system: NTSC/PAL
• Scanning system: interlaced/noninterlaced (NTSC : 262 lines/PAL : 312 lines)
• Input digital level: conforms to ITU-R601 (CCIR601)
• Input-output timing: conforms to ITU Rec. 656 or ITURBT 624-4
• Input signal sampling ratio : Y:Cb:Cr = 4:2:2
• Supported input formats
· ITU Rec. 656
· YCbCr 27 MHz format (8-bit input)
· ITU-R601 13.5 MHz (8-bit (Y) + 8-bit (CbCr) input)
• Sampling frequency : 27 MHz
• Internal SSG circuit (Can operate as a master in other operation modes than CCIR Rec. 656
mode)
• Internal 3ch 10-bit DAC
• 3-bit title graphics can be displayed
• Color bar function
• I2C-bus host interface function
• 3.3 V single power supply (each I/O pin is 5 V tolerable)
• Closed caption function
• Macrovision Rev. 7.01
• Package
56-pin plastic QFP (QFP56-P-910-0.65-2K)
(Product name: MSM7653GS-2K)
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¡ Semiconductor
MSM7653
APPLICATIONS
• Set top box
• DVD
• Digital VTR
(Note 1) This device is protected by U.S. Patent numbers 4631603, 4577216 and 4819098 and
other intellectual property rights. The use of Macrovision Corporation's copy protection
technology in the device must be authorized by Macrovision and is intended for home
and other limited pay-per-view uses only, unless otherwise authorized in writing by
Macrovision. Reverse engineering or disassembly is prohibited.
(Note 2) This data sheet does not describe the register setting method of implementing
Macrovision Corporation's anticopy function that this device provides.
Refer to MACROVISION ANTICOPY FUNCTION SETTING MANUAL for the
anticopy function.
2/35
OLC
OLR
OLG
OLB
YUV color
Generator
Y Level
converter
YD[7:0]
CD[7:0]
U Level
converter
Prologue
Block
Black &
Blank Pedestal
Overlay
Control
VSYNC_L
HSYNC_L
BLANK_L
CLKX2
DAC
YA
DAC
CVBSO
DAC
CA
Interpolator
+ LPF
Interpolator
+ LPF
V Level
converter
Anticopy
Function
Block
IPF
IPF
Color Burst
Generator
Closed
Caption
Block
Subcarrier
Generator
IPF
VREF
IPF = Interpolation Filter
Sync Generator & Timing Controller
¡ Semiconductor
BLOCK DIAGRAM
RESET_L
2
I C Control logic
FS
Test Control logic
COMP
SEL[2:1]
MS
MODE
CLKX1O CLKSEL
SCL SDA ADRS
TENB TEST1
OUTSEL
MSM7653
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¡ Semiconductor
MSM7653
43 DGND
44 TEST1
45 TENB
46 VREF
47 FS
48 COMP
49 AGND
50 CA
51 AVDD
52 CVBSO
53 AGND
54 YA
55 AVDD
56 DGND
PIN CONFIGURATION (TOP VIEW)
DVDD
1
42 DVDD
MS
2
41 SEL2
SDA
3
40 SEL1
SCL
4
39 CLKSEL
ADRS
5
38 CD0
RESET_L
6
37 CD1
MODE
7
36 CD2
OLC
8
35 CD3
OLR
9
34 CD4
OLG 10
33 CD5
OLB 11
32 CD6
CLKX1O 12
31 CD7
OUTSEL 13
30 CLKX2
DGND 28
YD0 27
YD1 26
YD2 25
YD3 24
YD4 23
YD5 22
NC 21
YD6 20
YD7 19
BLANK_L 18
HSYNC_L 17
VSYNC_L 16
29 DVDD
DGND 15
DVDD 14
NC : No-connection pin
56-Pin Plastic QFP
4/35
¡ Semiconductor
MSM7653
PIN DESCRIPTIONS (1/2)
Pin
I/O
1
Symbol
DVDD
Description
3.3 V digital power supply
2
I
MS
Selects between Master and Slave at 27 MHz or 13.5 MHz YCbCr operation. Pulled down
3
I/O
SDA
I2C interface data bus
4
I
SCL
I2C interface clock bus
5
I
ADRS
6
I
RESET_L
7
I
MODE
8
I
OLC
Transparent control signal. "1" indicates overlay signal. Normally fixed to "0".
9
I
OLR
Overlay text color (Red component). Normally fixed to "0".
10
I
OLG
Overlay text color (Green component). Normally fixed to "0".
I2C-bus Slave address setting pin ("0" : 1001100 / "1" : 1001110).
Pulled down
System reset signal. Negative porality
Broadcasting mode select pin. "0" : NTSC/"1" : PAL. Pulled down
Overlay text color (Blue component). Normally fixed to "0".
11
I
OLB
12
O
CLKX1O
13.5 MHz divided clock output signal
13
I
OUTSEL
Normally fixed to "0". Pulled down
14
DVDD
3.3 V digital power supply
15
DGND
Digital GND
16
I/O
VSYNC_L
17
I/O
HSYNC_L
18
I
BLANK_L
Vertical sync signal input/output pin (ITU656: O, YCbCr: I/O)
Negative polarity
Horizontal signal input/output pin (ITU656 : O, YCbCr: I/O)
Negative polarity
Composite blank signal. Negative polarity. See the description on page 15
for the operating requirement.
MSB 2 bits of 8-bit digital image data input pins (for ITU656 and
YCbCr 27 MHz). Level conforms to ITU-601.
19, 20
I
YD7 to YD6
MSB 2 bits of 8-bit digital image luminance signal input pins (for YCbCr).
Level conforms to ITU-601.
YD7 is MSB.
21
NC
Not connected
LSB 6 bits of 8-bit digital image data input pins (for ITU656 and
YCbCr 27 MHz). Level conforms to ITU-601.
22 to 27
I
YD5 to YD0
LSB 6 bits of 8-bit digital image luminance signal input pins (for YCbCr).
Level conforms to ITU-601.
YD0 is LSB.
28
DGND
Digital GND
29
DVDD
3.3 V digital power supply
Clock input pin (27 MHz)
30
I
CLKX2
31 to 38
I/O
CD7 to CD0
39
I
CLKSEL
8bit digital image chrominance signal data input pins (13.5 MHz mode).
Level conforms to ITU-601. Fixed to "0" for ITU Rec. 656, 27 MHz-YCbCr mode.
Operation mode select pin. "0" : 27 MHz mode / "1" : 13.5 MHz mode.
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¡ Semiconductor
MSM7653
PIN DESCRIPTIONS (2/2)
Pin
I/O
Symbol
Description
40
I
SEL1
41
I
SEL2
Interface select pin. ITU656 : "0", YCbCr 27 MHz : "1" (See Page 32 for details)
Pulled down
42
DVDD
3.3 V digital power supply
43
DGND
Digital GND
Enable pin. Normally fixed to "0". Sleep mode "1" with TEST1 = "0"
(See Page 32 for details)
44
I
TEST1
Input pin1 for testing. Normally fixed to "0". (See Page 32 for details)
Pulled down
45
I
TENB
Input pin2 for testing. Normally fixed to "0".
Pulled down
46
I/O
VREF
Reference voltage for DAC
47
I
FS
48
I
COMP
49
50
AGND
Analog GND
CA
O
CVBSO
Analog composite signal output pin.
AGND
Analog GND
AVDD
53
54
DAC phase complement pin.
O
51
52
DAC full scale adjustment pin.
O
YA
Analog color chrominance signal output pin.
3.3 V analog power supply
Analog luminance signal output pin.
55
AVDD
3.3 V analog power supply
56
DGND
Digital GND
6/35
¡ Semiconductor
MSM7653
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Condition
Rating
DVDD
—
–0.3 to +4.5
AVDD
—
–0.3 to +4.5
Input Voltage
VI
DVDD = 3.3 V
–0.3 to +5.5
V
Analog Output Current
IO
—
50
mA
Power Consumption
PW
—
600
mW
Storage Temperature
TSTG
—
–55 to +150
°C
Power Supply Voltage
Unit
V
RECOMMENDED OPERATING CONDITIONS
Symbol
Condition
Min.
Typ.
Max.
DVDD
—
3.0
3.3
3.6
AVDD
—
3.0
3.3
3.6
"H" Level Input Voltage
VIH
—
—
V
VIL
—
—
2.2
"L" Level Input Voltage
—
—
0.8
V
Operating Temperature 1
Ta1
DVDD = AVDD = 3.3 V
0
25
70
˚C
0
25
65
˚C
—
1.25
—
V
Parameter
Power Supply Voltage (*1)
Operating Temperature 2
Ta2
DVDD = AVDD = 3.3 V
DA output load = 37.5 W
DVDD = AVDD = 3.3 V,
Unit
V
External Reference Voltage
Vrefex
DA Current Setting Resistance
Riadj
(*2)
—
385
—
W
RL
(*3)
—
75
—
W
DA Output Load Resistance
(*1)
(*2)
(*3)
Ta = 25˚C
Supply an equal voltage to both DVDD and AVDD.
A volume control resistor of approx. 500 W is recommendable for adjusting the output
current. When a DA converter analog output is terminated with a 37.5 W load, Riadj
= approx. 192 W.
Indicates the value when Riadj = 385 W (typical value).
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¡ Semiconductor
MSM7653
ELECTRICAL CHARACTERISTICS
DC Characteristics
(Ta = 0 to 70°C, DVDD = 3.3 V ±0.3 V, AVDD = 3.3 V ±0.3 V)
Parameter
"H" Level Output Voltage
"L" Level Output Voltage
Symbol
Condition
Min.
Typ.
Max.
Unit
VOH
IOH = –4 mA (*1)
0.7VDD
—
—
V
—
—
0.4
V
VOL
IOL = 4 mA (*1)
IOL = 6 mA (*2)
Input Leakage Current
II
VI = GND to DVDD
–10
—
+10
mA
Output Leakage Current
IO
VI = GND to DVDD (*3)
–10
—
+10
mA
—
—
120
140
mA
—
60
65
mA
mA
Power Supply Current (operating)
IDDO
RESET_L = "L"
Power Supply Current (standby)
IDDS
Power Supply Current (Sleep mode)
IDDSM
SEL2 = "H"
0.03
0.05
0.5
I2C-bus
CLKX2 = 0 MHz
SDA Output Voltage
SDAVL
Low level, IOL = 3 mA
0
—
0.4
V
I2C-bus SDA Output Current
SDAIO
During Acknowledge
3
—
—
mA
Internal Reference Voltage
Vrefin
—
—
1.25
—
DA Output Load Resistance
RL
—
V
W
75
Integral Linearity
SINL
—
±2
LSB
Differential Linearity
SDNL
—
±1
LSB
(*1)
(*2)
(*3)
VSYNC_L, HSYNC_L, CD[7:0]
CLKX1O
SDA
AC Characteristics
(Ta = 0 to 70°C, DVDD = 3.3 V ±0.3 V, AVDD = 3.3 V ±0.3 V)
Parameter
Symbol
Condition
Min.
CLKX2 Cycle Time
TS
—
—
37.0
—
ns
Input Data Setup Time
ts1
—
7
—
—
ns
Input Data Hold Time
th1
—
5
—
—
ns
Output Delay Time
td1
—
5
—
25
ns
Unit
5
—
25
ns
I2C-bus Clock Cycle Time
tC_SCL
Rpull_up = 4.7 kW
200
—
—
ns
I2C-bus High Level Cycle
tH_SCL
Rpull_up = 4.7 kW
100
—
—
ns
I2C-bus Low Level Cycle
tL_SCL
Rpull_up = 4.7 kW
100
—
—
ns
CLKX1O Delay Time
td2
—
Typ. Max.
8/35
¡ Semiconductor
INPUT/OUTPUT TIMING
,
MSM7653
Input timing
TS
CLKX2
ts1
HSYNC_L,
VSYNC_L, BLANK_L,
YD, CD, MS, MODE,
OLR, OLG, OLB, OLC
Invalid data
th1
Output timing
HSYNC_L, VSYNC_L
td1
CLKX1O
valid data
td2
I2C-bus Interface Input/Output Timing
The following figure shows I2C-bus basic input/output timing.
SDA
SCL
MSB
S
1
2
7
Start Condition
Data Line Stable: Data Valid Change of Data Allowed
8
9
ACK
tC_SCL
1
2
3-8
tL_SCL
9
ACK
P
Stop Condition
tH_SCL
I2C-bus Basic Input/Output Timing
9/35
¡ Semiconductor
MSM7653
BLOCK FUNCTIONAL DESCRIPTION
1. Prologue Block
This block separates input data at the ITU Rec.656 format into a luminance signal (Y) and a
chrominance signal (Cb & Cr), and also generates information/concerning sync signals
HSYNC_L, VSYNC_L, and BLANK_L.
This block separates input data at the 27 MHz YCbCr (8-bit input) format into a luminance
signal (Y) and a chrominance signal (Cb & Cr).
This block separates input data at the 13.5 MHz YCbCr (16-bit input) format into a chrominance
signal Cb and a chrominance signal Cr.
Of the processed input data, luminance and chrominance signals other than valid pixel data
are replaced by 8'h10 and 8'h80 respectively.
2. Y Limiter Block
This block limits the luminance input signal by clipping the lower limit of an input signal outside
the ITU601 Standard
• Signals are limited to YD = 16 when YD < 16.
• Signals are limited to TD = 254 when YD (input during a valid pixel period) = 255.
In other cases, signals are fed as is to next processing.
3. C Limiter Block
This block limits the chrominance signal by clipping the upper and lower limits of the input
signal outside the ITU601 Standard.
CD = 1 when CD = 0 is input during a valid pixel period.
CD = 254 when CD = 255 is input during a valid pixel period.
• Y Level Converter
Converts ITU-601 standard luminance signal level to DAC digital input level.
• U Level Converter
Converts ITU-601 standard chrominance signal level to DAC digital input level.
• V Level Converter
Converts ITU-601 standard chrominance signal level to DAC digital input level.
• YUV Color Generator
This block generates luminance and chrominance signals from over lay color signals OLR,
OLG and OLB. Control signals (CR [2:0] ) control the output content (overlay or color bar) and
output level (100%, 75%, 50%, 25%).
• Overlay Control
This block selects input image data or YUV Color Generator output signals.
It is determined by the level of the control signal (OLC, CR [2]), as shown below: (x : don't care)
CR [2] = 1, OLC = x: Selects color bar signal (YUV Color Generator output signal).
CR [2] = 0, OLC = 1: Selects overlay signal (YUV Color Generator output signal).
CR [2] = 0, OLC = 0: Selects input image data.
10/35
¡ Semiconductor
MSM7653
• Black & Blank Pedestal
This block adds sync signals at the luminance side to luminance signals.
• Interpolator + LPF
This block executes data interpolation and the elimination of high frequency components by
LPF for input chrominance signals.
• I2C Control Logic
This is the serial interface block based on I2C standard of Phillips Corporation.
Internal registers MR and CR can be set from the master side.
When writing to the internal registers other than MR [2] (black level control) and CR [1:0]
(overlay level), written contents are immediately set to them. It is during the vertical blanking
period that written contents are set to MR [2] and CR [1:0].
• Sync Generator & Timing Controller
This block generates sync signals and control signals.
This block operates in slave mode, which performs external synchronization, and in master
mode, which internally generates sync signals.
• Color Burst Generator
Outputs U and V components of amplitude of burst signals.
• Subcarrier Generator
Executes color subcarrier generation.
• Interpolation Filter (IPF)
This block performs upsampling at CLKX2 (double speed CLKX1) for luminance signals and
chrominance signals modulated with CLKX1. Interpolation processing is executed in this
process.
• Closed Caption Block
This block generates the signal for closed caption.
• Anticopy Function Block
This block generates a macrovision anticopy signal.
11/35
¡ Semiconductor
MSM7653
INPUT DATA FORMAT
The signal level specified by the ITU601 is input.
When other signal levels than specified by the ITU601 are input, the luminance signal level is
clipped to 16 to 254 and the chrominance signal level to 1 to 254.
For chrominance signal input, the offset binary and 2's complement formats are available by
setting of internal registers.
Digital Level
Digital Level
100% White level
235
240(112)
128(0)
Black Level
16
16(–112)
Y data
C data
Input luminance signal level
Input chrominance signal level
Basic Pixel Sampling Ratio
4:2:2 is supported.
CLKX1
YD
Y1
Y2
Y3
Y4
Y5
Y6
CD
Cb1
Cr1
Cb3
Cr3
Cb5
Cr5
4:2:2 sampling
at 8bit Y/8bit CbCr input
12/35
¡ Semiconductor
MSM7653
INPUT TIMING (ITUR656 input)
The input data is fed in the encoder at the rising edge of a clock pulse.
CLKX2
DATA
SAV(1st) SAV(2nd) SAV(3rd) SAV(4th)
Cb0
Y00
Cr0
Y01
Cb1
Y10
Cr1
Y11
EAV(1st) EAV(2nd) EAV(3rd) EAV(4th)
CLKX1O
OLR, OLG,
OLB, OLC
don't care
don't care
VALID DATA
Input Timing
RELATIONSHIP BETWEEN BLANK SIGNAL AND INPUT IMAGE DATA
The blank signal is generated by the ITU Rec.656 standard input data. The input image data is
valid when the blank signal is "H".
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¡ Semiconductor
MSM7653
VALID DATA RANGE
According to the ITU Rec.656 standard, the pixel data immediately from SAV (4th word) to a
fixed value before EVA is valid.
The following figure shows the relationship between the input data at the CCIR Rec.656 format
and the sync, luminance, chrominance signals which are processed inside the encoder.
Note) The values in parenthesis indicate values in PAL mode.
1716Tclkx2 (NTSC)/1728clkx2 (PAL)
ITU Rec.656 standard input data
4Tclkx2
11Tclkx1 (4Tclkx1)
Cb0, Y00, Cr0, Y01, Cb1, Y10, Cr1, Y11....
EAV
EAV
SAV
1440T (NTSC/PAL)
4Tclkx2
Sync signal VSYNC_L (0H)
generated by input signal
Sync signal VSYNC_L (1/2)
generated by input signal
63Tclkx1 (63Tclkx1) <Normal>
67Tclkx1 (67Tclkx1) <Colorstripe>
1/2H
4Tclkx1
(4Tclkx1)
Sync signal HSYNC_L generated
by input data
9Tclkx1 (16Tclkx1)
127Tclkx1 (142Tclkx1)
711Tclkx1 (702Tclkx1)
20Tclkx1 (20Tclkx1)
711Tclkx1 (702Tclkx1)
20Tclkx1 (20Tclkx1)
136Tclkx1 (146Tclkx1)
Sync signal BLANK_L generated
by input data
127Tclkx1 (142Tclkx1)
BLANK_L internally generated to
assure the horizontal and vertical
periods
Luminance signal separated from
input data
8'h10
Y00 Y01 Y10 Y11
8'h10
Chrominance signal separated
from input data
8'h80
Cb0 Cr0 Cb1 Cr1
8'h80
1H
Composite signal
Relationship between input data and sync signal, luminance signal, chrominance signals
14/35
¡ Semiconductor
MSM7653
CLOCK TIMING2 (8bit Y/8bit CbCr input)
Input Data Timing
Input data and sync signals are fed into the encoder at the rising edge of CLKX2.
Input data is handled as valid pixel data when tSTART passes after the falling edge of HSYNC_L.
Chrominance signal of input data at this time is regarded as Cb.
ACTIVE VIDEO LINE
tACT
tSTART
CLKX2
HSYNC_L
YD, CD,
OLR, OLB,
OLG, OLC
ts1
th1
don't care
don't care
VALID DATA
BLANK_L
Video data input timing
Input data is recognized as valid pixel data when input signal BLANK_L is "H" in the tACT period.
When BLANK_L is "H" during the blanking period, however, input data is not output as valid
pixel data since processing to maintain blanking period is internally in-progress.
The values of tSTART differ slightly between in master mode and in slave mode. The values of
tSTART are as follows.
In YCbCr format input mode, the values of tSTART are the same, in 8 bit (Y) + 8 bit (CbCr) mode
or in 8 bit (YCbCr) mode.
In master mode
Operation mode
In slave mode
tSTA(Ts)
Operation mode
tSTA(Ts)
ITU 601 NTSC
250
ITU 601 NTSC
260
ITU 601 PAL
280
ITU 601 PAL
290
tSTA – tS1 = tSTART
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¡ Semiconductor
MSM7653
Timing of Input Data to HSYNC_L
CLKX2
CLKX1O
HSYNC_L
OLR,OLG, OLB, OLC
Invalid Data
YD
Invalid Data
Invalid Data
Invalid Data
Cb0
Valid Data
Y00
Cr0
tSTART
Y01
Cb1
Y10
Cr0
Y01
Cb1
tACT
Input Timing when BLANK_L is Input
CLKX2
BLANK_L
YD
Cb0
Y00
Input timing at 27 MHz in YCbCr format
Timing of Input Data to HSYNC_L
CLKX2
CLKX1O
HSYNC_L
OLR,OLG, OLB, OLC
Invalid Data
YD
Invalid Data
Invalid Data
Y0
Y1
Y2
CD
Invalid Data
Invalid Data
Cb0
Cr0
Cb1
Invalid Data
Valid Data
tACT
tSTART
Input Timing when BLANK_L is Input
CLKX2
BLANK_L
YD
Y0
Y1
Y2
CD
Cb0
Cr0
Cb1
Input timing at 13.5 MHz in YCbCr format
16/35
¡ Semiconductor
MSM7653
Internal Synchronization Output Timing
Output timing of HSYNC_L and VSYNC_L in master mode is as follows.
CLKX2
td1
td1
HSYNC_L
VSYNC_L
Output timing of internal synchronization, HSYNC_L and VSYNC_L
VSYNC_L
YA
523
524
525
1
2
3
4
5
6
7
17
18
Output timing of internal synchronization VSYNC_L
17/35
¡ Semiconductor
MSM7653
OUTPUT FORMAT
The timing conforms to the ITU624 standard.
In the NTSC operation mode, the existence/non-existence of setup level is selected by setting of
internal regsiters.
Data level on the DAC input terminal:
When the contents of 100% luminance order color bar are input into the encoder, the input level
is as follows.
DAC data Lumi (IRE)
Composite Wave Form (NTSC)
Yellow
White
957
133
775
100
715
89
610
70
549
59
450
41
390
338
285
266
224
30
20
11
7.5
0
114
–20
4
–40
Green
Cyan
Red
Magenta
Black
Blue
NTSC Composite Signal (Setup 7.5)
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¡ Semiconductor
DAC data Lumi (IRE)
MSM7653
Y Wave Form (NTSC)
White
775
100
715
89
610
70
549
59
450
41
390
30
285
11
224
0
4
–40
Cyan
Yellow
Magenta
Green
Blue
Red
Black
NTSC Y Signal Output (Setup 0)
DAC data Lumi (IRE)
C Wave Form (NTSC)
Yellow
Green
Cyan
858
836
63
59
754
44
622
20
512
0
402
–20
270
–44
188
166
–59
–63
Red
Magenta
Blue
Color Burst
NTSC C Signal Output
19/35
¡ Semiconductor
DAC data Lumi (IRE)
MSM7653
Composite Wave Form (PAL)
Yellow
White
973
133
792
100
731
89
627
70
566
59
467
41
406
359
302
30
21.5
11
241
0
123
–21.5
4
–43
Green
Cyan
Red
Black
Magenta
Blue
PAL Composite Signal
DAC data Lumi (IRE)
Y Wave Form (PAL)
White
792
100
731
89
627
70
566
59
467
41
406
30
302
11
241
0
4
–43
Cyan
Yellow
Magenta
Green
Blue
Red
Black
PAL Y Signal Output
20/35
¡ Semiconductor
DAC data Lumi (IRE)
MSM7653
C Wave Form (PAL)
Yellow
Green
Cyan
858
836
63
59
754
44
630
21.5
512
0
394
–21.5
270
–44
188
166
–59
–63
Red
Magenta
Blue
Color Burst
PAL C Signal Output
21/35
¡ Semiconductor
MSM7653
NTSC (Interlaced)
Field 1
259
Reference sub-carrier phase
260
261
262 263
1
A
NEGATIVE HALF CYCLE
Burst relative –180° to B-Y axis
2
3
4
B
5
POSITIVE HALF CYCLE
Burst relative 180° to B-Y axis
6
7
8
17
18
19
6
7
8
17
18
19
6
7
8
17
18
19
6
7
8
17
18
19
C
D
E
Field 2
259
Reference sub-carrier phase
260
261
262 263
1
A
2
3
4
B
5
C
D
E
Field 3
259
Reference sub-carrier phase
260
261
262 263
1
A
2
3
4
B
5
C
D
E
Field 4
259
Reference sub-carrier phase
260
261
262 263
A
1
2
3
4
B
5
C
D
E
Output timing (Interlaced NTSC)
22/35
¡ Semiconductor
Symbol
MSM7653
Name
Period
Odd field (Even field)
A
First equalizing pulse period (3H)
B
Vertical synchronization period (3H)
259.5 to 262.5H
1 to 3H
C
Second equalizing pulse period (3H)
D
Burst pause period
1 to 6,259.5 to 262.5H
4 to 6H
E
Vertical blanking period (20H)
1 to 17,259.5 to 262.5H
Output timing (Interlaced NTSC)
23/35
¡ Semiconductor
MSM7653
NTSC (Non-interlaced)
NEGATIVE HALF CYCLE
Burst relative –180° to B-Y axis
Continuous Odd Field
POSITIVE HALF CYCLE
Burst relative 180° to B-Y axis
Reference sub-carrier phase
260
261
262
1
A
2
3
4
5
B
6
7
8
17
18
19
6
7
8
17
18
19
6
7
8
17
18
19
6
7
8
17
18
19
C
D
E
Reference sub-carrier phase
260
261
262
1
A
2
3
4
5
B
C
D
E
Continuous Even Field
Reference sub-carrier phase
260
261
262
1
A
2
3
4
5
B
C
D
E
Reference sub-carrier phase
260
261
262
1
A
2
3
4
5
B
C
D
E
Output timing (Non-interlaced NTSC)
Symbol
Period
Name
Continuous odd • even field
A
First equalizing pulse period (2H)
261 to 262H
B
Vertical synchronization period (3H)
1 to 3H
C
Second equalizing pulse period (2H)
4 to 6H
D
Burst pause period
261 to 6H
E
Vertical blanking period (19H)
261 to 17H
Output timing (Non-interlaced NTSC)
24/35
¡ Semiconductor
MSM7653
PAL (Interlaced)
Burst phase +135°
+V
Field 1,5
309
310
311
312 313
1
2
A
3
Burst phase -135°
-V
4
B
5
6
7
8
23
24
25
5
6
7
8
23
24
25
5
6
7
8
23
24
25
5
6
7
8
23
24
25
C
D
E
Field 2,6
309
310
311
312 313
1
2
A
3
4
B
C
D
E
Field 3,7
309
310
311
312 313
1
A
2
3
4
B
C
D
E
Field 4,8
309
310
311
312 313
1
A
2
3
4
B
C
D
E
Output timing (Interlaced PAL)
Symbol
Name
Period
Field 1,5
Field 2,6
Field 3,7
Field 4,8
A
First equalizing pulse period (2.5H)
311 to 312.5H
311 to 312.5H
311 to 312.5H
311 to 312.5H
B
Vertical synchronization period (2.5H)
1 to 2.5H
1 to 2.5H
1 to 2.5H
1 to 2.5H
C
Second equalizing pulse period (2.5H)
2.5 to 5H
2.5 to 5H
2.5 to 5H
2.5 to 5H
D
Burst pause period
1 to 6,310 to 312.5H
1 to 5.5,308.5 to 312.5H
1 to 5,311 to 312.5H
1 to 6.5,309.5 to 312.5H
E
Vertical blanking period (25H)
1 to 22.5,311 to 312.5H
1 to 22.5,311 to 312.5H
1 to 22.5,311 to 312.5H
1 to 22.5,311 to 312.5H
Output timing (Interlaced PAL)
25/35
¡ Semiconductor
MSM7653
PAL (Non-interlaced)
Burst phase +135°
+V
Continuous Odd Field
309
310
311
312
1
A
2
3
Burst phase -135°
-V
4
B
5
6
7
8
23
24
25
5
6
7
8
23
24
25
5
6
7
8
23
24
25
5
6
7
8
23
24
25
C
D
E
309
310
311
312
1
A
2
3
4
B
C
D
E
Continuous Even Field
309
310
311
312
1
A
2
3
4
B
C
D
E
309
310
311
312
1
A
2
3
4
B
C
D
E
Output timing (Non-interlaced PAL)
Symbol
Period
Name
Continuous odd • even field
311 to 312H
A
First equalizing pulse period (2H)
B
Vertical synchronization period (2.5H)
1 to 2.5H
C
Second equalizing pulse period (2.5H)
2.5 to 5H
D
Burst pause period
311 to 6H
E
Vertical blanking period (24H)
311 to 22H
Output timing (Non-interlaced PAL)
26/35
¡ Semiconductor
MSM7653
<Equalizing pulse, vertical synchronization period>
EQUAL
q
w
e
r
q
w
1/2H
e
1/2H
Setting content of equalizing pulse vertical
synchronization period (Ts is sampling clock cycle in each mode)
q
w
e
1/2H
ITU 601 NTSC
31Ts 365Ts 64Ts 429Ts
ITU 601 PAL
32Ts 369Ts 63Ts 432Ts
qEqualizing pulse width qBlanking level
wVertical sync pulse width w(synchronizing + blanking level) ¥ (2/3)
e(synchronizing + blanking level) ¥ (1/3)
eSerration
rSynchronzing level
<Horizontal blanking period>
1H
r
t
e
w
q
q
w
e
r
t
qSynchronzing level
w(synchronizing + blanking level) ¥ (1/3)
e(synchronizing + blanking level) ¥ (2/3)
rBlanking level
tPeak to peak value of burst
qHorizontal sync pulse width
wBurst signal output period
eBurst signal start
rHorizontal blanking period (excluding front porch)
tFront porch start
Horizontal blanking period
Setting content of horizontal blanking period (Ts is sampling clock cycle in each mode)
e
r
t
q
w
ITU601 NTSC
63Ts
31Ts
71Ts 127Ts 838Ts
858
ITU601 PAL
63Ts
31Ts
75Ts 142Ts 844Ts
864
Total dots/1H
Setting content of horizontal blanking period
27/35
¡ Semiconductor
MSM7653
Setup Level Setting
When the NTSC operation mode is selected, one of the two kinds of setup level can be selected
by setting of registers.
When the setup level 0 is selected, the Black-to-White is 100IRE.
When the setup level 7.5IRE is selected, the Black-to-White is 92.5IRE.
However, this setup function is valid only for the NTSC mode and invalid for the PAL mode.
Color Bar Generation Function
25%, 50%, 75% or 100% luminance order color bar is output by setting internal registers. The
output timings for each color bar color is as follows.
White
Yellow
Cyan Green
Red
Blue
Black
Magenta
q
w
e
r
t
y
u
Output timing of each color bar color
hblank
q
w
e
r
t
y
u
1H
ITU601 NTSC
127Ts
216Ts
305Ts
394Ts
483Ts
572Ts
661Ts
750Ts
858Ts
ITU601 PAL
142Ts
230Ts
318Ts
406Ts
494Ts
582Ts
670Ts
757Ts
864Ts
Operation mode
(Ts : sampling block period)
Contents of color bar output timing setting
28/35
¡ Semiconductor
MSM7653
I2C BUS FORMAT
Basic input format of I2C-bus interface is shown below.
S
Slave Address
A
Subaddress
A
Data 0
Symbol
A
.....
Data n
A
P
Description
Start condition
S
Slave address 1000100X (ADRS pin : 0) or 1000110X (ADRS pin : 1),
Slave Address
the 8th bit is R (1)/W (0) signal.
A
Acknowledge. Generated by slave
Subaddress
Subaddress byte
Data n
Data byte and acknowledge continues until data byte stop condition is met.
P
Stop condition
As described above, it is possible to read and write data from subaddress to subaddress
continuously. Reading from and writing to discontinuous addresses is performed by repeating
the Acknowledge and Stop condition formats after Data 0.
If one of the following matters occurs, the encoder will not return "A" (Acknowledge).
• The slave address does not match.
• A non-existent subaddress is specified.
• The read/write attribute of a register does not match "X" (read : 1/write : 0 control bit).
The input timing is shown below.
SDA
SCL
MSB
S
1
2
7
Start Condition
Data Line Stable: Data Valid Change of Data Allowed
8
9
ACK
tC_SCL
1
2
3-8
tL_SCL
9
ACK
P
Stop Condition
tH_SCL
I2C-bus Basic Input/Output Timing
29/35
¡ Semiconductor
MSM7653
CLOSED CAPTION FUNCTION
The closed caption function based on the NCI standard is available.
The caption information on each line is multiplexed as a 26-cycle signal which is synchronized
at 503 kHz. Each cycle is described below.
Cycles 1 to 7
Clock-Run-in period
Cycles 8 to 10
Cycles 11 to 26
Start Code
Caption Information
7-cycle clock signal to synchronize caption data
with caption information.
Fixed signal with logical level "001"
2-byte multiplex information with combination of
the ASCII code bits 0 - 6 and the 7ODD parity bit.
The first byte is multiplexed in cycles 11 to 18 and
the second byte is multiplexed in cycles 19 to 26,
starting from LSB.
The output timing when data is multiplexed by the closed caption function is shown below.
50IRE
Cycle
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
50IRE
Transition time
20IRE
0IRE
–40IRE
Clock Run in
Start
Code
16-bit Information
13.9 ms
(reference)
6.0 ms
(reference)
31.8 ms
(reference)
10.0 ms
(reference)
61.7 ms (reference)
Caption signal
100%
50%
Transition time : ns
Transition time
30/35
¡ Semiconductor
MSM7653
INTERNAL REGISTERS
The register (ID number) for the Anticopy function and the register (CCSTAT) for the closed
caption are read-only registers.
The other registers are write-only registers.
Details of the internal registers are described below. (Values marked * are set by default.)
Sub- Default
Register name
R/W
Item to be set
Description
address value
MR
Write
(Mode register)
Only
00
00
MR[4]
Override
Switching between the external terminal and
internal register settings (for the operation mode)
*0 : External pin setting enabled
1 : Internal register setting enabled
MR[3]
Chroma format
Chrominance signal input format
*0 : Offset binary
1 : 2's complement
MR[2]
Black level control
Black level setup
Note : Valid in NTSC mode only
*0 : Black level 0IRE
1 : Black level 7.5IRE
MR[1]
Master/Slave
Master or slave operation select
*0 : Slave
1 : Master
MR[0]
Video mode select
Operation mode switching
*0 : ITU601 NTSC
1 : ITU601 PAL
CR
Write
(Command Register)
Only
01
03
CR[4]
Undefined
—
CR[3]
Interlace
Scanning method
(Note 1)
*0 : Interlace
1 : Non-interlace
CR[2]
Color bar
Adjusting luminance order color bar output control
*0 : Input image data or overlay data
1 : Luminance order color bar
CR[1:0]
Overlay level
Overlay signal/adjusting luminance order color
bar output level control
*00 : 100%
01 : 75%
10 : 50%
11 : 25%
(Note 1) When the MR[4] register is set to "1" to enable the settings of the internal registers, the
settings of pin 7 (MODE) and the MR[0] register should be the same.
31/35
¡ Semiconductor
MSM7653
Sub- Default
Register name
R/W
Item to be set
Description
address value
CCEN
Write
02
00
CCEN[1:0]
Closed Caption Enable
Closed caption function on/off control
Only
*0 : C.C. encoding off
1 : Odd field encoding on
2 : Even field encoding on
3 : Both field encoding on
CCLN
Write
03
11
CCLN[4:0]
Closed Caption Line Number
Closed caption data insertion line
Only
number setting
NTSC : CCLN + 4
PAL : CCLN + 1
CCODT0
Write
CCODT1
Write
CCEDT0
Write
04
00
CCODT0[7:0]
1st byte of C.C. data, ODD field
First byte closed caption data in odd-number
05
00
CCODT1[7:0]
2nd byte of C.C. data, ODD field
Second byte closed caption data in odd-number
06
00
CCEDT0[7:0]
1st byte of C.C. data, EVEN field
First byte closed caption data in even-number
Only
field
Only
field
Only
CCEDT1
Write
field
07
00
CCEDT1[7:0]
2nd byte of C.C. data, EVEN field
Second byte closed caption data in
Only
CCSTAT
Read
even-number field
08
00
CCSTAT[0]
Odd field C.C. status
odd-number field status
Only
*0 : CCODT0, CCODT1 writing completed
1 : ODD Field C.C. bytes ENCODE completed
CCSTAT[1]
Odd field C.C. status
Even-number field status
*0 : CCEDT0, CCEDT1 writing completed
1 : EVEN Field C.C. bytes ENCODE completed
OPERATION MODE SETTING BY PIN CONTROL
The contents of control using TEST1, SEL1, SEL2, CLKSEL, and MS are shown below.
TEST1
SEL1
SEL2
CLKSEL
MS
TEST1
0
0
0
0
0
0
0 : Normal operation
0 : Normal operation
0 : ITU Rec. 656
0 : 27 MHz
0 : Slave
SEL1
0
0
0
0
0
1
SEL2
0
0
0
1
1
x
1 : Test mode
1 : Sleep mode
1 : Y Cb Cr
1 : 13.5 MHz
1 : Master
CLKSEL
MS
0
0
1
0
1
1
0
0
0
1
x
x
x : don't care
Operation mode
ITUR656 Slave
13.5 MHz YCbCr Slave
13.5 MHz YCbCr Master
27 MHz YCbCr Slave
27 MHz YcbCr Master
Sleep Mode
32/35
¡ Semiconductor
MSM7653
FILTER CHARACTERISTICS
The characteristics of LPF used for color signal processing and interpolation filters used for
upsampling processing are shown below.
LPF for 422 color signals
The following shows the characteristics when the clock frequency is 13.5 MHz.
0
Level [dB]
–20
–40
–60
–80
–100
0
1
2
3
4
Frequency [MHz]
5
6
7
422 Interpolation + LPF Frequency Characteristic
Interpolation
The following shows the characteristics when the clock frequency is 27 MHz.
0
Level [dB]
–20
–40
–60
–80
–100
0
2
4
6
8
Frequency [MHz]
10
12
14
Up Sampling Filter Frequency Characteristic
(Note) The characteristics of these filters are based on design data.
33/35
¡ Semiconductor
MSM7653
APPLICATION CIRCUIT EXAMPLE
5 V or 3.3 V
SCL
MS
MODE
OUTSEL
CLKSEL
SEL1
SEL2
DVDD
3.3 V
Controller
SDA
DIP SW
5 V or 3.3 V
RL
VREF
Typ. 1.25 V
3.3 V
FS
COMP
YD[7:0]
CD[7:0]
CD[7:0]
LPF
AMP
LPF
AMP
LPF
AMP
YA
MSM7653
YD[7:0]
CC = 0.1 µF
RC
OLR
OLG
OLB
OLC
Overlay
Controller
3.3 V
AVDD
RL
I2C
R1
CVBSO
R1
CLKX1O
CA
VSYNC_L
R1
HSYNC_L
BLANK_L
DGND
AGND CLKX2
RC = 500 Ω VR
Recommended Analog Output Circuit
+AVCC
YA
CA
CVBSO
0.1 mF
3.6 mH
150 W
150 W
164 pF 164 pF
+
–
1000 mF
+
OUTPUT
75 W
560 W
560 W
0.1 mF
LPF (Toko-make 621LJN-1471 is recommended.)
–AVCC
Note: The termination of a DA converter analog output with a 37.5 W load eliminates need for
an AMP.
34/35
¡ Semiconductor
MSM7653
PACKAGE DIMENSIONS
(Unit : mm)
56-Pin Plastic QFP
35/35
E2Y0002-29-62
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
6.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.
Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior
permission.
Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan