DAC5681 www.ti.com SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 16-BIT, 1.0 GSPS Digital-to-Analog Converter (DAC) Check for Samples: DAC5681 FEATURES DESCRIPTION • • • The DAC5681 is a 16-bit 1.0 GSPS digital-to-analog converter (DAC) with wideband LVDS data input and internal voltage reference. The DAC5681 offers superior linearity and noise performance. 1 • • • • 16-Bit Digital-to-Analog Converter (DAC) 1.0 GSPS Update Rate 16-Bit Wideband Input LVDS Data Bus – 8 Sample Input FIFO – On-Chip Delay Lock Loop High Performance – 73 dBc ACLR WCDMA TM1 at 180 MHz On Chip 1.2 V Reference Differential Scalable Output: 2 to 20 mA Package: 64-Pin 9 × 9 mm QFN The DAC5681 integrates a wideband LVDS port with on-chip termination, providing full 1.0 GSPS data transfer into the DAC and lower EMI than traditional CMOS data interfaces. An on-chip delay lock loop (DLL) simplifies LVDS interfacing by providing skew control for the LVDS input data clock. The current-steering architecture of the DAC5681 consists of a segmented array of current sinking switches directing up to 20mA of full-scale current to complementary output nodes. An accurate on-chip voltage reference is temperature-compensated and delivers a stable 1.2-V reference voltage. Optionally, an external reference may be used. APPLICATIONS • • • • • • • Cellular Base Stations Broadband Wireless Access (BWA) WiMAX 802.16 Fixed Wireless Backhaul Cable Modem Termination System (CMTS) Medical / Test Instrumentation Radar Systems The DAC5681 is characterized for operation over the industrial temperature range of –40°C to 85°C and is available in a 64-pin QFN package. The device is pin upgradeable to the other members of the family: the DAC5681Z and DAC5682Z. The single-channel DAC5681Z and dual-channel DAC5682Z both provide optional 2x/4x interpolation and a clock multiplying PLL. ORDERING INFORMATION TA –40°C to 85°C (1) (2) (3) ORDER CODE DAC5681IRGCT DAC5681IRGCR PACKAGE DRAWING/TYPE (1) (2) (3) TRANSPORT MEDIA QUANTITY RGC / 64QFN Quad Flatpack NoLead Tape and Reel 250 Tape and Reel 2000 Thermal Pad Size: 7,4 mm × 7,4 mm MSL Peak Temperature: Level-3-260C-168 HR For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2012, Texas Instruments Incorporated DAC5681 SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. CLKIN Clock Distribution CLKINC (3.3V) AVDD (1.8V) VFUSE (1.8V) DVDD (1.8V) CLKVDD FUNCTIONAL BLOCK DIAGRAM EXTIO 1.2V Reference FDAC EXTLO BIASJ DCLKP Sync Disable Delay Lock Loop (DLL) DCLKN DLL Control Mode Control B A SYNCN DAC Delay (0-3) 13 SYNC=’0->1' (transition) TXEnable=’1' IOUTA1 16bit DAC IOUTA2 4 2 DAC Gain 100 SYNCP 16 16 Offset D0N DDR De-interleave 100 D0P 8 Sample FIFO 16 D15N Delay Value 100 D15P Sync & Control SW_Sync 2 Submit Documentation Feedback GND (3.3V) IOVDD RESETB SCLK SDENB SDO SDIO FIFO Sync Disable Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 DAC5681 www.ti.com SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 RESETB AVDD 54 49 AVDD DVDD EXTIO 56 55 50 BIASJ 57 51 AVDD EXTLO IOUTA2 AVDD 60 59 IOUTA1 AVDD AVDD 61 53 AVDD 62 52 DVDD 63 58 NC 64 DAC5681 RGC PACKAGE (TOP VIEW) CLKVDD 1 48 SDENB CLKIN 2 47 SCLK CLKINC 3 46 SDIO GND 4 45 SDO SYNCP 5 44 VFUSE SYNCN D15P 6 43 D0N 7 42 D0P 41 D1N 40 D1P D15N 8 IOVDD 9 DVDD 10 39 DVDD D14P 11 38 D2N D14N 12 37 D2P D13P 13 36 D3N D13N 14 35 D3P D12P 15 34 D4N D12N 16 33 D4P 31 D5P 32 30 D6N D5N 28 29 D6P 27 D7P D7N 25 26 DCLKP DCLKN 23 24 D8P D8N 21 20 D10N 22 19 D10P D9P 18 D11N D9N 17 D11P DAC5681 TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. AVDD 51, 54, 55, 59–62 I BIASJ 57 O Full-scale output current bias. For 20mA full-scale output current, connect a 960 Ω resistor to GND. CLKIN 2 I Positive external clock input with a self-bias of approximately CLKVDD/2. CLKINC 3 I Complementary external clock input. (See the CLKIN description) CLKVDD 1 I Internal clock buffer supply voltage. (1.8 V) D[15..0]P 7, 11, 13, 15, 17, 19, 21, 23, 27, 29, 31, 33, 35, 37, 40, 42 I LVDS positive input data bits 0 through 15. Each positive/negative LVDS pair has an internal 100 Ω termination resistor. Order of bus can be reversed via rev_bus bit in CONFIG5 register. Data format relative to DCLKP/N clock is Double Data Rate (DDR) with two data samples input per DCLKP/N clock. In dual-channel mode, data for the A-channel is input while DCLKP is high. D[15..0]N 8, 12, 14, 16, 18, 20, 22, 24, 28, 30, 32, 34, 36, 38, 41, 43 Analog supply voltage. (3.3V) D15P is most significant data bit (MSB) – pin 7 D0P is least significant data bit (LSB) – pin 42 LVDS negative input data bits 0 through 15. (See D[15:0]P description above) I D15N is most significant data bit (MSB) – pin 8 D0N is least significant data bit (LSB) – pin 43 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 3 DAC5681 SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL NAME NO. I/O DESCRIPTION DCLKP 25 I LVDS positive input clock. Unlike the other LVDS inputs, the DCLKP/N pair is self-biased to approximately DVDD/2 and does not have an internal termination resistor in order to optimize operation of the DLL circuit. See the “DLL Operation” section. For proper external termination, connect a 100 Ω resistor across LVDS clock source lines followed by series 0.01 μF capacitors connected to each of DCLKP and DCLKN pins (see Figure 17). For best performance, the resistor and capacitors should be placed as close as possible to these pins. DCLKN 26 I LVDS negative input clock. (See the DCLKP description) DVDD 10, 39, 50, 63 I EXTIO 56 Used as external reference input when internal reference is disabled (i.e., EXTLO connected to AVDD). I/O Used as 1.2V internal reference output when EXTLO = GND, requires a 0.1 μF decoupling capacitor to AGND when used as reference output. EXTLO Digital supply voltage. (1.8 V) 58 O Connect to GND for internal reference, or AVDD for external reference. 4, Thermal Pad I Pin 4 and the Thermal Pad located on the bottom of the QFN package is ground for AVDD, DVDD and IOVDD supplies. IOUTA1 52 O DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full scale current sink and the least positive voltage on the IOUTA1 pin. Similarly, a 0xFFFF data input results in a 0 mA current sink and the most positive voltage on the IOUTA1 pin. IOUTA2 53 O DAC complementary current output. The IOUTA2 has the opposite behavior of the IOUTA1 described above. An input data value of 0x0000 results in a 0mA sink and the most positive voltage on the IOUTA2 pin. IOVDD 9 I Digital I/O supply voltage (3.3V) for pins RESETB, SCLK, SDENB, SDIO, SDO. NC 64 I No Connect. Leave open for proper operation. RESETB 49 I Resets the chip when low. Internal pull-up. SCLK 47 I Serial interface clock. Internal pull-down. SDENB 48 I Active low serial data enable, always an input to the DAC5681. Internal pull-up. SDIO 46 I/O Bi-directional serial interface data in 3-pin mode (default). In 4-pin interface mode (CONFIG5 sif4), the SDIO pin is an input only. Internal pull-down. SDO 45 O Uni-directional serial interface data in 4-pin mode (CONFIG5 sif4). The SDO pin is in high-impedance state in 3-pin interface mode (default), but can optionally be used as a status output pin via CONFIG14 SDO_func_sel(2:0). Internal pull-down. SYNCP 5 I LVDS SYNC positive input data. The SYNCP/N LVDS pair has an internal 100 Ω termination resistor. By default, the SYNCP/N input must be logic ‘1’ to enable a DAC analog output. See the LVDS SYNCP/N Operation paragraph for a detailed description. SYNCN 6 I LVDS SYNC negative input data. VFUSE 44 I Digital supply voltage. (1.8V) Connect to DVDD pins for normal operation. This supply pin is also used for factory fuse programming. GND 4 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 DAC5681 www.ti.com SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) DVDD Supply voltage range (1) (2) VALUE UNIT –0.5 to 2.3 V VFUSE (2) –0.5 to 2.3 V CLKVDD (2) –0.5 to 2.3 V –0.5 to 4 V (2) –0.5 to 4 V AVDD to DVDD –2 to 2.6 V –0.5 to 0.5 V AVDD (2) IOVDD CLKVDD to DVDD IOVDD to AVDD –0.5 to 0.5 V –0.5 to DVDD + 0.5 V –0.3 to 2.1 V –0.5 to CLKVDD + 0.5 V –0.5 to IOVDD + 0.5 V –0.5 to AVDD + 0.5 V –0.5 to AVDD + 0.5 V Peak input current (any input) 20 mA Peak total input current (all inputs) –30 mA Operating free-air temperature range, TA: DAC5681 –40 To 85 °C Storage temperature range –65 To 150 °C D[15..0]P ,D[15..0]N, SYNCP, SYNCN Terminal voltage range (2) DCLKP, DCLKN (2) CLKIN, CLKINC (2) SDO, SDIO, SCLK, SDENB, RESETB IOUTA1, IOUTA2 (2) (2) EXTIO, EXTLO, BIASJ (2) (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Measured with respect to GND. THERMAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) THERMAL CONDUCTIVITY TJ Maximum junction temperature (1) 64ld QFN UNIT 125 °C Theta junction-to-ambient (still air) 20 Theta junction-to-ambient (150 lfm) 16 θJC Theta junction-to-case 7 °C/W θJP Theta junction-to-pad 0.2 °C/W θJA (1) °C/W Air flow or heat sinking reduces θJA and may be required for sustained operation at 85° under maximum operating conditions. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 5 DAC5681 SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com ELECTRICAL CHARACTERISTICS — DC SPECIFICATION over operating free-air temperature range , AVDD = 3.3 V, CLKVDD = 1.8 V, IOVDD = 3.3 V, DVDD = 1.8 V, IoutFS = 20 mA (unless otherwise noted) PARAMETER TEST CONDITIONS RESOLUTION DC ACCURACY MIN TYP MAX 16 UNIT Bits (1) INL Integral nonlinearity DNL Differential nonlinearity 1 LSB = IOUTFS/216 ±4 LSB ±2 ANALOG OUTPUT Coarse gain linearity ±0.04 LSB 0.01 %FSR With external reference 1 %FSR With internal reference 0.7 %FSR Offset error Mid code offset Gain error Gain error Minimum full scale output current (2) 2 Maximum full scale output current (2) 20 Output Compliance range (3) IOUTFS = 20 mA AVDD –0.5V Output resistance Output capacitance mA AVDD + 0.5V V 300 kΩ 5 pF REFERENCE OUTPUT Vref Reference voltage 1.14 Reference output current (4) 1.2 1.26 100 V nA REFERENCE INPUT VEXTIO Input voltage range 0.1 Input resistance Small signal bandwidth 1.25 1 CONFIG6: BiasLPF_A = 0 95 CONFIG6: BiasLPF_A = 1 472 Input capacitance V MΩ kHz 100 pF ±1 ppm of FSR/°C TEMPERATURE COEFFICIENTS Offset drift Gain drift With external reference ±15 With internal reference ±30 ppm of FSR/°C ±8 ppm/°C Reference voltage drift POWER SUPPLY Analog supply voltage, AVDD 3.0 3.3 3.6 V Digital supply voltage, DVDD 1.71 1.8 2.15 V Clock supply voltage, CLKVDD 1.71 1.8 2.15 V 3.0 3.3 3.6 V I/O supply voltage, IOVDD I(AVDD) Analog supply current 67 mA I(DVDD) Digital supply current 191 mA I(CLKVDD) Clock supply current 15 mA I(IOVDD) IO supply current 4 mA (1) (2) (3) (4) 6 Mode 1 (below) Measured differential across IOUTA1 and IOUTA2 with 25 Ω each to AVDD. Nominal full-scale current, IoutFS, equals 16 × IBIAS current. The lower limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown, resulting in reduced reliability of the DAC5681 device. The upper limit of the output compliance is determined by the load resistors and full-scale output current. Exceeding the upper limit adversely affects distortion performance and integral nonlinearity. Use an external buffer amplifier with high impedance input to drive any external load. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 DAC5681 www.ti.com SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 ELECTRICAL CHARACTERISTICS — DC SPECIFICATION (continued) over operating free-air temperature range , AVDD = 3.3 V, CLKVDD = 1.8 V, IOVDD = 3.3 V, DVDD = 1.8 V, IoutFS = 20 mA (unless otherwise noted) PARAMETER I(AVDD) Sleep mode, AVDD supply current I(DVDD) Sleep mode, DVDD supply current I(CLKVDD) Sleep mode, CLKVDD supply current I(IOVDD) Sleep mode, IOVDD supply current AVDD + IOVDD current, 3.3V DVDD + CLKVDD current, 1.8V TEST CONDITIONS MIN Mode 3 (below) Mode 1: CLKIN = 1000 MHz IF = 40 MHz Single Tone, 0 dBFS DVDD + CLKVDD current, 1.8V P DVDD + CLKVDD current, 1.8V Mode 2: CLKIN = 500 MHz IF = 40 MHz Single Tone, 0 dBFS DVDD + CLKVDD current, 1.8V Mode 3: CLKIN = 1000 MHz DAC on SLEEP, Static Data Pattern Mode 4: CLKIN = OFF DAC on SLEEP, Static Data Pattern Power Dissipation PSRR Power supply rejection ratio T Operating range 91 mA 15 mA 1.5 mA 71 mA mW mA 111 mA 435 mW 3 mA 106 mA 200 mW 3 mA 6 mA 20 DC tested mA 650 71 Power Dissipation AVDD + IOVDD current, 3.3V UNIT mA 605 Power Dissipation AVDD + IOVDD current, 3.3V MAX 1.5 206 Power Dissipation AVDD + IOVDD current, 3.3V TYP 30 mW –0.2 0.2 %FSR/V –40 85 °C Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 7 DAC5681 SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com ELECTRICAL CHARACTERISTICS — AC SPECIFICATION (1) Over recommended operating free-air temperature range, AVDD, IOVDD = 3.3 V, CLKVDD, DVDD = 1.8 V, IOUTFS = 20 mA, 4:1 transformer output termination, 50Ω doubly terminated load (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG OUTPUT fCLK Maximum output update rate ts(DAC) Output settling time to 0.1% Transition: Code 0x0000 to 0xFFFF 1000 tpd Output propagation delay DAC output is updated on falling edge of DAC clock. Does not include Digital Latency (see below). tr(IOUT) tf(IOUT) MSPS 10.4 ns 2.5 ns Output rise time 10% to 90% 220 ps Output fall time 90% to 10% 220 ps 76 DAC clock cycles BiasLPF_A enabled; register 0x06, Bit 3 set to 1. 8 μs BiasLPF_A disabled; register 0x06, Bit 3 set to 0. 80 μs BiasLPF_A enabled; register 0x06, Bit 3 set to 1. 8 μs BiasLPF_A disabled; register 0x06, Bit 3 set to 0. 80 μs CLKIN = 500 MHz, IF = 5.1 MHz, First Nyquist Zone < fDATA/2 81 CLKIN = 1000 MHz, IF = 5.1 MHz, First Nyquist Zone < fDATA/2 80 CLKIN = 1000 MHz, IF = 20.1 MHz, First Nyquist Zone < fDATA/2 77 CLKIN = 500 MHZ, Single tone, 0 dBFS, IF = 20.1 MHz 75 CLKIN = 1000 MHZ, Single tone, 0 dBFS, IF = 20.1 MHz 70 CLKIN = 1000 MHZ, Single tone, 0 dBFS, IF = 70.1 MHz 66 CLKIN = 1000 MHZ, Single tone, 0 dBFS, IF = 180 MHz 60 CLKIN = 1000 MHZ, Single tone, 0 dBFS, IF = 300.2 MHz 60 CLKIN = 1000 MHZ, Four tone, each -12 dBFS, IF = 24.7, 24.9, 25.1 and 25.3 MHz 73 CLKIN = 1000 MHZ, IF = 20.1 and 21.1 MHz 88 CLKIN = 1000 MHZ, IF = 70.1 and 71.1 MHz 75 CLKIN = 1000 MHZ, IF = 150.1 and 151.1 MHz 67 CLKIN = 1000 MHz, IF = 298.4, 299.2, 300.8 and 301.6 MHz 64 Digital Latency DAC Wake-up Time (2) Power-up Time DAC Sleep Time (3) AC PERFORMANCE SFDR Spurious free dynamic range SNR Signal-to-noise ratio Third-order two-tone intermodulation (each tone at –6 dBFS) IMD3 Four-tone intermodulation (each tone at –12 dBFS) IMD dBc Single carrier, baseband, CLKIN = 983.04 MHz ACLR (4) Adjacent channel leakage ratio Noise floor (5) (1) (2) (3) (4) (5) 8 dBc 80 dBc dBc 83 Single carrier, IF = 180 MHz, CLKIN = 983.04 MHz 73 Four carrier, IF = 180 MHz, CLKIN = 983.04 MHz 68 Four carrier, IF = 275 MHz, CLKIN = 983.04 MHz 66 50-MHz offset, 1-MHz BW, Single Carrier, baseband, CLKIN = 983.04 93 50-MHz offset, 1-MHz BW, Four Carrier, baseband, CLKIN = 983.04 85 dBc dBc Measured single-ended into 50 Ω load. IOUT current settling to 1% of IOUTFS. Measured from SDENB rising edge; Register 0x06, toggle Bit 4 from 1 to 0. IOUT current settling to less than 1% of IOUTFS. Measured from SDENB rising edge; Register 0x06, toggle Bit 4 from 0 to 1. W-CDMA with 3.84 MHz BW, 5-MHz spacing, centered at IF. TESTMODEL 1, 10 ms Carrier power measured in 3.84 MHz BW. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 DAC5681 www.ti.com SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS) over recommended operating free-air temperature range, AVDD, IOVDD = 3.3V, CLKVDD, DVDD = 1.8V. PARAMETER TEST CONDITIONS LVDS INTERFACE: D[15:0]P/N, SYNCP/N, DCLKP/N MIN TYP MAX UNIT (1) VA,B+ Logic high differential input voltage threshold 175 mV VA,B– Logic low differential input voltage threshold –175 mV VCOM1 Input Common Mode VCOM2 Input Common Mode ZT Internal termination CL LVDS Input capacitance tS, tH DCLK to Data SYNCP/N, D[15:0]P/N only 1.0 DCLKP/N only SYNCP/N, D[15:0]P/N only 85 DCLKP/N: 0 to 125MHz (see Figure 20) DLL Disabled, CONFIG5 DLL_bypass = 1, CONFIG10 = '00000000' DCLKP/N = 200 MHz DCLKP/N = 250 MHz DCLK to Data Skew (2) DLL Enabled, CONFIG5 DLL_bypass = 0, DDR format DCLKP/N = 300 MHz DCLKP/N = 350 MHz DCLKP/N = 400 MHz DCLKP/N = 450 MHz DCLKP/N = 500 MHz fDATA Input data rate supported DLL Operating Frequency (DCLKP/N Frequency) (1) (2) 110 V Ω 135 2 DCLKP/N = 150 MHz tSKEW(A), tSKEW(B) V DVDD ÷2 Setup_min 1100 Hold_min –600 Positive 1000 Negative –1800 Positive –1300 Positive 600 Negative –1000 Positive 450 Negative –800 Positive 400 Negative –700 Positive 300 Negative –600 Positive 300 Negative –500 Positive 350 Negative –300 DLL Disabled, CONFIG5 DLL_bypass = 1, DDR format, DCLKP frequency: <125 MHz DLL Enabled, CONFIG5 DLL_bypass = 0, DDR format ps 800 Negative DLL Enabled, CONFIG5 DLL_bypass = 0, DDR format, DCLKP frequency: 125 to 500 MHz pF ps 250 MSPS 250 1000 CONFIG10 = '11001101' = 0xCD 125-150 CONFIG10 = '11001110' = 0xCE 150-175 CONFIG10 = '11001111' = 0xCF 175-200 CONFIG10 = '11001000' = 0xC8 200-325 CONFIG10 = '11000000' = 0xC0 325-500 MHz See LVDS INPUTS section for terminology. Positive skew: Clock ahead of data. Negative skew: Data ahead of clock. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 9 DAC5681 SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS) (continued) over recommended operating free-air temperature range, AVDD, IOVDD = 3.3V, CLKVDD, DVDD = 1.8V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CMOS INTERFACE: SDO, SDIO, SCLK, SDENB, RESETB VIH High-level input voltage 2 3 VIL Low-level input voltage 0 0 IIH High-level input current ±20 μA IIL Low-level input current ±20 μA CI CMOS Input capacitance VOH SDO, SDIO 5 V 0.8 V pF IOVDD –0.2 V 0.8 x IOVDD V Iload = 100 μA 0.2 V Iload = 2 mA 0.5 V Iload = –100 μA Iload = –2mA VOL SDO, SDIO ts(SDENB) Setup time, SDENB to rising edge of SCLK 20 ns ts(SDIO) Setup time, SDIO valid to rising edge of SCLK 10 ns th(SDIO) Hold time, SDIO valid to rising edge of SCLK 5 ns t(SCLK) Period of SCLK 100 ns t(SCLKH) High time of SCLK 40 ns t(SCLKL) Low time of SCLK 40 ns td(Data) Data output delay after falling edge of SCLK 10 ns tRESET Minimum RESETB pulse width 25 ns CLOCK INPUT (CLKIN/CLKINC) Duty cycle Differential voltage 50% (3) 0.4 CLKIN/CLKINC input common mode (3) 10 1 V CLKVDD ÷2 V Driving the clock input with a differential voltage lower than 1V will result in degraded performance. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 DAC5681 www.ti.com SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS DNL 10 8 6 8 6 4 2 4 2 DNL- LSBs INL - LSBs INL 10 0 -2 0 -2 -4 -4 -6 -8 -10 0 -6 -8 -10 0 10000 20000 30000 Code 40000 50000 60000 10000 90 10 85 0 80 -10 75 -20 70 -12 dBFS 65 -6 dBFS 60 55 40000 50000 60000 Fdata = 1000 MSPS, FOUT = 20 MHz -30 -40 -50 -60 50 0 dBFS -70 45 -80 40 0 -90 50 100 150 200 250 300 350 400 450 IF - Intermediate Frequency - MHz 0 50 Figure 3. SFDR vs IF 100 150 200 250 300 350 400 450 500 f - Frequency - MHz Figure 4. Single-Tone Spectral Plot 10 10 Fdata = 1000 MSPS, FOUT = 170 MHz 0 -10 -10 -20 -20 -30 -40 -50 -30 -40 -50 -60 -60 -70 -70 -80 -80 -90 -90 0 50 100 150 200 250 300 350 400 450 500 f - Frequency - MHz Fdata = 1000 MSPS, FOUT = 270 MHz 0 Power - dBm Power - dBm 30000 Code Figure 2. Differential Nonlinearity Power - dBm SFDR - Spurious Free Dynamic Range - dBc Figure 1. Integral Nonlinearity 20000 0 50 Figure 5. Single-Tone Spectral Plot 100 150 200 250 300 350 400 450 500 f - Frequency - MHz Figure 6. Single-Tone Spectral Plot Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 11 DAC5681 SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) 0 100 95 -20 90 -12 dBFS 85 IMD - dBc Power - dBm -40 80 -6 dBFS 75 70 65 -60 -80 0 dBFS 60 -100 Fdata = 1000 MSPS, FOUT = 40 ±0.5 MHz 55 50 0 50 -120 38 100 150 200 250 300 350 400 450 IF - Intermediate Frequency - MHz 38.5 Figure 7. Two-Tone IMD vs Output Frequency 39 39.5 40 40.5 41 f - Frequency - MHz 41.5 42 Figure 8. Two-Tone IMD Spectral Plot 85 0 Fdata = 491.52 MSPS -20 80 ACLR - dBc Power - dBm -40 -60 75 -80 70 -100 Fdata = 1000 MSPS, FOUT = 250 MHz, ±0.5 MHz -120 248 249 249.5 250 250.5 251 f - Frequency - MHz 251.5 252 252.5 65 0 Figure 9. Two-Tone IMD Spectral Plot 12 Submit Documentation Feedback 61.44 122.88 184.32 IF - Intermediate Frequency - MHz 245.76 Figure 10. Single Carrier W-CDMA Test Model 1 - ACLR vs IF Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 DAC5681 www.ti.com SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS (continued) -20 -20 Fdata = 983.04 MSPS, FOUT = 61.44 MHz -30 -40 -40 -50 -50 Power - dBm Power - dBm -30 -60 -70 -80 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 48.7 53.7 58.7 63.7 f - Frequency - MHz 68.7 -120 171.5 73.7 Figure 11. Single Carrier W-CDMA Test Model 1 Carrier Power: -8.2 dBm, ACLR 79.7 dB -40 -50 -50 Power - dBm Power - dBm 196.5 Fdata = 983.04 MSPS, -30 FOUT = 184.32 MHz -40 -60 -70 -80 -60 -70 -80 -90 -90 -100 -100 -110 -110 179 184 189 f - Frequency - MHz 181.5 186.5 191.5 f - Frequency - MHz -20 Fdata = 983.04 MSPS, -30 FOUT = 184.32 MHz 174 176.5 Figure 12. Single Carrier W-CDMA Test Model 1 Carrier Power: -9 dBm, ACLR 73.3 dB -20 -120 169 Fdata = 983.04 MSPS, FOUT = 184.32 MHz 194 Figure 13. Two Carrier W-CDMA Test Model 1 Carrier Power: -12 dBm, ACLR 70.6 dB 199 -120 164 169 174 179 184 189 194 f - Frequency - MHz 199 204 Figure 14. Four Carrier W-CDMA Test Model 1 Carrier Power: -16.8 dBm, ACLR 68.3 dB Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 13 DAC5681 SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) -20 Fdata = 983.04 MSPS, -30 FOUT = 184.32 MHz -40 Power - dBm -50 -60 -70 -80 -90 -100 -110 -120 164 169 174 179 184 189 194 f - Frequency - MHz 199 204 Figure 15. Three Carrier W-CDMA Test Model 1 with GAP Carrier Power: -14.8 dBm, ACLR 70.1 dB 14 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 DAC5681 www.ti.com SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 TEST METHODOLOGY Typical AC specifications were characterized with the DAC5681EVM using the test configuration shown in Figure 16. A sinusoidal master clock frequency is generated by an HP8665B signal generator and into a splitter. One output drives an Agilent 8133A pulse generator, and the other drives the CDCM7005 clock driver. The 8133A converts the sinusoidal frequency into a square wave output clock and drives an Agilent ParBERT 81250A pattern-generator clock. On the EVM, the DAC5681 CLKIN/C input clock is driven by an CDCM7005 clock distribution chip that is configured to simply buffer the external 8665B clock. The DAC5681 output is characterized with a Rohde and Schwarz FSU spectrum analyzer. For WCDMA signal characterization, it is important to use a spectrum analyzer with high IP3 and noise subtraction capability so that the spectrum analyzer does not limit the ACPR measurement. DAC5681EVM SMA Adapter Board DAC5681 DAC P N D0 P N Pattern Memory SYNC P N DCLK P N 100 100 3.3 V FIFO & Demux Stacking Interface Connector D15 100 DLL Opt. Clock Divider Splitter 100 Rohde & Schwartz FSU Spectrum Analyzer 3.3 V CDCM7005 Agilent 8133A Pulse Generator 3.3 V DAC 100 36 each SMA-SMA cables Optional Divider 100 CLKIN CLKINC Agilent 81205A ParBERT 100 DAC5681EVM HP8665B Synthesized Signal Generator Figure 16. DAC5681 Test Configuration Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 15 DAC5681 SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com DEFINITION OF SPECIFICATIONS Adjacent Carrier Leakage Ratio (ACLR): Defined for a 3.84Mcps 3GPP W-CDMA input signal measured in a 3.84MHz bandwidth at a 5MHz offset from the carrier with a 12dB peak-to-average ratio. Analog and Digital Power Supply Rejection Ratio (APSSR, DPSSR): Defined as the percentage error in the ratio of the delta IOUT and delta supply voltage normalized with respect to the ideal IOUT current. Differential Nonlinearity (DNL): Defined as the variation in analog output associated with an ideal 1 LSB change in the digital input code. Gain Drift: Defined as the maximum change in gain, in terms of ppm of full-scale range (FSR) per °C, from the value at ambient (25°C) to values over the full operating temperature range. Gain Error: Defined as the percentage error (in FSR%) for the ratio between the measured full-scale output current and the ideal full-scale output current. Integral Nonlinearity (INL): Defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Intermodulation Distortion (IMD3, IMD): The two-tone IMD3 or four-tone IMD is defined as the ratio (in dBc) of the worst 3rd-order (or higher) intermodulation distortion product to either fundamental output tone. Offset Drift: Defined as the maximum change in DC offset, in terms of ppm of full-scale range (FSR) per °C, from the value at ambient (25°C) to values over the full operating temperature range. Offset Error: Defined as the percentage error (in FSR%) for the ratio of the differential output current (IOUT1–IOUT2) and the mid-scale output current. Output Compliance Range: Defined as the minimum and maximum allowable voltage at the output of the current-output DAC. Exceeding this limit may result reduced reliability of the device or adversely affecting distortion performance. Reference Voltage Drift: Defined as the maximum change of the reference voltage in ppm per degree Celsius from value at ambient (25°C) to values over the full operating temperature range. Spurious Free Dynamic Range (SFDR): Defined as the difference (in dBc) between the peak amplitude of the output signal and the peak spurious signal. Signal to Noise Ratio (SNR): Defined as the ratio of the RMS value of the fundamental output signal to the RMS sum of all other spectral components below the Nyquist frequency, including noise, but excluding the first six harmonics and dc. 16 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 DAC5681 www.ti.com SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 TYPICAL APPLICATION SCHEMATIC (1) Power supply decoupling capacitors not shown. (2) Internal Reference configuration shown. Figure 17. Schematic Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 17 DAC5681 SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com DETAILED DESCRIPTION Table 1. Register Map Name Address Default (MSB) Bit 7 STATUS0 0x00 0x1F Reserved CONFIG1 0x01 0x10 CONFIG2 0x02 0xC0 Bit 6 Bit 5 DLL_lock Unused DAC_delay(1:0) Unused Twos_ comp Reserved Bit 4 Bit 3 Reserved SLFTST _ena Bit 2 device_ID(2:0) Reserved Unused FIFO_err_ mask Pattern_err _mask (LSB) Bit 0 Bit 1 version(1:0) FIFO_offset(2:0) Reserved CONFIG3 0x03 0x70 DAC_offset _ena SLFTST_err _mask STATUS4 0x04 0x00 Unused SLFTST_err FIFO_err Pattern_ err Unused Unused Unused Unused CONFIG5 0x05 0x00 SIF4 rev_bus clkdiv_ sync_dis Reserved Reserved DLL_ bypass Reserved Reserved CONFIG6 0x06 0x0C Reserved Unused Reserved Sleep_A BiasLPF_A Reserved Reserved DLL_ sleep CONFIG7 0x07 0xFF CONFIG8 0x08 0x00 CONFIG9 0x09 0x00 CONFIG10 0x0A 0x00 CONFIG11 0x0B 0x00 CONFIG12 0x0C 0x00 CONFIG13 0x0D 0x00 CONFIG14 0x0E 0x00 CONFIG15 0x0F 0x00 18 Reserved DACA_gain(3:0) Reserved SW_sync SW_sync _sel Reserved Reserved DLL_ restart Reserved Reserved DLL_delay(3:0) DLL_invclk DLL_ifixed(2:0) Reserved Reserved Offset_sync OffsetA(12:8) OffsetA(7:0) SDO_func_sel(2:0) Reserved Reserved Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 DAC5681 www.ti.com SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 Register name: STATUS0 – Address: 0x00, Default = 0x1F Bit 7 Bit 6 Bit 5 Reserved 0 DLL_lock 0 Unused 0 Bit 4 Bit 3 1 device_ID(2:0) 1 Bit 2 Bit 1 Bit 0 version(1:0) 1 1 1 Reserved (Bit 7): Set to '0' by default. DLL_lock: Asserted when the internal DLL is locked. Once the DLL is locked, this bit should remain a ‘1’ unless the DCLK input clock is removed or abruptly changes frequency causing the DLL to fall out of lock. (Read Only) device_ID(2:0): Returns ‘111’ for DAC5681 Device_ID code. (ReadOnly) version(1:0): A hardwired register that contains the register set version of the chip. (ReadOnly) version (1:0) Identification ‘01’ ‘10’ ‘11' PG1.0 Initial Register Set PG1.1 Register Set Production Register Set Register name: CONFIG1 – Address: 0x01, Default = 0x10 Bit 7 Bit 6 DAC_delay(1:0) 0 0 Bit 5 Bit 4 Bit 3 Unused 0 Reserved 1 SLFTST_ena 0 Bit 2 Bit 1 Bit 0 0 FIFO_offset(2:0) 0 0 DAC_delay(1:0): DAC data delay adjustment. (0–3 periods of the DAC clock) This can be used to adjust system level output timing. The same delay is applied to DACA data paths. Reserved (Bit 4): Set to '1' for proper operation. SLFTST_ena: When set, a Digital Self Test (SLFTST) of the core logic is enabled. Refer to Digital Self Test Mode section for details on SLFTST operation. FIFO_offset(2:0): Programs the FIFO’s output pointer location, allowing the input pointer to be shifted –4 to +3 positions upon SYNC. Default offset is 0 and is updated upon each sync event. FIFO_offset(2:0) Offset 011 +3 010 +2 001 +1 000 0 111 –1 110 –2 101 –3 100 –4 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 19 DAC5681 SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com Register name: CONFIG2 – Address: 0x02, Default = 0xC0 Bit 7 Bit 6 Bit 5 Bit 4 Twos_comp 1 Reserved 1 Reserved 0 Unused 0 Bit 3 Bit 2 Bit 1 Bit 0 0 0 Reserved 0 0 Twos_comp: When set (default) the input data format is expected to be 2s complement, otherwise offset binary format is expected. Reserved (Bit 6): Set to '1' for proper operation. Reserved (Bit 5): Set to '0' for proper operation. Reserved (3:0): Set to '0000' for proper operation. Register name: CONFIG3 – Address: 0x03, Default = 0x70 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DAC_offset _ena 0 SLFTST_err _mask FIFO_err_ mask Pattern_err_ mask Reserved Reserved SW_sync SW_sync_sel 1 1 1 0 0 0 0 DAC_offset_ena: When set, the values of OffsetA(12:0) in CONFIG12 through CONFIG13 registers are summed into the DAC-A data path. This provides a system-level offset adjustment capability that is independent of the input data. SLFTST_err_mask: When set, masks out the SLFTST_err bit in STATUS4 register. Refer to Digital Self Test Mode section for details on SLFTST operation. FIFO_err_mask: When set, masks out the FIFO_err bit in STATUS4 register. Pattern_err_mask: When set, masks out the Pattern err bit in STATUS4 register. Reserved (Bit 3): Set to '0' for proper operation. Reserved (Bit 2): Set to '0' for proper operation. SW_sync: This bit can be used as a substitute for the LVDS external SYNC input pins for both synchronization and transmit enable control. SW_sync_sel: When set, the SW_sync bit is used as the only synchronization input and the LVDS external SYNC input pins are ignored. 20 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 DAC5681 www.ti.com SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 Register name: STATUS4 – Address: 0x04, Default = 0x00 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unused 0 SLFTST_err 0 FIFO_err 0 Pattern_err 0 Unused 0 Unused 0 Unused 0 Unused 0 SLFTST_err: Asserted when the Digital Self Test (SLFTST) fails. To clear the error, write a ‘0’ to this register bit. This bit is also output on the SDO pin when the Self Test is enabled via SLFTST_ena control bit in CONFIG1. Refer to Digital Self Test Mode section for details on SLFTST operation. FIFO_err: Asserted when the FIFO pointers over run each other causing a sample to be missed. To clear the error, write a ‘0’ to this register bit. Pattern_err: A digital checkerboard pattern compare function is provided for board level confidence testing and DLL limit checks. If the Pattern_err_mask bit via CONFIG3 is cleared, logic is enabled to continuously monitor input FIFO data. Any received data pattern other than 0xAAAA or 0x5555 causes this bit to be set. To clear the error, flush out the previous pattern error by inputting at least 8 samples of the 0xAAAA and/or 0x5555, then write a ‘0’ to this register bit. Register name: CONFIG5 – Address: 0x05, Default = 0x00 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIF4 rev_bus Reserved Reserved DLL_bypass Reserved Reserved 0 0 clkdiv_sync _dis 0 0 0 0 0 0 SIF4: When set, the serial interface is in 4 pin mode, otherwise it is in 3 pin mode. Refer to SDO_func_sel (2:0) bits in CONFIG14 register for options available to output status indicator data on the SDO pin. rev_bus: Reverses the LVDS input data bus so that the MSB to LSB order is swapped. This function is provided to ease board level layout and avoid wire crossovers in case the LVDS data source output bus is mirrored with respect to the DAC’s input data bus. clkdiv_sync_dis: Disables the clock divider sync when this bit is set. Reserved (Bit 4): Set to 0 for proper operation. Reserved (Bit 3): Set to '0' for proper operation. DLL_bypass: When set, the DLL is bypassed and the LVDS data source is responsible for providing correct setup and hold timing. Reserved (Bit 1): Set to '0' for proper operation. Reserved (Bit 0): Set to '0' for proper operation. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 21 DAC5681 SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com Register name: CONFIG6 – Address: 0x06, Default = 0x0C Bit 7 Reserved 0 Bit 6 Unused 0 Bit 5 Reserved 0 Bit 4 Sleep_A 0 Bit 3 Bit 2 Bit 1 Bit 0 BiasLPF_A 1 Reserved 1 Reserved 0 DLL_sleep 0 Reserved (Bit 7): Set to '0' for porper operation. Reserved (Bit 5): Set to '0' for proper operation. Sleep_A: When set, DACA is put into sleep mode. BiasLPF_A: Enables a 95 kHz low pass filter corner on the DACA current source bias when cleared. If this bit is set, a 472 kHz filter corner is used. Reserved (Bit 2): Set to '1' for proper operation. Reserved (Bit 1): Set to '0' for proper operation. DLL_sleep: When set, the DLL is put into sleep mode. Register name: CONFIG7 – Address: 0x07, Default = 0xFF Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 1 1 Bit 3 Bit 2 Bit 1 0 DLL_restart 0 DACA_gain(3:0) 1 1 Reserved 1 1 1 DACA_gain(3:0): Scales DACA output current in 16 equal steps. VEXTIO x (DACA_gain + 1) Rbias Reserved (3:0): Set to '1111' for proper operation. Register name: CONFIG8 – Address: 0x08, Default = 0x00 Bit 7 0 Bit 6 Bit 5 0 Reserved 0 Bit 4 0 Bit 0 Reserved 0 0 Reserved (7:3): Set to ‘00000’ for proper operation. DLL_restart: This bit is used to restart the DLL. When this bit is set, the internal DLL loop filter is reset to zero volts, and the DLL delay line is held at the center of its bias range. When cleared, the DLL will acquire lock to the DCLK signal. A DLL restart is accomplished by setting this bit with a serial interface write, and then clearing this bit with another serial interface write. Any interruption in the DCLK signal or changes to the DLL programming in the CONFIG10 register must be followed by this DLL restart sequence. Also, when this bit is set, the DLL_lock indicator in the STATUS0 register is cleared. Reserved (1:0): Set to ‘00’ for proper operation 22 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 DAC5681 www.ti.com SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 Register name: CONFIG9 – Address: 0x09, Default = 0x00 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 DLL_invclk 0 0 DLL_ifixed(2:0) 0 0 Reserved 0 Reserved (7:0): 0 0 0 Set to '0x00' for proper operation Register name: CONFIG10 – Address: 0x0A, Default = 0x00 Bit 7 Bit 6 Bit 5 DLL_delay(3:0) 0 DLL_delay(3:0): 0 0 The DCLKP/N LVDS input data clock has a DLL to automatically skew the clock to LVDS data timing relationship, providing proper setup and hold times. DLL_delay(3:0) is used to manually adjust the DLL delay ± from the fixed delay set by DLL_ifixed(2:0). Adjustment amounts are approximate. DLL_delay(3:0) Delay Adjust (degrees) 1000 50° 1001 55° 1010 60° 1011 65° 1100 70° 1101 75° 1110 80° 1111 85° 0000 90° (Default) 0001 95° 0010 100° 0011 105° 0100 110° 0101 115° 0110 120° 0111 125° DLL_invclk: When set, used to invert an internal DLL clock to force convergence to a different solution. This can be used in the case where the DLL delay adjustment has exceeded the limits of its range. DLL_ifixed(2:0): Adjusts the DLL delay line bias current. Refer to the Electrical Characteristics table. Used in conjunction with the DLL_invclk bit to select appropriate delay range for a given DCLK frequency: '011' – maximum bias current and minimum delay range '000' – mid scale bias current '101' – minimum bias current and maximum delay range '100' – do not use. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 23 DAC5681 SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com Register name: CONFIG11 – Address: 0x0B, Default = 0x00 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 Bit 3 Bit 2 Bit 1 Bit 0 0 OffsetA(12:8) 0 0 0 Reserved 0 0 Reserved (7:0): 0 0 Set to '0x00' for proper operation. Register name: CONFIG12 – Address: 0x0C, Default = 0x00 Bit 7 Bit 6 Bit 5 0 Offset_sync 0 Reserved 0 Bit 4 0 Reserved (1:0): Set to ‘00’ for proper operation. Offset_sync: On a change from ‘0’ to ‘1’ the values of the OffsetA(12:0) and OffsetB(12:0) control registers are transferred to the registers used in the DAC-A and DAC-B offset calculations. This double buffering allows complete control by the user as to when the change in the offset value occurs. This bit does not auto-clear. Prior to updating new offset values, it is recommended that the user clear this bit. OffsetA(12:8): Upper 5 bits of the offset adjustment value for the A data path. (SYNCED via Offset_sync) Register name: CONFIG13 – Address: 0x0D, Default = 0x00 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 OffsetA(7:0) 0 OffsetA(7:0): 24 0 0 0 Lower 8 bits of the offset adjustment value for the A data path. (SYNCED via Offset_sync) Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 DAC5681 www.ti.com SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 Register name: CONFIG14 – Address: 0x0E, Default = 0x00 Bit 7 Bit 6 0 SDO_func_sel(2:0) 0 SDO_func_sel(2:0): Reserved (4:0): Bit 5 Bit 4 0 0 Bit 3 Bit 2 Bit 1 Bit 0 0 Reserved 0 0 0 Selects the signal for output on the SDO pin. When using the 3 pin serial interface mode, this allows the user to multiplex several status indicators onto the SDO pin. In 4 pin serial interface mode, programming this register to view one of the 5 available status indicators will override normal SDO serial interface operation. SDO_func_sel (2:0) Output to SDO 000, 110, 111 Normal SDO function 001 Not defined 010 DLL_lock 011 Pattern_err 100 FIFO_err 101 SLFTST_err Set to '00000' for proper operation. Register name: CONFIG15 – Address: 0x0F, Default = 0x00 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 Reserved 0 Reserved (7:0): 0 0 0 Set to '0x00' for proper operation. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 25 DAC5681 SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com SERIAL INTERFACE The serial port of the DAC5681 is a flexible serial interface which communicates with industry standard microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the operating modes of DAC5681. It is compatible with most synchronous transfer formats and can be configured as a 3 or 4 pin interface by SIF4 in register CONFIG5. In both configurations, SCLK is the serial interface input clock and SDENB is serial interface enable. For 3 pin configuration, SDIO is a bidirectional pin for both data in and data out. For 4 pin configuration, SDIO is data in only and SDO is data out only. Data is input into the device with the rising edge of SCLK.Data is output from the device on the falling edge of SCLK. Each read/write operation is framed by signal SDENB (Serial Data Enable Bar) asserted low for 2 to 5 bytes, depending on the data length to be transferred (1–4 bytes). The first frame byte is the instruction cycle which identifies the following data transfer cycle as read or write, how many bytes to transfer, and what address to transfer the data. Table 2 indicates the function of each bit in the instruction cycle and is followed by a detailed description of each bit. Frame bytes 2 to 5 comprise the data transfer cycle. Table 2. Instruction Byte of the Serial Interface MSB Bit Description 7 R/W LSB 6 N1 5 N0 4 A4 3 A3 2 A2 1 A1 0 A0 R/W Identifies the following data transfer cycle as a read or write operation. A high indicates a read operation from DAC5681 and a low indicates a write operation to DAC5681. [N1 : N0] Identifies the number of data bytes to be transferred per Table 5 below. Data is transferred MSB first. Table 3. Number of Transferred Bytes Within One Communication Frame [A4 : A0] N1 N0 Description 0 0 Transfer 1 Byte 0 1 Transfer 2 Bytes 1 0 Transfer 3 Bytes 1 1 Transfer 4 Bytes Identifies the address of the register to be accessed during the read or write operation. For multibyte transfers, this address is the starting address. Note that the address is written to the DAC5681 MSB first and counts down for each byte. Figure 18 shows the serial interface timing diagram for a DAC5681 write operation. SCLK is the serial interface clock input to DAC5681. Serial data enable SDENB is an active low input to DAC5681. SDIO is serial data in. Input data to DAC5681 is clocked on the rising edges of SCLK. 26 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 DAC5681 www.ti.com SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 Instruction Cycle Data Transfer Cycle (s) SDENB SCLK SDIO r/w N1 N0 A4 A3 A2 A1 A0 D7 D6 tS (SDENB) D5 D4 D3 D2 D1 D0 tSCLK SDENB SCLK SDIO tSCLKL th (SDIO) tSCLKH tS (SDIO) Figure 18. Serial Interface Write Timing Diagram Figure 19 shows the serial interface timing diagram for a DAC5681 read operation. SCLK is the serial interface clock input to DAC5681. Serial data enable SDENB is an active low input to DAC5681. SDIO is serial data in during the instruction cycle. In 3 pin configuration, SDIO is data out from DAC5681 during the data transfer cycle(s), while SDO is in a high-impedance state. In 4 pin configuration, SDO is data out from DAC5681 during the data transfer cycle(s). At the end of the data transfer, SDO will output low on the final falling edge of SCLK until the rising edge of SDENB when it will 3-state. Instruction Cycle Data Transfer Cycle(s) SDENB SCLK SDIO r/w N1 N0 - A3 A2 A1 SDO A0 D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 3 pin Configuration Output 4 pin Configuration Output SDENB SCLK SDIO SDO Data n Data n-1 td (Data) Figure 19. Serial Interface Read Timing Diagram Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 27 DAC5681 SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com CLOCK AND DATA MODES The timing diagram for the DAC5681 is shown in Figure 20. The DAC5681 accepts an external full-rate clock input on the CLKIN/CLKINC pins to drive the DAC and final logic stages. An LVDS half-rate data clock (DCLKP/DCLKN) is provided by the user and is typically generated by a toggling data bit to maintain LVDS data to DCLK timing alignment. LVDS data relative to DCLK is input using Double Data Rate (DDR) switching using both rising and falling edges as shown in the both figures below. The CONFIG10 register contains user controlled settings for the DLL to adjust for the DCLK input frequency and various tSKEW timing offsets between the LVDS data and DCLK. The CDCM7005 and CDCE62005 from Texas Instruments are recommended for providing phase aligned clocks at different frequencies for device-to-device clock distribution and multiple DAC synchronization. CLKIN CLKINC DACCLK (Internal) DCLKN DCLKP tSKEW(A) tSKEW(B) Valid Data (A) tH tS Valid Data (B) SYNCN Transmit Enable / Synchronization Event SYNCP D[15:0]N D[15:0]P Single DAC Mode (1X1) A0 A1 A2 A3 AN AN+1 Figure 20. Clock and Data Timing Diagram 28 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 DAC5681 www.ti.com SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 CLOCK INPUTS Figure 21 shows an equivalent circuit for the LVDS data input clock (DCLKP/N). 27 kW DVDD DCLKP Note: Input and output common mode level self-biases to approximately DVDD/2, or 0.9 V normal. DVDD GND DCLKN GND 27 kW Figure 21. DCLKP/N Equivalent Input Circuit Figure 22 shows an equivalent circuit for the DAC input clock (CLKIN/C). 6 kW CLKVDD CLKIN Note: Input and output common mode level self-biases to approximately CLKVDD/2, or 0.9 V normal. CLKVDD GND CLKINC GND 6 kW Figure 22. CLKIN/C Equivalent Input Circuit Figure 23 shows the preferred configuration for driving the CLKIN/CLKINC input clock with a differential ECL/PECL source. Differential ECL or (LV)PECL Source 0.01 µF CLKIN CAC 100 CLKINC RPU VTT RPD 0.01 µF RPU and RPD are chosen based on the clock driver Figure 23. Preferred Clock Input Configuration With a Differential ECL/PECL Clock Source Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 29 DAC5681 SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com LVDS DATA INTERFACING Interfacing very high-speed LVDS data and clocks presents a big challenge to system designers as they have unique constraints and are often implemented with specialized circuits to increase bandwidth. One such specialized LVDS circuit used in many FPGAs and ASICs is a SERializer-DESerializer (SERDES) block. For interfacing to the DAC5681, only the SERializer functionality of the SERDES block is required. SERDES drivers accept lower rate parallel input data and output a serial stream using a shift register at a frequency multiple of the data bit width. For example, a 4-bit SERDES block can accept parallel 4-bit input data at 250 MSPS and output serial data 1000 MSPS. External clock distribution for FPGA and ASIC SERDES drivers often have a chip-to-chip system constraint of a limited input clock frequency compared to the desired LVDS data rate. In this case, an internal clock multiplying PLL is often used in the FPGA or ASIC to drive the high-rate SERDES outputs. Due to this possible system clocking constraint, the DAC5681 accommodates a scheme where a toggling LVDS SERDES data bit can provide a “data driven” half-rate clock (DCLK) from the data source. A DLL on-board the DAC is used to shift the DCLK edges relative to LVDS data to maintain internal setup and hold timing. To increase bandwidth of a single 16-bit input bus, the DAC5681 assumes Double Data Rate (DDR) style interfacing of data relative to the half-rate DCLK. Refer to Figure 24 and Figure 25 providing an example implementation using FPGA-based LVDS data and clock interfaces to drive the DAC5681. In this example, an assumed system constraint is that the FPGA can only receive a 250 MHz maximum input clock while the desired DAC clock is 1000 MHz. A clock distribution chip such as the CDCM7005 or the CDCE62005 is useful in this case to provide frequency and phase locked clocks at 250 MHz and 1000 MHz. FPGA / ASIC DAC5681 DAC Antenna SYNC 100 1.0 GHz CDCM7005 PLL_LOCK PD# LE DATA CLK RESET# CDCM7005 Control Status & Control PLL Synth VCTRL_IN Loop Filter REF_IN PFD RDiv Loop Filter Charge Pump CPOUT Status & Control VCXO 1000 MHz STRB ÷1 Clock Divider / Distribution VCO NDivider 10 MHz REF OSC Term ÷4 VCXO_STATUS REF_STATUS Div 1/2/4 1.0 GHz Term 100 TRF3761-X PLL/VCO CHIP_EN Freq/Phase Locked 250 MHz ~ 2.1 GHz CLK DAC5681 Control DLL To RX Path Control DATA 250 MHz DLL 100 500 MHz Toggling Data Bit CLKP CLKP DCLK 4x Clock Multiplier To TX Feedback 3.3V 100 SERDES Duplexer SERDES PA DAC LOCK_DET 100 3.3V PD_BUF D0 100 SERDES 3.3V 100 100 FIFO & Demux Q D15 1.0 GBPS (DDR) SDIO SDO SDENB SCLK RESETB I Parallel to SERDES Formatter TX Data Source SERDES TRF3761-X Control Figure 24. Example Direct Conversion System Diagram From the example provided by Figure 25, driving LVDS data into the DAC using SERDES blocks requires a parallel load of 4 consecutive data samples to shift registers. Color is used in the figure to indicate how data and clocks flow from the FPGA to the DAC5681. The figure also shows the use of the SYNCP/N input, which along with DCLK, requires 18 individual SERDES data blocks to drive the DAC’s input data FIFO that provides an elastic buffer to the DAC5681 digital processing chain. 30 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 DAC5681 www.ti.com SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 4x Clock Multiplier PLL Ref CLK Gen & Sync 250MHz Clock 4b SERDES (CLKOUT) 4 4b SERDES (SYNC) LVDS 4b SERDES (bit 15) LVDS 1,0,1,0... DAC DCLKP LVDS 500MHz (½ Rate) DCLK Delay Lock Loop DCLKN CLKA (500MHz) SYNCP SYNCN SYNC 16 1000MSPS DDR (2 bits/CLKIN cycle) 4 16 D15N 4b SERDES (bit 0) LVDS 100 4 D0P D0N 100 16 Serializer Format D15P 16 1 0 CLKB (500MHz) 8 Sample Input FIFO 1111 1101 1111 “ 250MHz Data Source (4 phases) x4 4 1010 1010 1010 “ System SYNC 1000MHz ÷1 100 250MHz Using common “data driven” SERDES blocks, relative delays from CLK, SYNC and DATA are matched. (200pS) 100 FPGA To DAC 250 MHz (FPGA) 1000 MHz (FPGA) DCLK Data Nibble 0101 DDR Clock Gen Repeating 4 bit Sequence “1010” … DCLKP/N 1 0 1 0 1 0 1 0 1 0 500 MHz CLKIN to DLL CLKA F 500 MHz CLKA (DAC) DLL Phase Offset control determines CLKA/B skew. CLKB F Sample “S1” S1[15:0] Sample “S2” S2[15:0] Sample “S3” S3[15:0] Sample “S4” S4[15:0] 500 MHz CLKB (DAC) SYNC Data Nibble 1011 SYNC Generator Normally = “1111” Ocassional = “1101” for SYNC event SYNCP/N SERDES 1 1 0 1 1 1 1 SYNC input combines TXENABLE function (normally “1”) and SYNChronizer function (“0” to “1” transition) 1 Bit 15 Data Nibble S1[15:0] S2[15:0] S4[15:0] S3[15:0] S4[15] S3[15] S2[15] S1[15] D15P/N SERDES Bit 0 Data Nibble S4[0] S3[0] S2[0] S1[0] D0P/N SERDES Figure 25. Example FPGA-Based LVDS Data Flow to DAC LVDS INPUTS The D[15:0]P/N and SYNCP/N LVDS pairs have the input configuration shown in Figure 26. Figure 27 shows the typical input levels and common-mode voltage used to drive these inputs. D[15:0]P, SYNCP 50 W To Adjacent LVDS Input D[15:0]N, SYNCN 100 pF Total 50 W Ref Note (1) To Adjacent LVDS Input LVDS Receiver Note (1): RCENTER node common to all D[15:0]P/N and SYNCP/N receiver inputs Figure 26. D[15:0]P/N and SYNCP/N LVDS Input Configuration Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 31 DAC5681 SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com Example DAC5681 D[15:0]P, SYNCP VCOM1 = (VA +VB )/2 LVDS Receiver 100 W VA,B VA VA 1.40 V VB 1.00 V VA,B 400 mV 0V D[15:0]N, SYNCN VB -400 mV GND 1 Logical Bit Equivalent 0 Figure 27. LVDS Data (D[15:0]P/N, SYNCP/N Pairs) Input Levels Table 4. Example LVDS Data Input Levels APPLIED VOLTAGES RESULTING DEFERENTIAL VOLTAGE RESULTING COMMONMODE VOLTAGE VA VB VA,B VCOM1 1.4 V 1.0 V 400 mV 1.2 V 1.0 V 1.4 V –400 mV 1.2 V 0.8 V 400 mV 0.8 V 1.2 V –400 mV LOGICAL BIT BINARY EQUIVALENT 1 0 1.0 V 1 0 Figure 28 shows the DCLKP/N LVDS clock input levels. Unlike the D[15:0]P/N and SYNCP/N LVDS pairs, the DCLKP/N pair does not have an internal resistor and the common-mode voltage is self-biased to approximately DVDD/2 in order to optimize the operation of the DLL circuit. For proper external termination a 100 Ω resistor needs to be connected across the LVDS clock source lines followed by series 0.01 μF capacitors connected to each of the DCLKP and DCLKN pins. For best performance, the resistor and capacitors should be placed as close as possible to these pins. Note: AC Coupled DAC5681 Self-bias (VBIAS) 0.01 mF 100 W DCLKP VA,B DLL Circuit VA 0.01 mF DCLKN VB GND VCOM2 =~ DVDD/2 Figure 28. LVDS Clock (DCLKP/N) Input Levels LVDS SYNCP/N Operation The SYNCP/N LVDS input control functions as a combination of Transmit Enable (TXENABLE) and Synchronization trigger. If SYNCP is low, the transmit chain is disabled so input data from the FIFO is ignored while zeros are inserted into the data path. If SYNCP is raised from low to high, a synchronization event occurs with behavior defined by individual control bits in registers CONFIG1 and CONFIG5. The SYNCP/N control is sampled and input into the FIFO along with the other LVDS data to maintain timing alignment with the data bus. See Figure 25. The software_sync_sel and software_sync controls in CONFIG3 provide a substitute for external SYNCP/N control; however, since the serial interface is used no timing control is provided with respect to the DAC clock. 32 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 DAC5681 www.ti.com SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 DLL OPERATION The DAC5681 provides a digital Delay Lock Loop (DLL) to skew the LVDS data clock (DCLK) relative to the data bits, D[15:0] and SYNC, in order to maintain proper setup and hold timing. Since the DLL operates closed-loop, it requires a stable DCLK to maintain delay lock. Refer to the description of DLL_ifixed(2:0) and DLL_delay(3:0) control bits in the CONFIG10 register. Prior to initializing the DLL, the DLL_ifixed value should be programmed to match the expected DCLK frequency range. To initialize the DLL, refer to the DLL_Restart programming bit in the CONFIG8 register. After initialization, the status of the DLL can be verified by reading the DLL_Lock bit from STATUS0. See Startup Sequence below. RECOMMENDED STARTUP SEQUENCE The following startup sequence is recommended to initialize the DAC5681: 1. Supply all 1.8V (CLKVDD, DVDD, VFUSE) voltages simultaneously followed by all 3.3V (AVDD and IOVDD) voltages. 2. Provide stable CLKIN/C clock. 3. Toggle RESETB pin for a minimum 25 nSec active low pulse width. 4. Program all desired SIF registers. Set DLL_Restart bit during this write cycle. The CONFIG10 register value should match the corresponding DCLKP/N frequency range in the Electrical Characteristics table. 5. Provide stable DCLKP/N clock. (This can also be provided earlier in the sequence) 6. Clear the DLL_Restart bit when the DCLKP/N clock is expected to be stable. 7. Verify the status of DLL_Lock and repeat until set to ‘1’. DLL_Lock can be monitored by reading the STATUS0 register or by monitoring the SDO pin in 3-wire SIF mode. (See description for CONFIG14 SDO_func_sel.) 8. Enable transmit of data by asserting the LVDS SYNCP/N input or setting CONFIG3 SW_sync bit. (See description for CONFIG3 SW_sync and SW_sync_sel) The SYNC source must be held at a logic ‘1’ to enable data flow through the DAC. If multiple DAC devices require synchronization, refer to the "Recommended Multi-DAC Synchronization Procedure" below. 9. Provide data flow to LVDS D[15:0]P/N pins. If using the LVDS SYNCP/N input, data can be input simultaneous with the logic ‘1’ transition of SYNCP/N. RECOMMENDED MULTI-DAC SYNCHRONIZATION PROCEDURE The DAC5681 provides a mechanism to synchronize multiple DAC devices in a system. The procedure has two steps involving control of the CONFIG5 clkdiv_sync_dis as well as external control of the LVDS SYNCP/N input. (All DACs involved need to be configured to accept the external SYNCP/N input and not "software" sync mode). 1. Synchronize Clock Dividers (for each DAC): (a) Set CONFIG5 clkdiv_sync_dis = 0. (b) Toggle SYNCP/N input to all DACs simultaneously (same input to all DACs). 2. Synchronize FIFO pointers (for each DAC): (a) Set CONFIG5 clkdiv_sync_dis = 1 (Disable clock divider re-sync). (b) Wait a minimum of 50 CLKIN cycles from previous SYNCP/N toggle. In practice, the time required to write the above register value will typically occupy more than 50 cycles. (c) Assert SYNCP/N input and hold at '1' to all DACs simultaneously. Holding this at '1' is effectively the TXENABLE for the chip so data will be output on the analog pins. 3. After the normal pipeline delay of the device, the outputs of all DACs will be synchronized to within ±1 DAC clock cycle. CMOS DIGITAL INPUTS Figure 29 shows a schematic of the equivalent CMOS digital inputs of the DAC5681. SDIO and SCLK have pulldown resistors while RESETB and SDENB have pull-up resistors internal the DAC5681. See the specification table for logic thresholds. The pull-up and pull-down circuitry is approximately equivalent to 100kΩ. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 33 DAC5681 SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com IOVDD IOVDD internal digital in SDIO SCLK internal digital in RESETB SDENB IOGND IOGND Figure 29. CMOS/TTL Digital Equivalent Input DIGITAL SELF TEST MODE The DAC5681 has a Digital Self Test (SLFTST) mode to designed to enable board level testing without requiring specific input data test patterns. The SLFTST mode is enabled via the CONFIG1 SLFTST_ena bit and results are only valid when CONFIG3 SLFTST_err_mask bit is cleared. An internal Linear Feedback Shift Register (LFSR) is used to generate the input test patterns for the full test cycle while a checksum result is computed on the digital signal chain outputs. The LVDS input data bus is ignored in SLFTST mode. After the test cycle completes, if the checksum result does not match a hardwired comparison value, the STATUS4 SLFTST_err bit is set and will remain set until cleared by writing a ‘0’ to the SLFTST_err bit. A full self test cycle requires no more than 400,000 CLKIN/C clock cycles to complete and will automatically repeat until the SLFTEST_ena bit is cleared. 34 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 DAC5681 www.ti.com To 1. 2. 3. 4. 5. 6. 7. 8. SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 initiate the Digital Self Test: Provide a normal CLKIN/C input clock. Provide a RESETB pulse to perform a hardware reset on device. Program the registers with the values shown in Table 5. These register values contain the settings to properly configure the SLFTST including SLFTST_ena and SLFTST_err_mask bits Provide a ‘1’ on the SYNCP/N input to initiate TXENABLE. Wait at a minimum of 400,000 CLKIN/C cycles for the SLFTST to complete. Example: If CLKIN = 1GHz, then the wait period is 400,000 × 1 / 1GHz = 400 μSec. Read STATUS4 SLFTST_err bit. If set, a self test error has occurred. The SLFTST_err status may optionally be programmed to output on the SDO pin if using the 3-bit SIF interface. See Table 5 Note (1). (Optional) The SLFTST function automatically repeats until SLFTST_ena bit is cleared. To loop the test, write a ‘0’ to STATUS4 SLFTST_err to clear previous errors and continue at step 5 above. To continue normal operating mode, provide another RESETB pulse and reprogram registers to the desired normal settings. Table 5. Digital Self Test (SLFTST) Register Values REGISTER ADDRESS (hex) VALUE (Binary) VALUE (Hex) CONFIG1 01 00011000 18 CONFIG2 02 11101010 EA CONFIG3 03 10110000 B0 STATUS4 04 00000000 00 CONFIG5 05 00000110 06 CONFIG6 06 00001111 0F CONFIG12 0C 00001010 0A CONFIG13 0D 01010101 55 CONFIG14 (1) (1) 0E 00001010 0A CONFIG15 0F 10101010 AA All others – Default Default If using a 3-bit SIF interface, the SDO pin can be programmed to report SLFTST_err status via the SDO_fun_sel(2:0) bits. In this case, set CONFIG14 = ‘10101010’ or AA hex. REFERENCE OPERATION The DAC5681 uses a bandgap reference and control amplifier for biasing the full-scale output current. The fullscale output current is set by applying an external resistor RBIAS to pin BIASJ. The bias current IBIAS through resistor RBIAS is defined by the on-chip bandgap reference voltage and control amplifier. The default full-scale output current equals 16 times this bias current and can thus be expressed as: IOUTFS = 16 × IBIAS = 16 × VEXTIO / RBIAS The DAC has a 4-bit coarse gain control via DACA_gain(3:0) in the CONFIG7 register so the IOUTFS can expressed as: IOUTAFS = (DACA_gain + 1) × IBIAS = (DACA_gain + 1) × VEXTIO / RBIAS where VEXTIO is the voltage at terminal EXTIO. The bandgap reference voltage delivers an accurate voltage of 1.2 V. This reference is active when terminal EXTLO is connected to AGND. An external decoupling capacitor CEXT of 0.1 μF should be connected externally to terminal EXTIO for compensation. The bandgap reference can additionally be used for external reference operation. In that case, an external buffer with high impedance input should be applied in order to limit the bandgap load current to a maximum of 100 nA. The internal reference can be disabled and overridden by an external reference by connecting EXTLO to AVDD. Capacitor CEXT may hence be omitted. Terminal EXTIO thus serves as either input or output node. The full-scale output current can be adjusted from 20 mA down to 2 mA by varying resistor RBIAS or changing the externally applied reference voltage. The internal control amplifier has a wide input range, supporting the fullscale output current range of 20 dB. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 35 DAC5681 SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com DAC TRANSFER FUNCTION The CMOS DAC’s consist of a segmented array of NMOS current sinks, capable of sinking a full-scale output current up to 20 mA. Differential current switches direct the current to either one of the complementary output nodes IOUT1 or IOUT2. Complementary output currents enable differential operation, thus canceling out common mode noise sources (digital feed-through, on-chip and PCB noise), dc offsets, even order distortion components, and increasing signal output power by a factor of two. The full-scale output current is set using external resistor RBIAS in combination with an on-chip bandgap voltage reference source (+1.2 V) and control amplifier. Current IBIAS through resistor RBIAS is mirrored internally to provide a maximum full-scale output current equal to 16 times IBIAS. The relation between IOUT1 and IOUT2 can be expressed as: IOUT1 = – IOUTFS – IOUT2 We will denote current flowing into a node as – current and current flowing out of a node as + current. Since the output stage is a current sink the current can only flow from AVDD into the IOUT1 and IOUT2 pins. The output current flow in each pin driving a resistive load can be expressed as: IOUT1 = IOUTFS × (65536 – CODE) / 65536 IOUT2 = IOUTFS × CODE / 65536 where CODE is the decimal representation of the DAC data input word. For the case where IOUT1 and IOUT2 drive resistor loads RL directly, this translates into single ended voltages at IOUT1 and IOUT2: VOUT1 = AVDD – | IOUT1 | × RL VOUT2 = AVDD – | IOUT2 | × RL Assuming that the data is full scale (65536 in offset binary notation) and the RL is 25 Ω, the differential voltage between pins IOUT1 and IOUT2 can be expressed as: VOUT1 = AVDD – | –0 mA | × 25 Ω = 3.3 V VOUT2 = AVDD – | –20 mA | × 25 Ω = 2.8 V VDIFF = VOUT1 – VOUT2 = 0.5 V Note that care should be taken not to exceed the compliance voltages at node IOUT1 and IOUT2, which would lead to increased signal distortion. 36 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 DAC5681 www.ti.com SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 DAC OUTPUT SINC RESPONSE Due to the sampled nature of a high-speed DAC, the well known sin(x)/x (or SINC) response can significantly attenuate higher frequency output signals. Figure 30 shows the unitized SINC attenuation roll-off with respect to the final DAC sample rate in 4 Nyquist zones. For example, if the final DAC sample rate FS = 1.0 GSPS, then a tone at 440MHz is attenuated by 3.0dB. Although the SINC response can create challenges in frequency planning, one side benefit is the natural attenuation of Nyquist images. Figure 30. Unitized DAC sin(x)/x (SINC) Response Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 37 DAC5681 SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com ANALOG CURRENT OUTPUTS Figure 31 shows a simplified schematic of the current source array output with corresponding switches in a current sink configuration. Differential switches direct the current into either the positive output node, IOUT1, or its complement, IOUT2, then through the individual NMOS current sources. The output impedance is determined by the stack of the current sources and differential switches, and is typically >300 kΩ in parallel with an output capacitance of 5 pF. The external output resistors are referenced to an external ground. The minimum output compliance at nodes IOUT1 and IOUT2 is limited to AVDD – 0.5 V, determined by the CMOS process. Beyond this value, transistor breakdown may occur resulting in reduced reliability of the DAC5681 device. The maximum output compliance voltage at nodes IOUT1 and IOUT2 equals AVDD + 0.5 V. Exceeding the minimum output compliance voltage adversely affects distortion performance and integral non-linearity. The optimum distortion performance for a single-ended or differential output is achieved when the maximum full-scale signal at IOUT1 and IOUT2 does not exceed 0.5 V. AVDD R LOAD IOUT1 R LOAD IOUT2 S(1) S(N) S(2) S(1)C S(2)C ... S(N)C Figure 31. Equivalent Analog Current Output The DAC5681 can be easily configured to drive a doubly terminated 50Ω cable using a properly selected RF transformer. Figure 32 and Figure 33 show the 50Ω doubly terminated transformer configuration with 1:1 and 4:1 impedance ratio, respectively. Note that the center tap of the primary input of the transformer has to be connected to AVDD to enable a dc current flow. Applying a 20 mA full-scale output current would lead to a 0.5 VPP for a 1:1 transformer, and a 1 VPP output for a 4:1 transformer. The low dc-impedance between IOUT1 or IOUT2 and the transformer center tap sets the center of the ac-signal at AVDD, so the 1 VPP output for the 4:1 transformer results in an output between AVDD + 0.5 V and AVDD – 0.5 V. 38 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 DAC5681 www.ti.com SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 AVDD (3.3 V) 50 W 1:1 IOUT1 RLOAD 100 W 50 W IOUT2 50 W AVDD (3.3 V) Figure 32. Driving a Doubly-Terminated 50-Ω Cable Using a 1:1 Impedance Ratio Transformer AVDD (3.3 V) 100 W 4:1 IOUT1 RLOAD 50 W IOUT2 100 W AVDD (3.3 V) Figure 33. Driving a Doubly-Terminated 50-Ω Cable Using a 4:1 Impedance Ratio Transformer Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 39 DAC5681 SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com APPLICATIONS EXAMPLES DIGITAL INTERFACE AND CLOCKING CONSIDERATIONS FOR APPLICATION EXAMPLES The DAC5681’s LVDS digital input bus can be driven by an FPGA or digital ASIC. This input signal can be generated directly by the FPGA, or fed by a Texas Instruments Digital Up Converter (DUC) such as the GC5016 or GC5316. Optionally, a GC1115 Crest Factor Reduction (CFR) or Digital Pre-Distortion (DPD) processor may be inserted in the digital signal chain for improving the efficiency of high-power RF amplifiers. For the details on the DAC’s high-rate digital interface, refer to the LVDS Data Interfacing section. A low phase noise clock for the DAC at the final sample rate can be generated by a VCXO and a Clock Synchronizer/PLL such as the Texas Instruments CDCM7005 or CDCE62005, which can also provide other system clocks. DIGITAL IF OUTPUT RADIO Refer to Figure 34 for an example Digital IF Output Radio. The high data rate of the DAC5681 (up to 1.0GSPS) allows for extremely wide bandwidth signals. The DAC output signal would typically be terminated with a transformer (see the Analog Current Outputs section). An IF filter, either LC or SAW, is used to suppress the DAC Nyquist zone images and other spurious signals before being mixed to RF with a mixer. The TRF3671 Frequency Synthesizer, with integrated VCO, may be used to drive a common LO input of the mixers for frequencies between 375 and 2380 MHz. DAC5681 DAC D0P/N 100 SYNCP/N 100 3.3V 100 100 3.3V RF Processing DAC 100 D15P/N FIFO & Demux LVDS Data Interface 3.3V DCLKP/N PLL/ DLL DLL 1000 MHz 100 250 MHz 375 MHz Min to 2380 MHz Max (Depends on divider and “dash #” of TRF3761) 100 100 CLKIN/C GC5016 or GC5316 DUC, With GC1115 CFR and/or DPD Processor FPGA Div 1/2/4 VCXO ÷4 ÷1 Clock Divider / Distribution VCO NDivider PLL PFD RDiv CDCM7005 Note : For clarity, only signal paths are shown. VCTRL_IN Loop Filter Loop Filter 10 MHz OSC CPOUT TRF3761-X PLL/VCO Figure 34. System Diagram of a Dual Channel Real IF Output Radio 40 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 DAC5681 www.ti.com SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 APPLICATIONS EXAMPLES (continued) CMTS/VOD TRANSMITTER The exceptional SNR of the DAC5681 enables a cable modem termination system (CMTS) or video on demand (VOD) QAM transmitter in excess of the stringent DOCSIS specification, with >74 dBc and 75 dBc in the adjacent and alternate channels. See Figure 34 for an example IF Output Radio – this signal chain is nearly identical to a typical system using the DAC5681 for a cost optimized two QAM transmitter. A GC5016 would accept two separate symbol rate inputs and provide pulse shaping and interpolation to ~ 128 MSPS. The two QAM carriers would be combined into two groups of two QAM carriers with intermediate frequencies of approximately 30 MHz to 40 MHz. The GC5016 would output data to the DAC5681 through an FPGA for CMOS to LVDS translation. The signal is output through a transformer and to an RF upconverter. HIGH-SPEED ARBITRARY WAVEFORM GENERATOR The 1GSPS bandwidth input data bus combined with the 16-bit DAC resolution of the DAC5681 allows wideband signal generation for test and measurement applications. The FPGA-based waveform generator can make use of the full Nyquist bandwidth of up to 500MHz. DAC5681 DAC D15P/N 100 D0P/N 100 SYNCP/N 100 FIFO LVDS Data Interface FPGA DAC DCLKP/N 100 DLL Figure 35. System Diagram of Arbitrary Waveform Generator Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 41 DAC5681 SLLS864C – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com REVISION HISTORY Note: Page numbers of current version may differ from previous versions. Changes from Original (August 2007) to Revision A Page • Changed tr(IOUT) spec. output rise time 10% to 90% typical value from 2 ns to 220 ps ........................................................ 8 • Changed tf(IOUT) spec. output fall time 10% to 90% typical value from 2 ns to 220 ps ......................................................... 8 • Changed ZT spec. internal termination from 100 Ω min, 120 Ω max; to 85 Ω min, 135 Ω max ........................................... 9 • Deleted temperature deratings for fDATA specifications ......................................................................................................... 9 • Added DLL operating frequency range specifications .......................................................................................................... 9 • Changed CAC values from 0.1 to 0.01μF, Figure 23 ........................................................................................................... 29 Changes from Revision A (January 2009) to Revision B Page • Changed Table 1 Bit 4 from FIFO_sync_dis to Reserved .................................................................................................. 18 • Changed Table 1 Bit 7 from Hold_sync _dis to Reserved .................................................................................................. 18 • Deleted "– unless disabled via FIFO_sync_dis in CONFIG5 register" from the Description of CONFIG1 FIFO_offset(2:0) .................................................................................................................................................................. 19 • Changed "FIFO_sync_dis", to "Reserved" in CONFIG5 table, Bit 4 .................................................................................. 21 • Changed CONFIG5: FIFO_sync_dis: Description from "....CONFIG1 register" to "Reserved (Bit 4): Set to 0 for poper operation." ........................................................................................................................................................................... 21 • Changed CONFIG6, Bit 7 from "Hold_sync _dis" to "Reserved" ........................................................................................ 22 • Changed CONFIG6 : Hold_sync_dis: Description from "When set.....in CONFIG5." to "Reserved (Bit 7): Set to 0 for proper operation." ............................................................................................................................................................... 22 • Changed LVDS SYNCP/N section text from "....with behavior defined by individual control bits in registers CONFIG1, CONFIG5 and CONFIG6. to "....with behavior defined by individual control bits in registers CONFIG1 and CONFIG5." ................................................................................................................................................................... 32 • Changed text in RECOMMENDED MULTI-DAC SYNCHRONIZATION PROCEDURE section from "The procedure has two steps ...... SYNCP/N input" to "The procedure has two steps involving control of the CONFIG5 clkdiv_sync_dis as well as external control of the LVDS SYNCP/N input" ...................................................................... 33 • Deleted the sub-step "Set CONFIG5 FIFO_sync_dis = 0" in procedural steps for Synchronize Clock Dividers (for each DAC) in RECOMMENDED ....PROCEDURE section. ............................................................................................... 33 • Deleted the sub-step "Set CONFIG5 FIFO_sync_dis = 0 (Keep same as step 1)" in procedural steps for Synchronize FIFO pointers (for each DAC) in RECOMMENDED ....PROCEDURE section. ............................................ 33 Changes from Revision B (April 2011) to Revision C Page • Changed the revision date to C, August 2012 ...................................................................................................................... 1 • Changed Figure 23 for clarification. .................................................................................................................................... 29 • Changed the first paragraph of ANALOG CURRENT OUTPUTS section for clarification. ................................................ 38 42 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: DAC5681 PACKAGE MATERIALS INFORMATION www.ti.com 6-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC5681IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 DAC5681IRGCT VQFN RGC 64 250 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC5681IRGCR VQFN RGC 64 2000 336.6 336.6 28.6 DAC5681IRGCT VQFN RGC 64 250 336.6 336.6 28.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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