DS90LV018A www.ti.com SNLS014D – JUNE 1998 – REVISED APRIL 2013 DS90LV018A 3V LVDS Single CMOS Differential Line Receiver Check for Samples: DS90LV018A FEATURES DESCRIPTION • • • • • • • • • The DS90LV018A is a single CMOS differential line receiver designed for applications requiring ultra low power dissipation, low noise and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology. 1 2 • • • • >400 Mbps (200 MHz) Switching Rates 50 ps Differential Skew (Typical) 2.5 ns Maximum Propagation Delay 3.3V Power Supply Design Flow-Through Pinout Power Down High Impedance on LVDS Inputs Low Power Design (18mW @ 3.3V Static) Interoperable with Existing 5V LVDS Networks Accepts Small Swing (350 mV Typical) Differential Signal Levels Supports Open, Short and Terminated Input Fail-Safe Conforms to ANSI/TIA/EIA-644 Standard Industrial Temperature Operating Range – (−40°C to +85°C) Available in SOIC Package The DS90LV018A accepts low voltage (350 mV typical) differential input signals and translates them to 3V CMOS output levels. The receiver also supports open, shorted and terminated (100Ω) input fail-safe. The receiver output will be HIGH for all failsafe conditions. The DS90LV018A has a flow-through design for easy PCB layout. The DS90LV018A and companion LVDS line driver provide a new alternative to high power PECL/ECL devices for high speed point-to-point interface applications. Connection Diagram Figure 1. SOIC See Package Number D (R-PDSO-G8) Functional Diagram Truth Table INPUTS OUTPUT [RIN+] − [RIN−] ROUT VID ≥ 0.1V H VID ≤ −0.1V L Full Fail-safe OPEN/SHORT or Terminated H 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1998–2013, Texas Instruments Incorporated DS90LV018A SNLS014D – JUNE 1998 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) −0.3V to +4V Supply Voltage (VCC) Input Voltage (RIN+, RIN−) −0.3V to +3.9V −0.3V to (VCC + 0.3V) Output Voltage (ROUT) Maximum Package Power Dissipation @ +25°C D Package 1025 mW Derate D Package 8.2 mW/°C above +25°C −65°C to +150°C Storage Temperature Range Lead Temperature Range Soldering (4 sec.) +260°C Maximum Junction Temperature +150°C ESD Rating ≥ 7 kV (HBM 1.5 kΩ, 100 pF) ≥ 500 V (EIAJ 0Ω, 200 pF) (1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be specified. They are not meant to imply that the devices should be operated at these limits. Electrical Characteristics specifies conditions of device operation. Recommended Operating Conditions Min Typ Max Units Supply Voltage (VCC) +3.0 +3.3 +3.6 V Receiver Input Voltage GND 3.0 V +85 °C Operating Free Air Temperature (TA) 2 −40 Submit Documentation Feedback 25 Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: DS90LV018A DS90LV018A www.ti.com SNLS014D – JUNE 1998 – REVISED APRIL 2013 Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (1) (2) Symbol Parameter Conditions VTH Differential Input High Threshold VTL Differential Input Low Threshold IIN Input Current VCM = +1.2V, 0V, 3V VIN = +2.8V (3) Pin Min RIN+, RIN− −100 VCC = 3.6V or 0V VIN = 0V VIN = +3.6V VOH VCC = 0V mV ±1 +10 μA −10 ±1 +10 μA +20 μA V 2.7 3.1 V IOH = −0.4 mA, Inputs shorted 2.7 3.1 IOS Output Short Circuit Current VOUT = 0V (4) VCL Input Clamp Voltage ICL = −18 mA ICC No Load Supply Current Inputs Open (4) mV IOH = −0.4 mA, Inputs terminated IOL = 2 mA, VID = −200 mV (2) (3) +100 3.1 Output Low Voltage (1) Units 2.7 VOL ROUT Max −10 -20 IOH = −0.4 mA, VID = +200 mV Output High Voltage Typ V 0.3 0.5 V −15 −50 −100 mA −1.5 −0.8 9 mA VCC 5.4 V Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise specified (such as VID). All typicals are given for: VCC = +3.3V and TA = +25°C. VCC is always higher than RIN+ and RIN− voltage. RIN+ and RIN− are allowed to have voltage range −0.05V to +3.05V. VID is not allowed to be greater than 100 mV when VCM = 0V or 3V. Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not exceed maximum junction temperature specification. Switching Characteristics VCC = +3.3V ± 10%, TA = −40°C to +85°C (1) (2) Min Typ Max Units tPHLD Symbol Differential Propagation Delay High to Low CL = 15 pF 1.0 1.6 2.5 ns tPLHD Differential Propagation Delay Low to High VID = 200 mV 1.0 1.7 2.5 ns tSKD1 Differential Pulse Skew |tPHLD − tPLHD| (3) 0 50 400 ps tSKD3 Differential Part to Part Skew (4) 0 1.0 ns tSKD4 Differential Part to Part Skew (5) 0 1.5 ns tTLH Rise Time 325 800 ps tTHL Fall Time 225 800 ps fMAX (1) (2) (3) (4) (5) (6) Parameter Maximum Operating Frequency Conditions (Figure 2 and Figure 3) (6) 200 250 MHz CL includes probe and jig capacitance. Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr and tf (0% to 100%) ≤ 3 ns for RIN. tSKD1 is the magnitude difference in differential propagation delay time between the positive-going-edge and the negative-going-edge of the same channel. tSKD3, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range. tSKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over the recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min| differential propagation delay. fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, differential (1.05V to 1.35V peak to peak). Output criteria: 60%/40% duty cycle, VOL (max 0.4V), VOH (min 2.7V), load = 15 pF (stray plus probes). Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: DS90LV018A 3 DS90LV018A SNLS014D – JUNE 1998 – REVISED APRIL 2013 www.ti.com PARAMETER MEASUREMENT INFORMATION Figure 2. Receiver Propagation Delay and Transition Time Test Circuit Figure 3. Receiver Propagation Delay and Transition Time Waveforms TYPICAL APPLICATION Balanced System Figure 4. Point-to-Point Application 4 Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: DS90LV018A DS90LV018A www.ti.com SNLS014D – JUNE 1998 – REVISED APRIL 2013 APPLICATION INFORMATION General application guidelines and hints for LVDS drivers and receivers may be found in the following application notes: LVDS Owner's Manual (lit #550062-001), AN-808 (SNLA028), AN-1035 (SNOA355), AN-977 (SNLA166), AN-971 (SNLA165), AN-916 (SNLA219), AN-805 (SNOA233), AN-903 (SNLA034). LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in Figure 4. This configuration provides a clean signaling environment for the fast edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically the characteristic impedance of the media is in the range of 100Ω. A termination resistor of 100Ω should be selected to match the media, and is located as close to the receiver input pins as possible. The termination resistor converts the driver output (current mode) into a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account. The DS90LV018A differential line receiver is capable of detecting signals as low as 100 mV, over a ±1V common-mode range centered around +1.2V. This is related to the driver offset voltage which is typically +1.2V. The driven signal is centered around this voltage and may shift ±1V around this center point. The ±1V shifting may be the result of a ground potential difference between the driver's ground reference and the receiver's ground reference, the common-mode effects of coupled noise, or a combination of the two. The AC parameters of both receiver input pins are optimized for a recommended operating input voltage range of 0V to +2.4V (measured from each pin to ground). The device will still operate for receivers input voltages up to VCC, but exceeding VCC will turn on the ESD protection circuitry which will clamp the bus voltages. POWER DECOUPLING RECOMMENDATIONS Bypass capacitors must be used on power pins. Use high frequency ceramic (surface mount is recommended) 0.1μF and 0.001μF capacitors in parallel at the power supply pin with the smallest value capacitor closest to the device supply pin. Additional scattered capacitors over the printed circuit board will improve decoupling. Multiple vias should be used to connect the decoupling capacitors to the power planes. A 10μF (35V) or greater solid tantalum capacitor should be connected at the power entry point on the printed circuit board between the supply and ground. PC BOARD CONSIDERATIONS Use at least 4 PCB board layers (top to bottom): LVDS signals, ground, power, TTL signals. Isolate TTL signals from LVDS signals, otherwise the TTL signals may couple onto the LVDS lines. It is best to put TTL and LVDS signals on different layers which are isolated by a power/ground plane(s). Keep drivers and receivers as close to the (LVDS port side) connectors as possible. DIFFERENTIAL TRACES Use controlled impedance traces which match the differential impedance of your transmission medium (ie. cable) and termination resistor. Run the differential pair trace lines as close together as possible as soon as they leave the IC (stubs should be < 10mm long). This will help eliminate reflections and ensure noise is coupled as commo-mode. In fact, we have seen that differential signals which are 1mm apart radiate far less noise than traces 3mm apart since magnetic field cancellation is much better with the closer traces. In addition, noise induced on the differential lines is much more likely to appear as common-mode which is rejected by the receiver. Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI will result! (Note that the velocity of propagation, v = c/E r where c (the speed of light) = 0.2997mm/ps or 0.0118 in/ps). Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match differential impedance and provide isolation for the differential lines. Minimize the number of vias and other discontinuities on the line. Avoid 90° turns (these cause impedance discontinuities). Use arcs or 45° bevels. Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: DS90LV018A 5 DS90LV018A SNLS014D – JUNE 1998 – REVISED APRIL 2013 www.ti.com Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid discontinuities in differential impedance. Minor violations at connection points are allowable. TERMINATION Use a termination resistor which best matches the differential impedance or your transmission line. The resistor should be between 90Ω and 130Ω. Remember that the current mode outputs need the termination resistor to generate the differential voltage. LVDS will not work without resistor termination. Typically, connecting a single resistor across the pair at the receiver end will suffice. Surface mount 1% - 2% resistors are the best. PCB stubs, component lead, and the distance from the termination to the receiver inputs should be minimized. The distance between the termination resistor and the receiver should be < 10mm (12mm MAX). FAIL-SAFE FEATURE The LVDS receiver is a high gain, high speed device that amplifies a small differential signal (20mV) to CMOS logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from appearing as a valid signal. The receiver's internal fail-safe circuitry is designed to source/sink a small amount of current, providing fail-safe protection (a stable known state of HIGH output voltage) for floating, terminated or shorted receiver inputs. 1. Open Input Pins. The DS90LV018A is a single receiver device. Do not tie the receiver inputs to ground or any other voltages. The input is biased by internal high value pull up and pull down resistors to set the output to a HIGH state. This internal circuitry will ensure a HIGH, stable output state for open inputs. 2. Terminated Input. If the driver is disconnected (cable unplugged), or if the driver is in a power-off condition, the receiver output will again be in a HIGH state, even with the end of cable 100Ω termination resistor across the input pins. The unplugged cable can become a floating antenna which can pick up noise. If the cable picks up more than 10mV of differential noise, the receiver may see the noise as a valid signal and switch. To insure that any noise is seen as common-mode and not differential, a balanced interconnect should be used. Twisted pair cable will offer better balance than flat ribbon cable. 3. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0V differential input voltage, the receiver output will remain in a HIGH state. Shorted input fail-safe is not supported across the common-mode range of the device (GND to 2.4V). It is only supported with inputs shorted and no external common-mode voltage applied. External lower value pull up and pull down resistors (for a stronger bias) may be used to boost fail-safe in the presence of higher noise levels. The pull up and pull down resistors should be in the 5kΩ to 15kΩ range to minimize loading and waveform distortion to the driver. The common-mode bias point should be set to approximately 1.2V (less than 1.75V) to be compatible with the internal circuitry. PROBING LVDS TRANSMISSION LINES Always use high impedance (> 100kΩ), low capacitance (< 2 pF) scope probes with a wide bandwidth (1 GHz) scope. Improper probing will give deceiving results. CABLES AND CONNECTORS, GENERAL COMMENTS When choosing cable and connectors for LVDS it is important to remember: Use controlled impedance media. The cables and connectors you use should have a matched differential impedance of about 100Ω. They should not introduce major impedance discontinuities. Balanced cables (e.g. twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax) for noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and also tend to pick up electromagnetic radiation a common-mode (not differential mode) noise which is rejected by the receiver. For cable distances < 0.5M, most cables can be made to work effectively. For distances 0.5M ≤ d ≤ 10M, CAT 3 (category 3) twisted pair cable works well, is readily available and relatively inexpensive. 6 Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: DS90LV018A DS90LV018A www.ti.com SNLS014D – JUNE 1998 – REVISED APRIL 2013 Pin Descriptions Pin No. Name 1 RIN- Inverting receiver input pin Description 2 RIN+ Non-inverting receiver input pin 7 ROUT Receiver output pin 8 VCC Power supply pin, +3.3V ± 0.3V 5 GND Ground pin 3, 4, 6 NC No connection Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: DS90LV018A 7 DS90LV018A SNLS014D – JUNE 1998 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics 8 Output High Voltage vs Power Supply Voltage Output Low Voltage vs Power Supply Voltage Output Short Circuit Current vs Power Supply Voltage Differential Transition Voltage vs Power Supply Voltage Power Supply Current vs Frequency Power Supply Current vs Ambient Temperature Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: DS90LV018A DS90LV018A www.ti.com SNLS014D – JUNE 1998 – REVISED APRIL 2013 Typical Performance Characteristics (continued) Differential Propagation Delay vs Power Supply Voltage Differential Propagation Delay vs Ambient Temperature Differential Skew vs Power Supply Voltage Differential Skew vs Ambient Temperature Differential Propagation Delay vs Differential Input Voltage Differential Propagation Delay vs Common-Mode Voltage Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: DS90LV018A 9 DS90LV018A SNLS014D – JUNE 1998 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) 10 Transition Time vs Power Supply Voltage Transition Time vs Ambient Temperature Differential Propagation Delay vs Load Transition Time vs Load Differential Propagation Delay vs Load Transition Time vs Load Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: DS90LV018A DS90LV018A www.ti.com SNLS014D – JUNE 1998 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision C (April 2013) to Revision D • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 10 Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: DS90LV018A 11 PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) DS90LV018ATM NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 90LV0 18ATM DS90LV018ATM/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 90LV0 18ATM DS90LV018ATMX NRND SOIC D 8 2500 TBD Call TI Call TI -40 to 85 90LV0 18ATM DS90LV018ATMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 90LV0 18ATM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DS90LV018ATMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 DS90LV018ATMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS90LV018ATMX SOIC D 8 2500 367.0 367.0 35.0 DS90LV018ATMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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