Dallas DS1742W-120 Y2kc nonvolatile timekeeping ram Datasheet

DS1742
Y2KC Nonvolatile Timekeeping RAM
www.dalsemi.com
PIN ASSIGNMENT
FEATURES
Integrated NV SRAM, real time clock,
crystal, power-fail control circuit and lithium
energy source
Clock registers are accessed identical to the
static RAM. These registers are resident in
the eight top RAM locations
Century byte register
Totally nonvolatile with over 10 years of
operation in the absence of power
BCD coded century, year, month, date, day,
hours, minutes, and seconds with automatic
leap year compensation valid up to the year
2100
Battery voltage level indicator flag
Power-fail write protection allows for ±10%
VCC power supply tolerance
Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time
Standard JEDEC bytewide 2k x 8 static RAM
pinout
Quartz accuracy ±1 minute a month @ 25°C,
factory calibrated
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
A8
A9
WE
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
PIN DESCRIPTION
A0-A10
CE
OE
WE
VCC
GND
DQ0-DQ7
- Address Inputs
- Chip Enable
- Output Enable
- Write Enable
- Power Supply Input
- Ground
- Data Input/Outputs
ORDERING INFORMATION
DS1742-XXX
DS1742W-XXX
(5V)
-70
-100
70 ns access
100 ns access
(3.3V)
-120 120 ns access
-150 150 ns access
DESCRIPTION
The DS1742 is a full function, year 2000-compliant (Y2KC), real-time clock/calendar (RTC) and 2k x 8
non-volatile static RAM. User access to all registers within the DS1742 is accomplished with a bytewide
interface as shown in Figure 1. The Real Time Clock (RTC) information and control bits reside in the
eight uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours,
minutes, and seconds data in 24-hour BCD format. Corrections for the day of the month and leap year
are made automatically.
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091800
DS1742
The RTC clock registers are double-buffered to avoid access of incorrect data that can occur during clock
update cycles. The double buffered system also prevents time loss as the timekeeping countdown
continues unabated by access to time register data. The DS1742 also contains its own power-fail
circuitry, which deselects the device when the VCC supply is in an out of tolerance condition. This feature
prevents loss of data from unpredictable system operation brought on by low VCC as errant access and
update cycles are avoided.
CLOCK OPERATIONS-READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1742 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a 1 is written into the read bit, bit 6 of the century register, see Table 2. As long
as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the count,
that is day, date, and time that was current at the moment the halt command was issued. However, the
internal clock registers of the double-buffered system continue to update so that the clock accuracy is not
affected by the access of data. All of the DS1742 registers are updated simultaneously after the internal
clock register updating process has been re-enabled. Updating is within a second after the read bit is
written to 0. The READ bit must be a zero for a minimum of 500 µs to ensure the external registers will
be updated.
DS1742 BLOCK DIAGRAM Figure 1
DS1742 TRUTH TABLE Table 1
VCC
VCC>VPF
VSO<VCC<VPF
VCC<VSO<VPF
CE
OE
WE
VIH
VIL
VIL
VIL
X
X
X
X
VIL
VIH
X
X
X
VIL
VIH
VIH
X
X
MODE
DESELECT
WRITE
READ
READ
DESELECT
DESELECT
DQ
HIGH-Z
DATA IN
DATA OUT
HIGH-Z
HIGH-Z
HIGH-Z
POWER
STANDBY
ACTIVE
ACTIVE
ACTIVE
CMOS STANDBY
DATA RETENTION MODE
SETTING THE CLOCK
As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a 1, like the read
bit, halts updates to the DS1742 registers. The user can then load them with the correct day, date and
time data in 24-hour BCD format. Resetting the write bit to a 0 then transfers those values to the actual
clock counters and allows normal operation to resume.
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DS1742
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned
off to minimize current drain from the battery. The OSC bit is the MSB (bit 7) of the seconds registers,
see Table 2. Setting it to a 1 stops the oscillator.
FREQUENCY TEST BIT
As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to
logic 1 and the oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the
seconds register is being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for
access remain valid (i.e., CE low, OE low, WE high, and address for seconds register remain valid and
stable).
CLOCK ACCURACY
The DS1742 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C. The RTC is
calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements. The DS1742 does
not require additional calibration. For this reason, methods of field clock calibration are not available and
not necessary. Clock accuracy is also effected by the electrical environment and caution should be taken
to place the RTC in the lowest level EMI section of the PCB layout. For additional information please
see application note 58.
DS1742 REGISTER MAP Table 2
ADDRESS
DATA
B7
B6
7FF
B5
B4
B3
B2
10 Year
FUNCTION/RANGE
YEAR
YEAR
00-99
MONTH
MONTH
01-12
DATE
DATE
01-31
DAY
01-07
HOUR
00-23
X
X
7FD
X
X
7FC
BF
FT
7FB
X
X
7FA
X
10 MINUTES
MINUTES
MINUTES
00-59
OSC
W
10 SECONDS
SECONDS
SECONDS
00-59
CENTURY
CONTROL
00-39
7F8
OSC = STOP BIT
W = WRITE BIT
R
10 Mo
B0
7FE
7F9
X
B1
10 Date
X
X
X
DAY
10 HOUR
10 CENTURY
HOUR
R = READ BIT
X = SEE NOTE BELOW
FT = FREQUENCY TEST
BF = BATTERY FLAG
NOTE:
All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1742 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE
(chip enable) is low. The device architecture allows ripplethrough access to any of the address locations
in the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address input is
stable, providing that the CE , and OE access times and states are satisfied. If CE , or OE access times
and states are not met, valid data will be available at the latter of chip enable access (tCEA) or at output
enable access time (tOEA). The state of the data input/output pins (DQ) is controlled by CE , and OE . If
the outputs are activated before tAA, the data lines are driven to an intermediate state until tAA. If the
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DS1742
address inputs are changed while CE , and OE remain valid, output data will remain valid for output data
hold time (tOH) but will then go indeterminate until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1742 is in the write mode whenever WE , and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE , on CE . The addresses must be held valid throughout
the cycle. CE , or WE must return inactive for a minimum of tWR prior to the initiation of another read or
write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a
typical application, the OE signal will be high during a write cycle. However, OE can be active provided
that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low
the data bus can become active with read data defined by the address inputs. A low transition on WE will
then disable the outputs tWEZ after WE goes active.
DATA RETENTION MODE
The 5-volt device is fully accessible and data can be written or read only when VCC is greater than VPF.
However, when VCC is below the power fail point, VPF, (point at which write protection occurs) the
internal clock registers and SRAM are blocked from any access. At this time the power fail reset output
signal ( RST ) is driven active and will remain active until VCC returns to nominal levels. When VCC falls
below the battery switch point VSO (battery supply level), device power is switched from the VCC pin to
the backup battery. RTC operation and SRAM data are maintained from the battery until VCC is returned
to nominal levels. The 3.3 volt device is fully accessible and data can be written or read only when VCC is
greater than VPF. When VCC falls below the power fail point, VPF, access to the device is inhibited. At this
time the power fail reset output signal ( RST ) is driven active and will remain active until VCC returns to
nominal levels. If VPF is less than Vso, the device power is switched from VCC to the backup supply (VBAT)
when VCC drops below VPF. If VPF is greater than Vso, the device power is switched from VCC to the
backup supply (VBAT) when VCC drops below Vso. RTC operation and SRAM data are maintained from
the battery until VCC is returned to nominal levels. The RST signal is an open drain output and requires a
pull up. Except for the RST , all control, data, and address signals must be powered down when VCC is
powered down.
BATTERY LONGEVITY
The DS1742 has a lithium power source that is designed to provide energy for clock activity, and clock
and RAM data retention when the VCC supply is not present. The capability of this internal power supply
is sufficient to power the DS1742 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at 25°C with the internal clock oscillator running in
the absence of VCC power. Each DS1742 is shipped from Dallas Semiconductor with its lithium energy
source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than
VPF, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the
DS1742 will be much longer than 10 years since no lithium battery energy is consumed when VCC is
present.
BATTERY MONITOR
The DS1742 constantly monitors the battery voltage of the internal battery. The Battery Flag bit (bit 7) of
the day register is used to indicate the voltage level range of the battery. This bit is not writable and
should always be a 1 when read. If a 0 is ever present, an exhausted lithium energy source is indicated
and both the contents of the RTC and RAM are questionable.
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DS1742
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
-0.3V to +6.0V
0°C to 70°C
-20°C to +70°C
See J-STD-020A Specification (See Note 7)
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
OPERATING RANGE
Range
Commercial
Temperature
0°C to +70°C
VCC
3.3V ± 10% or 5V ± 10%
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
Logic 1 Voltage All Inputs
VCC = 5V ±10%
VCC = 3.3V ±10%
Logic 0 Voltage All Inputs
VCC = 5V ±10%
VCC = 3.3V ±10%
SYMBOL
MIN
VIH
VIH
VIL
VIL
TYP
(Over the Operating Range)
MAX
UNITS
NOTES
2.2
2.0
VCC +0.3V
VCC +0.3V
V
V
1
1
-0.3
-0.3
0.8
0.6
V
V
1
1
DC ELECTRICAL CHARACTERISTICS
(Over the Operating Range; VCC = 5.0V ± 10%)
PARAMETER
Active Supply Current
TTL Standby Current ( CE =VIH )
CMOS Standby Current
( CE ≥=VCC - 0.2V)
Input Leakage Current
(any input)
Output Leakage Current
(any output)
Output Logic 1 Voltage
(IOUT = -1.0 mA)
Output Logic 0 Voltage
(IOUT = +2.1 mA)
Write Protection Voltage
Battery Switch-over Voltage
SYMBOL
MIN
ICC
ICC1
ICC2
TYP
MAX
UNITS
NOTES
15
1
1
50
3
3
mA
mA
mA
2, 3
2, 3
2, 3
IIL
-1
+1
µA
IOL
-1
+1
µA
VOH
2.4
VOL
VPF
1
0.4
4.50
4.25
VSO
VBAT
5 of 12
V
1
1
1, 4
DS1742
DC ELECTRICAL CHARACTERISTICS
(Over the Operating Range; VCC = 3.3V ± 10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Active Supply Current
ICC
10
30
mA
2, 3
TTL Standby Current ( CE = VIH )
CMOS Standby Current
( CE ≥=VCC - 0.2V)
Input Leakage Current (any input)
Output Leakage Current
(any output)
Output Logic 1 Voltage
(IOUT = -1.0 mA)
Output Logic 0 Voltage
(IOUT =2.1 mA)
Write Protection Voltage
Battery Switch-over Voltage
ICC1
ICC2
0.7
0.7
2
2
mA
mA
2, 3
2, 3
+1
+1
µA
µA
IIL
IOL
-1
-1
VOH
2.4
VOL
VPF
VSO
1
0.4
2.97
2.80
VBAT
or VPF
V
V
1
1
1, 4
READ CYCLE, AC CHARACTERISTICS
(Over the Operating Range; VCC = 5.0V ± 10%)
PARAMETER
Read Cycle Time
Address Access Time
to DQ Low-Z
CE Access Time
CE Data Off time
OE to DQ Low-Z
OE Access Time
OE Data Off Time
Output Hold from Address
CE
SYMBOL
tRC
tAA
tCEL
tCEA
tCEZ
tOEL
tOEA
tOEZ
tOH
70 ns access
MIN MAX
70
70
5
70
25
5
35
25
5
6 of 12
100 ns access
MIN MAX
100
100
5
100
35
5
55
35
5
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
DS1742
READ CYCLE, AC CHARACTERISTICS
(Over the Operating Range; VCC = 3.3V ± 10%)
PARAMETER
Read Cycle Time
Address Access Time
to DQ Low-Z
CE Access Time
CE Data Off time
OE to DQ Low-Z
OE Access Time
OE Data Off Time
Output Hold from Address
CE
SYMBOL
tRC
tAA
tCEL
tCEA
tCEZ
tOEL
tOEA
tOEZ
tOH
120 ns access
MIN MAX
120
120
5
120
40
5
100
35
5
READ CYCLE TIMING DIAGRAM
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150 ns access
MIN MAX
150
150
5
150
50
5
130
35
5
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
5
5
5
5
5
5
5
5
5
DS1742
WRITE CYCLE, AC CHARACTERISTICS
(Over the Operating Range; VCC = 5.0V ± 10%)
PARAMETER
Write Cycle Time
Address Access Time
Pulse Width
CE Pulse Width
Data Setup Time
Data Hold time
Address Hold Time
WE
Data Off Time
Write Recovery Time
WE
SYMBOL
tWC
tAS
tWEW
tCEW
tDS
tDH
tAH
tWEZ
tWR
70 ns access
MIN MAX
70
0
50
60
30
0
5
25
5
100 ns access
MIN MAX
100
0
70
75
40
0
5
35
5
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
WRITE CYCLE, AC CHARACTERISTICS
(Over the Operating Range; VCC = 3.3V ± 10%)
PARAMETER
Write Cycle Time
Address Setup Time
Pulse Width
CE Pulse Width
Data Setup Time
Data Hold Time
Address Hold Time
WE
Data Off Time
Write Recovery Time
WE
SYMBOL
tWC
tAS
tWEW
tCEW
tDS
tDH
tAH
tWEZ
tWR
120 ns access
MIN MAX
120
0
100
110
80
0
0
40
10
8 of 12
150 ns access
MIN MAX
150
0
130
140
90
0
0
50
10
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
DS1742
WRITE CYCLE TIMING DIAGRAM, WRITE ENABLE CONTROLLED
WRITE CYCLE TIMING DIAGRAM, CE CONTROLLED
POWER-UP/DOWN CHARACTERISTICS
(Over the Operating Range; VCC = 5.0V ± 10%)
PARAMETER
CE or WE at VIH , Before
Power-Down
VCC Fall Time: VPF(MAX) to
VPF(MIN)
VCC Fall Time: VPF(MIN) to VSO
VCC Rise Time: VPF(MIN) to
VPF(MAX)
Power-up Recover Time
Expected Data Retention Time
(Oscillator On)
SYMBOL
MIN
tPD
0
s
tF
300
s
tFB
10
s
tR
0
s
tREC
tDR
TYP
MAX
35
10
9 of 12
UNITS
NOTES
ms
years
5, 6
DS1742
POWER-UP/DOWN WAVEFORM TIMING 5-VOLT DEVICE
POWER-UP/DOWN CHARACTERISTIC
(Over the Operating Range; VCC = 3.3V ± 10%)
PARAMETER
CE or WE at VIH , Before
Power-Down
VCC Fall Time: VPF(MAX) to
VPF(MIN)
VCC Rise Time: VPF(MIN) to
VPF(MAX)
Power-up Recovery Time
Expected Data Retention Time
(Oscillator On)
SYMBOL
MIN
TYP
tPD
0
µs
tF
300
µs
tR
0
µs
tREC
tDR
MAX
35
10
UNITS
NOTES
ms
years
5, 6
POWER-UP/DOWN WAVEFORM TIMING 3.3-VOLT DEVICE
CAPACITANCE
PARAMETER
Capacitance on all input pins
Capacitance on all output pins
(TA = 25°C)
SYMBOL
CIN
CO
MIN
10 of 12
TYP
MAX
7
10
UNITS
pF
pF
NOTES
DS1742
AC TEST CONDITIONS
Output Load:
100 pF + 1TTL Gate
Input Pulse Levels:
0.0 to 3.0 Volts
Timing Measurement Reference Levels:
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5 ns
NOTES:
1. Voltage referenced to ground.
2. Typical values are at 25°C and nominal supplies.
3. Outputs are open.
4. Battery switch-over occurs at the lower of either the battery voltage or VPF.
5. Data retention time is at 25°C.
6. Each DS1742 has a built-in switch that disconnects the lithium source until VCC is first applied by the
user. The expected tDR is defined as a cumulative time in the absence of VCC starting from the time
power is first applied by the user.
7. Real Time Clock Modules can be successfully processed through conventional wave-soldering
techniques as long as temperature exposure to the lithium energy source contained within does not
exceed +85°C.
Post-solder cleaning with water washing techniques is acceptable, provided that
ultrasonic vibration is not used to prevent damage to the crystal.
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DS1742
DS1742 24-PIN PACKAGE
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