Data Sheet A m p l i fy t h e H u m a n E x p e r i e n c e CDK3402/CDK3403 General Description features n 8-bit resolution n 150 megapixels per second n ±0.2% linearity error n Sync and blank controls n 1.0Vpp video into 37.5Ω or 75Ω load n Internal bandgap voltage reference n Double-buffered data for low distortion n TTL-compatible inputs n Low glitch energy n Single +5V power supply CDK3402/3401 products are low-cost triple D/A converters that are tailored to fit graphics and video applications where speed is critical. Two speed grades are available: CDK3402 at 100MSPS and CDK3403 at 150MSPS. Few external components are required, just the current reference resistor, current output load resistors, and decoupling capacitors. Applications n Package is a 48-lead TQFP. Fabrication technology is CMOS. Performance is guaranteed from 0 to 70°C. Video signal conversion – RGB – YCBCR – Composite, Y, C n Multimedia systems n Image processing n True-color graphics systems TTL-level inputs are converted to analog current outputs that can drive 25-37.5Ω loads corresponding to doubly-terminated 50-75Ω loads. A sync current following SYNC input timing is added to the IOG output. BLANK will override RGB inputs, setting IOG, IOB and IOR currents to zero when BLANK = L. Although appropriate for many applications, the internal 1.235V reference voltage can be overridden by the VREF input. Block Diagram SYNC SYNC BLANK G7-0 R7-0 8-bit D/A Converter IO G 8 8-bit D/A Converter IO B 8 8-bit D/A Converter IO R CLOCK Rev 1B B7-0 8 COMP R REF V REF +1.235V Ref Ordering Information Part Number Package Pb-Free RoHS Compliant Operating Temp Range Packaging Method Package Quantity CDK3402CTQ48 TQFP-48 Yes Yes 0°C to +70°C Tray 250 CDK3402CTQ48Y TQFP-48 Yes Yes 0°C to +70°C Tray 1,250 CDK3403CTQ48 TQFP-48 Yes Yes 0°C to +70°C Tray 250 CDK3403CTQ48Y TQFP-48 Yes Yes 0°C to +70°C Tray 1,250 Moisture sensitivity level for all parts is MSL-3. ©2008 CADEKA Microcircuits LLC CDK3402/CDK3403 8-bit, 100/150MSPS, Triple Video DACs 8-bit, 100/150MSPS, Triple Video DACs www.cadeka.com Data Sheet Pin Configuration GND R7 R6 R5 R4 R3 R2 R1 R0 GND GND NC TQFP-48 48 47 46 45 44 43 42 41 40 39 38 37 CDK3402/CDK3403 8-bit, 100/150MSPS, Triple Video DACs 1 2 3 4 5 6 7 8 9 10 11 12 TQFP CDK3402/3403 36 35 34 33 32 31 30 29 28 27 26 25 RREF VREF COMP IOR IOG VDD VDD IOB GND GND CLOCK NC NC GND GND B0 B1 B2 B3 B4 B5 B6 B7 NC 13 14 15 16 17 18 19 20 21 22 23 24 GND G0 G1 G2 G3 G4 G5 G6 G7 BLANK SYNC VDD Pin Assignments Pin No. Pin Name Description Clock and Pixel I/O 26 CLK Clock Input 47-40 R7-0 Red Pixel Data Inputs 9–2 G7-0 Green Pixel Data Inputs 23–16 B7-0 Blue Pixel Data Inputs 11 SYNC Sync Pulse Input 10 BLANK Blanking Input Controls Rev 1B Video Outputs 33 IOR Red Current Output 32 IOG Green Current Output 29 IOB Blue Current Output Voltage Reference 35 VREF Voltage Reference Output/Input 36 RREF Current-Setting Resistor 34 COMP Compensation Capacitor Power and Ground 12, 30, 31 VDD Power Supply 1, 14, 15, 27, 28, 38, 39, 48 GND Ground 13, 24, 25, 37 NC ©2008 CADEKA Microcircuits LLC No Connect www.cadeka.com 2 Data Sheet Absolute Maximum Ratings The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots. Power Supply Voltage VDD (Measured to GND) Inputs Applied Voltage (measured to GND)(2) Forced Current(3,4) Outputs Applied Voltage (measured to GND)(2) Forced Current(3,4) Short Circuit Duration (single output in HIGH state to GND) Temperature Operating, Ambient Junction Lead Soldering (10 seconds) Vapor Phase Soldering (1 minute) Storage Min Max Unit -0.5 7.0 V -0.5 -10.0 VDD + 0.5 10.0 V mA -0.5 -60.0 VDD + 0.5 60.0 unlimited V mA sec -20 110 150 300 220 150 °C °C °C °C °C -65 CDK3402/CDK3403 8-bit, 100/150MSPS, Triple Video DACs Parameter Notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device. Recommended Operating Conditions Parameter Min Typ Max Unit VDD Power Supply Voltage 4.75 5.0 fS Conversion Rate 5.25 100 150 tPWH CLK Pulsewidth, HIGH tPWL CLK Pulsewidth, LOW tW CLK Pulsewidth tS Input Data Setup Time Input Date Hold Time Reference Voltage, External Compensation Capacitor Output Load Input Voltage, Logic HIGH Input Voltage, Logic LOW Ambient Temperature, Still Air 1.235 0.1 37.5 1.5 V MSPS MSPS ns ns ns ns ns ns ns ns V µF Ω V V °C th VREF CC RL VIH VIL TA ©2008 CADEKA Microcircuits LLC CDK3402 CDK3403 CDK3402 CDK3403 CDK3402 CDK3403 CDK3402 CDK3403 3.1 2.5 3.1 2.5 10 6.6 1.7 0 1.0 2.0 GND 0 VDD 0.8 70 www.cadeka.com Rev 1B Symbol 3 Data Sheet Electrical Characteristics (TA = 25°C, VDD = +5V, VREF = 1.235V, RL = 37.5Ω, RREF = 540Ω; unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units Power Supply Current PD Total Power Dissipation(1) VDD = 5.25V, TA = 0°C 125 mA VDD = 5.25V, TA = 0°C 655 mW RO Output Resistance CO Output Capacitance IOUT = 0mA 30 pF IIH Input Current, HIGH VDD = 5.25V, VIN = 2.4V -5 µA IIL Input Current, LOW VDD = 5.25V, VIN = 0.4V 5 µA IREF VREF Input Bias Current ±100 µA VREF Reference Voltage Output VOC Output Compliance CDI Digital Input Capacitance 100 0 kΩ 1.235 Referred to VDD -0.4 V 0 +1.5 V 4 10 pF Typ Max Units 10 15 ns 1 2 ns Notes: 1. 100% tested at 25°C. 2. Parameter is guaranteed (but not tested) by design and characterization data. Switching Characteristics (TA = 25°C, VDD = +5V, VREF = 1.235V, RL = 37.5Ω, RREF = 590Ω; unless otherwise noted) Symbol Parameter Conditions Min tD Clock to Output Delay tSKEW Output Skew VDD = 4.75V, TA = 0°C tR Output Risetime 10% to 90% of Full Scale 3 ns tF Output Falltime 90% to 10% of Full Scale 3 ns Typ Max Units Notes: 1. 100% production tested at +25°C. 2. Parameter is guaranteed (but not tested) by design and characterization data. System Performance Characteristics (TA = 25°C, VDD = +5V, VREF = 1.235V, RL = 37.5Ω, RREF = 590Ω; unless otherwise noted) Symbol Parameter Conditions Min Integral Linearity Error ±0.2 ±0.3 %/FS DNL Differential Linearity Error ±0.2 ±0.3 %/FS EDM DAC to DAC Matching PSRR Power Supply Rejection Ratio 5 10 % 0.05 %/% Notes: 1. 100% production tested at +25°C. 2. Parameter is guaranteed (but not tested) by design and characterization data. ©2008 CADEKA Microcircuits LLC www.cadeka.com 4 Rev 1B INL CDK3402/CDK3403 8-bit, 100/150MSPS, Triple Video DACs IDD (1) Data Sheet Table 1. Output Voltage vs. Input Code, SYNC and BLANK, VREF = 1.235V, RREF = 590Ω, RL = 37.5Ω RGB7-0 (MSB…LSB) BLUE AND RED GREEN BLANK VOUT SYNC BLANK VOUT 1111 1111 X 1 0.7140 1 1 1.0000 1111 1111 X 1 0.7140 0 1 0.7140 1111 1110 X 1 0.7134 1 1 0.9994 1111 1101 X 1 0.7127 1 1 0.9987 • • • • • • • • • • • • • • 0000 0000 X 1 0.3843 1 1 0.6703 1111 1111 X 1 0.3837 1 1 0.6697 • • • • • • • • • • • • • • 0000 0010 X 1 0.0553 1 1 0.3413 0000 0001 X 1 0.0546 1 1 0.3406 0000 0000 X 1 0.0540 1 1 0.3400 0000 0000 X 1 0.0540 0 1 0.054 XXXX XXXX X 0 0.0000 1 0 0.2860 XXXX XXXX X 0 0.0000 0 0 0.0000 XXXX XXXX X 1 valid 0 1 valid tPWL tPWH ts tH CDK3402/CDK3403 8-bit, 100/150MSPS, Triple Video DACs SYNC 1/fs CLK Data N Data N+1 Data N+2 Rev 1B Pixel Data and Controls 3%/FS tD OUTPUT 90% tSET tF 50% tR 10% Figure 1. CDK3402/3403 Timing Diagram ©2008 CADEKA Microcircuits LLC www.cadeka.com 5 Data Sheet Functional Description Digital Inputs All digital inputs are TTL-compatible. Data is registered on the rising edge of the CLK signal. Following one stage of pipeline delay, the analog output changes tDO after the rising edge of CLK. Clock Input - CLK The clock input is TTL-compatible and all pixel data is registered on the rising edge of CLK. It is recommended that CLK be driven by a dedicated TTL buffer to avoid reflection induced jitter, overshoot, and undershoot. Pixel Data Inputs - R7-0, B7-0, G7-0 TTL-compatible Red, Green and Blue Data Inputs are registered on the rising edge of CLK. SYNC and BLANK Data: 660mV max. Pedestal: 54mV Sync: 286mV Figure 2. Normal Output Levels BLANK gates the D/A inputs and sets the pedestal voltage. If BLANK = HIGH, the D/A inputs are added to a pedestal ©2008 CADEKA Microcircuits LLC Bringing SYNC LOW, turns off a 40 IRE (7.62mA) current source which forms a sync pulse on the Green D/A converter output. SYNC is registered on the rising edge of CLK with the same pipeline latency as BLANK and pixel data. SYNC does not override any other data and should be used only during the blanking interval. Since this is a single-supply D/A and all signals are positive-going, sync is added to the bottom of the Green D/A range. So turning SYNC OFF means turning the current source ON. When a sync pulse is desired, the current source is turned OFF. If the system does not require sync pulses from the Green D/A converter, SYNC should connected to GND. Blanking Input - BLANK When BLANK is LOW, pixel inputs are ignored and the D/A converter outputs fall to the blanking level. BLANK is registered on the rising edge of CLK and has the same pipeline latency as SYNC. D/A Outputs Each D/A output is a current source. To obtain a voltage output, a resistor must be connected to ground. Output voltage depends upon this external resistor, the reference voltage, and the value of the gain-setting resistor connected between RREF and GND. Normally, a source termination resistor of 75Ω is connected between the D/A current output pin and GND near the D/A converter. A 75Ω line may then be connected with another 75Ω termination resistor at the far end of the cable. This “double termination” presents the D/A converter with a net resistive load of 37.5Ω. The CDK3402/3403 may also be operated with a single 75Ω terminating resistor. To lower the output voltage swing to the desired range, the nominal value of the resistor on RREF should be doubled. R, G, and B Current Outputs - IOR, IOG, IOB The R, G, and B current source outputs of the D/A converters are capable of driving RS-343A/SMPTE-170M compatible levels into doubly-terminated 75Ω lines. Sync pulses may be added to the Green D/A output. www.cadeka.com 6 Rev 1B SYNC and BLANK inputs control the output level (Figure 2 and Table 1, on the previous page) of the D/A converters during CRT retrace intervals. BLANK forces the D/A outputs to the blanking level while SYNC = L turns off a current source that is connected to the green D/A converter. SYNC = H adds a 40 IRE sync pulse to the green output, SYNC = L sets the green output to 0.0V during the sync tip. SYNC and BLANK are registered on the rising edge of CLK. Sync Pulse Input - SYNC CDK3402/CDK3403 8-bit, 100/150MSPS, Triple Video DACs Within the CDK3402/3403 are three identical 8-bit D/A converters, each with a current source output. External loads are required to convert the current to voltage outputs. Data inputs RGB7-0 are overridden by the BLANK input. SYNC = H activates, sync current from IOS for syncon-green video signals. which offsets the current output. If BLANK = Low, data inputs and the pedestal are disabled. Data Sheet Current-Setting Resistor - RREF A 0.1µF capacitor must be connected between the COMP Full-scale output current of each D/A converter is determined by the value of the resistor connected between RREF and GND. Nominal value of RREF is found from: pin and VDD to stabilize internal bias circuitry and ensure low-noise operation. RREF = 9.1 (VREF/IFS) An internal voltage source of +1.235V is output on the where IFS is the full-scale (white) output current (in amps) from the D/A converter (without sync). Sync is 0.4 * IFS. VREF pin. An external +1.235V reference may be applied here which overrides the internal reference. Decoupling VREF to GND with a 0.1µF ceramic capacitor is required. IFS = VFS/RL Where VFS is the white voltage level and RL is the total resistive load (Ω) on each D/A converter. VFS is the blank to full-scale voltage. Voltage Reference All three D/A converters are supplied with a common voltage reference. Internal bandgap voltage reference voltage is +1.235V with a 3kΩ source resistance. An external voltage reference may be connected to the VREF pin, overriding the internal voltage reference. Power and Ground Required power is a single +5.0V supply. To minimize power supply induced noise, analog +5V should be connected to VDD pins with 0.1µF and 0.01µF decoupling capacitors placed adjacent to each VDD pin or pin pair. The high slew-rate of digital data makes capacitive coupling to the outputs of any D/A converter a potential problem. Since the digital signals contain high-frequency components of the CLK signal, as well as the video output signal, the resulting data feedthrough often looks like harmonic distortion or reduced signal-to-noise performance. All ground pins should be connected to a common solid ground plane for best performance. CDK3402/CDK3403 8-bit, 100/150MSPS, Triple Video DACs D/A full-scale (white) current may also be calculated from: Voltage Reference Output/Input - VREF Rev 1B ©2008 CADEKA Microcircuits LLC www.cadeka.com 7 Data Sheet Equivalent Circuits V DD V DD CDK3402/CDK3403 8-bit, 100/150MSPS, Triple Video DACs p n p Digital Input V DD n OUT GND GND Figure 3. Equivalent Digital Input Circuit Figure 4. Equivalent Analog Output Circuit V DD p p R REF V REF GND Rev 1B Figure 5. Equivalent Analog Input Circuit ©2008 CADEKA Microcircuits LLC www.cadeka.com 8 Data Sheet Typical Application Diagrams 1 IOR IN1 OUT1 8 75Ω 220µF 7 75Ω 220µF 6 75Ω 220µF 75Ω Video Cables 2 IOG OUT2 IN2 3 IOB 75Ω IN3 G 75Ω CLC3800 75Ω OUT3 B 75Ω +3V or +5V 4 1.0µF CDK3402/CDK3403 8-bit, 100/150MSPS, Triple Video DACs 75Ω 75Ω CDK3402/ CDK3403 R GND +Vs 5 0.1µF AC-Coupling Caps are Optional DVD Player or STB Figure 6. Standard Definition Video Output Circuit Diagram +Vs IOR CDK3402/ CDK3403 + 75Ω 75Ω 1/3 CLC3605 - 75Ω Video Cables 330Ω IOG 75Ω 330Ω IOB -Vs Figure 7. Graphics Output Driver Circuit Diagram Rev 1B +Vs IOR CDK3402/ CDK3403 + 75Ω 75Ω 1/3 CLC3605 - 330Ω IOG 75Ω 330Ω IOB -Vs 75Ω 75Ω Video Cables 75Ω Video Cables 75Ω Video Cables 75Ω 75Ω 75Ω Figure 8. Standard Definition Video Distribution Circuit Diagram ©2008 CADEKA Microcircuits LLC www.cadeka.com 9 Data Sheet Applications Dicussion Grounding It is important that the CDK3402/3403 power supply is well+5V 10µF 0.1µF VDD RED PIXEL INPUT R7-0 GREEN PIXEL INPUT G7-0 BLUE PIXEL INPUT B7-0 CLOCK SYNC BLANK GND Red IOR IOG IOB CDK3402/3403 Zo = 75Ω Zo = 75Ω Blue 75Ω Zo = 75Ω 75Ω 75Ω 75Ω Triple 8-bit D/A Converter +5V COMP CLK SYNC BLANK Green w/Sync 75Ω 75Ω 0.1µF 3.3kΩ (not required without external reference) V REF R REF LM185-1.2 590Ω 0.1µF (Optional) Figure 9. Typical Interface Circuit Diagram Printed Circuit Board Layout 1. Keep the critical analog traces (VREF, IREF, COMP, IOS, IOR, IOG) as short as possible and as far as possible from all digital signals. The CDK3402/3403 should be located near the board edge, close to the analog out-put connectors. 2. Power plane for the CDK3402/3403 should be separate from that which supplies the digital circuitry. A single power plane should be used for all of the VDD pins. If the power supply for the CDK3402/3403 is the same as that of the system’s digital circuitry, power to the CDK3402/3403 should be decoupled with 0.1µF and 0.01µF capacitors and iso-lated with a ferrite bead. ©2008 CADEKA Microcircuits LLC 4. If the digital power supply has a dedicated power plane layer, it should not be placed under the CDK3402/3403, the voltage reference, or the analog outputs. Capacitive coupling of digital power supply noise from this layer to the CDK3402/3403 and its related analog circuitry can have an adverse effect on performance. 5. CLK should be handled carefully. Jitter and noise on this clock will degrade performance. Terminate the clock line carefully to eliminate overshoot and ringing. Evaluation boards are available (CEB3402 and CEB3403), contact CADEKA for more information. Related Products n n CDK3400/3401 Triple 10-bit 100/150MSPS DACs CDK3404 Triple 8-bit 180MSPS DAC www.cadeka.com 10 Rev 1B Designing with high-performance mixed-signal circuits demands printed circuits with ground planes. Overall system performance is strongly influenced by the board layout. Capacitive coupling from digital to analog circuits may result in poor D/A conversion. Consider the following suggestions when doing the layout: 3. The ground plane should be solid, not cross-hatched. Connections to the ground plane should have very short leads. CDK3402/CDK3403 8-bit, 100/150MSPS, Triple Video DACs Figure 9 below illustrates a typical CDK3402/3403 interface circuit. In this example, an optional 1.2V bandgap reference is connected to the VREF output, overriding the internal voltage reference source. regulated and free of high-frequency noise. Careful power supply decoupling will ensure the highest quality video signals at the output of the circuit. The CDK3402/3403 has separate analog and digital circuits. To keep digital system noise from the D/A converter, it is recommended that power supply voltages (VDD) come from the system analog power source and all ground connections (GND) be made to the analog ground plane. Power supply pins should be individually decoupled at the pin. Data Sheet Mechanical Dimensions TQFP-48 Package CDK3402/CDK3403 8-bit, 100/150MSPS, Triple Video DACs Rev 1B For additional information regarding our products, please visit CADEKA at: cadeka.com CADEKA Headquarters Loveland, Colorado T: 970.663.5452 T: 877.663.5452 (toll free) CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies. CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright ©2008 by CADEKA Microcircuits LLC. All rights reserved. A m p l i fy t h e H u m a n E x p e r i e n c e