CYPD1120 USB Power Delivery Alternate Mode Controller on Type-C General Description The CYPD1120 device belongs to Cypress’s CCG1 product family, which provides a complete USB Type-C and USB Power Delivery port control solution. The scalable and reconfigurable core architecture of CCG1 enables a base Type-C solution that can scale to a complete 100-W USB Power Delivery with Alternate Mode mux support. CCG1 is also a Type-C cable ID IC for active and passive cables. The ARM® Cortex®-M0 CPU based core can use common open source firmware or custom solutions developed with common libraries and APIs. CCG1 is the CC controller that detects connector insert, plug orientation, and VCONN switching signals. CCG1 makes it easier to add USB Power Delivery to any architecture because it provides the control signals to manage external VBUS and VCONN power management solutions as well as external mux controls for most single cable-docking solutions. CCG1's packaging options, and programmability, enables any USB Type-C and USB Power Delivery solution. Applications Integrated Digital Blocks ■ Dongles, docking stations ■ ■ Type-C to DisplayPort ■ ■ Type-C to HDMI ■ Type-C to DVI ■ Type-C to VGA Type-C Support ■ ■ Supports VESA DisplayPort Alternate Mode on USB Type-C Standard Version 1.0 Low-power Operation 32-bit MCU Subsystem 48-MHz ARM Cortex-M0 CPU with 32-KB flash and 4-KB SRAM Integrated Analog Blocks ■ Integrated transceiver (BB PHY) PD Support Features ■ Two configurable 16-bit TCPWM blocks One I2C master or slave 12-bit, 1-Msps ADC for VBUS voltage and current monitoring ■ ■ 1.8-V to 5.5-V operation Sleep 1.3 mA, Deep Sleep 1.3 uA[2] Packages ■ ■ 40-pin QFN 35-ball wafer-level CSP (WLCSP) Figure 1. CCG1 Block Diagram[2, 3, 4, 5] Notes 1. Values measured for CCG1 silicon only. Application specific power numbers may be higher. 2. Timer, counter, pulse-width modulation block. 3. Serial communication block configurable as I2C. 4. Base band. 5. Termination resistor denoting an Alternate Mode Adaptor. Cypress Semiconductor Corporation Document Number: 001-96786 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 21, 2017 CYPD1120 Contents Functional Definition ........................................................ 3 CPU and Memory Subsystem ..................................... 3 System Resources ...................................................... 3 GPIO ........................................................................... 3 Pin Definitions .................................................................. 4 Pinouts .............................................................................. 6 Power ................................................................................. 7 Electrical Specifications .................................................. 9 Absolute Maximum Ratings ........................................ 9 Device Level Specifications ......................................... 9 Digital Peripherals ..................................................... 11 Memory ..................................................................... 12 System Resources .................................................... 12 Applications in Detail ..................................................... 14 Document Number: 001-96786 Rev. *C Ordering Information ...................................................... 18 Ordering Code Definitions ......................................... 18 Packaging ........................................................................ 19 Acronyms ........................................................................ 21 Document Conventions ................................................. 22 Units of Measure ....................................................... 22 Revision History ............................................................. 23 Sales, Solutions, and Legal Information ...................... 24 Worldwide Sales and Design Support ....................... 24 Products .................................................................... 24 PSoC Solutions ......................................................... 24 Cypress Developer Community ................................. 24 Technical Support ..................................................... 24 Page 2 of 24 CYPD1120 The I2C peripheral is compatible with the I2C Standard-mode, Fast-mode, and Fast-mode Plus devices, as defined in the NXP I2C-bus specification and user manual (UM10204). The I2C bus I/O is implemented with GPIO in open-drain modes. Functional Definition CPU and Memory Subsystem CPU The Cortex-M0 CPU in the CCG1 is part of the 32-bit MCU subsystem, which is optimized for low-power operation with extensive clock gating. It mostly uses 16-bit instructions and executes a subset of the Thumb-2 instruction set. This enables fully compatible binary upward migration of the code to higher performance processors such as the Cortex-M3 and M4, thus enabling upward compatibility. The Cypress implementation includes a hardware multiplier that provides a 32-bit result in one cycle. It includes a nested vectored interrupt controller (NVIC) block with 32 interrupt inputs and a Wakeup Interrupt Controller (WIC). The WIC can wake the processor up from the Deep Sleep mode, allowing power to be switched off to the main processor when the chip is in the Deep Sleep mode. The Cortex-M0 CPU provides a Non-Maskable Interrupt (NMI) input, which is made available to the user when it is not in use for system functions requested by the user. The CPU also includes a debug interface, the serial wire debug (SWD) interface, which is a 2-wire form of JTAG; the debug configuration used for CCG1 has four break-point (address) comparators and two watchpoint (data) comparators. The CCG1 is not completely compliant with the I2C spec in the following respects: ■ GPIO cells are not overvoltage tolerant and, therefore, cannot be hot-swapped or powered up independently of the rest of the I2C system. ■ Fast-mode Plus has an IOL specification of 20 mA at a VOL of 0.4 V. The GPIO cells can sink a maximum of 8 mA IOL with a VOL maximum of 0.6 V. ■ Fast-mode and Fast-mode Plus specify minimum Fall times, which are not met with the GPIO cell; Slow strong mode can help meet this spec depending on the Bus Load. ■ ■ Flash The CCG1 device has a flash module with a flash accelerator, tightly coupled to the CPU to improve average access times from the flash block. The flash block is designed to deliver 1 wait-state (WS) access time at 48 MHz and 0-WS access time at 24 MHz. The flash accelerator delivers 85% of single-cycle SRAM access performance on average. Part of the flash module can be used to emulate EEPROM operation if required. The CCG1 has up to 10 GPIOs, which are configured for various functions. Refer to the pinout tables for the definitions. The GPIO block implements the following: ■ Eight drive strength modes: ❐ Analog input mode (input and output buffers disabled) ❐ Input only ❐ Weak pull-up with strong pull-down ❐ Strong pull-up with weak pull-down ❐ Open drain with strong pull-down ❐ Open drain with strong pull-up ❐ Strong pull-up with strong pull-down ❐ Weak pull-up with weak pull-down ■ Input threshold select (CMOS or LVTTL). ■ Individual control of input and output buffer enabling/disabling in addition to the drive strength modes. ■ Hold mode for latching previous state (used for retaining I/O state in Deep Sleep mode). ■ Selectable slew rates for dV/dt related noise control to improve EMI. A supervisory ROM that contains boot and configuration routines is provided. System Resources Power System Serial Communication Blocks (SCB) I 2C The CCG1 has one SCB, which can implement an interface. The hardware I2C block implements a full multi-master and slave interface (it is capable of multimaster arbitration). In addition, the block supports an 8-deep FIFO for receive and transmit which, by increasing the time given for the CPU to read data, greatly reduces the need for clock stretching caused by the CPU not having read data on time. Document Number: 001-96786 Rev. *C When the SCB is in the I2C Slave mode, and Address Match on External Clock is enabled (EC_AM = 1) along with operation in the internally clocked mode (EC_OP = 0), then its I2C address must be even. GPIO SROM The power system is described in detail in the section Power on page 7. It provides assurance that voltage levels are as required for each respective mode and either delay mode entry (on power-on reset (POR), for example) until voltage levels are as required for proper function or generate resets (Brown-Out Detect (BOD)) or interrupts (Low Voltage Detect (LVD)). The CCG1 operates with a single external supply over the range of 1.8 to 5.5 V and has three different power modes: Active, Sleep, and Deep Sleep; transitions between modes are managed by the power system. When the SCB is an I2C Master, it interposes an IDLE state between NACK and Repeated Start; the I2C spec defines Bus free as following a Stop condition so other Active Masters do not intervene but a Master that has just become activated may start an Arbitration cycle. During power-on and reset, the I/O pins are forced to the disable state so as not to crowbar any inputs and/or cause excess turn-on current. A multiplexing network, known as a high-speed I/O matrix, is used to multiplex between various signals that may connect to an I/O pin. Page 3 of 24 CYPD1120 Pin Definitions Table 1 provides the pin definitions for 40-pin QFN and 35-ball WLCSP for the notebook, tablet, smartphone, and monitor applications. Refer to Table 20 on page 18 for par numbers to package mapping. Table 1. Pin Definition for 40-Pin QFN and 35-Ball WLCSP Functional Pin Name CYPD1120-35FNXIT CYPD1120-40LQXI CC1_RX C4 35 Type Description I CC1 control 0: TX enabled z: RX sense CC1_TX D7 38 O Configuration Channel 1 SWD_IO D1 12 I/O SWD IO SWD_CLK C1 13 I SWD Clock I2C_SCL B1 18 I I2C Slave Clock signal I2C_SDA B2 19 I/O I2C Slave Data signal I2C_INT A2 20 O I2C INT XRES B6 30 I Active Low Reset VCCD A7 31 POWER Connect 1-μF capacitor between VCCD and Ground VDDD C7 32 POWER VDDA C7 33 POWER VSSA B7 34 GND Ground VSS – 9 GND Ground CC_VREF C5 36 I Data reference signal for CC lines ADC_BYPASS E7 40 I No Connect TX_U B3 26 O TX_M B5 29 I Signals for internal use only. The TX_U output signal should be connected to the TX_M signal TX_REF_IN D3 3 I Reference signal for internal use. Connect to TX_REF output via a 2.4K 1% resistor TX_GND A3 25 I Connect to GND via 2K 1% resistor TX_REF_OUT D4 39 O Reference signal generated by connecting internal current source to two 1K external resistors VCONN Supply RA_DISCONNECT E4 4 O Optional control signal to remove RA after assertion of VCONN 0: RA disconnected 1: RA connected CC1_LPREF A5 23 I Reference signal for internal use. Connect to the output of resistor divider from VDDD. VCONN_DET E5 5 O Detects presence of VCONN before responding to CC communication I Bypass capacitor for internal analog circuits D5 – – 37 CC1_LPRX C3 22 I Configuration Channel 1 RX signal for Low Power States VBUS_DET B4 28 I Detects presence of VBUS before enabling Billboard device BYPASS Document Number: 001-96786 Rev. *C Page 4 of 24 CYPD1120 Table 1. Pin Definition for 40-Pin QFN and 35-Ball WLCSP (continued) Functional Pin Name CYPD1120-35FNXIT CYPD1120-40LQXI D6 – – 1 DP_AUX_CTRL E1 AUX_CH_P_SENSE BILLBOARD_CTRL Type Description O Enables Billboard Device 10 O Closes AUX_P/N switch after successful Alternate Mode entry E2 8 I Senses presence of DisplayPort on UFP_D AUX_CH_N_SENSE E3 7 I Senses presence of DisplayPort on DFP_D HOTPLUG_DET E6 6 I/O HotPlug Detection/Driver for DisplayPort Alternate Mode GPIO_0 A1 21 I/O GPIO GPIO_1 A6 27 I/O GPIO GPIO_2 C2 14 I/O GPIO GPIO_3 D2 11 I/O GPIO I/O GPIO C6 – – 2 GPIO_5 A4 24 I/O GPIO GPIO_6 – 15 I/O GPIO GPIO_7 – 16 I/O GPIO GPIO_8 – 17 I/O GPIO GPIO_4 Document Number: 001-96786 Rev. *C Page 5 of 24 CYPD1120 Pinouts 40 39 38 37 36 35 34 33 32 31 ADC_BYPASS TX_REF_OUT CC1_TX BYPASS CC_VREF CC1_RX VSSA VDDA VDDD VCCD Figure 2. 40-pin QFN Pinout 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 QFN 11 12 13 14 15 16 17 18 19 20 GPIO_3 SWD_CLK GPIO_2 GPIO_6 GPIO_7 GPIO_8 I2C_SCL I2C_SDA I2C_INT (Top View) SWD_IO BILLBD_CTRL GPIO_4 TX_REF_IN RA_DISCONNECT VCONN_DET HOTPLUG_DET AUX_CH_N_SENSE AUX_CH_P_SENSE VSS DP_AUX_CTRL XRES TX_M VBUS_DET GPIO_1 TX_U TX_GND GPIO_5 CC1_LPREF CC1_LPRX GPIO_0 Figure 3. 35-Ball WLCSP Pinout 7 6 5 4 3 2 1 VCCD GPIO_1 CC1_LPRE F GPIO_5 TX_GND I2C_INT GPIO_0 A VSSA XRES TX_M VBUS_DET TX_U I2C_SDA I2C_SCL B VDDD GPIO_4 CC_VREF CC1_RX CC1_LPRX GPIO_2 SWD_CLK C CC1_TX BILLBOAR D_CTRL BYPASS TX_REF_O UT TX_REF_IN GPIO_3 SWD_IO D ADC_BYPA SS HOTPLUG_ DET VCONN_D ET RA_DISCO NNECT AUX_CH_N _SENSE AUX_CH_P _SENSE DP_AUX_C TRL E Document Number: 001-96786 Rev. *C Page 6 of 24 CYPD1120 Power VDDA and VDDD must be shorted together; the grounds, VSSA and VSS must also be shorted together. Bypass capacitors must be used from VDDD to ground. The typical practice for systems in this frequency range is to use a capacitor in the 1-µF range in parallel with a smaller capacitor (0.1 µF, for example). Note that these are simply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and the bypass capacitor parasitic should be simulated to design and obtain optimal bypassing. The following power system diagram shows the minimum set of power supply pins as implemented for the CCG1. The system has one regulator in Active mode for the digital circuitry. There is no analog regulator; the analog circuits run directly from the VDDA input. There is a separate regulator for the Deep Sleep mode. There is a separate low-noise regulator for the bandgap. The supply voltage range is 1.8 V to 5.5 V with all functions and circuits operating over that range. The CCG1 is powered by an external power supply that can be anywhere in the range of 1.8 V to 5.5 V. This range is also designed for battery-powered operation.For example, the chip can be powered from a battery system that starts at 3.5 V and works down to 1.8 V. In this mode, the internal regulator of the CCG1 supplies the internal logic and the VCCD output of the CCG1 must be bypassed to ground via an external capacitor (in the range of 1 µF to 1.6 µF; X5R ceramic or better). No voltage source should be applied to this pin. Examples of bypass schemes follow. Figure 4. 40-pin QFN Example VDDA VDDD 1 µF VSSA C1 VSS ADC_BYPASS TX_REF_OUT CC1_TX BYPASS CC_VREF CC1_RX VSS VCCD 40 39 38 37 36 35 34 33 32 31 C4 1 µF Document Number: 001-96786 Rev. *C QFN 12 13 14 15 16 17 18 19 20 SWD_CLK GPIO_2 GPIO_6 GPIO_7 GPIO_8 I2C_SCL I2C_SDA I2C_INT (Top View) 11 VSS 30 29 28 27 26 25 24 23 22 21 GPIO_3 DP_AUX_CTRL 1 2 3 4 5 6 7 8 9 10 SWD_IO VSS BILLBD_CTRL GPIO_4 TX_REF_IN RA_DISCONNECT VCONN_DET HOTPLUG_DET AUX_CH_N_SENSE AUX_CH_P_SENSE XRES TX_M VBUS_DET GPIO_1 TX_U TX_GND GPIO_5 CC1_LPREF CC1_LPRX GPIO_0 VSS Page 7 of 24 CYPD1120 Figure 5. 35-ball WLCSP Example VCCD 7 6 5 4 3 2 1 VCCD GPIO_1 CC1_LP REF GPIO_5 TX_GN D I2C_INT GPIO_0 A VSSA XRES TX_M VBUS_ DET TX_U I2C_SD A I2C_SC L B VDDD GPIO_4 CC_VR EF CC1_R X CC1_LP RX GPIO_2 SWD_C LK C CC1_TX BILLBO ARD_C TRL BYPAS S TX_REF _OUT TX_REF _IN GPIO_3 SWD_I O D ADC_B YPASS HOTPL UG_DE T VCONN _DET RA_DIS CONNE CT AUX_C H_N_SE NSE AUX_C H_P_SE NSE DP_AU X_CTRL E 1uF C4 VSS VSS VDDD C1 1uF VSS Document Number: 001-96786 Rev. *C Page 8 of 24 CYPD1120 Electrical Specifications Absolute Maximum Ratings Table 2. Absolute Maximum Ratings[6] Spec ID# SID1 Parameter Description Min Typ Max Units Details/ Conditions VDDD_ABS Digital supply relative to VSSD –0.5 – 6.0 V Absolute max SID2 VCCD_ABS Direct digital core voltage input relative to VSSD –0.5 – 1.95 V Absolute max SID3 VGPIO_ABS GPIO voltage –0.5 – VDDD+0.5 V Absolute max SID4 IGPIO_ABS Maximum current per GPIO –25.0 – 25.0 mA Absolute max SID5 GPIO injection current, Max for VIH > IGPIO_injection VDDD, and Min for VIL < VSS –0.50 – 0.5 mA Absolute max, current injected per pin BID44 ESD_HBM Electrostatic discharge human body model 2200 – – V – BID45 ESD_CDM Electrostatic discharge charged device model 500 – – V – BID46 LU Pin current for latch-up –200 – 200 mA – Device Level Specifications All specifications are valid for –40 °C TA 85 °C and TJ 100 °C for 35-CSP and 40-QFN package options. Specifications are valid for 1.8 V to 5.5 V, except where noted. Table 3. DC Specifications Spec ID# Parameter Description SID53 VDDD Power supply input voltage SID54 VCCD Output voltage (for core logic) SID55 CEFC External regulator voltage bypass SID56 CEXC Power supply decoupling capacitor Min Typ Max Units 1.8 – 5.5 V Details/ Conditions With regulator enabled – 1.8 – V 1.0 1.3 1.6 µF X5R ceramic or better – – 1.0 – µF X5R ceramic or better T = 25 °C Active Mode, VDDD = 1.8 to 5.5 V. Typical values measured at VDD = 3.3 V. SID19 IDD14 Execute from flash; CPU at 48 MHz – 12.8 – mA SID20 IDD15 Execute from flash; CPU at 48 MHz – – 13.8 mA – – 1.7 2.2 mA – – 1.3 – µA T = 25 °C, 3.6 V – – 50.0 µA T = 85 °C I2C wakeup – 15.0 – µA T = 25 °C, 5.5 V Supply current while XRES asserted – 2.0 5.0 mA Sleep Mode, VDDD = 1.8 to 5.5 V SID25A IDD20A I2C wakeup and comparators on Deep Sleep Mode, VDDD = 1.8 to 3.6 V (Regulator on) SID31 SID32 IDD26 IDD27 I2C wakeup on 2 I C wakeup on Deep Sleep Mode, VDDD = 3.6 to 5.5 V SID34 IDD29 XRES Current SID307 IDD_XR – Note 6. Usage above the absolute maximum conditions listed in Table 2 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification. Document Number: 001-96786 Rev. *C Page 9 of 24 CYPD1120 Table 4. AC Specifications Spec ID# Parameter Description Min Typ Max Units Details/ Conditions 1.8 VDD 5.5 SID48 FCPU CPU frequency DC – 48.0 MHz SID49 TSLEEP Wakeup from sleep mode – 0 – µs Guaranteed by characterization SID50 TDEEPSLEEP Wakeup from Deep Sleep mode – – 25.0 µs 24-MHz IMO. Guaranteed by characterization SID52 TRESETWIDTH External reset pulse width 1.0 – – µs Guaranteed by characterization Min Typ Max Units I/O Table 5. I/O DC Specifications Spec ID# Parameter Description Details/ Conditions SID57 VIH[7] Input voltage high threshold 0.7 × VDDD – – V CMOS Input SID58 VIL Input voltage low threshold – – 0.3 × VDDD V CMOS Input SID241 VIH[7] LVTTL input, VDDD < 2.7 V 0.7× VDDD – – V – SID242 VIL LVTTL input, VDDD < 2.7 V – – 0.3 × VDDD V – SID243 VIH[7] LVTTL input, VDDD 2.7 V 2.0 – – V – SID244 VIL LVTTL input, VDDD 2.7 V – – 0.8 V – SID59 VOH Output voltage high level VDDD –0.6 – – V IOH = 4 mA at 3-V VDDD SID60 VOH Output voltage high level VDDD –0.5 – – V IOH = 1 mA at 1.8-V VDDD SID61 VOL Output voltage low level – – 0.6 V IOL = 4 mA at 1.8-V VDDD SID62 VOL Output voltage low level – – 0.6 V IOL = 8 mA at 3-V VDDD SID62A VOL Output voltage low level IOL = 3 mA at 3-V VDDD SID63 RPULLUP Pull-up resistor SID64 RPULLDOWN Pull-down resistor – – 0.4 V 3.5 5.6 8.5 kΩ – – 3.5 5.6 8.5 kΩ – – 2.0 nA SID65 IIL Input leakage current (absolute value) SID65A IIL_CTBM Input leakage current (absolute value) for analog pins – – 4.0 nA – SID66 CIN Input capacitance – – 7.0 pF – SID67 VHYSTTL Input hysteresis LVTTL 15.0 40.0 – mV VDDD 2.7 V. Guaranteed by characterization SID68 VHYSCMOS Input hysteresis CMOS 200.0 – – mV VDDD 4.5 V. Guaranteed by characterization SID69 IDIODE Current through protection diode to VDD/VSS – – 100.0 µA Guaranteed by characterization SID69A ITOT_GPIO Maximum Total Source or Sink Chip Current – – 200.0 mA Guaranteed by characterization 25 °C, VDDD = 3.0 V Note 7. VIH must not exceed VDDD + 0.2 V. Document Number: 001-96786 Rev. *C Page 10 of 24 CYPD1120 Table 6. I/O AC Specifications (Guaranteed by Characterization) Spec ID# Parameter Description Min Typ Max Units Details/ Conditions SID70 TRISEF Rise time 2.0 – 12.0 ns 3.3-V VDDD, Cload = 25 pF SID71 TFALLF Fall time 2.0 – 12.0 ns 3.3-V VDDD, Cload = 25 pF Min 0.7 × VDDD Typ Max Units – – V CMOS input – – V CMOS input 3.5 5.6 XRES Table 7. XRES DC Specifications Spec ID# Parameter Description Details/ Conditions SID77 VIH Input voltage high threshold SID78 VIL Input voltage low threshold SID79 RPULLUP Pull-up resistor SID80 CIN Input capacitance – 3.0 – pF – SID81 VHYSXRES – 100.0 – mV Guaranteed by characterization SID82 IDIODE Input voltage hysteresis Current through protection diode to VDDD/VSS – – 100.0 µA Guaranteed by characterization 0.3 × VDDD 8.5 kΩ – Digital Peripherals The following specifications apply to the Timer/Counter/PWM peripherals in the Timer mode. Pulse Width Modulation (PWM) for VSEL and CUR_LIM Pins Table 8. PWM AC Specifications (Guaranteed by Characterization) Spec ID# Parameter SID140 TPWMFREQ Description Operating frequency Min – Typ – Max 48.0 Units MHz Details/Conditions – SID141 TPWMPWINT Pulse width (internal) 42.0 – – ns – SID142 TPWMEXT Pulse width (external) 42.0 – – ns – SID143 TPWMKILLINT Kill pulse width (internal) 42.0 – – ns – SID144 TPWMKILLEXT Kill pulse width (external) 42.0 – – ns – SID145 TPWMEINT Enable pulse width (internal) 42.0 – – ns – SID146 TPWMENEXT Enable pulse width (external) 42.0 – – ns – SID147 TPWMRESWINT Reset pulse width (internal) 42.0 – – ns – SID148 TPWMRESWEXT Reset pulse width (external) 42.0 – – ns – Min Typ Max Units – – 10.5 µA – – 135.0 µA – – – 310.0 µA – – – 1.4 µA – I2C Table 9. Fixed I2C DC Specifications (Guaranteed by Characterization) Spec ID# Parameter SID149 II2C1 SID150 II2C2 SID151 II2C3 SID152 II2C4 Description Block current consumption at 100 kHz Block current consumption at 400 kHz Block current consumption at 1 Mbps I2C enabled in Deep Sleep mode Document Number: 001-96786 Rev. *C Details/Conditions – Page 11 of 24 CYPD1120 Table 10. Fixed I2C AC Specifications (Guaranteed by Characterization) Spec ID# SID153 Parameter FI2C1 Description Bit rate Min – Typ – Max 1.0 Units Mbps Details/Conditions – Memory Table 11. Flash DC Specifications Spec ID# SID173 Parameter VPE Description Min Typ Max Units Details/Conditions Erase and program voltage 1.8 – 5.5 V – Description Min Typ Max Units Table 12. Flash AC Specifications Spec ID# Parameter Details/Conditions SID174 TROWWRITE[8] Row (block) write time (erase and program) – – 20.0 ms SID175 TROWERASE[8] Row erase time – – 13.0 ms – SID176 TROWPROGRAM[8] Row program time after erase – – 7.0 ms – – – 35 ms – SID178 TBULKERASE [8] Bulk erase time (32 KB) SID180 TDEVPROG[8] Total device program time SID181 FEND Flash endurance SID182 FRET[9] Row (block) = 128 bytes second Guaranteed by characterization s – – 7.0 100 K – – cycles Guaranteed by characterization Flash retention. TA 55 °C, 100 K P/E cycles 20 – – years Guaranteed by characterization SID182A – Flash retention. TA 85 °C, 10 K P/E cycles 10 – – years Guaranteed by characterization SID182B – Flash retention. 85 °C < TA < 105 °C, 10K P/E cycles 3 – – years Guaranteed by characterization System Resources Power-on-Reset (POR) with Brown Out Table 13. Imprecise Power On Reset (PRES) Spec ID# Parameter Description Min Typ Max Units 0.80 – 1.45 V Details/Conditions SID185 VRISEIPOR Rising trip voltage SID186 VFALLIPOR Falling trip voltage 0.75 – 1.40 V Guaranteed by characterization SID187 VIPORHYST Hysteresis 15.0 – 200.0 mV Guaranteed by characterization Min Typ Max Units Guaranteed by characterization Table 14. Precise Power On Reset (POR) Spec ID# Parameter Description Details/Conditions SID190 VFALLPPOR BOD trip voltage in active and sleep modes 1.64 – – V Guaranteed by characterization SID192 VFALLDPSLP BOD trip voltage in Deep Sleep 1.40 – – V Guaranteed by characterization Note 8. It can take as much as 20 milliseconds to write to flash. During this time the device should not be Reset, or flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated. 9. Cypress provides a retention calculator to calculate the retention lifetime based on customers' individual temperature profiles for operation over the –40 °C to +105 °C ambient temperature range. Contact [email protected]. Document Number: 001-96786 Rev. *C Page 12 of 24 CYPD1120 SWD Interface Table 15. SWD Interface Specifications Spec ID Parameter Description Min Typ Max Units Details/Conditions SID213 F_SWDCLK1 3.3 V VDDD 5.5 V – – 14.0 MHz SWDCLK ≤ 1/3 CPU clock frequency SID214 F_SWDCLK2 1.8 V VDDD 3.3 V – – 7.0 MHz SWDCLK ≤ 1/3 CPU clock frequency SID215 T_SWDI_SETUP T = 1/f SWDCLK 0.25*T – – ns Guaranteed by characterization SID216 T_SWDI_HOLD 0.25*T – – ns Guaranteed by characterization SID217 T_SWDO_VALID T = 1/f SWDCLK – – 0.5*T ns Guaranteed by characterization SID217A T_SWDO_HOLD T = 1/f SWDCLK 1 – – ns Guaranteed by characterization Description Min Typ Max Units Details/Conditions IMO operating current at 48 MHz – – 1000.0 µA – Min Typ Max Units Details/Conditions – ±2.0 % T = 1/f SWDCLK Internal Main Oscillator Table 16. IMO DC Specifications (Guaranteed by Design) Spec ID SID218 Parameter IIMO1 Table 17. IMO AC Specifications Spec ID Parameter Description SID223 FIMOTOL1 Frequency variation – With API-called calibration SID226 TSTARTIMO IMO startup time – – 12.0 µs – SID229 TJITRMSIMO3 RMS Jitter at 48 MHz – 139.0 – ps – Internal Low-Speed Oscillator Table 18. ILO DC Specifications (Guaranteed by Design) Spec ID Parameter Description Min Typ Max Units Details/Conditions SID231 IILO1 ILO operating current at 32 kHz – 0.30 1.05 µA Guaranteed by characterization SID233 IILOLEAK ILO leakage current – 2.0 15.0 nA Guaranteed by design Min Typ Max Units Table 19. ILO AC Specifications Spec ID Parameter Description Details/Conditions SID234 TSTARTILO1 ILO startup time – – 2.0 ms Guaranteed by characterization SID236 TILODUTY ILO duty cycle 40.0 50.0 60.0 % Guaranteed by characterization SID237 FILOTRIM1 32-kHz trimmed frequency 15.0 32.0 50.0 kHz Document Number: 001-96786 Rev. *C ±60% with trim Page 13 of 24 CYPD1120 Applications in Detail Figure 6. Type-C to DisplayPort/Mini-DisplayPort Application Using 35-CSP Package Paddle Card on Type-C Plug VBUS 3.3V Regulator VCONN VBUS D+/- USB-Billboard SDA XRES INT SCL 3.3V VCONN 2.2k 5% 2.2k 5% 3.3V 100k 1% D6 D TF412S G S 800 1% C7 Ra 1uF 25V 10% VCONN 100k 1% BILLBOA RD_CTRL VDDD A2 VCCD A5 CC1_LPREF E5 VCONN_DET 100k 1% 22 1% D7 CC1_TX CYPD1120-35FNXIT C4 CC1_RX CC 35CSP C3 CC1_LPRX 5.1k 1% 2.4k 1% 0 D4 TX_REF_OUT D3 CC_VREF TX_GND AUX_CH_ AUX_CH DP_AU P_CTRL _N_CTRL X_CTRL E2 E3 E1 Document Number: 001-96786 Rev. *C XRES ADC_BYPASS TX_REF_IN 2k 1% SBU_1/2 GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 BYPASS C5 1uF 25V 10% VBUS B3 TX_U B5 TX_M B4 VBUS_DET E6 HOTPLUG_DET E4 RA_DISCONNECT 100k 1% A7 D1 SWD_IO C1 SWD_CLK 20k 1% Type-C Plug 2.2nF 25V 10% B2 B1 I2C_ I2C_SCL I2C_SDA INT SW for AUX VSSA 100k 1% HotPlug Detect 100k 1% mDP/ DP Plug A1 A6 C2 D2 C6 A4 B6 0.01µF 25V 10% E7 D5 A3 2k 1% 47pF 25V 10% DP/ mDP Wire Pads B7 AUX_P/N Display Port Data Lanes Page 14 of 24 CYPD1120 Figure 7. Type-C to DisplayPort/mini-DisplayPort Application Using 40-QFN Package Paddle Card on Type-C Plug VBUS 3.3V Regulator VCONN VBUS D+/- USB-Billboard SDA XRES INT SCL 3.3V VCONN 2.2k 5% 2.2k 5% 3.3V 100k 1% 1 D TF412S G S 800 1% BILLBOA RD_CTRL 32 VDDD Ra 1uF 25V 10% VCONN 100k 1% 33 23 20 19 18 I2C_ I2C_SCL I2C_SDA INT VCCD VDDA CC1_LPREF 5 VCONN_DET 100k 1% 22 1% CC 38 CC1_TX 35 CC1_RX GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_8 CYPD1120-40LQXI 40QFN 22 CC1_LPRX 5.1k 1% 2.4k 1% 2.2nF 25V 10% 0 39 TX_REF_OUT 3 TX_REF_IN XRES ADC_BYPASS BYPASS 36 CC_VREF 2k 1% TX_GND AUX_CH_ AUX_CH DP_AU P_CTRL _N_CTRL X_CTRL 8 7 10 SBU_1/2 Document Number: 001-96786 Rev. *C VBUS 26 TX_U 29 TX_M 28 VBUS_DET 6 HOTPLUG_DET 4 RA_DISCONNECT 100k 1% 1uF 25V 10% 12 SWD_IO 13 SWD_CLK 20k 1% Type-C Plug 31 SW for AUX VSSA 100k 1% HotPlug Detect 100k 1% mDP/ DP Plug 21 27 14 11 2 24 15 16 17 30 0.01µF 25V 10% 40 37 25 2k 1% 47pF 25V 10% DP/ mDP Wire Pads 34 VSS 9 AUX_P/N Display Port Data Lanes Page 15 of 24 CYPD1120 Figure 8. Type-C to HDMI Application Using 35-CSP Package 1.2V Paddle Card on Type-C Plug 5V 3.3V Regulator VBUS BuckBoost VCONN VBUS D+/- USB-Billboard SDA XRES INT SCL 3.3V VCONN 2.2k 5% 2.2k 5% 3.3V 100k 1% D6 D TF412S G S 800 1% C7 Ra 1uF 25V 10% VCONN 100k 1% BILLBOA RD_CTRL VDDD A2 B2 B1 I2C_ I2C_SCL I2C_SDA INT CC1_LPREF E5 VCONN_DET 100k 1% 22 1% D7 CC1_TX 35CSP C3 CC1_LPRX 5.1k 1% 2.4k 1% 2.2nF 25V 10% 0 GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 ADC_BYPASS BYPASS C5 CC_VREF 2k 1% TX_GND VSSA AUX_CH_ AUX_CH DP_AU P_CTRL _N_CTRL X_CTRL E2 E3 E1 3.3V SBU_1/2 Display Port Data Lanes Document Number: 001-96786 Rev. *C A1 A6 C2 D2 C6 A4 XRES D4 TX_REF_OUT D3 TX_REF_IN SW for AUX AUX_P/N 100k 1% 100k 1% E6 HOTPLUG_DET CYPD1120-35FNXIT C4 CC1_RX CC VBUS B3 TX_U B5 TX_M B4 VBUS_DET E4 RA_DISCONNECT 100k 1% 1uF 25V 10% D1 SWD_IO C1 SWD_CLK 20k 1% Type-C Plug A7 VCCD A5 HotPlug Detect B6 0.01µF 25V 10% E7 D5 A3 2k 1% 5V 47pF 25V 10% B7 1.2V HDMI/DVI/ VGA Receptacle DP to HDMI/ DVI/VGA Convertor Page 16 of 24 CYPD1120 Figure 9. Type-C to HDMI Application Using 40-QFN Package 1.2V 5V Paddle Card on Type-C Plug 3.3V Regulator VBUS BuckBoost VCONN VBUS D+/- USB-Billboard SDA XRES INT SCL 3.3V VCONN 2.2k 5% 2.2k 5% 3.3V 100k 1% 1 D TF412S G S 800 1% 32 VDDD Ra 1uF 25V 10% VCONN 100k 1% 33 23 19 18 20 BILLBOA I2C_INT I2C_SCL I2C_SDA RD_CTRL VCCD VDDA CC1_LPREF 1uF 25V 10% 12 SWD_IO 13 SWD_CLK 20k 1% Type-C Plug 31 VBUS 26 TX_U 29 TX_M 28 VBUS_DET 5 VCONN_DET 6 HOTPLUG_DET 21 GPIO_0 38 CC1_TX 27 GPIO_1 14 CYPD1120-40LQXI 35 CC1_RX GPIO_2 11 40QFN GPIO_3 22 CC1_LPRX 2 GPIO_4 24 GPIO_5 15 GPIO_6 16 GPIO_7 17 GPIO_8 30 XRES 39 TX_REF_OUT 40 3 ADC_BYPASS TX_REF_IN 37 BYPASS 4 RA_DISCONNECT 100k 1% 100k 1% 22 1% CC 5.1k 1% 2.4k 1% 2.2nF 25V 10% 0 36 CC_VREF 2k 1% TX_GND AUX_CH_ AUX_CH DP_AU P_CTRL _N_CTRL X_CTRL 8 7 10 VSSA 25 100k 1% 100k 1% HotPlug Detect 0.01µF 25V 10% 2k 1% 47pF 25V 10% 34 VSS 9 3.3V 1.2V SBU_1/2 Display Port Data Lanes Document Number: 001-96786 Rev. *C SW for AUX 5V AUX_P/N DP to HDMI/ DVI/VGA Convertor HDMI/DVI/ VGA Receptacle Page 17 of 24 CYPD1120 Ordering Information The CCG1 part numbers and features are listed in the following table. Table 20. CCG1 Ordering Information Part Number[10] Application Type-C Ports[11] Termination Resistor[12] Role[13] Package Si ID CYPD1120-35FNXIT Type-C to DP, Type-C to HDMI 1 Rd[14] UFP[17] 35-WLCSP[15] 0492 CYPD1120-40LQXI Type-C to DP, Type-C to HDMI 1 Rd[14] UFP[17] 40-QFN[16] 0488 CYPD1120-40LQXIT Type-C to DP, Type-C to HDMI 1 Rd[14] UFP[17] 40-QFN[16] 0488 Ordering Code Definitions CY PD X X XX- XX XX X X X T = Tape and reel for CSP, N/A for other packages Temperature Range: I = Industrial, Q = Extended industrial Lead: X = Pb-free Package Type: LQ = QFN, FN = CSP Number of pins in the package 0X: OCP and OVP not supported, 1X: reserved, 2X, 3X: OCP and OVP supported Number of Type-C Ports: 1 = 1 Port, 2 = 2 Port Product Type: 1 = First-generation product family, CCG1 Marketing Code: PD = Power delivery product family Company ID: CY = Cypress Notes 10. All part numbers support: Input voltage range from 1.8 to 5.5 V. Industrial parts support -40 °C to +85 °C, Extended Industrial parts support -40 °C to 105 °C. 11. Number of USB Type-C Ports Supported . 12. Default VCONN Termination. 13. PD Role. 14. Termination resistor denoting an upstream facing port. 15. 35-WLCSP#1 pinout. 16. 40-QFN#3 pinout. 17. Upstream Facing Port. Document Number: 001-96786 Rev. *C Page 18 of 24 CYPD1120 Packaging Table 21. Package Characteristics Conditions Min Typ Max Units TA (40-QFN, 35-CSP) Parameter Operating ambient temperature Description – –40 25.00 85 °C TJ (40-QFN, 35-CSP) Operating junction temperature – –40 – 100 °C TJA Package JA (40-pin QFN) – – 15.34 – °C/Watt TJA Package JA (35-CSP) – – 28.00 – °C/Watt TJC Package JC (40-pin QFN) – – 02.50 – °C/Watt Table 22. Solder Reflow Peak Temperature Package Maximum Peak Temperature Maximum Time at Peak Temperature 40-pin QFN 260 °C 30 seconds 35-ball WLCSP 260 °C 30 seconds Table 23. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Package MSL 40-pin QFN MSL 3 35-ball WLCSP MSL 1 Document Number: 001-96786 Rev. *C Page 19 of 24 CYPD1120 Figure 10. 40-pin QFN Package Outline, 001-80659 001-80659 *A The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floating and not connected to any other signal. Figure 11. 35-Ball WLCSP Package Outline, 001-93741 SIDE VIEW TOP VIEW 1 2 3 4 5 6 7 A BOTTOM VIEW 7 6 5 4 3 2 1 A B B C C D D E E NOTES: 1. REFERENCE JEDEC PUBLICATION 95, DESIGN GUIDE 4.18 2. ALL DIMENSIONS ARE IN MILLIMETERS Document Number: 001-96786 Rev. *C 001-93741 ** Page 20 of 24 CYPD1120 Acronyms Table 24. Acronyms Used in this Document Acronym Description Table 24. Acronyms Used in this Document (continued) Acronym Description analog-to-digital converter opamp operational amplifier API application programming interface OCP Overcurrent protection ARM® advanced RISC machine, a CPU architecture OVP Overvoltage protection CC Configuration Channel PCB printed circuit board CPU central processing unit PGA programmable gain amplifier CRC cyclic redundancy check, an error-checking protocol PHY physical layer POR power-on reset CS Current Sense PRES DFP Downstream Facing Port PSoC Programmable System-on-Chip™ DIO digital input/output, GPIO with only digital capabilities, no analog. See GPIO. PWM pulse-width modulator DP DisplayPort RAM random-access memory electrically erasable programmable read-only memory RISC reduced-instruction-set computing EEPROM ADC ® precise power-on reset RMS root-mean-square real-time clock EMI electromagnetic interference RTC ESD electrostatic discharge RX receive FPB flash patch and breakpoint SAR successive approximation register FS full-speed SCL I2C serial clock GPIO general-purpose input/output, applies to a PSoC pin SDA I2C serial data S/H sample and hold IC integrated circuit IDE integrated development environment SPI Serial Peripheral Interface, a communications protocol I2C, or IIC Inter-Integrated Circuit, a communications protocol SRAM static random access memory SWD serial wire debug, a test protocol ILO internal low-speed oscillator, see also IMO TX transmit IMO internal main oscillator, see also ILO I/O input/output, see also GPIO, DIO, SIO, USBIO UART Universal Asynchronous Transmitter Receiver, a communications protocol LVD low-voltage detect UFP Upstream Facing Port LVTTL low-voltage transistor-transistor logic USB Universal Serial Bus MCU microcontroller unit USBIO NC no connect USB input/output, PSoC pins used to connect to a USB port NMI nonmaskable interrupt VESA Video Electronics Standards Association NVIC nested vectored interrupt controller XRES external reset I/O pin Document Number: 001-96786 Rev. *C Page 21 of 24 CYPD1120 Document Conventions Units of Measure Table 25. Units of Measure Symbol Unit of Measure °C degrees Celsius Hz hertz KB 1024 bytes kHz kilohertz k kilo ohm Mbps megabits per second MHz megahertz M mega-ohm Msps megasamples per second µA microampere µF microfarad µs microsecond µV microvolt µW microwatt mA milliampere ms millisecond mV millivolt nA nanoampere ns nanosecond ohm pF picofarad ppm parts per million ps picosecond s second sps samples per second V volt Document Number: 001-96786 Rev. *C Page 22 of 24 CYPD1120 . Revision History Description Title: CYPD1120, USB Power Delivery Alternate Mode Controller on Type-C Document Number: 001-96786 Revision ECN Orig. of Change Submission Date ** 4686071 VGT 05/13/2015 New datasheet *A 4829889 VGT 07/20/2015 Added CYPD1120-40LQXIT in Ordering Information. Description of Change *B 5104916 VGT 02/05/2016 Updated Ordering Information. *C 5705375 VGT 04/21/2017 Updated Sales, Solutions, and Legal Information. Updated Copyright and Disclaimer. Updated template. Document Number: 001-96786 Rev. *C Page 23 of 24 CYPD1120 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products ARM® Cortex® Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface cypress.com/clocks cypress.com/interface Internet of Things Memory cypress.com/iot cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs Cypress Developer Community Forums | WICED IOT Forums | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers Wireless Connectivity PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP cypress.com/usb cypress.com/wireless Notice regarding compliance with Universal Serial Bus specification. Cypress offers firmware and hardware solutions that are certified to comply with the Universal Serial Bus specification, USB Type-C™ Cable and Connector Specification, and other specifications of USB Implementers Forum, Inc (USB-IF). You may use Cypress or third party software tools, including sample code, to modify the firmware for Cypress USB products. Modification of such firmware could cause the firmware/hardware combination to no longer comply with the relevant USB-IF specification. You are solely responsible ensuring the compliance of any modifications you make, and you must follow the compliance requirements of USB-IF before using any USB-IF trademarks or logos in connection with any modifications you make. In addition, if Cypress modifies firmware based on your specifications, then you are responsible for ensuring compliance with any desired standard or specifications as if you had made the modification. CYPRESS IS NOT RESPONSIBLE IN THE EVENT THAT YOU MODIFY OR HAVE MODIFIED A CERTIFIED CYPRESS PRODUCT AND SUCH MODIFIED PRODUCT NO LONGER COMPLIES WITH THE RELEVANT USB-IF SPECIFICATIONS. © Cypress Semiconductor Corporation, 2015-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. 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Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 001-96786 Rev. *C Revised April 21, 2017 Page 24 of 24