ICS85356I Integrated Circuit Systems, Inc. 2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER GENERAL DESCRIPTION FEATURES The ICS85356I is a dual 2:1 Differential-to-LVPECL Multiplexer and is a member of the HiPerClockSTM HiPerClockS™ family of High Performance Clock Solutions from ICS. The device has both common select and individual select inputs. When COM_SEL is logic High, the CLKxx input pairs will be passed to the output. When COM_SEL is logic Low, the output is determined by the setting of the SEL0 pin for channel 0 and the SEL1 pin for Channel 1. • High speed differential multiplexer. The device can be configured as a 2:1 multiplexer ICS • Dual 3.3V LVPECL outputs • Selectable differential CLKxx, nCLKxx inputs • CLKxx, nCLKxx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Output frequency: 900MHz (typical) The differential input has a common mode range that can accept most differential input types such as LVPECL, LVDS, LVHSTL, SSTL, and HCSL. The ICS85356I can therefore be used as a differential translator to translate almost any differential input type to LVPECL. It can also be used in ECL mode by setting VCC=0V and VEE to -3.0V to - 3.8V. • Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nCLKxx input • Output skew: 75ps (typical) • Propagation delay: 1.15ns (typical) • LVPECL mode operating voltage supply range: VCC = 3V to 3.8V, VEE = 0V The ICS85356I adds negligible jitter to the input clock and can operate at high frequencies in excess of 900MHz thus making it ideal for use in demanding applications such as SONET, Fibre Channel, 1 Gigabit/10 Gigabit Ethernet. • ECL mode operating voltage supply range: VCC = 0V, VEE = -3V to -3.8V • -40°C to 85°C ambient operating temperature • Lead-Free package available • Compatible with MC100LVEL56 BLOCK DIAGRAM CLK0A nCLK0A 0 CLK0B nCLK0B 1 PIN ASSIGNMENT CLK0A nCLK0A nc CLK0B nCLK0B CLK1A nCLK1A nc CLK1B nCLK1B Q0 nQ0 SEL0 COM_SEL 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q0 nQ0 SEL0 COM_SEL SEL1 VCC Q1 nQ1 VEE CLK0A nCLK0A nc CLK0B nCLK0B CLK1A nCLK1A nc CLK1B nCLK1B 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q0 nQ0 SEL0 COM_SEL SEL1 VCC Q1 nQ1 VEE SEL1 CLK1A nCLK1A 0 CLK1B nCLK1B 1 85356AMI Q1 nQ1 ICS85356I ICS85356I 20-Lead SOIC 7.5mm x 12.8mm x 2.3mm M Package Top View 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm G Package Top View www.icst.com/products/hiperclocks.html 1 REV. A OCTOBER 7, 2004 ICS85356I Integrated Circuit Systems, Inc. 2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER TABLE 1. PIN DESCRIPTIONS Number Name Type 14, 20 VCC Power Description Core supply pin. 1 CLK0A Input Pulldown 2 nCLK0A Input Pullup 3, 8 nc Unused 4 CLK0B Input Pulldown 5 nCLK0B Input Pullup No connect. 6 CLK1A Input Pulldown 7 nCLK1A Input Pullup 9 CLK1B Input Pulldown 10 nCLK1B Input Pullup 11 VEE Power 12, 13 nQ1, Q1 Output 15 SEL1 Input Pullup 16 COM_SEL Input Pulldown Pullup 17 SEL0 Input 18, 19 nQ0, Q0 Output Non-inver ting differential clock input. Inver ting differential clock input. Non-inver ting differential clock input. Inver ting differential clock input. Non-inver ting differential clock input. Inver ting differential clock input. Non-inver ting differential clock input. Inver ting differential clock input. Negative supply pins. Differential output pairs. LVPECL interface levels. Clock select input. LVCMOS / LVTTL interface levels. Common select input. LVCMOS / LVTTL interface levels. Clock select input. LVCMOS / LVTTL interface levels. Differential output pairs. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance RPULLUP Input Pullup Resistor 51 4 KΩ pF RPULLDOWN Input Pulldown Resistor 51 KΩ TABLE 3. CONTROL INPUT FUNCTION TABLE Inputs COM_SEL 85356AMI Outputs SEL1 SEL0 Q0 nQ0 Q1 nQ1 0 0 0 CLK0A nCLK0A CLK1A nCLK1A 0 0 1 CLK0B nCLK0B CLK1A nCLK1A 0 1 0 CLK0A nCLK0A CLK1B nCLK1B 0 1 1 CLK0B nCLK0B CLK1B nCLK1B 1 X X CLK0B nCLK0B CLK1B nCLK1B www.icst.com/products/hiperclocks.html 2 REV. A OCTOBER 7, 2004 ICS85356I Integrated Circuit Systems, Inc. 2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 46.2°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±0.3V, TA = -40°C TO 85°C Symbol Parameter VCC Positive Supply Voltage Test Conditions IEE Power Supply Current Minimum Typical Maximum Units 3.0 3.3 3.6 V 40 mA Maximum Units TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±0.3V, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical VIH Input High Voltage SEL0, SEL1, COM_SEL 2 VCC + 0.3 V VIL Input Low Voltage SEL0, SEL1, COM_SEL -0.3 0.8 V IIH Input High Current 5 µA IIL Input Low Current SEL0, SEL1 COM_SEL VCC = VIN = 3.6V VCC = VIN = 3.6V 150 µA SEL0, SEL1 VCC = 3.6V, VIN = 0V -150 µA COM_SEL VCC = 3.6V, VIN = 0V -5 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V±0.3V, TA = -40°C TO 85°C Symbol IIH Parameter Input High Current Test Conditions CLK0A, CLK0B, CLK1A, CLK1B VPP nCLK0A, nCLK0B, nCLK1A, nCLK1B CLK0A, CLK0B, CLK1A, CLK1B Input Low Current nCLK0A, nCLK0B, nCLK1A, nCLK1B Peak-to-Peak Voltage VCMR Common Mode Input Voltage; NOTE 1, 2 IIL Minimum Typical Maximum Units VCC = VIN = 3.6V 150 µA VCC = VIN = 3.6V 5 µA VCC = 3.6V, VIN = 0V -5 µA VCC = 3.6V, VIN = 0V -150 µA 0.15 1.0 V VEE + 0.5 VCC - 0.85 V NOTE 1: Common mode input voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLKx, nCLKx is VCC + 0.3V. 85356AMI www.icst.com/products/hiperclocks.html 3 REV. A OCTOBER 7, 2004 ICS85356I Integrated Circuit Systems, Inc. 2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V±0.3V, TA = -40°C TO 85°C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions VCC - 1.4 VCC - 1.0 V VOL Output Low Voltage; NOTE 1 VCC - 2.0 VCC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V Maximum Units ƒ≤ 700MHz Minimum Typical NOTE 1: Outputs terminated with 50Ω to VCC - 2V. TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±0.3V, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 Test Conditions Minimum Typical 900 ƒ≤ 900MHz 0.85 1.15 MHz 1.45 ns tsk(o) Output Skew; NOTE 2, 3 150 ps tR Output Rise Time 20% to 80% 200 580 ps tF Output Fall Time 20% to 80% 200 580 ps todc Duty Cycle Skew 100 ps 75 All parameters measured at ƒ ≤ 622MHz unless noted otherwise. This par t does not add measurable jitter. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 85356AMI www.icst.com/products/hiperclocks.html 4 REV. A OCTOBER 7, 2004 ICS85356I Integrated Circuit Systems, Inc. 2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER PARAMETER MEASUREMENT INFORMATION 2V V CC Qx V CC SCOPE nCLKxA, nCLKxB LVPECL V VEE V Cross Points PP nQx CMR CLKxA, CLKxB -1.3V ± 0.165V VEE DIFFERENTIAL INPUT LEVEL 3.3V OUTPUT LOAD AC TEST CIRCUIT nQx nQy nCLKxA, nCLKxB CLKxA, CLKxB nQ0, nQ1 Qy Q0, Q1 Qx tPD t sk(o) OUTPUT SKEW PROPAGATION DELAY nQ0, nQ1 80% 80% Q0, Q1 VSW I N G Clock Outputs Pulse Width 20% 20% tR t PERIOD tF odc = t PW t PERIOD OUTPUT RISE/FALL TIME 85356AMI OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD www.icst.com/products/hiperclocks.html 5 REV. A OCTOBER 7, 2004 ICS85356I Integrated Circuit Systems, Inc. 2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC R1 1K Single Ended Clock Input CLKx V_REF nCLKx C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT TERMINATION FOR LVPECL OUTPUTS 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 3.3V Zo = 50Ω 125Ω FOUT 125Ω FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω RTT = 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 2A. LVPECL OUTPUT TERMINATION 85356AMI FIN 50Ω 84Ω FIGURE 2B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 6 REV. A OCTOBER 7, 2004 ICS85356I Integrated Circuit Systems, Inc. 2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 BY R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER BY BY 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE 85356AMI BY www.icst.com/products/hiperclocks.html 7 REV. A OCTOBER 7, 2004 ICS85356I Integrated Circuit Systems, Inc. 2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS85356I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85356I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 0.3V = 3.6V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.6V * 40mA = 144mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30.2mW = 60.4mW Total Power_MAX (3.6V, with all outputs switching) = 144mW + 60.4mW = 204.4mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used . Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 39.7°C/W per Table 6A below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.204W * 39.7°C/W = 93.1°C. This is well below the limit of 125°C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). Table 6A. Thermal Resistance θJA for 20-pin SOIC, Forced Convection θJA by Velocity (Linear Feet per Minute) 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 83.2°C/W 65.7°C/W 57.5°C/W Multi-Layer PCB, JEDEC Standard Test Boards 46.2°C/W 39.7°C/W 36.8°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. Table 6B. Thermal Resistance θJA for 20-pin TSSOP, Forced Convection θJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 73.2°C/W 200 500 98.0°C/W 66.6°C/W 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 85356AMI www.icst.com/products/hiperclocks.html 8 REV. A OCTOBER 7, 2004 ICS85356I Integrated Circuit Systems, Inc. 2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4. VCC Q1 VOUT RL = 50 VCC - 2V Figure 4. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC • For logic high, VOUT = V OH_MAX (V CC_MAX • -V OH_MAX OL_MAX CC_MAX -V OL_MAX CC_MAX – 1.0V ) = 1.0V For logic low, VOUT = V (V =V =V CC_MAX – 1.7V ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. ))/R ] * (V Pd_H = [(V – (V - 2V))/R ] * (V -V ) = [(2V - (V -V -V )= OH_MAX CC_MAX CC_MAX OH_MAX OH_MAX CC_MAX OH_MAX L CC_MAX L [(2V - 1V)/50Ω] * 1V = 20.0mW Pd_L = [(V OL_MAX – (V CC_MAX - 2V))/R ] * (V L CC_MAX -V OL_MAX ) = [(2V - (V CC_MAX -V OL_MAX ))/R ] * (V L CC_MAX -V OL_MAX )= [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW 85356AMI www.icst.com/products/hiperclocks.html 9 REV. A OCTOBER 7, 2004 ICS85356I Integrated Circuit Systems, Inc. 2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER RELIABILITY INFORMATION TABLE 7A. θJAVS. AIR FLOW TABLE FOR 20 LEAD SOIC θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 83.2°C/W 46.2°C/W 65.7°C/W 39.7°C/W 57.5°C/W 36.8°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 7B. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP θJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 73.2°C/W 200 500 98.0°C/W 66.6°C/W 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS85356I is: 446 85356AMI www.icst.com/products/hiperclocks.html 10 REV. A OCTOBER 7, 2004 ICS85356I Integrated Circuit Systems, Inc. PACKAGE OUTLINE - M SUFFIX FOR 2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER 20 LEAD SOIC TABLE 8A. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N A Maximum 20 -- 2.65 A1 0.10 -- A2 2.05 2.55 B 0.33 0.51 C 0.18 0.32 D 12.60 13.00 E 7.40 e H 7.60 1.27 BASIC 10.00 10.65 h 0.25 0.75 L 0.40 1.27 α 0° 8° Reference Document: JEDEC Publication 95, MS - 013, MO - 119 85356AMI www.icst.com/products/hiperclocks.html 11 REV. A OCTOBER 7, 2004 ICS85356I Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR 2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER 20 LEAD TSSOP TABLE 8B. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N A Maximum 20 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 α 0° 8° aaa -- 0.10 0.75 REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MO-153 85356AMI www.icst.com/products/hiperclocks.html 12 REV. A OCTOBER 7, 2004 ICS85356I Integrated Circuit Systems, Inc. 2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS85356AMI ICS85356AMI 20 lead SOIC 38 per tube -40°C to 85°C ICS85356AMIT ICS85356AMI 20 lead SOIC on Tape and Reel 1000 -40°C to 85°C ICS85356AGI ICS85356AGI 20 lead TSSOP 72 per tube -40°C to 85°C ICS85356AGIT ICS85356AGI 20 lead TSSOP on Tape and Reel 2500 -40°C to 85°C ICS85356AGILF ICS85356AGIL 72 per tube -40°C to 85°C ICS85356AGILFT ICS85356AGIL 20 lead "Lead Free" TSSOP 20 lead "Lead Free" TSSOP on Tape and Reel 2500 -40°C to 85°C The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 85356AMI www.icst.com/products/hiperclocks.html 13 REV. A OCTOBER 7, 2004 ICS85356I Integrated Circuit Systems, Inc. 2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER REVISION HISTORY SHEET Rev A 85356AMI Table Page 7 13 Description of Change Added Differential Clock Input Interface section. Ordering Information Table - added Lead Free par t number. Updated data sheet format. www.icst.com/products/hiperclocks.html 14 Date 10/7/04 REV. A OCTOBER 7, 2004