LINER LTC2217 16-bit, 125/105/80msps low power dual adcs serial spi port for configuration Datasheet

LTC2195
LTC2194/LTC2193
16-Bit, 125/105/80Msps
Low Power Dual ADCs
FEATURES
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DESCRIPTION
2-Channel Simultaneous Sampling ADC
Serial LVDS Outputs: 1, 2 or 4 Bits per Channel
76.8dB SNR
90dB SFDR
Low Power: 432mW/360mW/249mW Total
216mW/180mW/125mW per Channel
Single 1.8V Supply
Selectable Input Ranges: 1VP-P to 2VP-P
550MHz Full-Power Bandwidth S/H
Shutdown and Nap Modes
Serial SPI Port for Configuration
52-Pin (7mm × 8mm) QFN Package
APPLICATIONS
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Communications
Cellular Base Stations
Software-Defined Radios
Portable Medical Imaging
Multi-Channel Data Acquisition
Nondestructive Testing
The LTC®2195/LTC2194/LTC2193 are 2-channel, simultaneous sampling 16-bit A/D converters designed for
digitizing high frequency, wide dynamic range signals.
They are perfect for demanding communications applications with AC performance that includes 76.8dB SNR and
90dB spurious free dynamic range (SFDR). Ultralow jitter
of 0.07psRMS allows undersampling of IF frequencies with
excellent noise performance.
DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 3.4LSBRMS.
To minimize the number of data lines the digital outputs
are serial LVDS. Each channel outputs two bits or four bits
at a time. At lower sampling rates there is a one bit per
channel option. The LVDS drivers have optional internal
termination and adjustable output levels to ensure clean
signal integrity.
The ENC+ and ENC– inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL or CMOS
inputs. An internal clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
2-Tone FFT, fIN = 70MHz and 69MHz
VDD
CH1
ANALOG
INPUT
CH2
ANALOG
INPUT
ENCODE
INPUT
S/H
S/H
1.8V
16-BIT
ADC CORE
16-BIT
ADC CORE
DATA
SERIALIZER
PLL
GND
0
OVDD
OGND
219543 TA01a
–10
OUT1A
OUT1B
OUT1C
OUT1D
OUT2A
OUT2B
OUT2C
OUT2D
DATA CLOCK OUT
FRAME
–20
–30
SERIALIZED
LVDS
OUTPUTS
AMPLITUDE (dBFS)
1.8V
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
10
20
30
40
FREQUENCY (MHz)
50
60
219543 TA01b
219543f
1
LTC2195
LTC2194/LTC2193
OUT1B–
OUT1B+
OUT1A–
OUT1A+
GND
SDO
GND
VREF
GND
TOP VIEW
SENSE
Supply Voltages
VDD, OVDD................................................. –0.3V to 2V
Analog Input Voltage
AIN+, AIN–, PAR/SER, SENSE
(Note 3).....................................–0.3V to (VDD + 0.2V)
Digital Input Voltage
ENC+, ENC–, CS, SDI, SCK (Note 4)....... –0.3V to 3.9V
SDO (Note 4)............................................. –0.3V to 3.9V
Digital Output Voltage................. –0.3V to (OVDD + 0.3V)
Operating Temperature Range
LTC2195C, LTC2194C, LTC2193C............. 0°C to 70°C
LTC2195I, LTC2194I, LTC2193I............. –40°C to 85°C
Storage Temperature Range.................... –65°C to 150°C
PIN CONFIGURATION
VDD
(Notes 1, 2)
VDD
ABSOLUTE MAXIMUM RATINGS
52 51 50 49 48 47 46 45 44 43 42 41
VCM1 1
40 OUT1C+
GND 2
39 OUT1C–
AIN1+ 3
38 OUT1D+
AIN1– 4
37 OUT1D–
GND 5
36 DCO+
REFH 6
35 DCO–
REFL 7
34 OVDD
53
GND
REFH 8
33 OGND
REFL 9
32 FR+
PAR/SER 10
31 FR–
AIN2+ 11
30 OUT2A+
AIN2– 12
29 OUT2A–
GND 13
28 OUT2B+
VCM2 14
27 OUT2B–
OUT2C+
OUT2C–
OUT2D+
OUT2D–
GND
SDI
SCK
CS
ENC–
ENC+
VDD
VDD
15 16 17 18 19 20 21 22 23 24 25 26
UKG PACKAGE
52-LEAD (7mm × 8mm) PLASTIC QFN
TJMAX = 150°C, θJA = 28°C/W
EXPOSED PAD (PIN 53) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2195CUKG#PBF
LTC2195CUKG#TRPBF
LTC2195UKG
52-Lead (7mm × 8mm) Plastic QFN
0°C to 70°C
LTC2195IUKG#PBF
LTC2195IUKG#TRPBF
LTC2195UKG
52-Lead (7mm × 8mm) Plastic QFN
–40°C to 85°C
LTC2194CUKG#PBF
LTC2194CUKG#TRPBF
LTC2194UKG
52-Lead (7mm × 8mm) Plastic QFN
0°C to 70°C
LTC2194IUKG#PBF
LTC2194IUKG#TRPBF
LTC2194UKG
52-Lead (7mm × 8mm) Plastic QFN
–40°C to 85°C
LTC2193CUKG#PBF
LTC2193CUKG#TRPBF
LTC2193UKG
52-Lead (7mm × 8mm) Plastic QFN
0°C to 70°C
LTC2193IUKG#PBF
LTC2193IUKG#TRPBF
LTC2193UKG
52-Lead (7mm × 8mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
219543f
2
LTC2195
LTC2194/LTC2193
CONVERTER CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
Resolution (No Missing Codes)
MIN
l
16
LTC2195
TYP
MAX
MIN
LTC2194
TYP
MAX
16
MIN
LTC2193
TYP
MAX
UNITS
16
Bits
Integral Linearity Error
Differential Analog Input
(Note 6)
l
–7
±2
7
–7.5
±2
7.5
–7.5
±2
7.5
LSB
Differential Linearity Error
Differential Analog Input
l
–0.9
±0.5
0.9
–0.9
±0.5
0.9
–0.9
±0.5
0.9
LSB
Offset Error
(Note 7)
l
–7
±1.5
7
–7
±1.5
7
–7
±1.5
7
mV
Gain Error
Internal Reference
External Reference
l
–2.0
±1.5
–0.7
0.6
–1.8
±1.5
–0.5
0.8
–1.8
±1.5
–0.5
0.8
%FS
%FS
Offset Drift
±10
±10
±10
µV/°C
±30
±10
±30
±10
±30
±10
ppm/°C
ppm/°C
Gain Matching
±0.3
±0.3
±0.3
%FS
Offset Matching
±1.5
±1.5
±1.5
mV
Transition Noise
3.4
3.5
3.2
LSBRMS
Full-Scale Drift
Internal Reference
External Reference
ANALOG INPUT
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
VIN
Analog Input Range (AIN+ – AIN–)
1.7V < VDD < 1.9V
l
MIN
TYP
MAX
VIN(CM)
Analog Input Common Mode (AIN+ + AIN–)/2
Differential Analog Input (Note 8)
l
0.7
VCM
1.25
l
0.625
1.250
1.300
1 to 2
UNITS
VP-P
V
VSENSE
External Voltage Reference Applied to SENSE
External Reference Mode
IINCM
Analog Input Common Mode Current
Per Pin, 125Msps
Per Pin, 105Msps
Per Pin, 80Msps
IIN1
Analog Input Leakage Current (No Encode)
0 < AIN+, AIN– < VDD
l
–1
1
µA
IIN2
PAR/SER Input Leakage Current
0 < PAR/SER < VDD
l
–3
3
µA
IIN3
SENSE Input Leakage Current
0.625V < SENSE < 1.3V
l
–6
6
µA
tAP
Sample-and-Hold Acquisition Delay Time
tJITTER
Sample-and-Hold Acquisition Delay Jitter
CMRR
Analog Input Common Mode Rejection Ratio
BW–3B
Full-Power Bandwidth
200
170
130
0
V
µA
µA
µA
ns
Single-Ended Encode
Differential Encode
0.07
0.09
psRMS
psRMS
80
dB
Figure 6 Test Circuit
550
MHz
219543f
3
LTC2195
LTC2194/LTC2193
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
SNR
Signal-to-Noise Ratio
5MHz Input
70MHz Input
140MHz Input
l
Spurious Free Dynamic Range 5MHz Input
2nd Harmonic
70MHz Input
140MHz Input
SFDR
S/(N+D)
MIN
LTC2195
TYP
MAX
74.5
76.8
76.6
76.1
l
79
Spurious Free Dynamic Range 5MHz Input
3rd Harmonic
70MHz Input
140MHz Input
l
Spurious Free Dynamic Range 5MHz Input
4th Harmonic or Higher
70MHz Input
140MHz Input
Signal-to-Noise Plus
Distortion Ratio
5MHz Input
70MHz Input
140MHz Input
Crosstalk
10MHz Input
MIN
LTC2194
TYP
MAX
74.8
76.7
76.5
76
90
89
84
81
81
90
89
84
l
88
l
73.3
MIN
LTC2193
TYP
MAX
UNITS
75.1
77.1
76.9
76.4
dBFS
dBFS
dBFS
90
89
84
81
90
89
84
dBFS
dBFS
dBFS
81
90
89
84
82
90
89
84
dBFS
dBFS
dBFS
95
95
95
89
95
95
95
89
95
95
95
dBFS
dBFS
dBFS
76.6
76.2
75.1
74
76.5
76.1
75
74.4
76.9
76.5
75.3
dBFS
dBFS
dBFS
–110
dBc
–110
–110
INTERNAL REFERENCE CHARACTERISTICS
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
VCM Output Voltage
IOUT = 0
MIN
TYP
MAX
0.5 • VDD – 25mV
0.5 • VDD
0.5 • VDD + 25mV
VCM Output Temperature Drift
UNITS
±25
VCM Output Resistance
–600µA < IOUT < 1mA
VREF Output Voltage
IOUT = 0
ppm/°C
4
1.225
Ω
1.250
VREF Output Temperature Drift
1.275
V
±25
VREF Output Resistance
–400µA < IOUT < 1mA
VREF Line Regulation
1.7V < VDD < 1.9V
V
ppm/°C
7
Ω
0.6
mV/V
DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ENCODE INPUTS (ENC+, ENC–)
Differential Encode Mode (ENC– Not Tied to GND)
VID
Differential Input Voltage
(Note 8)
l
0.2
VICM
Common Mode Input Voltage
Internally Set
Externally Set (Note 8)
l
1.1
l
0.2
V
1.2
1.6
V
V
VIN
Input Voltage Range
ENC+, ENC– to GND (Note 8)
RIN
Input Resistance
See Figure 10
10
kΩ
CIN
Input Capacitance
(Note 8)
3.5
pF
3.6
V
219543f
4
LTC2195
LTC2194/LTC2193
DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Single-Ended Encode Mode (ENC– Tied to GND)
VIH
High Level Input Voltage
VDD =1.8V
l
VIL
Low Level Input Voltage
VDD =1.8V
l
1.2
V
VIN
Input Voltage Range
ENC+ to GND
l
RIN
Input Resistance
See Figure 11
30
kΩ
CIN
Input Capacitance
(Note 8)
3.5
pF
0
0.6
V
3.6
V
DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
VIH
High Level Input Voltage
VDD =1.8V
l
VIL
Low Level Input Voltage
VDD =1.8V
l
IIN
Input Current
VIN = 0V to 3.6V
l
CIN
Input Capacitance
(Note 8)
1.3
V
–10
0.6
V
10
µA
3
pF
SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used)
ROL
Logic Low Output Resistance to GND
VDD =1.8V, SDO = 0V
IOH
Logic High Output Leakage Current
SDO = 0V to 3.6V
COUT
Output Capacitance
(Note 8)
200
l
Ω
–10
10
µA
3
pF
DIGITAL DATA OUTPUTS
VOD
Differential Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l
l
247
125
350
175
454
250
mV
mV
VOS
Common Mode Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l
l
1.125
1.125
1.250
1.250
1.375
1.375
RTERM
On-Chip Termination Resistance
Termination Enabled, OVDD = 1.8V
100
V
V
Ω
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
MIN
LTC2195
TYP MAX
CONDITIONS
VDD
Analog Supply Voltage
(Note 10)
l
1.7
OVDD
Output Supply Voltage
(Note 10)
l
1.7
IVDD
Analog Supply Current
Sine Wave Input
l
IOVDD
Digital Supply Current
2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
4-Lane Mode, 1.75mA Mode
4-Lane Mode, 3.5mA Mode
l
l
l
l
PDISS
Power Dissipation
2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
4-Lane Mode, 1.75mA Mode
4-Lane Mode, 3.5mA Mode
l
l
l
l
PSLEEP
Sleep Mode Power
1
1
1
mW
PNAP
Nap Mode Power
50
50
50
mW
PDIFFCLK
Power Increase with Diffential Encode Mode Enabled
(No Increase for Sleep Mode)
20
20
20
mW
1.9
1.7
1.8
1.9
1.7
224
248
16
27
23
42
20
32
27
49
432
452
445
479
482
504
495
535
1.8
MIN
LTC2193
TYP MAX
PARAMETER
1.8
MIN
LTC2194
TYP MAX
SYMBOL
1.8
1.9
UNITS
1.9
1.7
V
1.8
1.9
1.7
1.8
1.9
V
185
205
123
138
mA
15
27
23
42
19
32
27
49
15
26
22
41
19
31
26
48
mA
mA
mA
mA
360
382
375
409
403
427
418
457
249
269
261
295
283
304
295
335
mW
mW
mW
mW
219543f
5
LTC2195
LTC2194/LTC2193
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
fS
Sampling Frequency
(Notes 10, 11)
tENCL
MIN
l
5
ENC Low Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
3.8
2
tENCH
ENC High Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
3.8
2
tAP
Sample-and-Hold
Acquistion Delay Time
SYMBOL
PARAMETER
CONDITIONS
LTC2195
TYP MAX
MIN
125
5
4
4
100
100
4.52
2
4
4
100
100
4.52
2
LTC2194
TYP MAX
MIN
105
5
4.76
4.76
100
100
5.93
2
4.76
4.76
100
100
5.93
2
LTC2193
TYP MAX
UNITS
80
MHz
6.25
6.25
100
100
ns
ns
6.25
6.25
100
100
ns
ns
0
0
0
MIN
TYP
MAX
ns
UNITS
Digital Data Outputs (RTERM = 100Ω Differential, CL = 2pF to GND On Each Output)
tSER
Serial Data Bit Period
4-Lane Output Mode
2-Lane Output Mode
1-Lane Output Mode
1/(4 • fS)
1/(8 • fS)
1/(16 • fS)
tFRAME
FR to DCO Delay
(Note 8)
l
tDATA
Data to DCO Delay
(Note 8)
l
0.35 • tSER
tPD
Propagation Delay
(Note 8)
l
0.7n + 2 • tSER
tr
Output Rise Time
Data, DCO, FR, 20% to 80%
0.17
ns
tf
Output Fall Time
Data, DCO, FR, 20% to 80%
0.17
ns
DCO Cycle-Cycle Jitter
tSER = 1ns
0.35 • tSER
Pipeline Latency
0.5 • tSER
Sec
0.65 • tSER
Sec
0.5 • tSER
0.65 • tSER
Sec
1.1n + 2 • tSER
1.5n + 2 • tSER
Sec
60
psP-P
7
Cycles
SPI Port Timing (Note 8)
tSCK
SCK Period
tS
Write Mode
Readback Mode,
CSDO = 20pF, RPULLUP = 2k
l
l
40
250
ns
ns
CS-to-CLK Setup Time
l
5
ns
tH
SCK-to-CS Setup Time
l
5
ns
tDS
SDI Setup Time
l
5
ns
tDH
SDI Hold Time
l
5
ns
tDO
SCK Falling to SDO
Valid
Readback Mode,
CSDO = 20pF, RPULLUP = 2k
l
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above VDD
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
Note 5: VDD = OVDD = 1.8V, fSAMPLE = 125MHz (LTC2195), 105MHz
(LTC2194), or 80MHz (LTC2193), 2-lane output mode, differential
ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive,
unless otherwise noted.
125
ns
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5LSB when
the output code flickers between 0000 0000 0000 0000 and 1111 1111
1111 1111 in 2’s complement output mode.
Note 8: Guaranteed by design, not subject to test.
Note 9: VDD = OVDD=1.8V, fSAMPLE = 125MHz (LTC2195),
105MHz (LTC2194), or 80MHz (LTC2193), 2-lane output mode,
ENC+ = single‑ended 1.8V square wave, ENC– = 0V, input range = 2VP-P
with differential drive, unless otherwise noted. The supply current and
power dissipation specifications are totals for the entire IC, not per
channel.
Note 10: Recommended operating conditions.
Note 11: The maximum sampling frequency depends on the speed grade
of the part and also which serialization mode is used. The maximum serial
data rate is 1000Mbps, so tSER must be greater than or equal to 1ns.
219543f
6
LTC2195
LTC2194/LTC2193
TIMING DIAGRAMS
4-Lane Output Mode
tAP
ANALOG
INPUT
N
N+1
tENCL
tENCH
ENC–
ENC+
tDATA
DCO–
tSER
DCO+
FR–
OUT#A–
OUT#A+
OUT#B–
OUT#B+
OUT#C–
OUT#C+
OUT#D–
OUT#D+
tSER
tFRAME
FR+
tPD
tSER
D15
D13
D11
D9
D15
D13
D11
D9
D15
D14
D12
D10
D8
D14
D12
D10
D8
D14
D7
D5
D3
D1
D7
D5
D3
D1
D7
D6
D4
D2
D0
D6
D4
D2
D0
D6
SAMPLE N–7
SAMPLE N–6
SAMPLE N–5
219543 TD01
2-Lane Output Mode
tAP
ANALOG
INPUT
N+1
N
tENCL
tENCH
ENC–
ENC+
tSER
DCO–
DCO+
tFRAME
FR–
FR+
tSER
tPD
OUT#A–
OUT#A+
tDATA
tSER
D7
D5
D3
D1
D15
D13
D11
D9
D7
D5
D3
D1
D15
D13
D11
D6
D4
D2
D0
D14
D12
D10
D8
D6
D4
D2
D0
D14
D12
D10
OUT#B–
OUT#B+
SAMPLE N–7
SAMPLE N–6
OUT#C+, OUT#C–, OUT#D+, OUT#D– ARE DISABLED
SAMPLE N–5
219543 TD02
219543f
7
LTC2195
LTC2194/LTC2193
TIMING DIAGRAMS
1-Lane Output Mode
tAP
ANALOG
INPUT
N+1
N
tENCH
ENC–
tENCL
ENC+
tSER
DCO–
DCO+
tFRAME
FR–
FR+
tSER
tPD
OUT#A–
OUT#A+
tDATA
D3
D2
D1
tSER
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
D14
D13
D12
219543 TD03
SAMPLE N–7
SAMPLE N–6
SAMPLE N–5
OUT#B+, OUT#B–, OUT#C+, OUT#C–, OUT#D+, OUT#D– ARE DISABLED
SPI Port Timing (Readback Mode)
tDS
tS
tDH
tSCK
tH
CS
SCK
tDO
SDI
SDO
R/W
A6
A5
A4
A3
A2
A1
A0
XX
D7
HIGH IMPEDANCE
XX
D6
XX
D5
XX
D4
XX
D3
XX
D2
XX
XX
D1
D0
SPI Port Timing (Write Mode)
CS
SCK
SDI
SDO
R/W
HIGH IMPEDANCE
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
219543 TD04
219543f
8
LTC2195
LTC2194/LTC2193
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2195: Integral
Nonlinearity (INL)
LTC2195: Differential
Nonlinearity (DNL)
4.0
1.0
0
3.0
0.8
–10
1.0
0
–1.0
–2.0
–30
0.4
AMPLITUDE (dBFS)
DNL ERROR (LSB)
INL ERROR (LSB)
–20
0.6
2.0
0.2
0
–0.2
–0.4
–0.8
–4.0
–1.0
0
16384
32768
49152
OUTPUT CODE
65536
0
16384
32768
49152
OUTPUT CODE
219543 G01
–60
–70
–80
65536
–110
–120
0
–10
–20
–20
–20
–30
–30
–30
–70
–80
AMPLITUDE (dBFS)
0
–10
AMPLITUDE (dBFS)
0
–60
–40
–50
–60
–70
–80
–60
–70
–80
–90
–100
–110
–120
–110
–120
–110
–120
20
30
40
FREQUENCY (MHz)
50
60
0
10
20
30
40
FREQUENCY (MHz)
219543 G04
LTC2195: 64k Point 2-Tone FFT,
fIN = 69MHz, 70MHz, –7dBFS,
125Msps
0
10000
–10
9000
–20
–60
–70
–80
20
30
40
FREQUENCY (MHz)
50
60
219543 G07
60
78
77
6000
5000
4000
0
32750
SINGLE-ENDED
ENCODE
76
75
74
DIFFERENTIAL
ENCODE
73
72
71
1000
10
50
LTC2195: SNR vs Input Frequency,
–1dBFS, 125Msps, 2V Range
2000
0
20
30
40
FREQUENCY (MHz)
LTC2195: Shorted Input Histogram
3000
–90
–100
10
219543 G06
SNR (dBFS)
–50
0
219543 G05
7000
–40
COUNT
AMPLITUDE (dBFS)
60
8000
–30
–110
–120
50
60
–40
–90
–100
10
50
–50
–90
–100
0
20
30
40
FREQUENCY (MHz)
LTC2195: 64k Point FFT,
fIN = 140MHz, –1dBFS, 125Msps
–10
–50
10
219543 G03
LTC2195: 64k Point FFT,
fIN = 70MHz, –1dBFS, 125Msps
–40
0
219543 G02
LTC2195: 64k Point FFT,
fIN = 30MHz, –1dBFS, 125Msps
AMPLITUDE (dBFS)
–40
–50
–90
–100
–0.6
–3.0
LTC2195: 64k Point FFT,
fIN = 5MHz, –1dBFS, 125Msps
32756
32762 32768
OUTPUT CODE
32774
219543 G08
70
0
50
100
150
200
250
INPUT FREQUENCY (MHz)
300
219543 G09
219543f
9
LTC2195
LTC2194/LTC2193
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2195: 2nd, 3rd Harmonic
vs Input Frequency, –1dBFS,
125Msps, 1V Range
100
95
95
90
3RD
85
80
2ND
75
70
65
0
50
100
150
200
250
INPUT FREQUENCY (MHz)
85
2ND
80
75
100
90
80
60
50
40
30
0
50
100
150
200
250
INPUT FREQUENCY (MHz)
20
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
300
219543 G11
LTC2195: SNR vs SENSE,
fIN = 5MHz, –1dBFS
45
78
4-LANE, 3.5mA
77
220
35
76
2-LANE, 3.5mA
25
4-LANE, 1.75mA
1-LANE, 3.5mA
180
15
25
50
75
100
5
125
74
73
71
1-LANE, 1.75mA
0
75
72
2-LANE, 1.75mA
170
0
SAMPLE RATE (Msps)
25
75
100
50
SAMPLE RATE (Msps)
70
125
LTC2194: Integral
Nonlinearity (INL)
4.0
1.0
0
3.0
0.8
–10
–2.0
–4.0
0.2
0
–0.2
–0.4
–0.8
0
16384
32768
49152
OUTPUT CODE
65536
219543 G16
1.2
1.3
–1.0
LTC2194: 64k Point FFT,
fIN = 5MHz, –1dBFS, 105Msps
–40
–50
–60
–70
–80
–90
–100
–0.6
–3.0
0.9
1
1.1
SENSE PIN (V)
–30
0.4
AMPLITUDE (dBFS)
DNL ERROR (LSB)
–1.0
0.8
–20
0.6
2.0
0
0.7
219543 G15
LTC2194: Differential
Nonlinearity (DNL)
1.0
0.6
219543 G14
219543 G13
INL ERROR (LSB)
SNR (dBFS)
IOVDD (mA)
IVDD (mA)
210
0
219543 G12
LTC2195: IOVDD vs Sample Rate,
5MHz, –1dBFS Sine Wave Input
230
160
dBc
70
70
LTC2195: IVDD vs Sample Rate,
5MHz, –1dBFS Sine Wave Input
190
dBFS
110
3RD
219543 G10
200
LTC2195: SFDR vs Input Level,
fIN = 70MHz, 125Msps, 2V Range
120
90
65
300
130
SFDR (dBc AND dBFS)
100
2ND AND 3RD HARMONIC (dBFS)
2ND AND 3RD HARMONIC (dBFS)
LTC2195: 2nd, 3rd Harmonic
vs Input Frequency, –1dBFS,
125Msps, 2V Range
0
16384
32768
49152
OUTPUT CODE
65536
219543 G17
–110
–120
0
10
20
30
40
FREQUENCY (MHz)
50
219543 G18
219543f
10
LTC2195
LTC2194/LTC2193
TYPICAL PERFORMANCE CHARACTERISTICS
0
LTC2194: 64k Point FFT,
fIN = 70MHz, –1dBFS, 105Msps
–10
–20
–20
–20
–30
–30
–30
–40
–50
–60
–70
–80
AMPLITUDE (dBFS)
–10
–40
–50
–60
–70
–80
–50
–60
–70
–80
–90
–100
–90
–100
–110
–120
–110
–120
–110
–120
0
10
20
30
40
FREQUENCY (MHz)
50
0
10
20
30
40
FREQUENCY (MHz)
LTC2194: 64k Point 2-Tone FFT,
fIN = 69MHz, 70MHz, –7dBFS,
105Msps
9000
77
8000
–80
5000
4000
3000
–90
–100
10
20
30
40
FREQUENCY (MHz)
0
32790
50
32796
32802 32808
OUTPUT CODE
100
95
95
2ND AND 3RD HARMONIC (dBFS)
100
80
2ND
75
70
65
0
50
100
150
200
250
INPUT FREQUENCY (MHz)
300
219543 G25
50
100
150
200
250
INPUT FREQUENCY (MHz)
130
120
110
3RD
90
85
2ND
80
75
LTC2194: SFDR vs Input Level,
fIN = 70MHz, 105Msps, 2V Range
dBFS
100
90
80
70
dBc
60
50
40
70
65
300
219543 G24
LTC2194: 2nd, 3rd Harmonic
vs Input Frequency, –1dBFS,
105Msps, 1V Range
3RD
0
219543 G23
LTC2194: 2nd, 3rd Harmonic
vs Input Frequency, –1dBFS,
105Msps, 2V Range
90
DIFFERENTIAL
ENCODE
73
70
32814
219543 G22
85
74
71
1000
0
75
72
2000
SFDR (dBc AND dBFS)
–110
–120
6000
SNR (dBFS)
COUNT
–70
SINGLE-ENDED
ENCODE
76
7000
–60
50
LTC2194: SNR vs Input Frequency,
–1dBFS, 105Msps, 2V Range
78
–50
20
30
40
FREQUENCY (MHz)
LTC2194: Shorted Input Histogram
10000
–40
10
219543 G21
0
–30
0
219543 G20
–10
–20
AMPLITUDE (dBFS)
50
LTC2194: 64k Point FFT,
fIN = 140MHz, –1dBFS, 105Msps
–40
–90
–100
219543 G19
2ND AND 3RD HARMONIC (dBFS)
0
–10
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
LTC2194: 64k Point FFT,
fIN = 30MHz, –1dBFS, 105Msps
30
0
50
100
150
200
250
INPUT FREQUENCY (MHz)
300
219543 G26
20
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
219543 G27
219543f
11
LTC2195
LTC2194/LTC2193
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2194: IOVDD vs Sample Rate,
5MHz, –1dBFS Sine Wave Input
LTC2194: IVDD vs Sample Rate,
5MHz, –1dBFS Sine Wave Input
190
LTC2194: SNR vs SENSE,
fIN = 5MHz, –1dBFS
78
45
4-LANE, 3.5mA
77
180
35
76
160
2-LANE, 3.5mA
25
4-LANE, 1.75mA
150
1-LANE, 3.5mA
15
25
50
75
SAMPLE RATE (Msps)
5
100
0
25
75
50
SAMPLE RATE (Msps)
219543 G28
70
100
1.0
0
3.0
0.8
–10
–2.0
0.2
0
–0.2
–0.4
–0.8
0
16384
32768
49152
OUTPUT CODE
–1.0
65536
0
16384
32768
49152
OUTPUT CODE
219543 G31
–50
–60
–70
–80
65536
–110
–120
0
–10
–20
–20
–20
–30
–30
–30
–80
AMPLITUDE (dBFS)
0
–10
AMPLITUDE (dBFS)
0
–70
–40
–50
–60
–70
–80
–50
–70
–80
–90
–100
–110
–120
–110
–120
–110
–120
20
30
FREQUENCY (MHz)
40
219543 G34
0
10
20
30
FREQUENCY (MHz)
40
–60
–90
–100
10
20
30
FREQUENCY (MHz)
–40
–90
–100
0
10
LTC2193: 64k Point FFT,
fIN = 140MHz, –1dBFS, 80Msps
–10
–60
0
219543 G33
LTC2193: 64k Point FFT,
fIN = 70MHz, –1dBFS, 80Msps
–50
1.3
–40
219543 G32
LTC2193: 64k Point FFT,
fIN = 30MHz, –1dBFS, 80Msps
–40
1.2
–90
–100
–0.6
–3.0
–4.0
0.9
1
1.1
SENSE PIN (V)
–30
0.4
AMPLITUDE (dBFS)
DNL ERROR (LSB)
–1.0
0.8
–20
0.6
0
0.7
LTC2193: 64k Point FFT,
fIN = 5MHz, –1dBFS, 80Msps
4.0
1.0
0.6
219543 G30
LTC2193: Differential
Nonlinearity (DNL)
2.0
INL ERROR (LSB)
73
219543 G29
LTC2193: Integral
Nonlinearity (INL)
AMPLITUDE (dBFS)
74
71
1-LANE, 1.75mA
0
75
72
2-LANE, 1.75mA
140
130
SNR (dBFS)
IOVDD (mA)
IVDD (mA)
170
40
219543 G35
0
10
20
30
FREQUENCY (MHz)
40
219543 G36
219543f
12
LTC2195
LTC2194/LTC2193
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2193: 64k Point, 2-Tone FFT,
fIN = 69MHz, 70MHz, –7dBFS,
80Msps
0
10000
78
–10
9000
77
–20
8000
–60
–70
–80
5000
4000
3000
–90
–100
10
20
30
FREQUENCY (MHz)
0
32817
40
32823
32829
32835
OUTPUT CODE
219543 G37
95
95
2ND AND 3RD HARMONIC (dBFS)
100
85
80
2ND
75
70
65
0
50
100
150
200
250
INPUT FREQUENCY (MHz)
70
32841
2ND
80
75
0
50
100
150
200
250
INPUT FREQUENCY (MHz)
50
LTC2193: SNR vs SENSE,
fIN = 5MHz, –1dBFS
78
77
76
2-LANE, 3.5mA
25
4-LANE, 1.75mA
1-LANE, 3.5mA
15
2-LANE, 1.75mA
1-LANE, 1.75mA
219543 G43
5
0
219543 G42
SNR (dBFS)
IOVDD (mA)
IVDD (mA)
60
20
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
300
35
80
dBc
70
LTC2193: IOVDD vs Sample Rate,
5MHz, –1dBFS Sine Wave Input
120
40
20
60
SAMPLE RATE (Msps)
90
80
30
45
0
100
40
70
4-LANE, 3.5mA
80
dBFS
219543 G41
130
300
LTC2193: SFDR vs Input Level,
fIN = 70MHz, 80Msps, 2V Range
110
3RD
85
LTC2193: IVDD vs Sample Rate,
5MHz, –1dBFS Sine Wave Input
90
100
150
200
250
INPUT FREQUENCY (MHz)
120
219543 G40
100
50
130
90
65
300
110
0
219543 G39
LTC2193: 2nd, 3rd Harmonic vs
Input Frequency, –1dBFS, 80Msps,
1V Range
100
3RD
73
219543 G38
LTC2193: 2nd, 3rd Harmonic vs
Input Frequency, –1dBFS, 80Msps,
2V Range
90
DIFFERENTIAL
ENCODE
74
71
1000
0
75
72
2000
SFDR (dBc AND dBFS)
–110
–120
6000
SNR (dBFS)
–50
SINGLE-ENDED
ENCODE
76
7000
–40
COUNT
AMPLITUDE (dBFS)
–30
2ND AND 3RD HARMONIC (dBFS)
LTC2193: SNR vs Input Frequency,
–1dBFS, 80Msps, 2V Range
LTC2193: Shorted Input Histogram
0
40
60
20
SAMPLE RATE (Msps)
80
75
74
73
72
71
70
0.6
0.7
0.8
0.9
1
1.1
SENSE PIN (V)
1.2
1.3
219543 G45
219543 G44
219543f
13
LTC2195
LTC2194/LTC2193
PIN FUNCTIONS
VCM1 (Pin 1): Common Mode Bias Output, Nominally Equal
to VDD/2. VCM1 should be used to bias the common mode
of the analog inputs of channel 1. Bypass to ground with
a 0.1µF ceramic capacitor.
GND (Pins 2, 5, 13, 22, 45, 47, 49, Exposed Pad Pin 53):
ADC Power Ground. The exposed pad must be soldered
to the PCB ground.
AIN1+ (Pin 3): Channel 1 Positive Differential Analog
Input.
AIN1– (Pin 4): Channel 1 Negative Differential Analog
Input.
REFH (Pins 6, 8): ADC High Reference. See the Reference
section in the Applications Information for recommended
bypassing circuits for REFH and REFL.
REFL (Pins 7, 9): ADC Low Reference. See the Reference
section in the Applications Information for recommended
bypassing circuits for REFH and REFL.
PAR/SER (Pin 10): Programming Mode Selection Pin.
Connect to ground to enable the serial programming mode.
CS, SCK, SDI, SDO become a serial interface that control
the A/D operating modes. Connect to VDD to enable the
parallel programming mode where CS, SCK, SDI, SDO
become parallel logic inputs that control a reduced set of
the A/D operating modes. PAR/SER should be connected
directly to ground or the VDD of the part and not be driven
by a logic signal.
AIN2+ (Pin 11): Channel 2 Positive Differential Analog
Input.
AIN2– (Pin 12): Channel 2 Negative Differential Analog
Input.
VCM2 (Pin 14): Common Mode Bias Output, Nominally
Equal to VDD/2. VCM2 should be used to bias the common
mode of the analog inputs of channel 2. Bypass to ground
with a 0.1µF ceramic capacitor.
VDD (Pins 15, 16, 51, 52): Analog Power Supply, 1.7V
to 1.9V. Bypass to ground with 0.1µF ceramic capacitors.
Adjacent pins can share a bypass capacitor.
ENC+ (Pin 17): Encode Input. Conversion starts on the
rising edge.
ENC– (Pin 18): Encode Complement Input. Conversion
starts on the falling edge. Tie to GND for single-ended
encode mode.
CS (Pin 19): In serial programming mode, (PAR/SER =
0V), CS is the serial interface chip select input. When
CS is low, SCK is enabled for shifting data on SDI into
the mode control registers. In the parallel programming
mode (PAR/SER = VDD), CS along with SCK selects 1-,
2- or 4-lane output mode (see Table 3). CS can be driven
with 1.8V to 3.3V logic.
SCK (Pin 20): In serial programming mode, (PAR/SER =
0V), SCK is the serial interface clock input. In the parallel
programming mode (PAR/SER = VDD), SCK along with CS
selects 1-, 2- or 4-lane output mode (see Table 3). SCK
can be driven with 1.8V to 3.3V logic.
SDI (Pin 21): In Serial Programming Mode, (PAR/SER =
0V), SDI is the Serial Interface Data Input. Data on SDI
is clocked into the mode control registers on the rising
edge of SCK. In the parallel programming pode (PAR/SER
= VDD), SDI can be used to power down the part. SDI can
be driven with 1.8V to 3.3V logic.
OGND (Pin 33): Output Driver Ground. This pin must be
shorted to the ground plane by a very low inductance path.
Use multiple vias close to the pin.
OVDD (Pin 34): Output Driver Supply. Bypass to ground
with a 0.1µF ceramic capacitor.
SDO (Pin 46): In serial programming mode, (PAR/SER
= 0V), SDO is the optional serial interface data output.
Data on SDO is read back from the mode control registers and can be latched on the falling edge of SCK. SDO
is an open-drain NMOS output that requires an external
2k pull-up resistor to 1.8V to 3.3V. If read back from the
mode control registers is not needed, the pull-up resistor
is not necessary and SDO can be left unconnected. In the
parallel programming mode (PAR/SER = VDD), SDO selects
3.5mA or 1.75mA LVDS output currents. When used as an
input, SDO can be driven with 1.8V to 3.3V logic through
a 1k series resistor.
219543f
14
LTC2195
LTC2194/LTC2193
PIN FUNCTIONS
VREF (Pin 48): Reference Voltage Output. Bypass to ground
with a 2.2µF ceramic capacitor. The reference output is
nominally 1.25V.
SENSE (Pin 50): Reference Programming Pin. Connecting
SENSE to VDD selects the internal reference and a ±1V input
range. Connecting SENSE to ground selects the internal
reference and a ±0.5V input range. An external reference
between 0.625V and 1.3V applied to SENSE selects an
input range of ±0.8 • VSENSE.
LVDS Outputs
The following pins are differential LVDS outputs. The
output current level is programmable. There is an optional
internal 100Ω termination resistor between the pins of
each LVDS output pair.
OUT2D–/OUT2D+, OUT2C–/OUT2C+, OUT2B–/OUT2B+,
OUT2A–/OUT2A+ (Pins 23/24, 25/26, 27/28, 29/30): Serial
Data Outputs for Channel 2. In 1-lane output mode only
OUT2A–/OUT2A+ are used. In 2-lane output mode only
OUT2A–/OUT2A+ and OUT2B–/OUT2B+ are used.
FR–/FR+ (Pins 31/32): Frame Start Outputs.
DCO–/DCO+ (Pins 35/36): Data Clock Outputs.
OUT1D–/OUT1D+, OUT1C–/OUT1C+, OUT1B–/OUT1B+,
OUT1A–/OUT1A+ (Pins 37/38, 39/40, 41/42, 43/44): Serial
Data Outputs for Channel 1. In 1-lane output mode only
OUT1A–/OUT1A+ are used. In 2-lane output mode only
OUT1A–/OUT1A+ and OUT1B–/OUT1B+ are used.
219543f
15
LTC2195
LTC2194/LTC2193
FUNCTIONAL BLOCK DIAGRAM
1.8V
ENC+
ENC–
1.8V
VDD
CH1
ANALOG
INPUT
OVDD
PLL
16-BIT
ADC CORE
S/H
DATA
SERIALIZER
CH2
ANALOG
INPUT
16-BIT
ADC CORE
S/H
OUT1A
OUT1B
OUT1C
OUT1D
OUT2A
OUT2B
OUT2C
OUT2D
DATA CLOCK OUT
FRAME
OGND
VREF
2.2µF
1.25V
REFERENCE
RANGE
SELECT
REF BUF
REFH
REFL
SENSE
VDD/2
DIFF REF
AMP
MODE
CONTROL
REGISTERS
219543 F01
REFH
2.2µF
0.1µF
REFL
VCM1
VCM2
0.1µF
0.1µF
PAR/SER CS SCK SDI SDO
0.1µF
Figure 1. Functional Block Diagram
219543f
16
LTC2195
LTC2194/LTC2193
APPLICATIONS INFORMATION
CONVERTER OPERATION
Single-Ended Input
The LTC2195/LTC2194/LTC2193 are low power, 2-channel,
16-bit, 125/105/80Msps A/D converters that are powered
by a single 1.8V supply. The analog inputs should be driven
differentially. The encode input can be driven differentially
or single ended for lower power consumption. To minimize
the number of data lines the digital outputs are serial LVDS.
Each channel outputs two bits at a time (2-lane mode) or
four bits at a time (4‑lane mode). At lower sampling rates
there is a one bit per channel option (1-lane mode). Many
additional features can be chosen by programming the
mode control registers through a serial SPI port.
For applications less sensitive to harmonic distortion, the
AIN+ input can be driven singled ended with a 1VP-P signal
centered around VCM. The AIN– input should be connected
to VCM and the VCM bypass capacitor should be increased
to 2.2µF. With a singled-ended input the harmonic distortion
and INL will degrade, but the noise and DNL will remain
unchanged.
ANALOG INPUT
The analog inputs are differential CMOS sample-andhold circuits (Figure 2). The inputs should be driven
differentially around a common mode voltage set by the
VCM1 or VCM2 output pins, which are nominally VDD/2.
For the 2V input range, the inputs should swing from
VCM – 0.5V to VCM + 0.5V. There should be 180° phase
difference between the inputs.
The two channels are simultaneously sampled by a shared
encode circuit (Figure 2).
INPUT DRIVE CIRCUITS
Input Filtering
If possible, there should be an RC lowpass filter right at
the analog inputs. This lowpass filter isolates the drive
circuitry from the A/D sample-and-hold switching, and
also limits wideband noise from the drive circuitry. Figure 3
shows an example of an input RC filter. The RC component
values should be chosen based on the application’s input
frequency.
Transformer Coupled Circuits
Figure 3 shows the analog input being driven by an RF
transformer with a center-tapped secondary. The center
LTC2195
VDD
AIN+
RON
15Ω
10Ω
CPARASITIC
1.8pF
VDD
AIN–
CSAMPLE
5pF
RON
15Ω
10Ω
CSAMPLE
5pF
CPARASITIC
1.8pF
VDD
1.2V
10k
ENC+
ENC–
10k
1.2V
219543 F02
Figure 2. Equivalent Input Circuit. Only One of Two Analog Channels is Shown
219543f
17
LTC2195
LTC2194/LTC2193
APPLICATIONS INFORMATION
50Ω
50Ω
VCM
0.1µF
0.1µF
0.1µF
ANALOG
INPUT
T1
1:1
25Ω
25Ω
0.1µF
AIN+
ANALOG
INPUT
LTC2195
0.1µF
AIN+
T2
T1
25Ω
1.8pF
0.1µF
AIN–
T1: MA/COM MABAES0060
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
Figure 3. Analog Input Circuit Using a Transformer.
Recommended for Input Frequencies from 5MHz to 70MHz
25Ω
AIN–
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1TL
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
219543 F03
50Ω
ANALOG
INPUT
12Ω
T1
T2
25Ω
50Ω
VCM
VCM
0.1µF
0.1µF
AIN+
LTC2195
0.1µF
219543 F05
Figure 5. Recommended Front-End Circuit for Input Frequencies
from 150MHz to 250MHz
0.1µF
0.1µF
LTC2195
0.1µF
25Ω
12pF
25Ω
VCM
ANALOG
INPUT
4.7nH
T1
AIN+
LTC2195
0.1µF
25Ω
8.2pF
0.1µF
25Ω
12Ω
0.1µF
25Ω
AIN–
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1TL
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
tap is biased with VCM, setting the A/D input at its optimal
DC level. At higher input frequencies a transmission line
balun transformer (Figures 4 to 6) has better balance,
resulting in lower A/D distortion.
Amplifier Circuits
Figure 7 shows the analog input being driven by a high
speed differential amplifier. The output of the amplifier is AC
coupled to the A/D so the amplifier’s output common mode
voltage can be optimally set to minimize distortion.
At very high frequencies an RF gain block will often have
lower distortion than a differential amplifier. If the gain
block is single ended, then a transformer circuit (Figures 4
to 6) should convert the signal to differential before driving the A/D.
AIN–
T1: MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
219543 F04
Figure 4. Recommended Front-End Circuit for Input Frequencies
from 5MHz to 150MHz
4.7nH
219543 F06
Figure 6. Recommended Front-End Circuit for Input Frequencies
Above 250MHz
VCM
HIGH SPEED
DIFFERENTIAL
0.1µF
AMPLIFIER
ANALOG
INPUT
200Ω
200Ω
25Ω
+
–
0.1µF
AIN+
12pF
0.1µF
25Ω
LTC2195
AIN–
12pF
219543 F07
Figure 7. Front-End Circuit Using a High Speed
Differential Amplifier
219543f
18
LTC2195
LTC2194/LTC2193
APPLICATIONS INFORMATION
Reference
The LTC2195/LTC2194/LTC2193 have an internal 1.25V
voltage reference. For a 2V input range using the internal
reference, connect SENSE to VDD. For a 1V input range
using the internal reference, connect SENSE to ground.
For a 2V input range with an external reference, apply a
1.25V reference voltage to SENSE (Figure 9).
The input range can be adjusted by applying a voltage to
SENSE that is between 0.625V and 1.30V. The input range
will then be 1.6 • VSENSE.
The VREF, REFH and REFL pins should be bypassed as
shown in Figure 8. A low inductance 2.2µF interdigitated
capacitor is recommended for the bypass between REFH
and REFL. This type of capacitor is available at a low cost
from multiple suppliers.
At sample rates below 110Msps an interdigitated capacitor is not necessary for good performance and C1 can be
replaced by a standard 2.2µF capacitor between REFH and
REFL. The capacitors should be as close to the pins as
possible (not on the back side of the circuit board).
Figure 8c and 8d show the recommended circuit board
layout for the REFH/REFL bypass capacitors. Note that in
Figure 8c, every pin of the interdigitated capacitor (C1)
is connected since the pins are not internally connected
in some vendors’ capacitors. In Figure 8d the REFH and
REFL pins are connected by short jumpers in an internal
layer. To minimize the inductance of these jumpers they
can be placed in a small hole in the GND plane on the
second board layer.
REFH
C3
0.1µF
LTC2195
REFL
C1
2.2µF
REFH
C2
0.1µF
REFL
CAPACITORS ARE 0402 PACKAGE SIZE
219543 F08b
Figure 8b. Alternative REFH/REFL Bypass Circuit
LTC2195
VREF
1.25V
5Ω
2.2µF
1.25V BANDGAP
REFERENCE
219543 F08c
0.625V
TIE TO VDD FOR 2V RANGE;
TIE TO GND FOR 1V RANGE;
RANGE = 1.6 • VSENSE FOR
0.625V < VSENSE < 1.300V
Figure 8c. Recommended Layout for the REFH/REFL Bypass
Circuit in Figure 8a
RANGE
DETECT
AND
CONTROL
SENSE
BUFFER
INTERNAL ADC
HIGH REFERENCE
C2
0.1µF
–
+
REFH
+
–
REFL
–
+
REFH
+
–
REFL
C1
C3
0.1µF
C1: 2.2µF LOW INDUCTANCE
INTERDIGITATED CAPACITOR
TDK CLLE1AX7S0G225M
MURATA LLA219C70G225M
AVX W2L14Z225M
OR EQUIVALENT
219543 F08d
Figure 8d. Recommended Layout for the REFH/REFL Bypass
Circuit in Figure 8b
0.8x
DIFF AMP
VREF
2.2µF
INTERNAL ADC
LOW REFERENCE
Figure 8a. Reference Circuit
219543 F08a
1.25V
EXTERNAL
REFERENCE
LTC2195
SENSE
1µF
219543 F09
Figure 9. Using an External 1.25V Reference
219543f
19
LTC2195
LTC2194/LTC2193
APPLICATIONS INFORMATION
Encode Input
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals—do not route them next to
digital traces on the circuit board. There are two modes
of operation for the encode inputs: the differential encode
mode (Figure 10), and the single-ended encode mode
(Figure 11).
The differential encode mode is recommended for sinusoidal, PECL, or LVDS encode inputs (Figures 12, 13). The
encode inputs are internally biased to 1.2V through 10k
equivalent resistance. The encode inputs can be taken above
VDD (up to 3.6V), and the common mode range is from 1.1V
to 1.6V. In the differential encode mode, ENC– should stay
at least 200mV above ground to avoid falsely triggering the
single-ended encode mode. For good jitter performance
ENC+ should have fast rise and fall times.
encode input. ENC+ can be taken above VDD (up to 3.6V)
so 1.8V to 3.3V CMOS logic levels can be used. The ENC+
threshold is 0.9V. For good jitter performance ENC+ should
have fast rise and fall times. If the encode signal is turned
off or drops below approximately 500kHz, the A/D enters
nap mode.
0.1µF
ENC+
T1
0.1µF
50Ω
ENC–
0.1µF
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
219543 F12
Figure 12. Sinusoidal Encode Drive
0.1µF
PECL OR
LVDS
CLOCK
VDD
50Ω
100Ω
The single-ended encode mode should be used with
CMOS encode inputs. To select this mode, ENC– is connected to ground and ENC+ is driven with a square wave
LTC2195
ENC+
LTC2195
0.1µF
ENC–
DIFFERENTIAL
COMPARATOR
VDD
LTC2195
219543 F13
Figure 13. PECL or LVDS Encode Drive
15k
ENC+
Clock PLL and Duty Cycle Stabilizer
ENC–
30k
219543 F10
Figure 10. Equivalent Encode Input Circuit
for Differential Encode Mode
LTC2195
1.8V TO 3.3V
0V
ENC+
ENC–
30k
The encode clock is multiplied by an internal phase-locked
loop (PLL) to generate the serial digital output data. If the
encode signal changes frequency or is turned off, the PLL
requires 25µs to lock onto the input clock.
A clock duty cycle stabilizer circuit allows the duty cycle
of the applied encode signal to vary from 30% to 70%.
In the serial programming mode it is possible to disable
the duty cycle stabilizer, but this is not recommended. In
the parallel programming mode the duty cycle stabilizer
is always enabled.
CMOS LOGIC
BUFFER
219543 F11
Figure 11. Equivalent Encode Input Circuit
for Single-Ended Encode Mode
20
219543f
LTC2195
LTC2194/LTC2193
APPLICATIONS INFORMATION
DIGITAL OUTPUTS
Optional LVDS Driver Internal Termination
The digital outputs of the LTC2195/LTC2194/LTC2193 are
serialized LVDS signals. Each channel outputs two bits at
a time (2-lane mode) or four bits at a time (4-lane mode).
At lower sampling rates there is a one bit per channel option (1-lane mode). Please refer to the Timing Diagrams
for details. In 4-lane mode the clock duty cycle stabilizer
must be enabled.
In most cases using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addition, an optional internal 100Ω termination resistor can
be enabled by serially programming mode control register
A2. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When
the internal termination is enabled, the output driver
current is doubled to maintain the same output voltage
swing. Internal termination can only be selected in serial
programming mode.
The output data should be latched on the rising and falling
edges of the data clock out (DCO). A data frame output
(FR) can be used to determine when the data from a new
conversion result begins.
The maximum serial data rate for the data outputs is 1Gbps,
so the maximum sample rate of the ADC will depend on
the serialization mode as well as the speed grade of the
ADC (See Table 1). The minimum sample rate for all serialization modes is 5Msps.
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode voltage. An external 100Ω differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
The outputs are powered by OVDD and OGND which are
isolated from the A/D core power and ground.
Table 1. Maximum Sampling Frequency for All Serialization
Modes. Note That These Limits are for the LTC2195. The
Sampling Frequency for the Slower Speed Grades Cannot
Exceed 105MHz (LTC2194) or 80MHz (LTC2193).
MAXIMUM
SAMPLING
SERIALIZATION FREQUENCY,
DCO
FR
SERIAL
MODE
fS (MHz)
FREQUENCY FREQUENCY DATA RATE
fS
4 • fS
4-Lane
125
2 • fS
2-Lane
125
4 • fS
fS
8 • fS
1-Lane
62.5
8 • fS
fS
16 • fS
Programmable LVDS Output Current
In LVDS mode, the default output driver current is 3.5mA.
This current can be adjusted by control register A2 in the
serial programming mode. Available current levels are
1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.
In the parallel programming mode the SDO pin can select
either 3.5mA or 1.75mA.
DATA FORMAT
Table 2 shows the relationship between the analog input
voltage and the digital data output bits. By default the
output data format is offset binary. The 2’s complement
format can be selected by serially programming mode
control register A1.
Table 2. Output Codes vs Input Voltage
AIN+-AIN–
(2V RANGE)
D15-D0
(OFFSET BINARY)
D15-D0
(2’ s COMPLEMENT)
>1.000000V
+0.999970V
+0.999939V
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1110
0111 1111 1111 1111
0111 1111 1111 1111
0111 1111 1111 1110
+0.000030V
+0.000000V
–0.000030V
–0.000061V
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0111 1111 1111 1110
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1110
–0.999939V
–1.000000V
<–1.000000V
0000 0000 0000 0001
0000 0000 0000 0000
0000 0000 0000 0000
1000 0000 0000 0001
1000 0000 0000 0000
1000 0000 0000 0000
Digital Output Randomizer
Interference from the A/D digital outputs is sometimes
unavoidable. Digital interference may be from capacitive or
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off-chip, these unwanted
tones can be randomized which reduces the unwanted
tone amplitude.
The digital output is randomized by applying an exclusive OR logic operation between the LSB and all other
data output bits. To decode, the reverse operation is
219543f
21
LTC2195
LTC2194/LTC2193
APPLICATIONS INFORMATION
applied—an exclusive OR operation is applied between
the LSB and all other bits. The FR and DCO outputs are
not affected. The output randomizer is enabled by serially
programming mode control register A1.
Digital Output Test Pattern
To allow in-circuit testing of the digital interface to the
A/D, there is a test mode that forces the A/D data outputs
(D15-D0) of both channels to known values. The digital
output test patterns are enabled by serially programming
mode control registers A2, A3 and A4. When enabled,
the test patterns override all other formatting modes: 2’s
complement and randomizer.
Output Disable
The digital outputs may be disabled by serially programming mode control register A2. The current drive for all
digital outputs including DCO and FR are disabled to save
power or enable in-circuit testing. When disabled the common mode of each output pair becomes high impedance,
but the differential impedance may remain low.
Sleep and Nap Modes
The A/D may be placed in sleep or nap modes to conserve
power. In sleep mode the entire device is powered down,
resulting in 1mW power consumption. Sleep mode is
enabled by mode control register A1 (serial programming mode), or by SDI (parallel programming mode).
The amount of time required to recover from sleep mode
depends on the size of the bypass capacitors on VREF ,
REFH and REFL. For the suggested values in Figure 8, the
A/D will stabilize after 2ms.
In nap mode any combination of A/D channels can be
powered down while the internal reference circuits and the
PLL stay active, allowing faster wake up than from sleep
mode. Recovering from nap mode requires at least 100
clock cycles. If the application demands very accurate DC
settling then an additional 50µs should be allowed so the
on-chip references can settle from the slight temperature
shift caused by the change in supply current as the A/D
leaves nap mode. Nap mode is enabled by mode control
register A1 in the serial programming mode.
DEVICE PROGRAMMING MODES
The operating modes of the LTC2195/LTC2194/LTC2193
can be programmed by either a parallel interface or a
simple serial interface. The serial interface has more flexibility and can program all available modes. The parallel
interface is more limited and can only program some of
the more commonly used modes.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to VDD. The CS, SCK, SDI and SDO pins are binary
logic inputs that set certain operating modes. These pins
can be tied to VDD or ground, or driven by 1.8V, 2.5V or
3.3V CMOS logic. When used as an input, SDO should
be driven through a 1k series resistor. Table 3 shows the
modes set by CS, SCK, SDI and SDO.
Table 3. Parallel Programming Mode Control Bits (PAR/SER = VDD)
PIN
CS/SCK
DESCRIPTION
2-Lane/4-Lane/1-Lane Selection Bits
00 = 2-Lane Output Mode
01 = 4-Lane Output Mode
10 = 1-Lane Output Mode
11 = Not Used
SDI
Power Down Control Bit
0 = Normal Operation
1 = Sleep Mode
SDO
LVDS Current Selection Bit
0 = 3.5mA LVDS Current Mode
1 = 1.75mA LVDS Current Mode
Serial Programming Mode
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become
a serial interface that program the A/D mode control
registers. Data is written to a register with a 16-bit serial
word. Data can also be read back from a register to verify
its contents.
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the first 16 rising edges of
SCK. Any SCK rising edges after the first 16 are ignored.
The data transfer ends when CS is taken high again.
219543f
22
LTC2195
LTC2194/LTC2193
APPLICATIONS INFORMATION
The first bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The final eight bits are the register data (D7:D0).
If the R/W bit is low, the serial data (D7:D0) will be written to the register set by the address bits (A6:A0). If the
R/W bit is high, data in the register set by the address bits
(A6:A0) will be read back on the SDO pin (see the Timing
Diagrams). During a read back command the register is
not updated and data on SDI is ignored.
The SDO pin is an open-drain output that pulls to ground
with a 200Ω impedance. If register data is read back
through SDO, an external 2k pull-up resistor is required.
If serial data is only written and read back is not needed,
then SDO can be left floating and no pull-up resistor is
needed.
Table 4 shows a map of the mode control registers.
Software Reset
If serial programming is used, the mode control registers
should be programmed as soon as possible after the power
supplies turn on and are stable. The first serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset, bit D7 in the
reset register is written with a logic 1. After the reset SPI
write command is complete, bit D7 is automatically set
back to zero.
Table 4. Serial Programming Mode Register Map (PAR/SER = GND)
REGISTER A0: RESET REGISTER (ADDRESS 00h)
D7
D6
RESET
X
RESET
Bit 7
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
Software Reset Bit
0 = Not Used
1 = Software Reset. All Mode Control Registers are Reset to 00h. The ADC is Momentarily Placed in Sleep Mode.
This Bit is Automatically Set Back to Zero at the End of the SPI Write Command. The Reset Register Is Write Only.
Data Read Back from the Reset Register Will Be Random
Bits 6-0
Unused, Don’t Care Bits.
REGISTER A1: FORMAT AND POWER-DOWN REGISTER (ADDRESS 01h)
D7
D6
D5
D4
D3
D2
D1
D0
DCSOFF
RAND
TWOSCOMP
SLEEP
NAP_2
X
X
NAP_1
Bit 7
Clock Duty Cycle Stabilizer Bit
DCSOFF
0 = Clock Duty Cycle Stabilizer On
1 = Clock Duty Cycle Stabilizer Off. This is not recommended.
Bit 6
RAND
Data Output Randomizer Mode Control Bit
0 = Data Output Randomizer Mode Off
1 = Data Output Randomizer Mode On
Bit 5
TWOSCOMP
Two’s Complement Mode Control Bit
0 = Offset Binary Data Format
1 = Two’s Complement Data Format
Bits 4, 3, 0
SLEEP:NAP_2:NAP_1 Sleep/Nap Mode Control Bits
000 = Normal Operation
0X1 = Channel 1 in Nap Mode
01X = Channel 2 in Nap Mode
1XX = Sleep Mode. Both Channels are Disabled.
Note: Any Combination of Channels Can Be Placed in Nap Mode
Bits 1, 2
Unused, Don’t Care Bits
219543f
23
LTC2195
LTC2194/LTC2193
APPLICATIONS INFORMATION
REGISTER A2: OUTPUT MODE REGISTER (ADDRESS 02h)
D7
ILVDS2
D6
D5
D4
D3
D2
D1
D0
ILVDS1
ILVDS0
TERMON
OUTOFF
OUTTEST
OUTMODE1
OUTMODE0
Bits 7-5
ILVDS2:ILVDS0 LVDS Output Current Bits
000 = 3.5mA LVDS Output Driver Current
001 = 4.0mA LVDS Output Driver Current
010 = 4.5mA LVDS Output Driver Current
011 = Not Used
100 = 3.0mA LVDS Output Driver Current
101 = 2.5mA LVDS Output Driver Current
110 = 2.1mA LVDS Output Driver Current
111 = 1.75mA LVDS Output Driver Current
Bit 4
TERMON
LVDS Internal Termination Bit
0 = Internal Termination Off
1 = Internal Termination On. LVDS Output Driver Current is 2× the Current Set by ILVDS2:ILVDS0
Bit 3
OUTOFF
Output Disable Bit
0 = Digital Outputs are Enabled
1 = Digital Outputs are Disabled
Bit 2
OUTTEST
Digital Output Test Pattern Control Bit
0 = Digital Output Test Pattern Off
1 = Digital Output Test Pattern On
Bits 1-0
OUTMODE1:OUTMODE0
00 = 2-Lane Output Mode
01 = 4-Lane Output Mode
10 = 1-Lane Output Mode
11 = Not Used
Digital Output Mode Control Bits
REGISTER A3: TEST PATTERN MSB REGISTER (ADDRESS 03h)
D7
D6
D5
D4
D3
D2
D1
D0
TP15
TP14
TP13
TP12
TP11
TP10
TP9
TP8
Bits 7-0
TP15:TP8
Test Pattern Data Bits (MSB)
TP15:TP8 Set the Test Pattern for Data Bit 15 (MSB) Through Data Bit 8.
REGISTER A4: TEST PATTERN LSB REGISTER (ADDRESS 04h)
D7
D6
D5
D4
D3
D2
D1
D0
TP7
TP6
TP5
TP4
TP3
TP2
TP1
TP0
Bits 7-0
TP7:TP0
Test Pattern Data Bits (LSB)
TP7:TP0 Set the Test Pattern for Data Bit 7 Through Data Bit 0 (LSB).
219543f
24
LTC2195
LTC2194/LTC2193
APPLICATIONS INFORMATION
GROUNDING AND BYPASSING
the circuit board as the A/D, and as close to the device
as possible. A low inductance interdigitated capacitor is
suggested for REFH/REFL if the sampling frequency is
greater than 110Msps.
The LTC2195/LTC2194/LTC2193 require a printed circuit
board with a clean unbroken ground plane. A multilayer
board with an internal ground plane in the first layer beneath the ADC is recommended. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track or underneath the ADC.
The analog inputs, encode signals, and digital outputs
should not be routed next to each other. Ground fill and
grounded vias should be used as barriers to isolate these
signals from each other.
HEAT TRANSFER
High quality ceramic bypass capacitors should be used at
the VDD, OVDD, VCM, VREF, REFH and REFL pins. Bypass
capacitors must be located as close to the pins as possible.
Size 0402 ceramic capacitors are recommended. The traces
connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.
Most of the heat generated by the LTC2195/LTC2194/
LTC2193 is transferred from the die through the bottomside exposed pad and package leads onto the printed circuit
board. For good electrical and thermal performance, the
exposed pad must be soldered to a large grounded pad
on the PC board. This pad should be connected to the
internal ground planes by an array of vias.
Of particular importance is the capacitor between REFH
and REFL. This capacitor should be on the same side of
TYPICAL APPLICATIONS
C4
2.2µF
SDO
41
OUT1B–
42
OUT1B+
44
45
43
OUT1A–
OUT1A
+
GND
46
SDO
47
GND
48
VREF
49
GND
50
SENSE
VDD
52
VDD
OUT2B+
C7
0.1µF
ENCODE
INPUT
SPI
PORT
OUT2B–
40
39
38
37
36
35
34
OVDD
33
32
31
DIGITAL
OUTPUTS
C16 0.1µF
30
29
28
27
26
25
VDD
OUT2D
VCM2
OUT2C+
GND
OUT2C–
OUT2A–
OUT2D+
AIN2–
–
OUT2A+
24
C37
0.1µF
AIN2+
GND
14
FR–
23
13
PAR/SER
SDI
12
FR+
22
AIN2–
11
OGND
REFL
SCK
PAR/SER
AIN2+
REFH
21
10
OVDD
LTC2195
CS
9
REFL
20
8
REFH
DCO–
19
7
GND
DCO+
ENC–
6
AIN1–
OUT1D–
ENC+
C2 0.1µF
+
–
–
+
CN1 +
–
–
+
OUT1C–
AIN1+
18
C3 0.1µF
5
OUT1C+
OUT1D+
VDD
AIN1–
4
GND
17
AIN1+
3
VCM1
VDD
2
16
1
15
C29
0.1µF
C5
0.1µF
51
SENSE
VDD
219543 TA02
219543f
25
LTC2195
LTC2194/LTC2193
TYPICAL APPLICATIONS
Top Side
Inner Layer 2
Inner Layer 3
Inner Layer 4
Inner Layer 5
Bottom Side
219543f
26
LTC2195
LTC2194/LTC2193
PACKAGE DESCRIPTION
UKG Package
52-Lead Plastic QFN (7mm × 8mm)
(Reference LTC DWG # 05-08-1729 Rev Ø)
7.50 ±0.05
6.10 ±0.05
5.50 REF
(2 SIDES)
0.70 ±0.05
6.45 ±0.05
6.50 REF 7.10 ±0.05 8.50 ±0.05
(2 SIDES)
5.41 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
7.00 ± 0.10
(2 SIDES)
0.75 ± 0.05
0.00 – 0.05
R = 0.115
TYP
5.50 REF
(2 SIDES)
51
52
0.40 ± 0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
2
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45°C
CHAMFER
8.00 ± 0.10
(2 SIDES)
6.50 REF
(2 SIDES)
6.45 ±0.10
5.41 ±0.10
R = 0.10
TYP
TOP VIEW
0.200 REF
0.00 – 0.05
0.75 ± 0.05
(UKG52) QFN REV Ø 0306
0.25 ± 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
SIDE VIEW
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
219543f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC2195
LTC2194/LTC2193
TYPICAL APPLICATION
2-Tone FFT, fIN = 70MHz and 69MHz
1.8V
CH1
ANALOG
INPUT
CH2
ANALOG
INPUT
S/H
S/H
0
OVDD
VDD
–10
OUT1A
OUT1B
OUT1C
OUT1D
OUT2A
OUT2B
OUT2C
OUT2D
DATA CLOCK OUT
FRAME
16-BIT
ADC CORE
16-BIT
ADC CORE
ENCODE
INPUT
DATA
SERIALIZER
PLL
GND
–20
–30
SERIALIZED
LVDS
OUTPUTS
AMPLITUDE (dBFS)
1.8V
–40
–50
–60
–70
–80
–90
–100
–110
–120
OGND
219543 TA01a
0
10
20
30
40
FREQUENCY (MHz)
50
60
219543 TA01b
RELATED PARTS
PART NUMBER
ADCs
LTC2259-14/LTC2260-14/
LTC2261-14
LTC2262-14
DESCRIPTION
COMMENTS
14-Bit, 80Msps/105Msps/125Msps
1.8V ADCs, Ultralow Power
14-Bit, 150Msps 1.8V ADC, Ultralow
Power
LTC2266-14/LTC2267-14/ 14-Bit, 80Msps/105Msps/125Msps
LTC2268-14
1.8V Dual ADCs, Ultralow Power
LTC2266-12/LTC2267-12/ 12-Bit, 80Msps/105Msps/125Msps
LTC2268-12
1.8V VDual ADCs, Ultralow Power
LTC2208
16-Bit, 130Msps 3.3V ADC
89mW/106mW/127mW, 73.4dB SNR, 85dB SFDR, DDR LVDS/DDR CMOS/CMOS
Outputs, 6mm × 6mm QFN-40
149mW, 72.8dB SNR, 88dB SFDR, DDR LVDS/DDR CMOS/CMOS Outputs,
6mm × 6mm QFN-40
216mW/250mW/293mW, 73.4dB SNR, 85dB SFDR, Serial LVDS Outputs,
6mm × 6mm QFN-40
216mW/250mW/293mW, 70.5dB SNR, 85dB SFDR, Serial LVDS Outputs,
6mm × 6mm QFN-40
LTC2207/LTC2206
16-Bit, 105Msps/80Msps 3.3V ADCs
LTC2217/LTC2216
16-Bit, 105Msps/80Msps 3.3V ADCs
900mW/725mW, 77.9dB SNR, 100dB SFDR, CMOS Outputs, 7mm × 7mm QFN-48
1190mW/970mW, 81.2dB SNR, 100dB SFDR, CMOS/LVDS Outputs,
9mm × 9mm QFN-64
RF Mixers/Demodulators
LTC5517
40MHz to 900MHz Direct Conversion
Quadrature Demodulator
LTC5527
400MHz to 3.7GHz High Linearity
Downconverting Mixer
LTC5557
400MHz to 3.8GHz High Linearity
Downconverting Mixer
LTC5575
800MHz to 2.7GHz Direct Conversion
Quadrature Demodulator
Amplifiers/Filters
LTC6412
800MHz, 31dB Range, Analog-Controlled
Variable Gain Amplifier
LTC6420-20
1.8GHz Dual Low Noise, Low Distortion
Differential ADC Drivers for 300MHz IF
LTC6421-20
1.3GHz Dual Low Noise, Low Distortion
Differential ADC Drivers
LTC6605-7/LTC6605-10/ Dual Matched 7MHz/10MHz/14MHz
LTC6605-14
Filters with ADC Drivers
Signal Chain Receivers
LTM9002
14-Bit Dual Channel IF/Baseband
Receiver Subsystem
1250mW, 77.7dB SNR, 100dB SFDR, CMOS/LVDS Outputs, 9mm × 9mm QFN-64
High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator
24.5dBm IIP3 at 900MHz, 23.5dBm IIP3 at 3.5GHz, NF = 12.5dB,
50Ω Single-Ended RF and LO Ports
23.7dBm IIP3 at 2.6GHz, 23.5dBm IIP3 at 3.5GHz, NF = 13.2dB, 3.3V Supply
Operation, Integrated Transformer
High IIP3: 28dBm at 900MHz, Integrated LO Quadrature Generator, Integrated RF
and LO Transformer
Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz, 10dB Noise Figure,
4mm × 4mm QFN-24
Fixed Gain 10V/V, 1nV/√Hz Total Input Noise, 80mA Supply Current per Amplifier,
3mm × 4mm QFN-20
Fixed Gain 10V/V, 1nV/√Hz Total Input Noise, 40mA Supply Current per Amplifier,
3mm × 4mm QFN-20
Dual Matched 2nd Order Lowpass Filters with Differential Drivers,
Pin-Programmable Gain, 6mm × 3mm DFN-22
Integrated High Speed ADC, Passive Filters and Fixed Gain Differential Amplifiers
219543f
28 Linear Technology Corporation
LT 0411 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2011